From d905a7701d7e9b395d8ce696377e650ad9eb9eda Mon Sep 17 00:00:00 2001 From: xiajingze Date: Sat, 28 Dec 2024 11:16:29 +0800 Subject: [PATCH] [AArch64] Support HiSilicon's hip11 subtarget --- clang/test/Driver/aarch64-hip11.c | 8 ++++++++ clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- .../llvm/TargetParser/AArch64TargetParser.h | 7 +++++++ llvm/lib/Target/AArch64/AArch64.td | 18 ++++++++++++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 7 +++++++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 3 ++- llvm/lib/TargetParser/Host.cpp | 1 + llvm/test/CodeGen/AArch64/cpus.ll | 1 + llvm/test/CodeGen/AArch64/remat.ll | 1 + llvm/unittests/TargetParser/Host.cpp | 3 +++ .../TargetParser/TargetParserTest.cpp | 14 +++++++++++++- 11 files changed, 63 insertions(+), 4 deletions(-) create mode 100644 clang/test/Driver/aarch64-hip11.c diff --git a/clang/test/Driver/aarch64-hip11.c b/clang/test/Driver/aarch64-hip11.c new file mode 100644 index 000000000000..a43205adf079 --- /dev/null +++ b/clang/test/Driver/aarch64-hip11.c @@ -0,0 +1,8 @@ +// RUN: %clang -target aarch64_be -mcpu=hip11 -### -c %s 2>&1 | FileCheck -check-prefix=HIP11-BE %s +// RUN: %clang -target aarch64 -mbig-endian -mcpu=hip11 -### -c %s 2>&1 | FileCheck -check-prefix=HIP11-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -mcpu=hip11 -### -c %s 2>&1 | FileCheck -check-prefix=HIP11-BE %s +// RUN: %clang -target aarch64_be -mtune=hip11 -### -c %s 2>&1 | FileCheck -check-prefix=HIP11-BE-TUNE %s +// RUN: %clang -target aarch64 -mbig-endian -mtune=hip11 -### -c %s 2>&1 | FileCheck -check-prefix=HIP11-BE-TUNE %s +// RUN: %clang -target aarch64_be -mbig-endian -mtune=hip11 -### -c %s 2>&1 | FileCheck -check-prefix=HIP11_BE_TUNE %s +// HIP11-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "hip11" +// HIP11-BE_TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" \ No newline at end of file diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index ebf739073eb8..e7d8b38bb6a5 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, hip10c, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, hip10c, hip11, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, hip10c, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, hip10c, hip11, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 1f61531c24a4..9362ef0bce6f 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -556,6 +556,13 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_RAND | AArch64::AEK_SB | AArch64::AEK_SHA2 | AArch64::AEK_SHA3 | AArch64::AEK_SM4 | AArch64::AEK_SSBS | AArch64::AEK_SVE | AArch64::AEK_BF16 | AArch64::AEK_I8MM)}, + {"hip11", ARMV9A, + (AArch64::AEK_AES | AArch64::AEK_SM4 | AArch64::AEK_SHA2 | + AArch64::AEK_SHA3 | AArch64::AEK_MTE | AArch64::AEK_PAUTH | + AArch64::AEK_FLAGM | AArch64::AEK_SB | AArch64::AEK_I8MM | + AArch64::AEK_FP16FML | AArch64::AEK_SVE | AArch64::AEK_SVE2 | + AArch64::AEK_SVE2BITPERM | AArch64::AEK_BF16 | AArch64::AEK_SME | + AArch64::AEK_SMEF64F64 | AArch64::AEK_SMEFA64)}, }; // An alias for a CPU. diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 4183fd7314f9..b572ee6d0ebb 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -1236,6 +1236,17 @@ def TuneHIP10C : SubtargetFeature<"hip10c", "ARMProcFamily", "HIP10C", FeatureAscendStoreAddress, FeaturePostRAScheduler]>; +def TuneHIP11 : SubtargetFeature<"hip11", "ARMProcFamily", "HIP11", + "HiSilicon HIP11 processors", [ + FeatureCustomCheapAsMoveHandling, + FeatureExperimentalZeroingPseudos, + FeatureFuseAES, + FeatureLSLFast, + FeatureAscendStoreAddress, + FeatureCmpBccFusion, + FeatureArithmeticBccFusion, + FeaturePostRAScheduler]>; + def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", "Ampere Computing Ampere-1 processors", [ FeaturePostRAScheduler, @@ -1400,6 +1411,10 @@ def ProcessorFeatures { FeatureMatMulFP32, FeatureMatMulFP64, FeatureMTE, FeaturePerfMon, FeatureRandGen, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureWFxT, FeatureBF16, FeatureMatMulInt8]; + list HIP11 = [HasV9_0aOps, FeaturePerfMon, FeatureETE, FeatureMTE, + FeatureFP16FML, FeatureSVE2BitPerm, FeatureBF16, + FeatureMatMulInt8, FeatureCrypto, FeatureSHA3, FeatureSM4, + FeatureSME, FeatureSMEF64F64, FeatureSMEFA64]; list Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureSSBS, FeatureRandGen, FeatureSB, FeatureSHA2, FeatureSHA3, FeatureAES]; @@ -1514,6 +1529,9 @@ def : ProcessorModel<"hip09", HIP09Model, ProcessorFeatures.HIP09, // FIXME: Hisilicon HIP10C is currently modeled as a Cortex-A57 def : ProcessorModel<"hip10c", CortexA57Model, ProcessorFeatures.HIP10C, [TuneHIP10C]>; +// FIXME: Hisilicon HIP11 is currently modeled as a Cortex-A57. +def : ProcessorModel<"hip11", CortexA57Model, ProcessorFeatures.HIP11, + [TuneHIP11]>; // Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 652d68441cf8..89a586e52ee7 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -280,6 +280,13 @@ void AArch64Subtarget::initializeProperties() { VScaleForTuning = 2; DefaultSVETFOpts = TailFoldingOpts::Simple; break; + case HIP11: + CacheLineSize = 64; + PrefFunctionAlignment = Align(16); + PrefLoopAlignment = Align(4); + VScaleForTuning = 4; + DefaultSVETFOpts = TailFoldingOpts::Simple; + break; case ThunderX3T110: CacheLineSize = 64; PrefFunctionAlignment = Align(16); diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index dd88d5b0f600..ddaf3c983ef6 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -89,7 +89,8 @@ public: ThunderX3T110, TSV110, HIP09, - HIP10C + HIP10C, + HIP11 }; protected: diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index ea3106bd60c9..9358b1365958 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -259,6 +259,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xd01", "tsv110") .Case("0xd02", "hip09") .Case("0xd45", "hip10c") + .Case("0xd22", "hip11") .Default("generic"); if (Implementer == "0x51") // Qualcomm Technologies, Inc. diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll index 0b0ae772c11c..f7d91bc87e21 100644 --- a/llvm/test/CodeGen/AArch64/cpus.ll +++ b/llvm/test/CodeGen/AArch64/cpus.ll @@ -35,6 +35,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=tsv110 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip09 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip10c 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip11 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s diff --git a/llvm/test/CodeGen/AArch64/remat.ll b/llvm/test/CodeGen/AArch64/remat.ll index 9c39c660ff44..9f3ae3e7fa14 100644 --- a/llvm/test/CodeGen/AArch64/remat.ll +++ b/llvm/test/CodeGen/AArch64/remat.ll @@ -24,6 +24,7 @@ ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip09 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip10c -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip11 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp index 52d52d786baf..f67cb700dbb0 100644 --- a/llvm/unittests/TargetParser/Host.cpp +++ b/llvm/unittests/TargetParser/Host.cpp @@ -256,6 +256,9 @@ CPU part : 0x0a1 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n" "CPU part : 0xd45"), "hip10c"); + EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n" + "CPU part : 0xd22"), + "hip11"); // Verify A64FX. const std::string A64FXProcCpuInfo = R"( diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 35e011ef0717..eb08c964104c 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1443,6 +1443,18 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_LSE | AArch64::AEK_RAS | AArch64::AEK_RCPC | AArch64::AEK_RDM | AArch64::AEK_SIMD, "8.5-A"), + ARMCPUTestParams( + "hip11", "armv9-a", "neon-fp-armv8", + AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD | + AArch64::AEK_RAS | AArch64::AEK_LSE | AArch64::AEK_RDM | + AArch64::AEK_RCPC | AArch64::AEK_SVE | AArch64::AEK_SVE2 | + AArch64::AEK_DOTPROD | AArch64::AEK_MTE | AArch64::AEK_FP16FML | + AArch64::AEK_FP16 | AArch64::AEK_SVE2BITPERM | + AArch64::AEK_PAUTH | AArch64::AEK_FLAGM | AArch64::AEK_SB | + AArch64::AEK_I8MM | AArch64::AEK_BF16 | AArch64::AEK_SME | + AArch64::AEK_SMEF64F64 | AArch64::AEK_AES | AArch64::AEK_SM4 | + AArch64::AEK_SHA2 | AArch64::AEK_SHA3 | AArch64::AEK_SMEFA64, + "9-A"), ARMCPUTestParams("a64fx", "armv8.2-a", "crypto-neon-fp-armv8", AArch64::AEK_CRC | AArch64::AEK_AES | AArch64::AEK_SHA2 | AArch64::AEK_FP | @@ -1459,7 +1471,7 @@ INSTANTIATE_TEST_SUITE_P( "8.2-A"))); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 64; +static constexpr unsigned NumAArch64CPUArchs = 65; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List; -- Gitee