From 111f55e8649f6606b53e337536e65bcb297d8d5c Mon Sep 17 00:00:00 2001 From: xiajingze Date: Thu, 2 Jan 2025 19:35:15 +0800 Subject: [PATCH] [AArch64] Support HiSilicon's hip10c subtarget --- clang/test/Driver/aarch64-hip10c.c | 8 ++++++++ clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- .../llvm/TargetParser/AArch64TargetParser.h | 7 +++++++ llvm/lib/Target/AArch64/AArch64.td | 17 +++++++++++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 7 +++++++ llvm/lib/Target/AArch64/AArch64Subtarget.h | 3 ++- llvm/lib/TargetParser/Host.cpp | 1 + llvm/test/CodeGen/AArch64/cpus.ll | 1 + llvm/test/CodeGen/AArch64/remat.ll | 1 + llvm/unittests/TargetParser/Host.cpp | 3 +++ .../unittests/TargetParser/TargetParserTest.cpp | 14 +++++++++++++- 11 files changed, 62 insertions(+), 4 deletions(-) create mode 100644 clang/test/Driver/aarch64-hip10c.c diff --git a/clang/test/Driver/aarch64-hip10c.c b/clang/test/Driver/aarch64-hip10c.c new file mode 100644 index 000000000000..4b93b97c6b18 --- /dev/null +++ b/clang/test/Driver/aarch64-hip10c.c @@ -0,0 +1,8 @@ +// RUN: %clang -target aarch64_be -mcpu=hip10c -### -c %s 2>&1 | FileCheck -check-prefix=hip10c-BE %s +// RUN: %clang -target aarch64 -mbig-endian -mcpu=hip10c -### -c %s 2>&1 | FileCheck -check-prefix=hip10c-BE %s +// RUN: %clang -target aarch64_be -mbig-endian -mcpu=hip10c -### -c %s 2>&1 | FileCheck -check-prefix=hip10c-BE %s +// RUN: %clang -target aarch64_be -mtune=hip10c -### -c %s 2>&1 | FileCheck -check-prefix=hip10c-BE-TUNE %s +// RUN: %clang -target aarch64 -mbig-endian -mtune=hip10c -### -c %s 2>&1 | FileCheck -check-prefix=hip10c-BE-TUNE %s +// RUN: %clang -target aarch64_be -mbig-endian -mtune=hip10c -### -c %s 2>&1 | FileCheck -check-prefix=hip10c-BE-TUNE %s +// hip10c-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "hip10c" +// hip10c-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 906be590e857..ebf739073eb8 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, hip10c, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-a715, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, hip09, hip10c, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 154e7e1ce987..1f61531c24a4 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -549,6 +549,13 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_SHA3 | AArch64::AEK_FP16 | AArch64::AEK_PROFILE | AArch64::AEK_FP16FML | AArch64::AEK_SVE | AArch64::AEK_I8MM | AArch64::AEK_F32MM | AArch64::AEK_F64MM | AArch64::AEK_BF16)}, + {"hip10c", ARMV8_5A, + (AArch64::AEK_F32MM | AArch64::AEK_F64MM | AArch64::AEK_FLAGM | + AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_MTE | + AArch64::AEK_PAUTH | AArch64::AEK_PERFMON | AArch64::AEK_PROFILE | + AArch64::AEK_RAND | AArch64::AEK_SB | AArch64::AEK_SHA2 | + AArch64::AEK_SHA3 | AArch64::AEK_SM4 | AArch64::AEK_SSBS | + AArch64::AEK_SVE | AArch64::AEK_BF16 | AArch64::AEK_I8MM)}, }; // An alias for a CPU. diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 865c8c38213c..4183fd7314f9 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -1226,6 +1226,16 @@ def TuneHIP09 : SubtargetFeature<"hip09", "ARMProcFamily", "HIP09", FeatureFuseMvnClz, FeaturePostRAScheduler]>; +def TuneHIP10C : SubtargetFeature<"hip10c", "ARMProcFamily", "HIP10C", + "HiSilicon HIP10C processors", [ + FeatureCustomCheapAsMoveHandling, + FeatureCmpBccFusion, + FeatureExperimentalZeroingPseudos, + FeatureFuseAES, + FeatureLSLFast, + FeatureAscendStoreAddress, + FeaturePostRAScheduler]>; + def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", "Ampere Computing Ampere-1 processors", [ FeaturePostRAScheduler, @@ -1386,6 +1396,10 @@ def ProcessorFeatures { FeatureFullFP16, FeatureFP16FML, FeatureDotProd, FeatureJS, FeatureComplxNum, FeatureSHA3, FeatureSM4, FeatureSVE]; + list HIP10C = [HasV8_5aOps, FeatureAES, FeatureFP16FML, FeatureFullFP16, + FeatureMatMulFP32, FeatureMatMulFP64, FeatureMTE, FeaturePerfMon, + FeatureRandGen, FeatureSHA2, FeatureSHA3, FeatureSM4, FeatureWFxT, + FeatureBF16, FeatureMatMulInt8]; list Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureSSBS, FeatureRandGen, FeatureSB, FeatureSHA2, FeatureSHA3, FeatureAES]; @@ -1497,6 +1511,9 @@ def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, [TuneTSV110]>; def : ProcessorModel<"hip09", HIP09Model, ProcessorFeatures.HIP09, [TuneHIP09]>; +// FIXME: Hisilicon HIP10C is currently modeled as a Cortex-A57 +def : ProcessorModel<"hip10c", CortexA57Model, ProcessorFeatures.HIP10C, + [TuneHIP10C]>; // Support cyclone as an alias for apple-a7 so we can still LTO old bitcode. def : ProcessorModel<"cyclone", CycloneModel, ProcessorFeatures.AppleA7, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index d1ad8b69deae..652d68441cf8 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -273,6 +273,13 @@ void AArch64Subtarget::initializeProperties() { VScaleForTuning = 2; DefaultSVETFOpts = TailFoldingOpts::Simple; break; + case HIP10C: + CacheLineSize = 64; + PrefFunctionAlignment = Align(16); + PrefLoopAlignment = Align(4); + VScaleForTuning = 2; + DefaultSVETFOpts = TailFoldingOpts::Simple; + break; case ThunderX3T110: CacheLineSize = 64; PrefFunctionAlignment = Align(16); diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 47058b5f4578..dd88d5b0f600 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -88,7 +88,8 @@ public: ThunderXT88, ThunderX3T110, TSV110, - HIP09 + HIP09, + HIP10C }; protected: diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index a92b14abf8ba..ea3106bd60c9 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -258,6 +258,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { return StringSwitch(Part) .Case("0xd01", "tsv110") .Case("0xd02", "hip09") + .Case("0xd45", "hip10c") .Default("generic"); if (Implementer == "0x51") // Qualcomm Technologies, Inc. diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll index 56772f6c6049..0b0ae772c11c 100644 --- a/llvm/test/CodeGen/AArch64/cpus.ll +++ b/llvm/test/CodeGen/AArch64/cpus.ll @@ -34,6 +34,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx3t110 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=tsv110 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip09 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip10c 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=ampere1 2>&1 | FileCheck %s diff --git a/llvm/test/CodeGen/AArch64/remat.ll b/llvm/test/CodeGen/AArch64/remat.ll index fa039246c7f5..9c39c660ff44 100644 --- a/llvm/test/CodeGen/AArch64/remat.ll +++ b/llvm/test/CodeGen/AArch64/remat.ll @@ -23,6 +23,7 @@ ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip09 -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=hip10c -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=ampere1 -o - %s | FileCheck %s diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp index cfc41486b173..52d52d786baf 100644 --- a/llvm/unittests/TargetParser/Host.cpp +++ b/llvm/unittests/TargetParser/Host.cpp @@ -253,6 +253,9 @@ CPU part : 0x0a1 EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n" "CPU part : 0xd02"), "hip09"); + EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n" + "CPU part : 0xd45"), + "hip10c"); // Verify A64FX. const std::string A64FXProcCpuInfo = R"( diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 465efa04c3da..35e011ef0717 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1431,6 +1431,18 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FP16FML | AArch64::AEK_SVE | AArch64::AEK_I8MM | AArch64::AEK_F32MM | AArch64::AEK_F64MM | AArch64::AEK_BF16, "8.5-A"), + ARMCPUTestParams( + "hip10c", "armv8.5-a", "crypto-neon-fp-armv8", + AArch64::AEK_F32MM | AArch64::AEK_F64MM | AArch64::AEK_FLAGM | + AArch64::AEK_FP16 | AArch64::AEK_FP16FML | AArch64::AEK_MTE | + AArch64::AEK_PAUTH | AArch64::AEK_PERFMON | AArch64::AEK_PROFILE | + AArch64::AEK_RAND | AArch64::AEK_SB | AArch64::AEK_SHA2 | + AArch64::AEK_SHA3 | AArch64::AEK_SM4 | AArch64::AEK_SSBS | + AArch64::AEK_SVE | AArch64::AEK_BF16 | AArch64::AEK_CRC | + AArch64::AEK_DOTPROD | AArch64::AEK_FP | AArch64::AEK_I8MM | + AArch64::AEK_LSE | AArch64::AEK_RAS | AArch64::AEK_RCPC | + AArch64::AEK_RDM | AArch64::AEK_SIMD, + "8.5-A"), ARMCPUTestParams("a64fx", "armv8.2-a", "crypto-neon-fp-armv8", AArch64::AEK_CRC | AArch64::AEK_AES | AArch64::AEK_SHA2 | AArch64::AEK_FP | @@ -1447,7 +1459,7 @@ INSTANTIATE_TEST_SUITE_P( "8.2-A"))); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 63; +static constexpr unsigned NumAArch64CPUArchs = 64; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List; -- Gitee