diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
index feaa40b14e9d76a1933e1f3d65c3744c224a8d44..93641e983540f01cfc5ab26b57e97051b46984d3 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -82,26 +82,7 @@ define i32 @constraint_m2(i32* %a) nounwind {
   ret i32 %1
 }
 
-define i32 @constraint_m_with_offset(ptr %a) nounwind {
-; RV32I-LABEL: constraint_m_with_offset:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    #APP
-; RV32I-NEXT:    lw a0, 4(a0)
-; RV32I-NEXT:    #NO_APP
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: constraint_m_with_offset:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    #APP
-; RV64I-NEXT:    lw a0, 4(a0)
-; RV64I-NEXT:    #NO_APP
-; RV64I-NEXT:    ret
-  %1 = getelementptr i32, ptr %a, i32 1
-  %2 = tail call i32 asm "lw $0, $1", "=r,*m"(ptr elementtype(i32) %1)
-  ret i32 %2
-}
-
-define void @constraint_o(ptr %a) nounwind {
+define void @constraint_o(i32* %a) nounwind {
 ; RV32I-LABEL: constraint_o:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -117,7 +98,7 @@ define void @constraint_o(ptr %a) nounwind {
   ret void
 }
 
-define i32 @constraint_o2(ptr %a) nounwind {
+define i32 @constraint_o2(i32* %a) nounwind {
 ; RV32I-LABEL: constraint_o2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
@@ -135,25 +116,6 @@ define i32 @constraint_o2(ptr %a) nounwind {
   ret i32 %1
 }
 
-define i32 @constraint_o_with_offset(ptr %a) nounwind {
-; RV32I-LABEL: constraint_o_with_offset:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    #APP
-; RV32I-NEXT:    lw a0, 4(a0)
-; RV32I-NEXT:    #NO_APP
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: constraint_o_with_offset:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    #APP
-; RV64I-NEXT:    lw a0, 4(a0)
-; RV64I-NEXT:    #NO_APP
-; RV64I-NEXT:    ret
-  %1 = getelementptr i32, ptr %a, i32 1
-  %2 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %1)
-  ret i32 %2
-}
-
 define void @constraint_I() nounwind {
 ; RV32I-LABEL: constraint_I:
 ; RV32I:       # %bb.0: