From 0fd83255f7063c62d8bcef0751e2c44c59a47149 Mon Sep 17 00:00:00 2001
From: Cathy Sheng <cathy.sheng@huawei.com>
Date: Wed, 13 Aug 2025 09:46:40 -0400
Subject: [PATCH] [ISEL] Emit rev16 when loading/storing 2 reversed bytes

---
 llvm/lib/Target/AArch64/AArch64InstrInfo.td    | 14 ++++++++++++++
 llvm/test/CodeGen/AArch64/arm64-rev.ll         |  6 ++----
 llvm/test/CodeGen/AArch64/merge-trunc-store.ll | 12 ++++--------
 3 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 8adceb9ffd15..62ac95c68117 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -3543,6 +3543,12 @@ def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32z, "ldrh">;
 // load sign-extended word
 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64z, "ldrsw">;
 
+def : Pat<(srl (bswap (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))), (i64 16)),
+  (REV16Wr (LDRHHui GPR64sp:$Rn, uimm12s2:$offset))>;
+
+def : Pat<(srl (bswap (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))), (i64 16)),
+  (REV16Wr (LDURHHi GPR64sp:$Rn, simm9:$offset))>;
+
 //===----------------------------------------------------------------------===//
 // Store instructions.
 //===----------------------------------------------------------------------===//
@@ -3861,6 +3867,14 @@ defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32z, "sturb",
                          [(truncstorei8 GPR32z:$Rt,
                                   (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
 
+def : Pat<(truncstorei16 (srl (bswap GPR32:$a), (i64 16)),
+                         (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
+  (STRHHui (REV16Wr GPR32:$a), GPR64sp:$Rn, uimm12s2:$offset)>;
+
+def : Pat<(truncstorei16 (srl (bswap GPR32:$a), (i64 16)),
+                         (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
+  (STURHHi (REV16Wr GPR32:$a), GPR64sp:$Rn, uimm12s2:$offset)>;
+
 // Armv8.4 Weaker Release Consistency enhancements
 //         LDAPR & STLR with Immediate Offset instructions
 let Predicates = [HasRCPC_IMMO] in {
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index 90f937afb5a6..b5ee8f4c0cd8 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -60,8 +60,7 @@ define i32 @test_rev_w_srl16_load(ptr %a) {
 ; CHECK-LABEL: test_rev_w_srl16_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ldrh w8, [x0]
-; CHECK-NEXT:    rev w8, w8
-; CHECK-NEXT:    lsr w0, w8, #16
+; CHECK-NEXT:    rev16 w0, w8
 ; CHECK-NEXT:    ret
 ;
 ; GISEL-LABEL: test_rev_w_srl16_load:
@@ -618,8 +617,7 @@ define void @test_rev16_truncstore() {
 ; GISEL-NEXT:  .LBB30_1: // %cleanup
 ; GISEL-NEXT:    // =>This Inner Loop Header: Depth=1
 ; GISEL-NEXT:    ldrh w8, [x8]
-; GISEL-NEXT:    rev w8, w8
-; GISEL-NEXT:    lsr w8, w8, #16
+; GISEL-NEXT:    rev16 w8, w8
 ; GISEL-NEXT:    strh w8, [x8]
 ; GISEL-NEXT:    tbz wzr, #0, .LBB30_1
 ; GISEL-NEXT:  .LBB30_2: // %fail
diff --git a/llvm/test/CodeGen/AArch64/merge-trunc-store.ll b/llvm/test/CodeGen/AArch64/merge-trunc-store.ll
index 0f2cb775e98e..39bb12b7e679 100644
--- a/llvm/test/CodeGen/AArch64/merge-trunc-store.ll
+++ b/llvm/test/CodeGen/AArch64/merge-trunc-store.ll
@@ -10,8 +10,7 @@ define void @le_i16_to_i8(i16 %x, ptr %p0) {
 ;
 ; BE-LABEL: le_i16_to_i8:
 ; BE:       // %bb.0:
-; BE-NEXT:    rev w8, w0
-; BE-NEXT:    lsr w8, w8, #16
+; BE-NEXT:    rev16 w8, w0
 ; BE-NEXT:    strh w8, [x1]
 ; BE-NEXT:    ret
   %sh1 = lshr i16 %x, 8
@@ -31,8 +30,7 @@ define void @le_i16_to_i8_order(i16 %x, ptr %p0) {
 ;
 ; BE-LABEL: le_i16_to_i8_order:
 ; BE:       // %bb.0:
-; BE-NEXT:    rev w8, w0
-; BE-NEXT:    lsr w8, w8, #16
+; BE-NEXT:    rev16 w8, w0
 ; BE-NEXT:    strh w8, [x1]
 ; BE-NEXT:    ret
   %sh1 = lshr i16 %x, 8
@@ -47,8 +45,7 @@ define void @le_i16_to_i8_order(i16 %x, ptr %p0) {
 define void @be_i16_to_i8_offset(i16 %x, ptr %p0) {
 ; LE-LABEL: be_i16_to_i8_offset:
 ; LE:       // %bb.0:
-; LE-NEXT:    rev w8, w0
-; LE-NEXT:    lsr w8, w8, #16
+; LE-NEXT:    rev16 w8, w0
 ; LE-NEXT:    sturh w8, [x1, #11]
 ; LE-NEXT:    ret
 ;
@@ -69,8 +66,7 @@ define void @be_i16_to_i8_offset(i16 %x, ptr %p0) {
 define void @be_i16_to_i8_order(i16 %x, ptr %p0) {
 ; LE-LABEL: be_i16_to_i8_order:
 ; LE:       // %bb.0:
-; LE-NEXT:    rev w8, w0
-; LE-NEXT:    lsr w8, w8, #16
+; LE-NEXT:    rev16 w8, w0
 ; LE-NEXT:    strh w8, [x1]
 ; LE-NEXT:    ret
 ;
-- 
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