From 1ad09007da426e9cd1585babcdd4de25ddfb2f8b Mon Sep 17 00:00:00 2001 From: gubin Date: Thu, 28 Nov 2024 14:39:05 +0800 Subject: [PATCH] target/arm: Fix incorrect aa64_tidcp1 feature check cherry-pick from ee0a2e3c9d2991a11c13ffadb15e4d0add43c257 A typo in the implementation of isar_feature_aa64_tidcp1() means we were checking the field in the wrong ID register, so we might have provided the feature on CPUs that don't have it and not provided it on CPUs that should have it. Correct this bug. Cc: qemu-stable@nongnu.org Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240123160333.958841-1-peter.maydell@linaro.org Signed-off-by: gubin --- target/arm/cpu-features.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 954d358268..165a497f7b 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -771,7 +771,7 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0; + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0; } static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) -- Gitee