diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index ed220d5d4070db0c46162ace03f92074bbb04f7b..5ed23e627a46a7ec24cedf182c3c645c38301f36 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -64,46 +64,62 @@ * ACPI spec, Revision 6.3 * 5.2.29.2 Cache Type Structure (Type 1) */ -static void build_cache_hierarchy_node(GArray *tbl, uint32_t next_level, - uint32_t cache_type) +static void build_cache_hierarchy_node(MachineState *ms, GArray *tbl, + uint32_t next_level, uint32_t cache_type) { build_append_byte(tbl, 1); build_append_byte(tbl, 24); build_append_int_noprefix(tbl, 0, 2); build_append_int_noprefix(tbl, 127, 4); build_append_int_noprefix(tbl, next_level, 4); + uint64_t cache_size; switch (cache_type) { case ARM_L1D_CACHE: /* L1 dcache info */ - build_append_int_noprefix(tbl, ARM_L1DCACHE_SIZE, 4); + cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L1D); + build_append_int_noprefix(tbl, + cache_size > 0 ? cache_size : ARM_L1DCACHE_SIZE, + 4); build_append_int_noprefix(tbl, ARM_L1DCACHE_SETS, 4); build_append_byte(tbl, ARM_L1DCACHE_ASSOCIATIVITY); build_append_byte(tbl, ARM_L1DCACHE_ATTRIBUTES); build_append_int_noprefix(tbl, ARM_L1DCACHE_LINE_SIZE, 2); break; case ARM_L1I_CACHE: /* L1 icache info */ - build_append_int_noprefix(tbl, ARM_L1ICACHE_SIZE, 4); + cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L1I); + build_append_int_noprefix(tbl, + cache_size > 0 ? cache_size : ARM_L1ICACHE_SIZE, + 4); build_append_int_noprefix(tbl, ARM_L1ICACHE_SETS, 4); build_append_byte(tbl, ARM_L1ICACHE_ASSOCIATIVITY); build_append_byte(tbl, ARM_L1ICACHE_ATTRIBUTES); build_append_int_noprefix(tbl, ARM_L1ICACHE_LINE_SIZE, 2); break; case ARM_L1_CACHE: /* L1 cache info */ - build_append_int_noprefix(tbl, ARM_L1CACHE_SIZE, 4); + cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L1); + build_append_int_noprefix(tbl, + cache_size > 0 ? cache_size : ARM_L1CACHE_SIZE, + 4); build_append_int_noprefix(tbl, ARM_L1CACHE_SETS, 4); build_append_byte(tbl, ARM_L1CACHE_ASSOCIATIVITY); build_append_byte(tbl, ARM_L1CACHE_ATTRIBUTES); build_append_int_noprefix(tbl, ARM_L1CACHE_LINE_SIZE, 2); break; case ARM_L2_CACHE: /* L2 cache info */ - build_append_int_noprefix(tbl, ARM_L2CACHE_SIZE, 4); + cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L2); + build_append_int_noprefix(tbl, + cache_size > 0 ? cache_size : ARM_L2CACHE_SIZE, + 4); build_append_int_noprefix(tbl, ARM_L2CACHE_SETS, 4); build_append_byte(tbl, ARM_L2CACHE_ASSOCIATIVITY); build_append_byte(tbl, ARM_L2CACHE_ATTRIBUTES); build_append_int_noprefix(tbl, ARM_L2CACHE_LINE_SIZE, 2); break; case ARM_L3_CACHE: /* L3 cache info */ - build_append_int_noprefix(tbl, ARM_L3CACHE_SIZE, 4); + cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L3); + build_append_int_noprefix(tbl, + cache_size > 0 ? cache_size : ARM_L3CACHE_SIZE, + 4); build_append_int_noprefix(tbl, ARM_L3CACHE_SETS, 4); build_append_byte(tbl, ARM_L3CACHE_ASSOCIATIVITY); build_append_byte(tbl, ARM_L3CACHE_ATTRIBUTES); @@ -140,7 +156,7 @@ static void build_pptt_arm(GArray *table_data, BIOSLinker *linker, MachineState for (socket = 0; socket < ms->smp.sockets; socket++) { uint32_t l3_cache_offset = table_data->len - pptt_start; - build_cache_hierarchy_node(table_data, 0, ARM_L3_CACHE); + build_cache_hierarchy_node(ms, table_data, 0, ARM_L3_CACHE); g_queue_push_tail(list, GUINT_TO_POINTER(table_data->len - pptt_start)); @@ -179,16 +195,16 @@ static void build_pptt_arm(GArray *table_data, BIOSLinker *linker, MachineState for (core = 0; core < ms->smp.cores; core++) { uint32_t priv_rsrc[3] = {}; priv_rsrc[0] = table_data->len - pptt_start; /* L2 cache offset */ - build_cache_hierarchy_node(table_data, 0, ARM_L2_CACHE); + build_cache_hierarchy_node(ms, table_data, 0, ARM_L2_CACHE); if (unified_l1) { priv_rsrc[1] = table_data->len - pptt_start; /* L1 cache offset */ - build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1_CACHE); + build_cache_hierarchy_node(ms, table_data, priv_rsrc[0], ARM_L1_CACHE); } else { priv_rsrc[1] = table_data->len - pptt_start; /* L1 dcache offset */ - build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1D_CACHE); + build_cache_hierarchy_node(ms, table_data, priv_rsrc[0], ARM_L1D_CACHE); priv_rsrc[2] = table_data->len - pptt_start; /* L1 icache offset */ - build_cache_hierarchy_node(table_data, priv_rsrc[0], ARM_L1I_CACHE); + build_cache_hierarchy_node(ms, table_data, priv_rsrc[0], ARM_L1I_CACHE); } if (ms->smp.threads > 1) { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d31675b0fda51960151078924e57fe8df8865152..c581f65a22de60ffcf56985423d7ebc47df87e04 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -408,6 +408,7 @@ static void fdt_add_l3cache_nodes(const VirtMachineState *vms) const MachineState *ms = MACHINE(vms); int cpus_per_socket = ms->smp.clusters * ms->smp.cores * ms->smp.threads; int sockets = (ms->smp.cpus + cpus_per_socket - 1) / cpus_per_socket; + uint64_t cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L3); for (i = 0; i < sockets; i++) { char *nodename = g_strdup_printf("/cpus/l3-cache%d", i); @@ -416,7 +417,8 @@ static void fdt_add_l3cache_nodes(const VirtMachineState *vms) qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cache"); qemu_fdt_setprop_string(ms->fdt, nodename, "cache-unified", "true"); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-level", 3); - qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", ARM_L3CACHE_SIZE); + qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", + cache_size > 0 ? cache_size : ARM_L3CACHE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", ARM_L3CACHE_LINE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", ARM_L3CACHE_SETS); @@ -431,6 +433,7 @@ static void fdt_add_l2cache_nodes(const VirtMachineState *vms) const MachineState *ms = MACHINE(vms); int cpus_per_socket = ms->smp.clusters * ms->smp.cores * ms->smp.threads; int cpu; + uint64_t cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L2); for (cpu = 0; cpu < ms->smp.cpus; cpu++) { char *next_path = g_strdup_printf("/cpus/l3-cache%d", @@ -440,7 +443,8 @@ static void fdt_add_l2cache_nodes(const VirtMachineState *vms) qemu_fdt_add_subnode(ms->fdt, nodename); qemu_fdt_setprop_string(ms->fdt, nodename, "cache-unified", "true"); qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cache"); - qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", ARM_L2CACHE_SIZE); + qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", + cache_size > 0 ? cache_size : ARM_L2CACHE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", ARM_L2CACHE_LINE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", ARM_L2CACHE_SETS); @@ -460,21 +464,25 @@ static void fdt_add_l1cache_prop(const VirtMachineState *vms, const MachineState *ms = MACHINE(vms); char *next_path = g_strdup_printf("/cpus/l2-cache%d", cpu); bool unified_l1 = cpu_l1_cache_unified(0); + uint64_t l1d_cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L1D); + uint64_t l1i_cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L1I); + uint64_t l1_cache_size = machine_get_cache_size(ms, CACHE_LEVEL_AND_TYPE_L1); if (unified_l1) { - qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", ARM_L1CACHE_SIZE); + qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-size", + l1_cache_size > 0 ? l1_cache_size : ARM_L1CACHE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-line-size", ARM_L1CACHE_LINE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "cache-sets", ARM_L1CACHE_SETS); } else { qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-size", - ARM_L1DCACHE_SIZE); + l1d_cache_size > 0 ? l1d_cache_size : ARM_L1DCACHE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-line-size", ARM_L1DCACHE_LINE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "d-cache-sets", ARM_L1DCACHE_SETS); qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-size", - ARM_L1ICACHE_SIZE); + l1i_cache_size > 0 ? l1i_cache_size : ARM_L1ICACHE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-line-size", ARM_L1ICACHE_LINE_SIZE); qemu_fdt_setprop_cell(ms->fdt, nodename, "i-cache-sets", diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c index b39ed21e65406563a012408240af228be4d74981..47922ec4aa8717e63823243e10b15412ea987fbf 100644 --- a/hw/core/machine-smp.c +++ b/hw/core/machine-smp.c @@ -193,3 +193,41 @@ void machine_parse_smp_config(MachineState *ms, return; } } + +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp) +{ + const SmpCachePropertiesList *node; + DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); + + bitmap_zero(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); + for (node = caches; node; node = node->next) { + /* Prohibit users from repeating settings. */ + if (test_bit(node->value->cache, caches_bitmap)) { + error_setg(errp, + "Invalid cache properties: %s. " + "The cache properties are duplicated", + CacheLevelAndType_str(node->value->cache)); + return false; + } + + machine_set_cache_size(ms, node->value->cache, + node->value->size); + set_bit(node->value->cache, caches_bitmap); + } + + return true; +} + +uint64_t machine_get_cache_size(const MachineState *ms, + CacheLevelAndType cache) +{ + return ms->smp_cache.props[cache].size; +} + +void machine_set_cache_size(MachineState *ms, CacheLevelAndType cache, + uint64_t size) +{ + ms->smp_cache.props[cache].size = size; +} \ No newline at end of file diff --git a/hw/core/machine.c b/hw/core/machine.c index cb539104a1292da1da24564d9411cc721f8da828..35a7c1d328a572d86afc9288ffb03a0b65f6a3b8 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -777,6 +777,40 @@ static void machine_set_smp(Object *obj, Visitor *v, const char *name, machine_parse_smp_config(ms, config, errp); } +static void machine_get_smp_cache(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MachineState *ms = MACHINE(obj); + SmpCache *cache = &ms->smp_cache; + SmpCachePropertiesList *head = NULL; + SmpCachePropertiesList **tail = &head; + + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + SmpCacheProperties *node = g_new(SmpCacheProperties, 1); + + node->cache = cache->props[i].cache; + node->size = cache->props[i].size; + QAPI_LIST_APPEND(tail, node); + } + + visit_type_SmpCachePropertiesList(v, name, &head, errp); + qapi_free_SmpCachePropertiesList(head); +} + +static void machine_set_smp_cache(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + MachineState *ms = MACHINE(obj); + SmpCachePropertiesList *caches; + + if (!visit_type_SmpCachePropertiesList(v, name, &caches, errp)) { + return; + } + + machine_parse_smp_cache(ms, caches, errp); + qapi_free_SmpCachePropertiesList(caches); +} + static void machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -821,6 +855,11 @@ static void machine_class_init(ObjectClass *oc, void *data) object_class_property_set_description(oc, "smp", "CPU topology"); + object_class_property_add(oc, "smp-cache", "SmpCachePropertiesWrapper", + machine_get_smp_cache, machine_set_smp_cache, NULL, NULL); + object_class_property_set_description(oc, "smp-cache", + "Cache properties list for SMP machine"); + object_class_property_add(oc, "phandle-start", "int", machine_get_phandle_start, machine_set_phandle_start, NULL, NULL); @@ -948,6 +987,11 @@ static void machine_initfn(Object *obj) ms->smp.clusters = 1; ms->smp.cores = 1; ms->smp.threads = 1; + + for (int i = 0; i < CACHE_LEVEL_AND_TYPE__MAX; i++) { + ms->smp_cache.props[i].cache = (CacheLevelAndType)i; + ms->smp_cache.props[i].size = 0; + } } static void machine_finalize(Object *obj) diff --git a/include/hw/boards.h b/include/hw/boards.h index f49a2578ead07af604ca40f7aafab510568e39a7..f7ba05c56adfacf8f6c01c1b6bc4d94494ace4be 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -36,6 +36,13 @@ void machine_set_cpu_numa_node(MachineState *machine, Error **errp); void machine_parse_smp_config(MachineState *ms, const SMPConfiguration *config, Error **errp); +bool machine_parse_smp_cache(MachineState *ms, + const SmpCachePropertiesList *caches, + Error **errp); +uint64_t machine_get_cache_size(const MachineState *ms, + CacheLevelAndType cache); +void machine_set_cache_size(MachineState *ms, CacheLevelAndType cache, + uint64_t size); /** * machine_class_allow_dynamic_sysbus_dev: Add type to list of valid devices @@ -316,6 +323,10 @@ typedef struct CpuTopology { unsigned int max_cpus; } CpuTopology; +typedef struct SmpCache { + SmpCacheProperties props[CACHE_LEVEL_AND_TYPE__MAX]; +} SmpCache; + /** * MachineState: */ @@ -359,6 +370,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + SmpCache smp_cache; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; diff --git a/qapi/machine.json b/qapi/machine.json index 31b0350b99342b8c489b5f1daa8da1fa75828797..c12fa1e39930397180f50a1e2caf35eadf2905a5 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1570,3 +1570,52 @@ { 'command': 'x-query-usb', 'returns': 'HumanReadableText', 'features': [ 'unstable' ] } + +## +# @CacheLevelAndType: +# +# Caches a system may have. The enumeration value here is the +# combination of cache level and cache type. +# +# @l1d: L1 data cache. +# +# @l1i: L1 instruction cache. +# +# @l1: L1 (unified) cache. +# +# @l2: L2 (unified) cache. +# +# @l3: L3 (unified) cache +# +# Since: 6.2 +## +{ 'enum': 'CacheLevelAndType', + 'data': [ 'l1d', 'l1i', 'l1', 'l2', 'l3' ] } + +## +# @SmpCacheProperties: +# +# Cache information for SMP system. +# +# @cache: Cache name, which is the combination of cache level and cache type. +# +# @size: Cache size in units of Byte. +# +# Since: 6.2 +## +{ 'struct': 'SmpCacheProperties', + 'data': { + 'cache': 'CacheLevelAndType', + 'size': 'uint64' } } + +## +# @SmpCachePropertiesWrapper: +# +# List wrapper of SmpCacheProperties. +# +# @caches: the list of SmpCacheProperties. +# +# Since 6.2 +## +{ 'struct': 'SmpCachePropertiesWrapper', + 'data': { 'caches': ['SmpCacheProperties'] } }