From b21cd8b017c68ff4749bf4a2f38e340846cf8299 Mon Sep 17 00:00:00 2001 From: lijunwei Date: Wed, 12 Jul 2023 09:57:29 +0800 Subject: [PATCH 1/4] Update Phytium's cpu model --- target/arm/cpu64.c | 55 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3ec788fc29..531d8bc8e4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -700,7 +700,6 @@ static Property arm_cpu_pauth_impdef_property = static void aarch64_max_ft2000plus_initfn(Object *obj) { - ARMCPU *cpu = ARM_CPU(obj); if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); @@ -708,7 +707,33 @@ static void aarch64_max_ft2000plus_initfn(Object *obj) } else { aarch64_a72_initfn(obj); cpu->midr = 0x70186622; + uint64_t t; + aarch64_a57_initfn(obj); + + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating + * "v7 or later, check ID registers to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0x70); + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 0x662); + t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0x1); + t = FIELD_DP64(t, MIDR_EL1, REVISION, 2); + cpu->midr = t; } + + aarch64_add_sve_properties(obj); + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, + cpu_max_set_sve_max_vq, NULL, NULL); + } static void aarch64_max_tengyun_s2500_initfn(Object *obj) @@ -717,11 +742,33 @@ static void aarch64_max_tengyun_s2500_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); - kvm_arm_add_vcpu_properties(obj); } else { - aarch64_a72_initfn(obj); - cpu->midr = 0x70186632; + uint64_t t; + aarch64_a57_initfn(obj); + + /* + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating + * "v7 or later, check ID registers to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0x70); + t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 0x663); + t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0x1); + t = FIELD_DP64(t, MIDR_EL1, REVISION, 3); + cpu->midr = t; } + + aarch64_add_sve_properties(obj); + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq, + cpu_max_set_sve_max_vq, NULL, NULL); } /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); -- Gitee From 96f333f95ecd493f0de4ef10e400e37a7983d25a Mon Sep 17 00:00:00 2001 From: lijunwei Date: Mon, 17 Jul 2023 00:55:04 +0000 Subject: [PATCH 2/4] update target/arm/cpu64.c. Signed-off-by: lijunwei --- target/arm/cpu64.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 531d8bc8e4..18fbe11716 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -705,8 +705,6 @@ static void aarch64_max_ft2000plus_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); kvm_arm_add_vcpu_properties(obj); } else { - aarch64_a72_initfn(obj); - cpu->midr = 0x70186622; uint64_t t; aarch64_a57_initfn(obj); -- Gitee From 38ffb7a476407e9b69f505c72b10c0e0636df6d8 Mon Sep 17 00:00:00 2001 From: lijunwei Date: Mon, 17 Jul 2023 00:57:33 +0000 Subject: [PATCH 3/4] update target/arm/cpu64.c. Signed-off-by: lijunwei --- target/arm/cpu64.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 18fbe11716..a0ce1100a3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -703,7 +703,6 @@ static void aarch64_max_ft2000plus_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); - kvm_arm_add_vcpu_properties(obj); } else { uint64_t t; aarch64_a57_initfn(obj); -- Gitee From e9dd88ffcb5df083b074c92cbdbf74bb66b1e1ca Mon Sep 17 00:00:00 2001 From: lijunwei Date: Thu, 20 Jul 2023 03:16:42 +0000 Subject: [PATCH 4/4] update target/arm/cpu64.c. Signed-off-by: lijunwei --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a0ce1100a3..5564dd10d7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -700,6 +700,7 @@ static Property arm_cpu_pauth_impdef_property = static void aarch64_max_ft2000plus_initfn(Object *obj) { + ARMCPU *cpu = ARM_CPU(obj); if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); -- Gitee