From 968073d72e780de93f81d4599c8a723d38c6175b Mon Sep 17 00:00:00 2001
From: wangjinlei <wangjinlei_yewu@cmss.chinamobile.com>
Date: Fri, 22 Sep 2023 14:39:51 +0800
Subject: [PATCH] target/i386: Add few security fix bits in ARCH_CAPABILITIES
 into SapphireRapids CPU model

SapphireRapids has bit 13, 14 and 15 of MSR_IA32_ARCH_CAPABILITIES
enabled, which are related to some security fixes.

Add version 2 of SapphireRapids CPU model with those bits enabled also.

cherry-pick form 3baf7ae63505eb1652d1e52d65798307fead8539

Signed-off-by: Lei Wang <lei4.wang@intel.com>
Signed-off-by: Tao Su <tao1.su@linux.intel.com>
Message-ID: <20230706054949.66556-6-tao1.su@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/cpu.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 66b5eaa14e..653b781f4e 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3655,8 +3655,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "Intel Xeon Processor (SapphireRapids)",
         .versions = (X86CPUVersionDefinition[]) {
             { .version = 1 },
-            { /* end of list */ },
-        },
+            {
+                .version = 2,
+                .props = (PropValue[]) {
+                    { "sbdr-ssdp-no", "on" },
+                    { "fbsdp-no", "on" },
+                    { "psdp-no", "on" },
+                    { /* end of list */ }
+                }
+            },
+            { /* end of list */ }
+        }
     },
     {
         .name = "Denverton",
-- 
Gitee