diff --git a/arch/arm/boot/dts/bcm2710.dtsi b/arch/arm/boot/dts/bcm2710.dtsi index 5c45ded273fe3e6e5fbea9d042c29e3a18bf541e..a2e084dc3867b527c0ea7344eb6dbaabe50f1b70 100644 --- a/arch/arm/boot/dts/bcm2710.dtsi +++ b/arch/arm/boot/dts/bcm2710.dtsi @@ -5,11 +5,7 @@ compatible = "brcm,bcm2837", "brcm,bcm2836"; arm-pmu { -#ifdef RPI364 - compatible = "arm,armv8-pmuv3", "arm,cortex-a7-pmu"; -#else - compatible = "arm,cortex-a7-pmu"; -#endif + compatible = "arm,cortex-a53-pmu", "arm,cortex-a7-pmu"; }; soc { diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index fabd02e5863db72804b898358a60c29a11206ad0..42259dbf39191b9c1fd8cdd73bda2dcaf8dbc18a 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -31,6 +31,30 @@ /delete-property/ intc; ethernet0 = &genet; pcie0 = &pcie_0; + emmc2bus = &emmc2bus; + }; +}; + +/delete-node/ &emmc2; + +/ { + emmc2bus: emmc2bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; + dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x3c000000>; + + emmc2: emmc2@7e340000 { + compatible = "brcm,bcm2711-emmc2"; + status = "okay"; + interrupts = ; + clocks = <&clocks BCM2711_CLOCK_EMMC2>; + reg = <0x0 0x7e340000 0x100>; + vqmmc-supply = <&sd_io_1v8_reg>; + broken-cd; + }; }; }; @@ -341,5 +365,7 @@ eth_led1 = <&phy1>,"led-modes:4"; sd_poll_once = <&emmc2>, "non-removable?"; + spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, + <&spi0>, "dmas:8=", <&dma40>; }; }; diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi index 5f837e84132cdee1fa99a91ee7d85eb6e60ef6cc..36d250d7053bbff935302a77b74723ce894a9a9f 100644 --- a/arch/arm/boot/dts/bcm2838.dtsi +++ b/arch/arm/boot/dts/bcm2838.dtsi @@ -224,7 +224,7 @@ }; arm-pmu { - compatible = "arm,cortex-a72-pmu"; + compatible = "arm,cortex-a72-pmu", "arm,cortex-a15-pmu"; interrupts = , , , @@ -316,7 +316,9 @@ <0x0 0x40000000 0x0 0xff800000 0x00800000>, <0x6 0x00000000 0x6 0x00000000 0x40000000>, <0x0 0x00000000 0x0 0x00000000 0xfc000000>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>, + <0x1 0x00000000 0x1 0x00000000 0x80000000>, + <0x1 0x80000000 0x1 0x80000000 0x80000000>; pcie_0: pcie@7d500000 { reg = <0x0 0x7d500000 0x9310>, diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile index 85d8249a2f20123fb7741dced3adb9a4ac2287f9..9863b50ad6da2c7f4feb645bacc5f03ab4aa9403 100644 --- a/arch/arm/boot/dts/overlays/Makefile +++ b/arch/arm/boot/dts/overlays/Makefile @@ -20,6 +20,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \ applepi-dac.dtbo \ at86rf233.dtbo \ audioinjector-addons.dtbo \ + audioinjector-isolated-soundcard.dtbo \ audioinjector-ultra.dtbo \ audioinjector-wm8731-audio.dtbo \ audiosense-pi.dtbo \ @@ -143,6 +144,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \ rra-digidac1-wm8741-audio.dtbo \ sc16is750-i2c.dtbo \ sc16is752-i2c.dtbo \ + sc16is752-spi0.dtbo \ sc16is752-spi1.dtbo \ sdhost.dtbo \ sdio.dtbo \ diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index 62ad35f78badaf5076381afa341f1d582d1ff6cf..aced2cd3c08440077188882bfed0473e25ebc74b 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -159,6 +159,10 @@ Params: spi Set to "on" to enable the spi interfaces (default "off") + spi_dma4 Use to enable 40-bit DMA on spi interfaces + (the assigned value doesn't matter) + (2711 only) + random Set to "on" to enable the hardware random number generator (default "on") @@ -505,6 +509,12 @@ Params: non-stop-clocks Keeps the clocks running even when the stream is paused or stopped (default off) +Name: audioinjector-isolated-soundcard +Info: Configures the audioinjector.net isolated soundcard +Load: dtoverlay=audioinjector-isolated-soundcard +Params: + + Name: audioinjector-ultra Info: Configures the audioinjector.net ultra soundcard Load: dtoverlay=audioinjector-ultra @@ -832,6 +842,7 @@ Params: gpiopin GPIO for signalling (default 26) Name: gpio-shutdown Info: Initiates a shutdown when GPIO pin changes. The given GPIO pin is configured as an input key that generates KEY_POWER events. + This event is handled by systemd-logind by initiating a shutdown. Systemd versions older than 225 need an udev rule enable listening to the input device: @@ -840,13 +851,41 @@ Info: Initiates a shutdown when GPIO pin changes. The given GPIO pin SUBSYSTEMS=="platform", DRIVERS=="gpio-keys", \ ATTRS{keys}=="116", TAG+="power-switch" + Alternatively this event can be handled also on systems without + systemd, just by traditional SysV init daemon. KEY_POWER event + (keycode 116) needs to be mapped to KeyboardSignal on console + and then kb::kbrequest inittab action which is triggered by + KeyboardSignal from console can be configured to issue system + shutdown. Steps for this configuration are: + + Add following lines to the /etc/console-setup/remap.inc file: + + # Key Power as special keypress + keycode 116 = KeyboardSignal + + Then add following lines to /etc/inittab file: + + # Action on special keypress (Key Power) + kb::kbrequest:/sbin/shutdown -t1 -a -h -P now + + And finally reload configuration by calling following commands: + + # dpkg-reconfigure console-setup + # service console-setup reload + # init q + This overlay only handles shutdown. After shutdown, the system can be powered up again by driving GPIO3 low. The default configuration uses GPIO3 with a pullup, so if you connect a button between GPIO3 and GND (pin 5 and 6 on the 40-pin header), - you get a shutdown and power-up button. + you get a shutdown and power-up button. Please note that + Raspberry Pi 1 Model B rev 1 uses GPIO1 instead of GPIO3. Load: dtoverlay=gpio-shutdown,= Params: gpio_pin GPIO pin to trigger on (default 3) + For Raspberry Pi 1 Model B rev 1 set this + explicitly to value 1, e.g.: + + dtoverlay=gpio-shutdown,gpio_pin=1 active_low When this is 1 (active low), a falling edge generates a key down event and a @@ -858,7 +897,8 @@ Params: gpio_pin GPIO pin to trigger on (default 3) Default is "up". Note that the default pin (GPIO3) has an - external pullup. + external pullup. Same applies for GPIO1 + on Raspberry Pi 1 Model B rev 1. debounce Specify the debounce interval in milliseconds (default 100) @@ -2034,12 +2074,20 @@ Name: rpi-poe Info: Raspberry Pi PoE HAT fan Load: dtoverlay=rpi-poe,[=] Params: poe_fan_temp0 Temperature (in millicelcius) at which the fan - turns on (default 50000) + turns on (default 40000) poe_fan_temp0_hyst Temperature delta (in millicelcius) at which - the fan turns off (default 5000) + the fan turns off (default 2000) poe_fan_temp1 Temperature (in millicelcius) at which the fan - speeds up (default 55000) + speeds up (default 45000) poe_fan_temp1_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp2 Temperature (in millicelcius) at which the fan + speeds up (default 50000) + poe_fan_temp2_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp3 Temperature (in millicelcius) at which the fan + speeds up (default 55000) + poe_fan_temp3_hyst Temperature delta (in millicelcius) at which the fan slows down (default 5000) @@ -2087,6 +2135,14 @@ Params: int_pin GPIO used for IRQ (default 24) xtal On-board crystal frequency (default 14745600) +Name: sc16is752-spi0 +Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface + Enables the chip on SPI0. +Load: dtoverlay=sc16is752-spi0,= +Params: int_pin GPIO used for IRQ (default 24) + xtal On-board crystal frequency (default 14745600) + + Name: sc16is752-spi1 Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface Enables the chip on SPI1. @@ -2095,6 +2151,7 @@ Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface Load: dtoverlay=sc16is752-spi1,= Params: int_pin GPIO used for IRQ (default 24) + xtal On-board crystal frequency (default 14745600) Name: sdhost diff --git a/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts new file mode 100644 index 0000000000000000000000000000000000000000..afc51108e5c83e6629464a713d6bc6d7247ec469 --- /dev/null +++ b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts @@ -0,0 +1,55 @@ +// Definitions for audioinjector.net audio isolated soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + cs4272_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cs4272: cs4272@10 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs4271"; + reg = <0x10>; + reset-gpio = <&gpio 5 0>; + clocks = <&cs4272_mclk>; + clock-names = "mclk"; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + snd: __overlay__ { + compatible = "ai,audioinjector-isolated-soundcard"; + mute-gpios = <&gpio 17 0>; + i2s-controller = <&i2s>; + codec = <&cs4272>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/balena-fin-overlay.dts b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts index 249c8202b2ed4ed4031994cd84789835ed53ab18..e7ead7cdf5f5e1267709e071daaf4899e9266922 100644 --- a/arch/arm/boot/dts/overlays/balena-fin-overlay.dts +++ b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts @@ -1,6 +1,8 @@ /dts-v1/; /plugin/; +#include + /{ compatible = "brcm,bcm2835"; @@ -48,7 +50,8 @@ i2c_soft: i2c@0 { compatible = "i2c-gpio"; - gpios = <&gpio 43 0 /* sda */ &gpio 42 0 /* scl */>; + gpios = <&gpio 43 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 42 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */>; i2c-gpio,delay-us = <5>; i2c-gpio,scl-open-drain; i2c-gpio,sda-open-drain; diff --git a/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts index db07ba67781d71011c665ae653ed3c3a2b22df92..0a27595143ec108f8ea3a38bbba0b79d775cb6ea 100644 --- a/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts +++ b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts @@ -4,7 +4,9 @@ // This overlay sets up an input device that generates KEY_POWER events // when a given GPIO pin changes. It defaults to using GPIO3, which can -// also be used to wake up (start) the Rpi again after shutdown. Since +// also be used to wake up (start) the Rpi again after shutdown. +// Raspberry Pi 1 Model B rev 1 can be wake up only by GPIO1 pin, so for +// these boards change default GPIO pin to 1 via gpio_pin parameter. Since // wakeup is active-low, this defaults to active-low with a pullup // enabled, but all of this can be changed using overlay parameters (but // note that GPIO3 has an external pullup on at least some boards). @@ -71,7 +73,7 @@ // Allow changing the internal pullup/down state. 0 = none, 1 = pulldown, 2 = pullup // Note that GPIO3 and GPIO2 are the I2c pins and have an external pullup (at least - // on some boards). + // on some boards). Same applies for GPIO1 on Raspberry Pi 1 Model B rev 1. gpio_pull = <&pin_state>,"brcm,pull:0"; // Allow setting the active_low flag. 0 = active high, 1 = active low diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts index 39e7bc5fa9d8849f110d275dfd43806e5218e122..63231b5d7c0c114d7de53fc460e0637c24855699 100644 --- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts @@ -2,6 +2,8 @@ /dts-v1/; /plugin/; +#include + / { compatible = "brcm,bcm2835"; @@ -12,8 +14,8 @@ i2c_gpio: i2c@0 { reg = <0xffffffff>; compatible = "i2c-gpio"; - gpios = <&gpio 23 0 /* sda */ - &gpio 24 0 /* scl */ + gpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */ >; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts index 44df77459520b3c3862eedc6faa40546c0f80c86..2ce968a5b2d6053f8e52f7234821b894bf913fe9 100644 --- a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts @@ -3,6 +3,8 @@ /dts-v1/; /plugin/; +#include + / { compatible = "brcm,bcm2835"; @@ -11,8 +13,8 @@ __overlay__ { i2c_gpio: i2c-gpio-rtc@0 { compatible = "i2c-gpio"; - gpios = <&gpio 23 0 /* sda */ - &gpio 24 0 /* scl */ + gpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */ >; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; @@ -230,7 +232,7 @@ trickle-diode-type = <&abx80x>,"abracon,tc-diode"; trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0", - <&abx80x>,"abracon,tc-resistor", + <&abx80x>,"abracon,tc-resistor:0", <&rv3028>,"trickle-resistor-ohms:0"; backup-switchover-mode = <&rv3028>,"backup-switchover-mode:0"; wakeup-source = <&ds1339>,"wakeup-source?", diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts index 5df390b52a7bb352353c8f8de1c313e5d032b63b..24c86974b0dbd843dee246ea4eaf3cdb4ed121b9 100644 --- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts @@ -229,7 +229,7 @@ <&m41t62>, "reg:0"; trickle-diode-type = <&abx80x>,"abracon,tc-diode"; trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0", - <&abx80x>,"abracon,tc-resistor", + <&abx80x>,"abracon,tc-resistor:0", <&rv3028>,"trickle-resistor-ohms:0"; backup-switchover-mode = <&rv3028>,"backup-switchover-mode:0"; wakeup-source = <&ds1339>,"wakeup-source?", diff --git a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts index 21f8fe6f12295e30294bf9189a418db2a155ff39..544038b614e1075ba4ba7cfc95c69086da3eda76 100644 --- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts +++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts @@ -14,9 +14,9 @@ compatible = "raspberrypi,rpi-poe-fan"; firmware = <&firmware>; cooling-min-state = <0>; - cooling-max-state = <2>; + cooling-max-state = <4>; #cooling-cells = <2>; - cooling-levels = <0 150 255>; + cooling-levels = <0 31 63 150 255>; status = "okay"; }; }; @@ -27,12 +27,21 @@ __overlay__ { trips { trip0: trip0 { - temperature = <50000>; - hysteresis = <5000>; + temperature = <40000>; + hysteresis = <2000>; type = "active"; }; trip1: trip1 { - + temperature = <45000>; + hysteresis = <2000>; + type = "active"; + }; + trip2: trip2 { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + trip3: trip3 { temperature = <55000>; hysteresis = <5000>; type = "active"; @@ -47,6 +56,14 @@ trip = <&trip1>; cooling-device = <&fan0 1 2>; }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + }; }; }; }; @@ -58,6 +75,10 @@ poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; poe_fan_temp1 = <&trip1>,"temperature:0"; poe_fan_temp1_hyst = <&trip1>,"hysteresis:0"; + poe_fan_temp2 = <&trip2>,"temperature:0"; + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; }; }; @@ -66,5 +87,9 @@ poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; poe_fan_temp1 = <&trip1>,"temperature:0"; poe_fan_temp1_hyst = <&trip1>,"hysteresis:0"; + poe_fan_temp2 = <&trip2>,"temperature:0"; + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; }; }; diff --git a/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts new file mode 100644 index 0000000000000000000000000000000000000000..ccce7ad599bc14302dd4cca3ee3e3cb7a78c105c --- /dev/null +++ b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts @@ -0,0 +1,44 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sc16is752: sc16is752@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ + #gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <4000000>; + + sc16is752_clk: sc16is752_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; + }; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + __overrides__ { + int_pin = <&sc16is752>,"interrupts:0"; + xtal = <&sc16is752_clk>, "clock-frequency:0"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts index 4e33b14afc78498760a1239237753df9a2dbf496..131d3ab43d3a5f8557e3e694d195df1e2dc04f38 100644 --- a/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts +++ b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts @@ -56,6 +56,7 @@ }; __overrides__ { - int_pin = <&sc16is752>,"interrupts:0"; + int_pin = <&sc16is752>,"interrupts:0"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; }; }; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig index 0683026145eb1c01b86d25dc3b871487cdebe566..4fd6bcc8b2bb4db6c6e123289b3ee058aa84d6ec 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig @@ -995,6 +995,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -1012,8 +1013,8 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm/configs/bcm2711_defconfig b/arch/arm/configs/bcm2711_defconfig index 67f2ba9a773ca7241d8ac108bd006ce0a0e35655..4d3edbacb8fc1a900cb5020729b4638de589d2dd 100644 --- a/arch/arm/configs/bcm2711_defconfig +++ b/arch/arm/configs/bcm2711_defconfig @@ -1009,6 +1009,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -1026,8 +1027,8 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig index ea5dede6bfaae4b6957eb590ffe9344ea81f0a1e..65b0a035a0f2846d49feabc05e4e4ecb69f0a7aa 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -987,6 +987,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -1004,8 +1005,8 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts index 116cdbf94b9b0d948dc116307a3720f217484a1c..36ecea71f0ef9925b249acb275bc105eb82de574 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-2-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts index d9242ff77079c41243a298c1034d2c8685f5db47..22fc6a82f2a960b50a1ea58e0f770a71342c30d3 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts index deb33441da95220db0ed672e41639626fba682a5..4cacc5b72ae3cdb918f6dc52ce6ac8093e5da98a 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts index 1c2560017c02f3afd87f5a45e06f0b245e085eb8..e1e13784cff6335c2bf275484e19a15f53c2d89d 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-cm3.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts index 1fd86f81f5426f1825b9427e2c7e70a02d477940..bf69a4b0b172a19cd25832f07e409e372a0267a2 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2711-rpi-4-b.dts" diff --git a/arch/arm64/configs/bcm2711_defconfig b/arch/arm64/configs/bcm2711_defconfig index 310eeca672b08a2e26701879173eb9ce90c432c1..a876f527b195666bb7300e873e2c8d5a7725dac5 100644 --- a/arch/arm64/configs/bcm2711_defconfig +++ b/arch/arm64/configs/bcm2711_defconfig @@ -1002,6 +1002,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -1019,8 +1020,8 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig index bdcab6646d80cd839b797cb16543dfc9370b1791..d66d80f95c0018a62430f2160b8d0dc102b67ae5 100644 --- a/arch/arm64/configs/bcmrpi3_defconfig +++ b/arch/arm64/configs/bcmrpi3_defconfig @@ -132,6 +132,33 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_SET=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m CONFIG_NETFILTER_XT_SET=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -220,6 +247,14 @@ CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_REDIR_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -239,6 +274,12 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_CHAIN_NAT_IPV6=m +CONFIG_NFT_MASQ_IPV6=m +CONFIG_NFT_REDIR_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -257,6 +298,9 @@ CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -854,6 +898,7 @@ CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -864,8 +909,8 @@ CONFIG_SND_SOC_AD193X_I2C=m CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m CONFIG_HIDRAW=y diff --git a/arch/arm64/configs/openeuler-raspi_defconfig b/arch/arm64/configs/openeuler-raspi_defconfig index ffc3e8e132a673a646cb18ea3f3ca906066fd7fb..4fa649be2878e03e89f843cfe1fca43be13ca46a 100644 --- a/arch/arm64/configs/openeuler-raspi_defconfig +++ b/arch/arm64/configs/openeuler-raspi_defconfig @@ -5179,6 +5179,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -5255,7 +5256,6 @@ CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m # CONFIG_SND_SOC_CS4270 is not set CONFIG_SND_SOC_CS4271=m -CONFIG_SND_SOC_CS4271_I2C=m # CONFIG_SND_SOC_CS4271_SPI is not set CONFIG_SND_SOC_CS42XX8=m CONFIG_SND_SOC_CS42XX8_I2C=m @@ -5272,8 +5272,8 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m # CONFIG_SND_SOC_INNO_RK3036 is not set -# CONFIG_SND_SOC_MA120X0P is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set diff --git a/drivers/base/component.c b/drivers/base/component.c index e8d676fad0c95600f426d36796c0ffac270ae98d..684c5b70ef318b1233be0368c3da98323c0ff1cc 100644 --- a/drivers/base/component.c +++ b/drivers/base/component.c @@ -235,7 +235,8 @@ static int try_to_bring_up_master(struct master *master, ret = master->ops->bind(master->dev); if (ret < 0) { devres_release_group(master->dev, NULL); - dev_info(master->dev, "master bind failed: %d\n", ret); + if (ret != -EPROBE_DEFER) + dev_info(master->dev, "master bind failed: %d\n", ret); return ret; } @@ -506,8 +507,9 @@ static int component_bind(struct component *component, struct master *master, devres_release_group(component->dev, NULL); devres_release_group(master->dev, NULL); - dev_err(master->dev, "failed to bind %s (ops %ps): %d\n", - dev_name(component->dev), component->ops, ret); + if (ret != -EPROBE_DEFER) + dev_err(master->dev, "failed to bind %s (ops %ps): %d\n", + dev_name(component->dev), component->ops, ret); } return ret; diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index 03a9d08dd5a9aa17bbad31f43a855b56e44246eb..6dbe1525b9739c628e09ca9968e8530d6b9dd001 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -536,7 +536,8 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( /* link this the last controlblock */ if (frame && c->is_40bit_channel) - d->cb_list[frame - 1].cb->next = + ((struct bcm2838_dma40_scb *) + d->cb_list[frame - 1].cb)->next_cb = to_bcm2838_cbaddr(cb_entry->paddr); if (frame && !c->is_40bit_channel) d->cb_list[frame - 1].cb->next = cb_entry->paddr; @@ -587,12 +588,13 @@ static void bcm2835_dma_fill_cb_chain_with_sg( max_len = bcm2835_dma_max_frame_length(c); for_each_sg(sgl, sgent, sg_len, i) { if (c->is_40bit_channel) { - struct bcm2838_dma40_scb *scb = - (struct bcm2838_dma40_scb *)cb->cb; + struct bcm2838_dma40_scb *scb; + for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent); - len > 0; - addr += scb->len, len -= scb->len, scb++) { + len > 0; + addr += scb->len, len -= scb->len, cb++) { + scb = (struct bcm2838_dma40_scb *)cb->cb; if (direction == DMA_DEV_TO_MEM) { scb->dst = lower_32_bits(addr); scb->dsti = upper_32_bits(addr) | BCM2838_DMA40_INC; @@ -700,9 +702,7 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) * if this IRQ handler is threaded.) If the channel is finished, it * will remain idle despite the ACTIVE flag being set. */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | - (c->is_40bit_channel ? BCM2838_DMA40_CS_FLAGS(c->dreq) : - BCM2835_DMA_CS_FLAGS(c->dreq)), + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); d = c->desc; diff --git a/drivers/gpu/drm/v3d/v3d_drv.h b/drivers/gpu/drm/v3d/v3d_drv.h index 7b4f3b5a086ed3c12ea2ff9d0e6259124a468f64..069fefe16d28fb2391729ca238b747d424e37e34 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.h +++ b/drivers/gpu/drm/v3d/v3d_drv.h @@ -267,27 +267,42 @@ struct v3d_csd_job { }; /** - * _wait_for - magic (register) wait macro + * __wait_for - magic wait macro * - * Does the right thing for modeset paths when run under kdgb or similar atomic - * contexts. Note that it's important that we check the condition again after - * having timed out, since the timeout could be due to preemption or similar and - * we've never had a chance to check the condition before the timeout. + * Macro to help avoid open coding check/wait/timeout patterns. Note that it's + * important that we check the condition again after having timed out, since the + * timeout could be due to preemption or similar and we've never had a chance to + * check the condition before the timeout. */ -#define wait_for(COND, MS) ({ \ - unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ - int ret__ = 0; \ - while (!(COND)) { \ - if (time_after(jiffies, timeout__)) { \ - if (!(COND)) \ - ret__ = -ETIMEDOUT; \ +#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ + const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ + long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ + int ret__; \ + might_sleep(); \ + for (;;) { \ + const bool expired__ = ktime_after(ktime_get_raw(), end__); \ + OP; \ + /* Guarantee COND check prior to timeout */ \ + barrier(); \ + if (COND) { \ + ret__ = 0; \ break; \ } \ - msleep(1); \ + if (expired__) { \ + ret__ = -ETIMEDOUT; \ + break; \ + } \ + usleep_range(wait__, wait__ * 2); \ + if (wait__ < (Wmax)) \ + wait__ <<= 1; \ } \ ret__; \ }) +#define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ + (Wmax)) +#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) + static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) { /* nsecs_to_jiffies64() does not guard against overflow */ diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 9dc0fc6b8a2a8194bdb068d9115c3468fca101c6..5e9d6582cf62dc6d14fa54ad216e9a608b58b30e 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -1349,8 +1349,10 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) hdmi->pixel_clock = devm_clk_get(dev, "pixel"); if (IS_ERR(hdmi->pixel_clock)) { - DRM_ERROR("Failed to get pixel clock\n"); - return PTR_ERR(hdmi->pixel_clock); + ret = PTR_ERR(hdmi->pixel_clock); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Failed to get pixel clock\n"); + return ret; } hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); if (IS_ERR(hdmi->hsm_clock)) { diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c index 72abca2bac3a52fd460a995f6314ef5b9407a04d..1d8ceb2a4b907238fadb0c2c33868b027e8db2e6 100644 --- a/drivers/irqchip/irq-bcm2835.c +++ b/drivers/irqchip/irq-bcm2835.c @@ -76,8 +76,7 @@ #define ARM_LOCAL_GPU_INT_ROUTING 0x0c #define REG_FIQ_CONTROL 0x0c -#define REG_FIQ_ENABLE 0x80 -#define REG_FIQ_DISABLE 0 +#define FIQ_CONTROL_ENABLE BIT(7) #define NR_BANKS 3 #define IRQS_PER_BANK 32 @@ -125,7 +124,7 @@ static inline unsigned int hwirq_to_fiq(unsigned long hwirq) static void armctrl_mask_irq(struct irq_data *d) { if (d->hwirq >= NUMBER_IRQS) - writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); + writel_relaxed(0, intc.base + REG_FIQ_CONTROL); else writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); @@ -152,7 +151,7 @@ static void armctrl_unmask_irq(struct irq_data *d) ARM_LOCAL_GPU_INT_ROUTING); } - writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), + writel_relaxed(FIQ_CONTROL_ENABLE | hwirq_to_fiq(d->hwirq), intc.base + REG_FIQ_CONTROL); } else { writel_relaxed(HWIRQ_BIT(d->hwirq), @@ -210,6 +209,7 @@ static int __init armctrl_of_init(struct device_node *node, { void __iomem *base; int irq = 0, last_irq, b, i; + u32 reg; base = of_iomap(node, 0); if (!base) @@ -233,6 +233,19 @@ static int __init armctrl_of_init(struct device_node *node, handle_level_irq); irq_set_probe(irq); } + + reg = readl_relaxed(intc.enable[b]); + if (reg) { + writel_relaxed(reg, intc.disable[b]); + pr_err(FW_BUG "Bootloader left irq enabled: " + "bank %d irq %*pbl\n", b, IRQS_PER_BANK, ®); + } + } + + reg = readl_relaxed(base + REG_FIQ_CONTROL); + if (reg & FIQ_CONTROL_ENABLE) { + writel_relaxed(0, base + REG_FIQ_CONTROL); + pr_err(FW_BUG "Bootloader left fiq enabled\n"); } last_irq = irq; diff --git a/drivers/media/i2c/irs1125.c b/drivers/media/i2c/irs1125.c index 25e1dd5a08efafd2e33ac3458885e1adabb16bbc..30c3d264038651ef7729596ef711d779c39eb045 100644 --- a/drivers/media/i2c/irs1125.c +++ b/drivers/media/i2c/irs1125.c @@ -15,6 +15,7 @@ #include "irs1125.h" #include #include +#include #include #include #include @@ -22,13 +23,13 @@ #include #include #include +#include #include -#include +#include #include #include #include #include -#include #define CHECK_BIT(val, pos) ((val) & BIT(pos)) @@ -38,18 +39,19 @@ #define IRS1125_ALTERNATE_FW "irs1125_af.bin" -#define IRS1125_REG_CSICFG 0xA882 -#define IRS1125_REG_DESIGN_STEP 0xB0AD -#define IRS1125_REG_EFUSEVAL2 0xB09F -#define IRS1125_REG_EFUSEVAL3 0xB0A0 -#define IRS1125_REG_EFUSEVAL4 0xB0A1 -#define IRS1125_REG_DMEM_SHADOW 0xC320 +#define IRS1125_REG_SAFE_RECONFIG 0xA850 +#define IRS1125_REG_CSICFG 0xA882 +#define IRS1125_REG_DESIGN_STEP 0xB0AD +#define IRS1125_REG_EFUSEVAL2 0xB09F +#define IRS1125_REG_EFUSEVAL3 0xB0A0 +#define IRS1125_REG_EFUSEVAL4 0xB0A1 +#define IRS1125_REG_DMEM_SHADOW 0xC320 -#define IRS1125_DESIGN_STEP_EXPECTED 0x0a12 +#define IRS1125_DESIGN_STEP_EXPECTED 0x0a12 #define IRS1125_ROW_START_DEF 0 #define IRS1125_COLUMN_START_DEF 0 -#define IRS1125_WINDOW_HEIGHT_DEF 288 +#define IRS1125_WINDOW_HEIGHT_DEF 288 #define IRS1125_WINDOW_WIDTH_DEF 352 struct regval_list { @@ -80,6 +82,7 @@ struct irs1125 { struct v4l2_ctrl *ctrl_numseq; int power_count; + bool mod_pll_init; }; static inline struct irs1125 *to_state(struct v4l2_subdev *sd) @@ -87,7 +90,53 @@ static inline struct irs1125 *to_state(struct v4l2_subdev *sd) return container_of(sd, struct irs1125, sd); } -static struct regval_list irs1125_26MHz[] = { +static const char *expo_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = { + "safe reconfiguration of exposure of sequence 0", + "safe reconfiguration of exposure of sequence 1", + "safe reconfiguration of exposure of sequence 2", + "safe reconfiguration of exposure of sequence 3", + "safe reconfiguration of exposure of sequence 4", + "safe reconfiguration of exposure of sequence 5", + "safe reconfiguration of exposure of sequence 6", + "safe reconfiguration of exposure of sequence 7", + "safe reconfiguration of exposure of sequence 8", + "safe reconfiguration of exposure of sequence 9", + "safe reconfiguration of exposure of sequence 10", + "safe reconfiguration of exposure of sequence 11", + "safe reconfiguration of exposure of sequence 12", + "safe reconfiguration of exposure of sequence 13", + "safe reconfiguration of exposure of sequence 14", + "safe reconfiguration of exposure of sequence 15", + "safe reconfiguration of exposure of sequence 16", + "safe reconfiguration of exposure of sequence 17", + "safe reconfiguration of exposure of sequence 18", + "safe reconfiguration of exposure of sequence 19", +}; + +static const char *frame_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = { + "safe reconfiguration of framerate of sequence 0", + "safe reconfiguration of framerate of sequence 1", + "safe reconfiguration of framerate of sequence 2", + "safe reconfiguration of framerate of sequence 3", + "safe reconfiguration of framerate of sequence 4", + "safe reconfiguration of framerate of sequence 5", + "safe reconfiguration of framerate of sequence 6", + "safe reconfiguration of framerate of sequence 7", + "safe reconfiguration of framerate of sequence 8", + "safe reconfiguration of framerate of sequence 9", + "safe reconfiguration of framerate of sequence 10", + "safe reconfiguration of framerate of sequence 11", + "safe reconfiguration of framerate of sequence 12", + "safe reconfiguration of framerate of sequence 13", + "safe reconfiguration of framerate of sequence 14", + "safe reconfiguration of framerate of sequence 15", + "safe reconfiguration of framerate of sequence 16", + "safe reconfiguration of framerate of sequence 17", + "safe reconfiguration of framerate of sequence 18", + "safe reconfiguration of framerate of sequence 19", +}; + +static struct regval_list irs1125_26mhz[] = { {0xB017, 0x0413}, {0xB086, 0x3535}, {0xB0AE, 0xEF02}, @@ -153,7 +202,7 @@ static struct regval_list irs1125_26MHz[] = { {0xFFFF, 100} }; -static struct regval_list irs1125_seq_cfg[] = { +static struct regval_list irs1125_seq_cfg_init[] = { {0xC3A0, 0x823D}, {0xC3A1, 0xB13B}, {0xC3A2, 0x0313}, @@ -228,8 +277,7 @@ static struct regval_list irs1125_seq_cfg[] = { {0xC039, 0x0000}, {0xC401, 0x0002}, - {0xFFFF, 1}, - {0xA87C, 0x0001} + {0xFFFF, 1} }; static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val) @@ -243,32 +291,40 @@ static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val) dev_err(&client->dev, "%s: i2c write error, reg: %x\n", __func__, reg); + dev_dbg(&client->dev, "write addr 0x%04x, val 0x%04x\n", reg, val); return ret; } static int irs1125_read(struct v4l2_subdev *sd, u16 reg, u16 *val) { - int ret; - unsigned char data_w[2] = { reg >> 8, reg & 0xff }; - char rdval[2]; - struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_msg msgs[2]; + u8 addr_buf[2] = { reg >> 8, reg & 0xff }; + u8 data_buf[2] = { 0, }; + int ret; - ret = i2c_master_send(client, data_w, 2); - if (ret < 0) { - dev_dbg(&client->dev, "%s: i2c write error, reg: %x\n", - __func__, reg); + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = ARRAY_SIZE(addr_buf); + msgs[0].buf = addr_buf; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = 2; + msgs[1].buf = data_buf; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + if (ret >= 0) + ret = -EIO; return ret; } - ret = i2c_master_recv(client, rdval, 2); - if (ret < 0) - dev_err(&client->dev, "%s: i2c read error, reg: %x\n", - __func__, reg); - - *val = rdval[1] | (rdval[0] << 8); + *val = data_buf[1] | (data_buf[0] << 8); - return ret; + return 0; } static int irs1125_write_array(struct v4l2_subdev *sd, @@ -357,8 +413,8 @@ static int __sensor_init(struct v4l2_subdev *sd) cnt++; } - ret = irs1125_write_array(sd, irs1125_26MHz, - ARRAY_SIZE(irs1125_26MHz)); + ret = irs1125_write_array(sd, irs1125_26mhz, + ARRAY_SIZE(irs1125_26mhz)); if (ret < 0) { dev_err(&client->dev, "write sensor default regs error\n"); return ret; @@ -408,14 +464,18 @@ static int __sensor_init(struct v4l2_subdev *sd) } release_firmware(fw); - ret = irs1125_write_array(sd, irs1125_seq_cfg, - ARRAY_SIZE(irs1125_seq_cfg)); + ret = irs1125_write_array(sd, irs1125_seq_cfg_init, + ARRAY_SIZE(irs1125_seq_cfg_init)); if (ret < 0) { dev_err(&client->dev, "write default sequence failed\n"); return ret; } - return 0; + irs1125->mod_pll_init = true; + v4l2_ctrl_handler_setup(&irs1125->ctrl_handler); + irs1125->mod_pll_init = false; + + return irs1125_write(sd, 0xA87C, 0x0001); } static int irs1125_sensor_power(struct v4l2_subdev *sd, int on) @@ -551,134 +611,146 @@ static int irs1125_s_ctrl(struct v4l2_ctrl *ctrl) struct irs1125 *dev = container_of(ctrl->handler, struct irs1125, ctrl_handler); struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); - int err, i; - struct irs1125_mod_pll *mod_cur, *mod_new; - struct irs1125_seq_cfg *cfg_cur, *cfg_new; - u16 addr, val; - - err = 0; + int err = 0, i; switch (ctrl->id) { - case IRS1125_CID_SAFE_RECONFIG: - { - struct irs1125_illu *illu_cur, *illu_new; - - illu_new = (struct irs1125_illu *)ctrl->p_new.p; - illu_cur = (struct irs1125_illu *)ctrl->p_cur.p; - for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { - if (illu_cur[i].exposure != illu_new[i].exposure) { - addr = 0xA850 + i * 2; - val = illu_new[i].exposure; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (illu_cur[i].framerate != illu_new[i].framerate) { - addr = 0xA851 + i * 2; - val = illu_new[i].framerate; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - } + case IRS1125_CID_SAFE_RECONFIG_S0_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S0_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S1_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S1_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S2_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S2_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S3_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S3_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S4_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S4_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S5_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S5_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S6_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S6_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S7_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S7_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S8_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S8_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S9_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S9_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S10_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S10_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S11_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S11_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S12_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S12_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S13_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S13_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S14_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S14_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S15_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S15_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S16_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S16_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S17_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S17_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S18_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S18_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S19_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S19_FRAME: { + unsigned int offset = ctrl->id - + IRS1125_CID_SAFE_RECONFIG_S0_EXPO; + + err = irs1125_write(&dev->sd, + IRS1125_REG_SAFE_RECONFIG + offset, + ctrl->val); break; } - case IRS1125_CID_MOD_PLL: + case IRS1125_CID_MOD_PLL: { + struct irs1125_mod_pll *mod_new; + + if (dev->mod_pll_init) + break; + mod_new = (struct irs1125_mod_pll *)ctrl->p_new.p; - mod_cur = (struct irs1125_mod_pll *)ctrl->p_cur.p; for (i = 0; i < IRS1125_NUM_MOD_PLLS; i++) { - if (mod_cur[i].pllcfg1 != mod_new[i].pllcfg1) { - addr = 0xC3A0 + i * 3; - val = mod_new[i].pllcfg1; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg2 != mod_new[i].pllcfg2) { - addr = 0xC3A1 + i * 3; - val = mod_new[i].pllcfg2; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg3 != mod_new[i].pllcfg3) { - addr = 0xC3A2 + i * 3; - val = mod_new[i].pllcfg3; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg4 != mod_new[i].pllcfg4) { - addr = 0xC24C + i * 5; - val = mod_new[i].pllcfg4; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg5 != mod_new[i].pllcfg5) { - addr = 0xC24D + i * 5; - val = mod_new[i].pllcfg5; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg6 != mod_new[i].pllcfg6) { - addr = 0xC24E + i * 5; - val = mod_new[i].pllcfg6; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg7 != mod_new[i].pllcfg7) { - addr = 0xC24F + i * 5; - val = mod_new[i].pllcfg7; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg8 != mod_new[i].pllcfg8) { - addr = 0xC250 + i * 5; - val = mod_new[i].pllcfg8; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } + unsigned int pll_offset, ssc_offset; + + pll_offset = i * 3; + ssc_offset = i * 5; + + err = irs1125_write(&dev->sd, 0xC3A0 + pll_offset, + mod_new[i].pllcfg1); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC3A1 + pll_offset, + mod_new[i].pllcfg2); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC3A2 + pll_offset, + mod_new[i].pllcfg3); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24C + ssc_offset, + mod_new[i].pllcfg4); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24D + ssc_offset, + mod_new[i].pllcfg5); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24E + ssc_offset, + mod_new[i].pllcfg6); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24F + ssc_offset, + mod_new[i].pllcfg7); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC250 + ssc_offset, + mod_new[i].pllcfg8); + if (err < 0) + break; } break; - case IRS1125_CID_SEQ_CONFIG: + } + case IRS1125_CID_SEQ_CONFIG: { + struct irs1125_seq_cfg *cfg_new; + cfg_new = (struct irs1125_seq_cfg *)ctrl->p_new.p; - cfg_cur = (struct irs1125_seq_cfg *)ctrl->p_cur.p; for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { - if (cfg_cur[i].exposure != cfg_new[i].exposure) { - addr = IRS1125_REG_DMEM_SHADOW + i * 4; - val = cfg_new[i].exposure; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (cfg_cur[i].framerate != cfg_new[i].framerate) { - addr = IRS1125_REG_DMEM_SHADOW + 1 + i * 4; - val = cfg_new[i].framerate; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (cfg_cur[i].ps != cfg_new[i].ps) { - addr = IRS1125_REG_DMEM_SHADOW + 2 + i * 4; - val = cfg_new[i].ps; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (cfg_cur[i].pll != cfg_new[i].pll) { - addr = IRS1125_REG_DMEM_SHADOW + 3 + i * 4; - val = cfg_new[i].pll; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } + unsigned int seq_offset = i * 4; + u16 addr, val; + + addr = IRS1125_REG_DMEM_SHADOW + seq_offset; + val = cfg_new[i].exposure; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; + + addr = IRS1125_REG_DMEM_SHADOW + 1 + seq_offset; + val = cfg_new[i].framerate; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; + + addr = IRS1125_REG_DMEM_SHADOW + 2 + seq_offset; + val = cfg_new[i].ps; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; + + addr = IRS1125_REG_DMEM_SHADOW + 3 + seq_offset; + val = cfg_new[i].pll; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; } break; + } case IRS1125_CID_NUM_SEQS: err = irs1125_write(&dev->sd, 0xA88D, ctrl->val - 1); if (err >= 0) @@ -748,19 +820,6 @@ static const struct v4l2_ctrl_config irs1125_custom_ctrls[] = { .elem_size = sizeof(u16), .dims = {sizeof(struct irs1125_mod_pll) / sizeof(u16), IRS1125_NUM_MOD_PLLS} - }, { - .ops = &irs1125_ctrl_ops, - .id = IRS1125_CID_SAFE_RECONFIG, - .name = "Change exposure and pause of single seq", - .type = V4L2_CTRL_TYPE_U16, - .flags = V4L2_CTRL_FLAG_HAS_PAYLOAD, - .min = 0, - .max = U16_MAX, - .step = 1, - .def = 0, - .elem_size = sizeof(u16), - .dims = {sizeof(struct irs1125_illu) / sizeof(u16), - IRS1125_NUM_SEQ_ENTRIES} }, { .ops = &irs1125_ctrl_ops, .id = IRS1125_CID_SEQ_CONFIG, @@ -890,9 +949,16 @@ static int irs1125_ctrls_init(struct irs1125 *sensor, struct device *dev) { struct v4l2_ctrl *ctrl; int err, i; - struct v4l2_ctrl_handler *hdl; + struct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler; + struct v4l2_ctrl_config ctrl_cfg = { + .ops = &irs1125_ctrl_ops, + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = U16_MAX, + .step = 1, + .def = 0x1000 + }; - hdl = &sensor->ctrl_handler; v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(irs1125_custom_ctrls)); for (i = 0; i < ARRAY_SIZE(irs1125_custom_ctrls); i++) { @@ -913,6 +979,27 @@ static int irs1125_ctrls_init(struct irs1125 *sensor, struct device *dev) goto error_ctrls; } + for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { + ctrl_cfg.name = expo_ctrl_names[i]; + ctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_EXPO + i * 2; + ctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg, + NULL); + if (!ctrl) + dev_err(dev, "Failed to init exposure control %s\n", + ctrl_cfg.name); + } + + ctrl_cfg.def = 0; + for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { + ctrl_cfg.name = frame_ctrl_names[i]; + ctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_FRAME + i * 2; + ctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg, + NULL); + if (!ctrl) + dev_err(dev, "Failed to init framerate control %s\n", + ctrl_cfg.name); + } + sensor->sd.ctrl_handler = hdl; return 0; @@ -1030,6 +1117,7 @@ static int irs1125_probe(struct i2c_client *client, } gpio_num = desc_to_gpio(sensor->reset); + dev_dbg(&client->dev, "reset on GPIO num %d\n", gpio_num); mutex_init(&sensor->lock); diff --git a/drivers/media/i2c/irs1125.h b/drivers/media/i2c/irs1125.h index dccaca23aa76abed58752615dc7991f6166ee742..96d676123d5ed6ae6fcb5dab2e5af5eac4a6c7b8 100644 --- a/drivers/media/i2c/irs1125.h +++ b/drivers/media/i2c/irs1125.h @@ -21,18 +21,57 @@ #define IRS1125_NUM_SEQ_ENTRIES 20 #define IRS1125_NUM_MOD_PLLS 4 -#define IRS1125_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0xf000) -#define IRS1125_CID_SAFE_RECONFIG (IRS1125_CID_CUSTOM_BASE + 0) -#define IRS1125_CID_CONTINUOUS_TRIG (IRS1125_CID_CUSTOM_BASE + 1) -#define IRS1125_CID_TRIGGER (IRS1125_CID_CUSTOM_BASE + 2) -#define IRS1125_CID_RECONFIG (IRS1125_CID_CUSTOM_BASE + 3) -#define IRS1125_CID_ILLU_ON (IRS1125_CID_CUSTOM_BASE + 4) -#define IRS1125_CID_NUM_SEQS (IRS1125_CID_CUSTOM_BASE + 5) -#define IRS1125_CID_MOD_PLL (IRS1125_CID_CUSTOM_BASE + 6) -#define IRS1125_CID_SEQ_CONFIG (IRS1125_CID_CUSTOM_BASE + 7) -#define IRS1125_CID_IDENT0 (IRS1125_CID_CUSTOM_BASE + 8) -#define IRS1125_CID_IDENT1 (IRS1125_CID_CUSTOM_BASE + 9) -#define IRS1125_CID_IDENT2 (IRS1125_CID_CUSTOM_BASE + 10) +#define IRS1125_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0xf000) +#define IRS1125_CID_CONTINUOUS_TRIG (IRS1125_CID_CUSTOM_BASE + 1) +#define IRS1125_CID_TRIGGER (IRS1125_CID_CUSTOM_BASE + 2) +#define IRS1125_CID_RECONFIG (IRS1125_CID_CUSTOM_BASE + 3) +#define IRS1125_CID_ILLU_ON (IRS1125_CID_CUSTOM_BASE + 4) +#define IRS1125_CID_NUM_SEQS (IRS1125_CID_CUSTOM_BASE + 5) +#define IRS1125_CID_MOD_PLL (IRS1125_CID_CUSTOM_BASE + 6) +#define IRS1125_CID_SEQ_CONFIG (IRS1125_CID_CUSTOM_BASE + 7) +#define IRS1125_CID_IDENT0 (IRS1125_CID_CUSTOM_BASE + 8) +#define IRS1125_CID_IDENT1 (IRS1125_CID_CUSTOM_BASE + 9) +#define IRS1125_CID_IDENT2 (IRS1125_CID_CUSTOM_BASE + 10) +#define IRS1125_CID_SAFE_RECONFIG_S0_EXPO (IRS1125_CID_CUSTOM_BASE + 11) +#define IRS1125_CID_SAFE_RECONFIG_S0_FRAME (IRS1125_CID_CUSTOM_BASE + 12) +#define IRS1125_CID_SAFE_RECONFIG_S1_EXPO (IRS1125_CID_CUSTOM_BASE + 13) +#define IRS1125_CID_SAFE_RECONFIG_S1_FRAME (IRS1125_CID_CUSTOM_BASE + 14) +#define IRS1125_CID_SAFE_RECONFIG_S2_EXPO (IRS1125_CID_CUSTOM_BASE + 15) +#define IRS1125_CID_SAFE_RECONFIG_S2_FRAME (IRS1125_CID_CUSTOM_BASE + 16) +#define IRS1125_CID_SAFE_RECONFIG_S3_EXPO (IRS1125_CID_CUSTOM_BASE + 17) +#define IRS1125_CID_SAFE_RECONFIG_S3_FRAME (IRS1125_CID_CUSTOM_BASE + 18) +#define IRS1125_CID_SAFE_RECONFIG_S4_EXPO (IRS1125_CID_CUSTOM_BASE + 19) +#define IRS1125_CID_SAFE_RECONFIG_S4_FRAME (IRS1125_CID_CUSTOM_BASE + 20) +#define IRS1125_CID_SAFE_RECONFIG_S5_EXPO (IRS1125_CID_CUSTOM_BASE + 21) +#define IRS1125_CID_SAFE_RECONFIG_S5_FRAME (IRS1125_CID_CUSTOM_BASE + 22) +#define IRS1125_CID_SAFE_RECONFIG_S6_EXPO (IRS1125_CID_CUSTOM_BASE + 23) +#define IRS1125_CID_SAFE_RECONFIG_S6_FRAME (IRS1125_CID_CUSTOM_BASE + 24) +#define IRS1125_CID_SAFE_RECONFIG_S7_EXPO (IRS1125_CID_CUSTOM_BASE + 25) +#define IRS1125_CID_SAFE_RECONFIG_S7_FRAME (IRS1125_CID_CUSTOM_BASE + 26) +#define IRS1125_CID_SAFE_RECONFIG_S8_EXPO (IRS1125_CID_CUSTOM_BASE + 27) +#define IRS1125_CID_SAFE_RECONFIG_S8_FRAME (IRS1125_CID_CUSTOM_BASE + 28) +#define IRS1125_CID_SAFE_RECONFIG_S9_EXPO (IRS1125_CID_CUSTOM_BASE + 29) +#define IRS1125_CID_SAFE_RECONFIG_S9_FRAME (IRS1125_CID_CUSTOM_BASE + 30) +#define IRS1125_CID_SAFE_RECONFIG_S10_EXPO (IRS1125_CID_CUSTOM_BASE + 31) +#define IRS1125_CID_SAFE_RECONFIG_S10_FRAME (IRS1125_CID_CUSTOM_BASE + 32) +#define IRS1125_CID_SAFE_RECONFIG_S11_EXPO (IRS1125_CID_CUSTOM_BASE + 33) +#define IRS1125_CID_SAFE_RECONFIG_S11_FRAME (IRS1125_CID_CUSTOM_BASE + 34) +#define IRS1125_CID_SAFE_RECONFIG_S12_EXPO (IRS1125_CID_CUSTOM_BASE + 35) +#define IRS1125_CID_SAFE_RECONFIG_S12_FRAME (IRS1125_CID_CUSTOM_BASE + 36) +#define IRS1125_CID_SAFE_RECONFIG_S13_EXPO (IRS1125_CID_CUSTOM_BASE + 37) +#define IRS1125_CID_SAFE_RECONFIG_S13_FRAME (IRS1125_CID_CUSTOM_BASE + 38) +#define IRS1125_CID_SAFE_RECONFIG_S14_EXPO (IRS1125_CID_CUSTOM_BASE + 39) +#define IRS1125_CID_SAFE_RECONFIG_S14_FRAME (IRS1125_CID_CUSTOM_BASE + 40) +#define IRS1125_CID_SAFE_RECONFIG_S15_EXPO (IRS1125_CID_CUSTOM_BASE + 41) +#define IRS1125_CID_SAFE_RECONFIG_S15_FRAME (IRS1125_CID_CUSTOM_BASE + 42) +#define IRS1125_CID_SAFE_RECONFIG_S16_EXPO (IRS1125_CID_CUSTOM_BASE + 43) +#define IRS1125_CID_SAFE_RECONFIG_S16_FRAME (IRS1125_CID_CUSTOM_BASE + 44) +#define IRS1125_CID_SAFE_RECONFIG_S17_EXPO (IRS1125_CID_CUSTOM_BASE + 45) +#define IRS1125_CID_SAFE_RECONFIG_S17_FRAME (IRS1125_CID_CUSTOM_BASE + 46) +#define IRS1125_CID_SAFE_RECONFIG_S18_EXPO (IRS1125_CID_CUSTOM_BASE + 47) +#define IRS1125_CID_SAFE_RECONFIG_S18_FRAME (IRS1125_CID_CUSTOM_BASE + 48) +#define IRS1125_CID_SAFE_RECONFIG_S19_EXPO (IRS1125_CID_CUSTOM_BASE + 49) +#define IRS1125_CID_SAFE_RECONFIG_S19_FRAME (IRS1125_CID_CUSTOM_BASE + 50) struct irs1125_seq_cfg { __u16 exposure; @@ -41,11 +80,6 @@ struct irs1125_seq_cfg { __u16 pll; }; -struct irs1125_illu { - __u16 exposure; - __u16 framerate; -}; - struct irs1125_mod_pll { __u16 pllcfg1; __u16 pllcfg2; diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c index f862f1b7f99657c6cff3a816a68bc853d2d01033..d6f5f5b3f75f247897acee52446003713854f3da 100644 --- a/drivers/media/rc/lirc_dev.c +++ b/drivers/media/rc/lirc_dev.c @@ -29,7 +29,7 @@ #include "rc-core-priv.h" #include -#define LIRCBUF_SIZE 256 +#define LIRCBUF_SIZE 1024 static dev_t lirc_base_dev; diff --git a/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c b/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c index 8fa8ed51b721c14d98e2f7522107c0070bfb3dbf..bdd9c73cba3fc6807d2b324aa42f43ddf4965f7e 100644 --- a/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c +++ b/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c @@ -1502,10 +1502,10 @@ _func_enter_; /* Insert MIC into payload */ for (j = 0; j < 8; j++) - pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; + pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; - payload_index = hdrlen + 8; - for (i=0; i< num_blocks; i++) + payload_index = hdrlen + 8; + for (i=0; i< num_blocks; i++) { construct_ctr_preload( ctr_preload, @@ -1876,10 +1876,10 @@ _func_enter_; /* Insert MIC into payload */ for (j = 0; j < 8; j++) - message[payload_index+j] = mic[j]; + message[payload_index+j] = mic[j]; - payload_index = hdrlen + 8; - for (i=0; i< num_blocks; i++) + payload_index = hdrlen + 8; + for (i=0; i< num_blocks; i++) { construct_ctr_preload( ctr_preload, diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig index a17c25115f5446f8d6496981ade8705ec5f9a63d..6f5b6cefcb3a4277517b88c422659953a4d026c6 100644 --- a/sound/soc/bcm/Kconfig +++ b/sound/soc/bcm/Kconfig @@ -187,6 +187,13 @@ config SND_AUDIOINJECTOR_OCTO_SOUNDCARD help Say Y or M if you want to add support for audioinjector.net octo add on +config SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD + tristate "Support for audioinjector.net isolated DAC and ADC soundcard" + depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S + select SND_SOC_CS4271_I2C + help + Say Y or M if you want to add support for audioinjector.net isolated soundcard + config SND_AUDIOSENSE_PI tristate "Support for AudioSense Add-On Soundcard" depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S diff --git a/sound/soc/bcm/Makefile b/sound/soc/bcm/Makefile index 254801fc0feac1089cfb5dd54199c5dd892ad022..6557e444837db90102825a5fd09f8799404195f1 100644 --- a/sound/soc/bcm/Makefile +++ b/sound/soc/bcm/Makefile @@ -26,6 +26,7 @@ snd-soc-iqaudio-dac-objs := iqaudio-dac.o snd-soc-i-sabre-q2m-objs := i-sabre-q2m.o snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o snd-soc-audioinjector-octo-soundcard-objs := audioinjector-octo-soundcard.o +snd-soc-audioinjector-isolated-soundcard-objs := audioinjector-isolated-soundcard.o snd-soc-audiosense-pi-objs := audiosense-pi.o snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o snd-soc-dionaudio-loco-objs := dionaudio_loco.o @@ -54,6 +55,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o obj-$(CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M) += snd-soc-i-sabre-q2m.o obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o obj-$(CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD) += snd-soc-audioinjector-octo-soundcard.o +obj-$(CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD) += snd-soc-audioinjector-isolated-soundcard.o obj-$(CONFIG_SND_AUDIOSENSE_PI) += snd-soc-audiosense-pi.o obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o diff --git a/sound/soc/bcm/audioinjector-isolated-soundcard.c b/sound/soc/bcm/audioinjector-isolated-soundcard.c new file mode 100644 index 0000000000000000000000000000000000000000..6b9ae9051bd2e19eed37fb74098df211a092aa1c --- /dev/null +++ b/sound/soc/bcm/audioinjector-isolated-soundcard.c @@ -0,0 +1,168 @@ +/* + * ASoC Driver for AudioInjector.net isolated soundcard + * + * Created on: 20-February-2020 + * Author: flatmax@flatmax.org + * based on audioinjector-octo-soundcard.c + * + * Copyright (C) 2020 Flatmax Pty. Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include + +static struct gpio_desc *mute_gpio; + +static const unsigned int audioinjector_isolated_rates[] = { + 192000, 96000, 48000, 32000, 24000, 16000, 8000 +}; + +static struct snd_pcm_hw_constraint_list audioinjector_isolated_constraints = { + .list = audioinjector_isolated_rates, + .count = ARRAY_SIZE(audioinjector_isolated_rates), +}; + +static int audioinjector_isolated_dai_init(struct snd_soc_pcm_runtime *rtd) +{ + int ret=snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 24576000, 0); + if (ret) + return ret; + return snd_soc_dai_set_bclk_ratio(rtd->cpu_dai, 64); +} + +static int audioinjector_isolated_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, &audioinjector_isolated_constraints); + + gpiod_set_value(mute_gpio, 1); + return 0; +} + +static struct snd_soc_ops audioinjector_isolated_ops = { + .startup = audioinjector_isolated_startup, +}; + +static struct snd_soc_dai_link audioinjector_isolated_dai[] = { + { + .name = "AudioInjector ISO", + .stream_name = "AI-HIFI", + .codec_dai_name = "cs4271-hifi", + .ops = &audioinjector_isolated_ops, + .init = audioinjector_isolated_dai_init, + .symmetric_rates = 1, + .symmetric_channels = 1, + .dai_fmt = SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF, + } +}; + +static const struct snd_soc_dapm_widget audioinjector_isolated_widgets[] = { + SND_SOC_DAPM_OUTPUT("OUTPUTS"), + SND_SOC_DAPM_INPUT("INPUTS"), +}; + +static const struct snd_soc_dapm_route audioinjector_isolated_route[] = { + /* Balanced outputs */ + {"OUTPUTS", NULL, "AOUTA+"}, + {"OUTPUTS", NULL, "AOUTA-"}, + {"OUTPUTS", NULL, "AOUTB+"}, + {"OUTPUTS", NULL, "AOUTB-"}, + + /* Balanced inputs */ + {"AINA", NULL, "INPUTS"}, + {"AINB", NULL, "INPUTS"}, +}; + +static struct snd_soc_card snd_soc_audioinjector_isolated = { + .name = "audioinjector-isolated-soundcard", + .dai_link = audioinjector_isolated_dai, + .num_links = ARRAY_SIZE(audioinjector_isolated_dai), + + .dapm_widgets = audioinjector_isolated_widgets, + .num_dapm_widgets = ARRAY_SIZE(audioinjector_isolated_widgets), + .dapm_routes = audioinjector_isolated_route, + .num_dapm_routes = ARRAY_SIZE(audioinjector_isolated_route), +}; + +static int audioinjector_isolated_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card = &snd_soc_audioinjector_isolated; + int ret; + + card->dev = &pdev->dev; + + if (pdev->dev.of_node) { + struct snd_soc_dai_link *dai = &audioinjector_isolated_dai[0]; + struct device_node *i2s_node = + of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); + struct device_node *codec_node = + of_parse_phandle(pdev->dev.of_node, "codec", 0); + + mute_gpio = devm_gpiod_get_optional(&pdev->dev, "mute", GPIOD_OUT_LOW); + if (IS_ERR(mute_gpio)){ + dev_err(&pdev->dev, "mute gpio not found in dt overlay\n"); + return PTR_ERR(mute_gpio); + } + gpiod_set_value(mute_gpio, 0); + + if (i2s_node && codec_node) { + dai->cpu_dai_name = NULL; + dai->cpu_of_node = i2s_node; + dai->platform_name = NULL; + dai->platform_of_node = i2s_node; + dai->codec_name = NULL; + dai->codec_of_node = codec_node; + } else + if (!i2s_node) { + dev_err(&pdev->dev, + "i2s-controller missing or invalid in DT\n"); + return -EINVAL; + } else { + dev_err(&pdev->dev, + "Property 'codec' missing or invalid\n"); + return -EINVAL; + } + } + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret != 0) + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); + return ret; +} + +static const struct of_device_id audioinjector_isolated_of_match[] = { + { .compatible = "ai,audioinjector-isolated-soundcard", }, + {}, +}; +MODULE_DEVICE_TABLE(of, audioinjector_isolated_of_match); + +static struct platform_driver audioinjector_isolated_driver = { + .driver = { + .name = "audioinjector-isolated", + .owner = THIS_MODULE, + .of_match_table = audioinjector_isolated_of_match, + }, + .probe = audioinjector_isolated_probe, +}; + +module_platform_driver(audioinjector_isolated_driver); +MODULE_AUTHOR("Matt Flax "); +MODULE_DESCRIPTION("AudioInjector.net isolated Soundcard"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:audioinjector-isolated-soundcard"); diff --git a/sound/soc/bcm/hifiberry_dacplusadcpro.c b/sound/soc/bcm/hifiberry_dacplusadcpro.c index 75fc8f010421c8e554cfd3792d150a5f82b73bc7..2f83dbee3f9fe0216a81e39a2de1317b78049985 100644 --- a/sound/soc/bcm/hifiberry_dacplusadcpro.c +++ b/sound/soc/bcm/hifiberry_dacplusadcpro.c @@ -390,9 +390,11 @@ static int snd_rpi_hifiberry_dacplusadcpro_hw_params( int channels = params_channels(params); int width = 32; struct snd_soc_component *dac = rtd->codec_dais[0]->component; + struct snd_soc_dai *dai = rtd->codec_dais[0]; + struct snd_soc_dai_driver *drv = dai->driver; + const struct snd_soc_dai_ops *ops = drv->ops; if (snd_rpi_hifiberry_is_dacpro) { - width = snd_pcm_format_physical_width(params_format(params)); snd_rpi_hifiberry_dacplusadcpro_set_sclk(dac, @@ -414,6 +416,11 @@ static int snd_rpi_hifiberry_dacplusadcpro_hw_params( return ret; ret = snd_soc_dai_set_tdm_slot(rtd->codec_dais[1], 0x03, 0x03, channels, width); + if (ret) + return ret; + + if (snd_rpi_hifiberry_is_dacpro && ops->hw_params) + ret = ops->hw_params(substream, params, dai); return ret; } diff --git a/sound/soc/codecs/ma120x0p.c b/sound/soc/codecs/ma120x0p.c index 39c74b17e0077b443e79e1d93f05d335099029c2..e1591b6aff4319a4ebe252b6eaf822d40ef424b5 100644 --- a/sound/soc/codecs/ma120x0p.c +++ b/sound/soc/codecs/ma120x0p.c @@ -1002,7 +1002,7 @@ static struct snd_soc_dai_driver ma120x0p_dai = { .channels_max = 2, .rates = SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 44100, - .rate_max = 48000, + .rate_max = 96000, .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE }, .ops = &ma120x0p_dai_ops, @@ -1235,7 +1235,7 @@ static int ma120x0p_i2c_probe(struct i2c_client *i2c, //Startup sequence //Make sure the device is muted - priv_data->mute_gpio = devm_gpiod_get(&i2c->dev, "mute_gp", + priv_data->mute_gpio = devm_gpiod_get_optional(&i2c->dev, "mute_gp", GPIOD_OUT_LOW); if (IS_ERR(priv_data->mute_gpio)) { ret = PTR_ERR(priv_data->mute_gpio); @@ -1262,7 +1262,7 @@ static int ma120x0p_i2c_probe(struct i2c_client *i2c, msleep(200); //Enable ma120x0pp - priv_data->enable_gpio = devm_gpiod_get(&i2c->dev, + priv_data->enable_gpio = devm_gpiod_get_optional(&i2c->dev, "enable_gp", GPIOD_OUT_LOW); if (IS_ERR(priv_data->enable_gpio)) { ret = PTR_ERR(priv_data->enable_gpio); diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index bc70212031df4cc1cd8d740489ede26f9d9b4590..257a38407ee2509ba1c86e05b9029b449430f2b7 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -1383,7 +1383,7 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip, case USB_ID(0x0d8c, 0x0316): /* Hegel HD12 DSD */ case USB_ID(0x10cb, 0x0103): /* The Bit Opus #3; with fp->dsd_raw */ - case USB_ID(0x16b0, 0x06b2): /* NuPrime DAC-10 */ + case USB_ID(0x16d0, 0x06b2): /* NuPrime DAC-10 */ case USB_ID(0x16d0, 0x09dd): /* Encore mDSD */ case USB_ID(0x16d0, 0x0733): /* Furutech ADL Stratos */ case USB_ID(0x16d0, 0x09db): /* NuPrime Audio DAC-9 */