From d597582c192966313158260b2157a9e4ed63ec3c Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 17 Mar 2020 16:39:07 +0000 Subject: [PATCH 01/41] ARM: dts: bcm2711: Add 32-bit PMU compatibility The "arm" architecture has no support for the cortex-a72 as such, but the performance and measurement unit from the cortex-a15 seems to be compatible. Signed-off-by: Phil Elwell --- arch/arm/boot/dts/bcm2838.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi index 5f837e84132c..0f54f0586069 100644 --- a/arch/arm/boot/dts/bcm2838.dtsi +++ b/arch/arm/boot/dts/bcm2838.dtsi @@ -224,7 +224,7 @@ }; arm-pmu { - compatible = "arm,cortex-a72-pmu"; + compatible = "arm,cortex-a72-pmu", "arm,cortex-a15-pmu"; interrupts = , , , -- Gitee From f6a9dd1c3584ccefbb497e5cd30b8b0f46f49d9a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 19 Mar 2020 10:04:46 +0000 Subject: [PATCH 02/41] ARM: dts: bcm271x: Use a53 pmu, drop RPI364 The upstream bcm2837.dtsi uses cortex-a53-pmu, so we can do the same but with a fallback to the cortex-a7-pmu which is supported by the 32-bit kernel. Now that we're using the natural fallback mechanism of compatible strings, the RPI364 macro no longer serves any purpose - remove it. Signed-off-by: Phil Elwell --- arch/arm/boot/dts/bcm2710.dtsi | 6 +----- arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts | 2 -- arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts | 2 -- arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts | 2 -- arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts | 2 -- arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 2 -- 6 files changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/arm/boot/dts/bcm2710.dtsi b/arch/arm/boot/dts/bcm2710.dtsi index 5c45ded273fe..a2e084dc3867 100644 --- a/arch/arm/boot/dts/bcm2710.dtsi +++ b/arch/arm/boot/dts/bcm2710.dtsi @@ -5,11 +5,7 @@ compatible = "brcm,bcm2837", "brcm,bcm2836"; arm-pmu { -#ifdef RPI364 - compatible = "arm,armv8-pmuv3", "arm,cortex-a7-pmu"; -#else - compatible = "arm,cortex-a7-pmu"; -#endif + compatible = "arm,cortex-a53-pmu", "arm,cortex-a7-pmu"; }; soc { diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts index 116cdbf94b9b..36ecea71f0ef 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-2-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts index d9242ff77079..22fc6a82f2a9 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts index deb33441da95..4cacc5b72ae3 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts index 1c2560017c02..e1e13784cff6 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2710-rpi-cm3.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts index 1fd86f81f542..bf69a4b0b172 100644 --- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts @@ -1,3 +1 @@ -#define RPI364 - #include "../../../../arm/boot/dts/bcm2711-rpi-4-b.dts" -- Gitee From 49bceccfaf8769d7f78e41f54e7784caeb71d59f Mon Sep 17 00:00:00 2001 From: Yukimasa Sugizaki <4298265+Terminus-IMRC@users.noreply.github.com> Date: Fri, 20 Mar 2020 19:01:23 +0900 Subject: [PATCH 03/41] drm/v3d: Replace wait_for macros to remove use of msleep (#3510) commit 9daee6141cc9c75b09659b02b1cb9eeb2f5e16cc upstream. The wait_for macro's for Broadcom V3D driver used msleep, which is inappropriate due to its inaccuracy at low values (minimum wait time is about 30ms on the Raspberry Pi). This sleep was triggering in v3d_clean_caches(), causing us to only be able to dispatch ~33 compute jobs per second. This patch replaces the macro with the one from the Intel i915 version which uses usleep_range to provide more accurate waits. v2: Split from the vc4 patch so that we can confidently apply to stable (by anholt) Signed-off-by: James Hughes Signed-off-by: Eric Anholt Link: https://patchwork.freedesktop.org/patch/msgid/20200217153145.13780-1-james.hughes@raspberrypi.com Link: https://github.com/raspberrypi/linux/issues/3460 Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+") Co-authored-by: James Hughes --- drivers/gpu/drm/v3d/v3d_drv.h | 41 ++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/v3d/v3d_drv.h b/drivers/gpu/drm/v3d/v3d_drv.h index 7b4f3b5a086e..069fefe16d28 100644 --- a/drivers/gpu/drm/v3d/v3d_drv.h +++ b/drivers/gpu/drm/v3d/v3d_drv.h @@ -267,27 +267,42 @@ struct v3d_csd_job { }; /** - * _wait_for - magic (register) wait macro + * __wait_for - magic wait macro * - * Does the right thing for modeset paths when run under kdgb or similar atomic - * contexts. Note that it's important that we check the condition again after - * having timed out, since the timeout could be due to preemption or similar and - * we've never had a chance to check the condition before the timeout. + * Macro to help avoid open coding check/wait/timeout patterns. Note that it's + * important that we check the condition again after having timed out, since the + * timeout could be due to preemption or similar and we've never had a chance to + * check the condition before the timeout. */ -#define wait_for(COND, MS) ({ \ - unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ - int ret__ = 0; \ - while (!(COND)) { \ - if (time_after(jiffies, timeout__)) { \ - if (!(COND)) \ - ret__ = -ETIMEDOUT; \ +#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ + const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ + long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ + int ret__; \ + might_sleep(); \ + for (;;) { \ + const bool expired__ = ktime_after(ktime_get_raw(), end__); \ + OP; \ + /* Guarantee COND check prior to timeout */ \ + barrier(); \ + if (COND) { \ + ret__ = 0; \ break; \ } \ - msleep(1); \ + if (expired__) { \ + ret__ = -ETIMEDOUT; \ + break; \ + } \ + usleep_range(wait__, wait__ * 2); \ + if (wait__ < (Wmax)) \ + wait__ <<= 1; \ } \ ret__; \ }) +#define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ + (Wmax)) +#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) + static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) { /* nsecs_to_jiffies64() does not guard against overflow */ -- Gitee From 0fee9902730aed230e29bd8c1a324e830576f4a8 Mon Sep 17 00:00:00 2001 From: Nick B Date: Mon, 9 Mar 2020 09:05:39 -0400 Subject: [PATCH 04/41] Reduce noise from rpi poe hat fan This adds 2 extra states, at 40c and 45c, with PWM of 31 and 63 (out of 255) for the rpi poe hat fan. This significantly improves user experience by providing a smoother ramp up of the fan, from a pwm 0 to 31 to 63 then finally to 150, and additionally makes it very easy for users to further tweak the values as needed for their specific application. The possible concerns I have are that a hysteresis of 2000 (2c) could be too narrow, and that running the fan more at a reduced temperature (40000 - 40c) could cause problems. Signed-off-by: Nick B --- .../arm/boot/dts/overlays/rpi-poe-overlay.dts | 35 ++++++++++++++++--- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts index 21f8fe6f1229..544038b614e1 100644 --- a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts +++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts @@ -14,9 +14,9 @@ compatible = "raspberrypi,rpi-poe-fan"; firmware = <&firmware>; cooling-min-state = <0>; - cooling-max-state = <2>; + cooling-max-state = <4>; #cooling-cells = <2>; - cooling-levels = <0 150 255>; + cooling-levels = <0 31 63 150 255>; status = "okay"; }; }; @@ -27,12 +27,21 @@ __overlay__ { trips { trip0: trip0 { - temperature = <50000>; - hysteresis = <5000>; + temperature = <40000>; + hysteresis = <2000>; type = "active"; }; trip1: trip1 { - + temperature = <45000>; + hysteresis = <2000>; + type = "active"; + }; + trip2: trip2 { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + trip3: trip3 { temperature = <55000>; hysteresis = <5000>; type = "active"; @@ -47,6 +56,14 @@ trip = <&trip1>; cooling-device = <&fan0 1 2>; }; + map2 { + trip = <&trip2>; + cooling-device = <&fan0 2 3>; + }; + map3 { + trip = <&trip3>; + cooling-device = <&fan0 3 4>; + }; }; }; }; @@ -58,6 +75,10 @@ poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; poe_fan_temp1 = <&trip1>,"temperature:0"; poe_fan_temp1_hyst = <&trip1>,"hysteresis:0"; + poe_fan_temp2 = <&trip2>,"temperature:0"; + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; }; }; @@ -66,5 +87,9 @@ poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; poe_fan_temp1 = <&trip1>,"temperature:0"; poe_fan_temp1_hyst = <&trip1>,"hysteresis:0"; + poe_fan_temp2 = <&trip2>,"temperature:0"; + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; }; }; -- Gitee From 984952e09c3718b8d34d495e4d096249f6307dfe Mon Sep 17 00:00:00 2001 From: Tim Thomson Date: Sun, 16 Feb 2020 11:29:40 +0000 Subject: [PATCH 05/41] arm: bcm2835: Support alternate FIQ drivers Simplify and replace the dwc_otg specific memory maps with a single mapping for the entire SOC I/O range. The I/O range is still resolved from device tree, however the entire I/O range is mapped, rather than the two specific USB ranges. This allows use of alternate I/O drivers utilising FIQ mode. Signed-off-by: Tim Thomson --- arch/arm/mach-bcm/board_bcm2835.c | 49 ++++++++----------------------- 1 file changed, 12 insertions(+), 37 deletions(-) diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 1f60f20bdb0c..f07619fa0260 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -26,8 +26,7 @@ #include "platsmp.h" -#define BCM2835_USB_VIRT_BASE (VMALLOC_START) -#define BCM2835_USB_VIRT_MPHI (VMALLOC_START + 0x10000) +#define BCM2835_VIRT_BASE (VMALLOC_START) static void __init bcm2835_init(void) { @@ -52,44 +51,13 @@ static void __init bcm2835_init(void) * For more background see the following old mailing list thread: * https://www.spinics.net/lists/arm-kernel/msg325250.html */ -static int __init bcm2835_map_usb(unsigned long node, const char *uname, - int depth, void *data) -{ - struct map_desc map[2]; - const __be32 *reg; - int len; - unsigned long p2b_offset = *((unsigned long *) data); - - if (!of_flat_dt_is_compatible(node, "brcm,bcm2708-usb")) - return 0; - reg = of_get_flat_dt_prop(node, "reg", &len); - if (!reg || len != (sizeof(unsigned long) * 4)) - return 0; - - /* Use information about the physical addresses of the - * registers from the device tree, but use legacy - * iotable_init() static mapping function to map them, - * as ioremap() is not functional at this stage in boot. - */ - map[0].virtual = (unsigned long) BCM2835_USB_VIRT_BASE; - map[0].pfn = __phys_to_pfn(be32_to_cpu(reg[0]) - p2b_offset); - map[0].length = be32_to_cpu(reg[1]); - map[0].type = MT_DEVICE; - map[1].virtual = (unsigned long) BCM2835_USB_VIRT_MPHI; - map[1].pfn = __phys_to_pfn(be32_to_cpu(reg[2]) - p2b_offset); - map[1].length = be32_to_cpu(reg[3]); - map[1].type = MT_DEVICE; - iotable_init(map, 2); - - return 1; -} static void __init bcm2835_map_io(void) { const __be32 *ranges, *address_cells; unsigned long root, addr_cells; int soc, len; - unsigned long p2b_offset; + struct map_desc map[1]; debug_ll_io_init(); @@ -105,10 +73,17 @@ static void __init bcm2835_map_io(void) ranges = of_get_flat_dt_prop(soc, "ranges", &len); if (!ranges || len < (sizeof(unsigned long) * (2 + addr_cells))) return; - p2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[addr_cells]); - /* Now search for bcm2708-usb node in device tree */ - of_scan_flat_dt(bcm2835_map_usb, &p2b_offset); + /* Use information about the physical addresses of the + * ranges from the device tree, but use legacy + * iotable_init() static mapping function to map them, + * as ioremap() is not functional at this stage in boot. + */ + map[0].virtual = (unsigned long) BCM2835_VIRT_BASE; + map[0].pfn = __phys_to_pfn(be32_to_cpu(ranges[1])); + map[0].length = be32_to_cpu(ranges[2]); + map[0].type = MT_DEVICE; + iotable_init(map, 1); } static const char * const bcm2835_compat[] = { -- Gitee From dfac571cdf044a2ca2a337f55127887a380d081c Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 31 Mar 2020 13:41:32 +0100 Subject: [PATCH 06/41] Revert "arm: bcm2835: Support alternate FIQ drivers" This reverts commit 21e506ae53d3e1a0a507f759e1f3477bb5fc4df8. --- arch/arm/mach-bcm/board_bcm2835.c | 49 +++++++++++++++++++++++-------- 1 file changed, 37 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index f07619fa0260..1f60f20bdb0c 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -26,7 +26,8 @@ #include "platsmp.h" -#define BCM2835_VIRT_BASE (VMALLOC_START) +#define BCM2835_USB_VIRT_BASE (VMALLOC_START) +#define BCM2835_USB_VIRT_MPHI (VMALLOC_START + 0x10000) static void __init bcm2835_init(void) { @@ -51,13 +52,44 @@ static void __init bcm2835_init(void) * For more background see the following old mailing list thread: * https://www.spinics.net/lists/arm-kernel/msg325250.html */ +static int __init bcm2835_map_usb(unsigned long node, const char *uname, + int depth, void *data) +{ + struct map_desc map[2]; + const __be32 *reg; + int len; + unsigned long p2b_offset = *((unsigned long *) data); + + if (!of_flat_dt_is_compatible(node, "brcm,bcm2708-usb")) + return 0; + reg = of_get_flat_dt_prop(node, "reg", &len); + if (!reg || len != (sizeof(unsigned long) * 4)) + return 0; + + /* Use information about the physical addresses of the + * registers from the device tree, but use legacy + * iotable_init() static mapping function to map them, + * as ioremap() is not functional at this stage in boot. + */ + map[0].virtual = (unsigned long) BCM2835_USB_VIRT_BASE; + map[0].pfn = __phys_to_pfn(be32_to_cpu(reg[0]) - p2b_offset); + map[0].length = be32_to_cpu(reg[1]); + map[0].type = MT_DEVICE; + map[1].virtual = (unsigned long) BCM2835_USB_VIRT_MPHI; + map[1].pfn = __phys_to_pfn(be32_to_cpu(reg[2]) - p2b_offset); + map[1].length = be32_to_cpu(reg[3]); + map[1].type = MT_DEVICE; + iotable_init(map, 2); + + return 1; +} static void __init bcm2835_map_io(void) { const __be32 *ranges, *address_cells; unsigned long root, addr_cells; int soc, len; - struct map_desc map[1]; + unsigned long p2b_offset; debug_ll_io_init(); @@ -73,17 +105,10 @@ static void __init bcm2835_map_io(void) ranges = of_get_flat_dt_prop(soc, "ranges", &len); if (!ranges || len < (sizeof(unsigned long) * (2 + addr_cells))) return; + p2b_offset = be32_to_cpu(ranges[0]) - be32_to_cpu(ranges[addr_cells]); - /* Use information about the physical addresses of the - * ranges from the device tree, but use legacy - * iotable_init() static mapping function to map them, - * as ioremap() is not functional at this stage in boot. - */ - map[0].virtual = (unsigned long) BCM2835_VIRT_BASE; - map[0].pfn = __phys_to_pfn(be32_to_cpu(ranges[1])); - map[0].length = be32_to_cpu(ranges[2]); - map[0].type = MT_DEVICE; - iotable_init(map, 1); + /* Now search for bcm2708-usb node in device tree */ + of_scan_flat_dt(bcm2835_map_usb, &p2b_offset); } static const char * const bcm2835_compat[] = { -- Gitee From 391b52a91ca7fe6bb632b261bf056e579753b22f Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 27 Mar 2020 13:49:25 +0000 Subject: [PATCH 07/41] overlays: Add missing rpi-poe parameters The rpi-poe fan overlay has gained two more fan speeds and adjusted the thresholds and hystereses. Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/README | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index 62ad35f78bad..6c70ec22d2ae 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -2034,12 +2034,20 @@ Name: rpi-poe Info: Raspberry Pi PoE HAT fan Load: dtoverlay=rpi-poe,[=] Params: poe_fan_temp0 Temperature (in millicelcius) at which the fan - turns on (default 50000) + turns on (default 40000) poe_fan_temp0_hyst Temperature delta (in millicelcius) at which - the fan turns off (default 5000) + the fan turns off (default 2000) poe_fan_temp1 Temperature (in millicelcius) at which the fan - speeds up (default 55000) + speeds up (default 45000) poe_fan_temp1_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp2 Temperature (in millicelcius) at which the fan + speeds up (default 50000) + poe_fan_temp2_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 2000) + poe_fan_temp3 Temperature (in millicelcius) at which the fan + speeds up (default 55000) + poe_fan_temp3_hyst Temperature delta (in millicelcius) at which the fan slows down (default 5000) -- Gitee From 33b5f0e00194742962c2b71034f39be48f4745b0 Mon Sep 17 00:00:00 2001 From: Matt Flax Date: Tue, 7 Apr 2020 18:25:42 +1000 Subject: [PATCH 08/41] Add support for the AudioInjector.net Isolated sound card (#3532) This patch adds support for the Audio Injector Isolated sound card. Signed-off-by: Matt Flax --- arch/arm/boot/dts/overlays/Makefile | 1 + arch/arm/boot/dts/overlays/README | 6 + ...dioinjector-isolated-soundcard-overlay.dts | 55 ++++++ arch/arm/configs/bcm2709_defconfig | 1 + arch/arm/configs/bcm2711_defconfig | 1 + arch/arm/configs/bcmrpi_defconfig | 1 + arch/arm64/configs/bcm2711_defconfig | 1 + sound/soc/bcm/Kconfig | 7 + sound/soc/bcm/Makefile | 2 + .../bcm/audioinjector-isolated-soundcard.c | 187 ++++++++++++++++++ 10 files changed, 262 insertions(+) create mode 100644 arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts create mode 100644 sound/soc/bcm/audioinjector-isolated-soundcard.c diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile index 85d8249a2f20..d2e66ab46de5 100644 --- a/arch/arm/boot/dts/overlays/Makefile +++ b/arch/arm/boot/dts/overlays/Makefile @@ -20,6 +20,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \ applepi-dac.dtbo \ at86rf233.dtbo \ audioinjector-addons.dtbo \ + audioinjector-isolated-soundcard.dtbo \ audioinjector-ultra.dtbo \ audioinjector-wm8731-audio.dtbo \ audiosense-pi.dtbo \ diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index 6c70ec22d2ae..905c53ea4ccb 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -505,6 +505,12 @@ Params: non-stop-clocks Keeps the clocks running even when the stream is paused or stopped (default off) +Name: audioinjector-isolated-soundcard +Info: Configures the audioinjector.net isolated soundcard +Load: dtoverlay=audioinjector-isolated-soundcard +Params: + + Name: audioinjector-ultra Info: Configures the audioinjector.net ultra soundcard Load: dtoverlay=audioinjector-ultra diff --git a/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts new file mode 100644 index 000000000000..afc51108e5c8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts @@ -0,0 +1,55 @@ +// Definitions for audioinjector.net audio isolated soundcard +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&i2s>; + __overlay__ { + status = "okay"; + }; + }; + + fragment@1 { + target-path = "/"; + __overlay__ { + cs4272_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + }; + }; + + fragment@2 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + cs4272: cs4272@10 { + #sound-dai-cells = <0>; + compatible = "cirrus,cs4271"; + reg = <0x10>; + reset-gpio = <&gpio 5 0>; + clocks = <&cs4272_mclk>; + clock-names = "mclk"; + status = "okay"; + }; + }; + }; + + fragment@3 { + target = <&sound>; + snd: __overlay__ { + compatible = "ai,audioinjector-isolated-soundcard"; + mute-gpios = <&gpio 17 0>; + i2s-controller = <&i2s>; + codec = <&cs4272>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig index 0683026145eb..f5d42ee3fb82 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig @@ -995,6 +995,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m diff --git a/arch/arm/configs/bcm2711_defconfig b/arch/arm/configs/bcm2711_defconfig index 67f2ba9a773c..54d3c03f4026 100644 --- a/arch/arm/configs/bcm2711_defconfig +++ b/arch/arm/configs/bcm2711_defconfig @@ -1009,6 +1009,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig index ea5dede6bfaa..b769d73c6c4c 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -987,6 +987,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m diff --git a/arch/arm64/configs/bcm2711_defconfig b/arch/arm64/configs/bcm2711_defconfig index 310eeca672b0..a06064221688 100644 --- a/arch/arm64/configs/bcm2711_defconfig +++ b/arch/arm64/configs/bcm2711_defconfig @@ -1002,6 +1002,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig index a17c25115f54..6f5b6cefcb3a 100644 --- a/sound/soc/bcm/Kconfig +++ b/sound/soc/bcm/Kconfig @@ -187,6 +187,13 @@ config SND_AUDIOINJECTOR_OCTO_SOUNDCARD help Say Y or M if you want to add support for audioinjector.net octo add on +config SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD + tristate "Support for audioinjector.net isolated DAC and ADC soundcard" + depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S + select SND_SOC_CS4271_I2C + help + Say Y or M if you want to add support for audioinjector.net isolated soundcard + config SND_AUDIOSENSE_PI tristate "Support for AudioSense Add-On Soundcard" depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S diff --git a/sound/soc/bcm/Makefile b/sound/soc/bcm/Makefile index 254801fc0fea..6557e444837d 100644 --- a/sound/soc/bcm/Makefile +++ b/sound/soc/bcm/Makefile @@ -26,6 +26,7 @@ snd-soc-iqaudio-dac-objs := iqaudio-dac.o snd-soc-i-sabre-q2m-objs := i-sabre-q2m.o snd-soc-audioinjector-pi-soundcard-objs := audioinjector-pi-soundcard.o snd-soc-audioinjector-octo-soundcard-objs := audioinjector-octo-soundcard.o +snd-soc-audioinjector-isolated-soundcard-objs := audioinjector-isolated-soundcard.o snd-soc-audiosense-pi-objs := audiosense-pi.o snd-soc-digidac1-soundcard-objs := digidac1-soundcard.o snd-soc-dionaudio-loco-objs := dionaudio_loco.o @@ -54,6 +55,7 @@ obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o obj-$(CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M) += snd-soc-i-sabre-q2m.o obj-$(CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD) += snd-soc-audioinjector-pi-soundcard.o obj-$(CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD) += snd-soc-audioinjector-octo-soundcard.o +obj-$(CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD) += snd-soc-audioinjector-isolated-soundcard.o obj-$(CONFIG_SND_AUDIOSENSE_PI) += snd-soc-audiosense-pi.o obj-$(CONFIG_SND_DIGIDAC1_SOUNDCARD) += snd-soc-digidac1-soundcard.o obj-$(CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO) += snd-soc-dionaudio-loco.o diff --git a/sound/soc/bcm/audioinjector-isolated-soundcard.c b/sound/soc/bcm/audioinjector-isolated-soundcard.c new file mode 100644 index 000000000000..f71b426d880d --- /dev/null +++ b/sound/soc/bcm/audioinjector-isolated-soundcard.c @@ -0,0 +1,187 @@ +/* + * ASoC Driver for AudioInjector.net isolated soundcard + * + * Created on: 20-February-2020 + * Author: flatmax@flatmax.org + * based on audioinjector-octo-soundcard.c + * + * Copyright (C) 2020 Flatmax Pty. Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include + +static struct gpio_desc *mute_gpio; + +static const unsigned int audioinjector_isolated_rates[] = { + 192000, 96000, 48000, 32000, 24000, 16000, 8000 +}; + +static struct snd_pcm_hw_constraint_list audioinjector_isolated_constraints = { + .list = audioinjector_isolated_rates, + .count = ARRAY_SIZE(audioinjector_isolated_rates), +}; + +static int audioinjector_isolated_dai_init(struct snd_soc_pcm_runtime *rtd) +{ + int ret=snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 24576000, 0); + if (ret) + return ret; + + return snd_soc_dai_set_bclk_ratio(rtd->cpu_dai, 64); +} + +static int audioinjector_isolated_startup(struct snd_pcm_substream *substream) +{ + snd_pcm_hw_constraint_list(substream->runtime, 0, + SNDRV_PCM_HW_PARAM_RATE, &audioinjector_isolated_constraints); + + return 0; +} + +static int audioinjector_isolated_trigger(struct snd_pcm_substream *substream, + int cmd){ + + switch (cmd) { + case SNDRV_PCM_TRIGGER_STOP: + case SNDRV_PCM_TRIGGER_SUSPEND: + case SNDRV_PCM_TRIGGER_PAUSE_PUSH: + gpiod_set_value(mute_gpio, 0); + break; + case SNDRV_PCM_TRIGGER_START: + case SNDRV_PCM_TRIGGER_RESUME: + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: + gpiod_set_value(mute_gpio, 1); + break; + default: + return -EINVAL; + } + return 0; +} + +static struct snd_soc_ops audioinjector_isolated_ops = { + .startup = audioinjector_isolated_startup, + .trigger = audioinjector_isolated_trigger, +}; + +static struct snd_soc_dai_link audioinjector_isolated_dai[] = { + { + .name = "AudioInjector ISO", + .stream_name = "AI-HIFI", + .codec_dai_name = "cs4271-hifi", + .ops = &audioinjector_isolated_ops, + .init = audioinjector_isolated_dai_init, + .symmetric_rates = 1, + .symmetric_channels = 1, + .dai_fmt = SND_SOC_DAIFMT_CBM_CFM|SND_SOC_DAIFMT_I2S|SND_SOC_DAIFMT_NB_NF, + } +}; + +static const struct snd_soc_dapm_widget audioinjector_isolated_widgets[] = { + SND_SOC_DAPM_OUTPUT("OUTPUTS"), + SND_SOC_DAPM_INPUT("INPUTS"), +}; + +static const struct snd_soc_dapm_route audioinjector_isolated_route[] = { + /* Balanced outputs */ + {"OUTPUTS", NULL, "AOUTA+"}, + {"OUTPUTS", NULL, "AOUTA-"}, + {"OUTPUTS", NULL, "AOUTB+"}, + {"OUTPUTS", NULL, "AOUTB-"}, + + /* Balanced inputs */ + {"AINA", NULL, "INPUTS"}, + {"AINB", NULL, "INPUTS"}, +}; + +static struct snd_soc_card snd_soc_audioinjector_isolated = { + .name = "audioinjector-isolated-soundcard", + .dai_link = audioinjector_isolated_dai, + .num_links = ARRAY_SIZE(audioinjector_isolated_dai), + + .dapm_widgets = audioinjector_isolated_widgets, + .num_dapm_widgets = ARRAY_SIZE(audioinjector_isolated_widgets), + .dapm_routes = audioinjector_isolated_route, + .num_dapm_routes = ARRAY_SIZE(audioinjector_isolated_route), +}; + +static int audioinjector_isolated_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card = &snd_soc_audioinjector_isolated; + int ret; + + card->dev = &pdev->dev; + + if (pdev->dev.of_node) { + struct snd_soc_dai_link *dai = &audioinjector_isolated_dai[0]; + struct device_node *i2s_node = + of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); + struct device_node *codec_node = + of_parse_phandle(pdev->dev.of_node, "codec", 0); + + mute_gpio = devm_gpiod_get_optional(&pdev->dev, "mute", GPIOD_OUT_LOW); + if (IS_ERR(mute_gpio)){ + dev_err(&pdev->dev, "mute gpio not found in dt overlay\n"); + return PTR_ERR(mute_gpio); + } + + if (i2s_node && codec_node) { + dai->cpu_dai_name = NULL; + dai->cpu_of_node = i2s_node; + dai->platform_name = NULL; + dai->platform_of_node = i2s_node; + dai->codec_name = NULL; + dai->codec_of_node = codec_node; + } else + if (!i2s_node) { + dev_err(&pdev->dev, + "i2s-controller missing or invalid in DT\n"); + return -EINVAL; + } else { + dev_err(&pdev->dev, + "Property 'codec' missing or invalid\n"); + return -EINVAL; + } + } + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret != 0) + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret); + return ret; +} + +static const struct of_device_id audioinjector_isolated_of_match[] = { + { .compatible = "ai,audioinjector-isolated-soundcard", }, + {}, +}; +MODULE_DEVICE_TABLE(of, audioinjector_isolated_of_match); + +static struct platform_driver audioinjector_isolated_driver = { + .driver = { + .name = "audioinjector-isolated", + .owner = THIS_MODULE, + .of_match_table = audioinjector_isolated_of_match, + }, + .probe = audioinjector_isolated_probe, +}; + +module_platform_driver(audioinjector_isolated_driver); +MODULE_AUTHOR("Matt Flax "); +MODULE_DESCRIPTION("AudioInjector.net isolated Soundcard"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:audioinjector-isolated-soundcard"); -- Gitee From ad9bed27892ed26b480b2170b4139030796314a9 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 8 Apr 2020 10:01:11 +0100 Subject: [PATCH 09/41] configs: Add AUDIOINJECTOR_ISOLATED for Pi3 64-bit Also regenerate the defconfigs, which don't need an explicit SND_SOC_CS4271_I2C=m because the soundcard config enables it. Signed-off-by: Phil Elwell --- arch/arm/configs/bcm2709_defconfig | 1 - arch/arm/configs/bcm2711_defconfig | 1 - arch/arm/configs/bcmrpi_defconfig | 1 - arch/arm64/configs/bcm2711_defconfig | 1 - arch/arm64/configs/bcmrpi3_defconfig | 2 +- 5 files changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig index f5d42ee3fb82..ce78c5f41e15 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig @@ -1013,7 +1013,6 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m diff --git a/arch/arm/configs/bcm2711_defconfig b/arch/arm/configs/bcm2711_defconfig index 54d3c03f4026..fb33e17cc487 100644 --- a/arch/arm/configs/bcm2711_defconfig +++ b/arch/arm/configs/bcm2711_defconfig @@ -1027,7 +1027,6 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig index b769d73c6c4c..6b84db497341 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -1005,7 +1005,6 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m diff --git a/arch/arm64/configs/bcm2711_defconfig b/arch/arm64/configs/bcm2711_defconfig index a06064221688..a78aea612b5d 100644 --- a/arch/arm64/configs/bcm2711_defconfig +++ b/arch/arm64/configs/bcm2711_defconfig @@ -1020,7 +1020,6 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig index bdcab6646d80..78e396a45fed 100644 --- a/arch/arm64/configs/bcmrpi3_defconfig +++ b/arch/arm64/configs/bcmrpi3_defconfig @@ -854,6 +854,7 @@ CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -864,7 +865,6 @@ CONFIG_SND_SOC_AD193X_I2C=m CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m -CONFIG_SND_SOC_CS4271_I2C=m CONFIG_SND_SOC_ICS43432=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m -- Gitee From b95680ed46e8c9e2c4ce5fa02f6c260b4b13a458 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 8 Apr 2020 11:59:39 +0100 Subject: [PATCH 10/41] overlays: Fix dtc warnings in i2c-gpio Better late than never. Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts index 39e7bc5fa9d8..e94053b55610 100644 --- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts @@ -9,6 +9,9 @@ target-path = "/"; __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + i2c_gpio: i2c@0 { reg = <0xffffffff>; compatible = "i2c-gpio"; -- Gitee From a28363d5c0c2770f68dce54d75eda06ac2cc7c24 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Thu, 13 Jun 2019 04:49:26 -0400 Subject: [PATCH 11/41] media: rc: IR signal for Panasonic air conditioner too long [ Upstream commit 5c4c8b4a999019f19e770cb55cbacb89c95897bd ] The IR signal to control the Panasonic ACXA75C00600 air conditioner has 439 pulse/spaces. Increase limit to make it possible to transmit signal. Reported-by: Takashi Kanamaru Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab --- drivers/media/rc/lirc_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c index f862f1b7f996..d6f5f5b3f75f 100644 --- a/drivers/media/rc/lirc_dev.c +++ b/drivers/media/rc/lirc_dev.c @@ -29,7 +29,7 @@ #include "rc-core-priv.h" #include -#define LIRCBUF_SIZE 256 +#define LIRCBUF_SIZE 1024 static dev_t lirc_base_dev; -- Gitee From e807feacb80c7e03168a9549620404406655471e Mon Sep 17 00:00:00 2001 From: AMuszkat Date: Wed, 8 Apr 2020 09:31:39 +0200 Subject: [PATCH 12/41] configs: add MA120X0P codec Signed-off-by: AMuszkat --- arch/arm/configs/bcm2709_defconfig | 1 + arch/arm/configs/bcm2711_defconfig | 1 + arch/arm/configs/bcmrpi_defconfig | 1 + arch/arm64/configs/bcm2711_defconfig | 1 + arch/arm64/configs/bcmrpi3_defconfig | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig index ce78c5f41e15..4fd6bcc8b2bb 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig @@ -1014,6 +1014,7 @@ CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm/configs/bcm2711_defconfig b/arch/arm/configs/bcm2711_defconfig index fb33e17cc487..4d3edbacb8fc 100644 --- a/arch/arm/configs/bcm2711_defconfig +++ b/arch/arm/configs/bcm2711_defconfig @@ -1028,6 +1028,7 @@ CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig index 6b84db497341..65b0a035a0f2 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -1006,6 +1006,7 @@ CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm64/configs/bcm2711_defconfig b/arch/arm64/configs/bcm2711_defconfig index a78aea612b5d..a876f527b195 100644 --- a/arch/arm64/configs/bcm2711_defconfig +++ b/arch/arm64/configs/bcm2711_defconfig @@ -1021,6 +1021,7 @@ CONFIG_SND_SOC_ADAU7002=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_SPDIF=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig index 78e396a45fed..63e0cc8ab89f 100644 --- a/arch/arm64/configs/bcmrpi3_defconfig +++ b/arch/arm64/configs/bcmrpi3_defconfig @@ -866,6 +866,7 @@ CONFIG_SND_SOC_ADAU1701=m CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m CONFIG_HIDRAW=y -- Gitee From 54498bf0d1b449a416fd0da6654ebb0e7bd0729b Mon Sep 17 00:00:00 2001 From: AMuszkat Date: Wed, 8 Apr 2020 10:04:49 +0200 Subject: [PATCH 13/41] ASoC: ma120x0p: Add 96KHz rate support Add 96KHz rate support to MA120X0P codec and make enable and mute gpio pins optional. Signed-off-by: AMuszkat --- sound/soc/codecs/ma120x0p.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/ma120x0p.c b/sound/soc/codecs/ma120x0p.c index 39c74b17e007..e1591b6aff43 100644 --- a/sound/soc/codecs/ma120x0p.c +++ b/sound/soc/codecs/ma120x0p.c @@ -1002,7 +1002,7 @@ static struct snd_soc_dai_driver ma120x0p_dai = { .channels_max = 2, .rates = SNDRV_PCM_RATE_CONTINUOUS, .rate_min = 44100, - .rate_max = 48000, + .rate_max = 96000, .formats = SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE }, .ops = &ma120x0p_dai_ops, @@ -1235,7 +1235,7 @@ static int ma120x0p_i2c_probe(struct i2c_client *i2c, //Startup sequence //Make sure the device is muted - priv_data->mute_gpio = devm_gpiod_get(&i2c->dev, "mute_gp", + priv_data->mute_gpio = devm_gpiod_get_optional(&i2c->dev, "mute_gp", GPIOD_OUT_LOW); if (IS_ERR(priv_data->mute_gpio)) { ret = PTR_ERR(priv_data->mute_gpio); @@ -1262,7 +1262,7 @@ static int ma120x0p_i2c_probe(struct i2c_client *i2c, msleep(200); //Enable ma120x0pp - priv_data->enable_gpio = devm_gpiod_get(&i2c->dev, + priv_data->enable_gpio = devm_gpiod_get_optional(&i2c->dev, "enable_gp", GPIOD_OUT_LOW); if (IS_ERR(priv_data->enable_gpio)) { ret = PTR_ERR(priv_data->enable_gpio); -- Gitee From a50a00068788e737154fbf40acb62c48f6adc869 Mon Sep 17 00:00:00 2001 From: James Hilliard Date: Fri, 10 Apr 2020 19:24:40 -0600 Subject: [PATCH 14/41] drm/vc4: hdmi: Silence pixel clock error on -EPROBE_DEFER If the vc4 hdmi driver loads before the pixel clock is available we see a spurious "*ERROR* Failed to get pixel clock" error. Signed-off-by: James Hilliard --- drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index 9dc0fc6b8a2a..5e9d6582cf62 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -1349,8 +1349,10 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) hdmi->pixel_clock = devm_clk_get(dev, "pixel"); if (IS_ERR(hdmi->pixel_clock)) { - DRM_ERROR("Failed to get pixel clock\n"); - return PTR_ERR(hdmi->pixel_clock); + ret = PTR_ERR(hdmi->pixel_clock); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Failed to get pixel clock\n"); + return ret; } hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); if (IS_ERR(hdmi->hsm_clock)) { -- Gitee From 803957b2bd7be7986f7a360149fe02fb1f3c42f9 Mon Sep 17 00:00:00 2001 From: James Hilliard Date: Fri, 10 Apr 2020 20:23:13 -0600 Subject: [PATCH 15/41] component: Silence bind error on -EPROBE_DEFER If a component fails to bind due to -EPROBE_DEFER we should not log an error as this is not a real failure. Fixes: vc4-drm soc:gpu: failed to bind 3f902000.hdmi (ops vc4_hdmi_ops): -517 vc4-drm soc:gpu: master bind failed: -517 Signed-off-by: James Hilliard --- drivers/base/component.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/base/component.c b/drivers/base/component.c index e8d676fad0c9..684c5b70ef31 100644 --- a/drivers/base/component.c +++ b/drivers/base/component.c @@ -235,7 +235,8 @@ static int try_to_bring_up_master(struct master *master, ret = master->ops->bind(master->dev); if (ret < 0) { devres_release_group(master->dev, NULL); - dev_info(master->dev, "master bind failed: %d\n", ret); + if (ret != -EPROBE_DEFER) + dev_info(master->dev, "master bind failed: %d\n", ret); return ret; } @@ -506,8 +507,9 @@ static int component_bind(struct component *component, struct master *master, devres_release_group(component->dev, NULL); devres_release_group(master->dev, NULL); - dev_err(master->dev, "failed to bind %s (ops %ps): %d\n", - dev_name(component->dev), component->ops, ret); + if (ret != -EPROBE_DEFER) + dev_err(master->dev, "failed to bind %s (ops %ps): %d\n", + dev_name(component->dev), component->ops, ret); } return ret; -- Gitee From 4603d2b072173192afd410028609e9fbc153152a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=B6rg=20Schambacher?= Date: Wed, 15 Apr 2020 11:48:29 +0200 Subject: [PATCH 16/41] Fixes a problem with clock settings of HiFiBerry DAC+ADC PRO (#3545) This patch fixes a problem of the re-calculation of i2s-clock and -parameter settings when only the ADC is activated. Signed-off-by: Joerg Schambacher --- sound/soc/bcm/hifiberry_dacplusadcpro.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/sound/soc/bcm/hifiberry_dacplusadcpro.c b/sound/soc/bcm/hifiberry_dacplusadcpro.c index 75fc8f010421..2f83dbee3f9f 100644 --- a/sound/soc/bcm/hifiberry_dacplusadcpro.c +++ b/sound/soc/bcm/hifiberry_dacplusadcpro.c @@ -390,9 +390,11 @@ static int snd_rpi_hifiberry_dacplusadcpro_hw_params( int channels = params_channels(params); int width = 32; struct snd_soc_component *dac = rtd->codec_dais[0]->component; + struct snd_soc_dai *dai = rtd->codec_dais[0]; + struct snd_soc_dai_driver *drv = dai->driver; + const struct snd_soc_dai_ops *ops = drv->ops; if (snd_rpi_hifiberry_is_dacpro) { - width = snd_pcm_format_physical_width(params_format(params)); snd_rpi_hifiberry_dacplusadcpro_set_sclk(dac, @@ -414,6 +416,11 @@ static int snd_rpi_hifiberry_dacplusadcpro_hw_params( return ret; ret = snd_soc_dai_set_tdm_slot(rtd->codec_dais[1], 0x03, 0x03, channels, width); + if (ret) + return ret; + + if (snd_rpi_hifiberry_is_dacpro && ops->hw_params) + ret = ops->hw_params(substream, params, dai); return ret; } -- Gitee From 1d62c3d6a94697c29a1f79bc3b5f39ed7af475bb Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Tue, 4 Feb 2020 12:51:56 +0000 Subject: [PATCH 17/41] ARM: dts: Extend SCB bus address range Signed-off-by: Phil Elwell --- arch/arm/boot/dts/bcm2838.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi index 0f54f0586069..36d250d7053b 100644 --- a/arch/arm/boot/dts/bcm2838.dtsi +++ b/arch/arm/boot/dts/bcm2838.dtsi @@ -316,7 +316,9 @@ <0x0 0x40000000 0x0 0xff800000 0x00800000>, <0x6 0x00000000 0x6 0x00000000 0x40000000>, <0x0 0x00000000 0x0 0x00000000 0xfc000000>; - dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>, + <0x1 0x00000000 0x1 0x00000000 0x80000000>, + <0x1 0x80000000 0x1 0x80000000 0x80000000>; pcie_0: pcie@7d500000 { reg = <0x0 0x7d500000 0x9310>, -- Gitee From 781f0f5183a3db9b514b81374658b778e227c8b3 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 5 Dec 2019 18:02:08 +0000 Subject: [PATCH 18/41] dts: bcm2711: Move emmc2 to its own "bus" Moving the EMMC2 controller under a dedicated bus allows the firmware to patch the dma-ranges property for different memory sizes without affecting anything else. Signed-off-by: Phil Elwell --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index fabd02e5863d..b452e9785946 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -31,6 +31,28 @@ /delete-property/ intc; ethernet0 = &genet; pcie0 = &pcie_0; + emmc2bus = &emmc2bus; + }; +}; + +/delete-node/ &emmc2; + +/ { + emmc2bus: emmc2bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + + ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>; + dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x3c000000>; + + emmc2: emmc2@7e340000 { + compatible = "brcm,bcm2711-emmc2"; + status = "okay"; + interrupts = ; + clocks = <&clocks BCM2711_CLOCK_EMMC2>; + reg = <0x0 0x7e340000 0x100>; + }; }; }; -- Gitee From 72dd070ad94c6e9642fd5216c419496128d8e6cd Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 15 Apr 2020 20:58:22 +0100 Subject: [PATCH 19/41] dts: bcm2711: Restore emmc2 regulator, brokencd Signed-off-by: Phil Elwell --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index b452e9785946..5cd6c7bd344a 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -52,6 +52,8 @@ interrupts = ; clocks = <&clocks BCM2711_CLOCK_EMMC2>; reg = <0x0 0x7e340000 0x100>; + vqmmc-supply = <&sd_io_1v8_reg>; + broken-cd; }; }; }; -- Gitee From 7b88d53af4374318b7f38b3b8c8b05c918b2676d Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 30 Apr 2020 12:41:59 +0100 Subject: [PATCH 20/41] dmaengine: bcm2835: Fix 40-bit DMA support Signed-off-by: Phil Elwell --- drivers/dma/bcm2835-dma.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c index 03a9d08dd5a9..6dbe1525b973 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c @@ -536,7 +536,8 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( /* link this the last controlblock */ if (frame && c->is_40bit_channel) - d->cb_list[frame - 1].cb->next = + ((struct bcm2838_dma40_scb *) + d->cb_list[frame - 1].cb)->next_cb = to_bcm2838_cbaddr(cb_entry->paddr); if (frame && !c->is_40bit_channel) d->cb_list[frame - 1].cb->next = cb_entry->paddr; @@ -587,12 +588,13 @@ static void bcm2835_dma_fill_cb_chain_with_sg( max_len = bcm2835_dma_max_frame_length(c); for_each_sg(sgl, sgent, sg_len, i) { if (c->is_40bit_channel) { - struct bcm2838_dma40_scb *scb = - (struct bcm2838_dma40_scb *)cb->cb; + struct bcm2838_dma40_scb *scb; + for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent); - len > 0; - addr += scb->len, len -= scb->len, scb++) { + len > 0; + addr += scb->len, len -= scb->len, cb++) { + scb = (struct bcm2838_dma40_scb *)cb->cb; if (direction == DMA_DEV_TO_MEM) { scb->dst = lower_32_bits(addr); scb->dsti = upper_32_bits(addr) | BCM2838_DMA40_INC; @@ -700,9 +702,7 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) * if this IRQ handler is threaded.) If the channel is finished, it * will remain idle despite the ACTIVE flag being set. */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | - (c->is_40bit_channel ? BCM2838_DMA40_CS_FLAGS(c->dreq) : - BCM2835_DMA_CS_FLAGS(c->dreq)), + writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); d = c->desc; -- Gitee From 7db85bacdabef16a95612a372961989f6145a9d6 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 30 Apr 2020 12:43:05 +0100 Subject: [PATCH 21/41] ARM: dts: bcm2711: Allow 40-bit DMA for SPI Add the spi_dma4 DT parameter to enable use of the 40-bit DMA channels to drive SPI. Note that there are only 3-4 40-bit channels available, and using this parameter claims 2 of them. Usage: dtparam=spi_dma4 Signed-off-by: Phil Elwell --- arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 2 ++ arch/arm/boot/dts/overlays/README | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 5cd6c7bd344a..42259dbf3919 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -365,5 +365,7 @@ eth_led1 = <&phy1>,"led-modes:4"; sd_poll_once = <&emmc2>, "non-removable?"; + spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, + <&spi0>, "dmas:8=", <&dma40>; }; }; diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index 905c53ea4ccb..ef99bb081b42 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -159,6 +159,10 @@ Params: spi Set to "on" to enable the spi interfaces (default "off") + spi_dma4 Use to enable 40-bit DMA on spi interfaces + (the assigned value doesn't matter) + (2711 only) + random Set to "on" to enable the hardware random number generator (default "on") -- Gitee From f2fb5e52697ba8a4d31484ea571fbe65825791c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 30 Apr 2020 19:40:07 +0200 Subject: [PATCH 22/41] overlays: gpio-shutdown: Add information for SysV init / inittab KeyboardSignal and kb::kbrequest can be used to call /sbin/shutdown --- arch/arm/boot/dts/overlays/README | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index ef99bb081b42..a41b638456f4 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -842,6 +842,7 @@ Params: gpiopin GPIO for signalling (default 26) Name: gpio-shutdown Info: Initiates a shutdown when GPIO pin changes. The given GPIO pin is configured as an input key that generates KEY_POWER events. + This event is handled by systemd-logind by initiating a shutdown. Systemd versions older than 225 need an udev rule enable listening to the input device: @@ -850,6 +851,29 @@ Info: Initiates a shutdown when GPIO pin changes. The given GPIO pin SUBSYSTEMS=="platform", DRIVERS=="gpio-keys", \ ATTRS{keys}=="116", TAG+="power-switch" + Alternatively this event can be handled also on systems without + systemd, just by traditional SysV init daemon. KEY_POWER event + (keycode 116) needs to be mapped to KeyboardSignal on console + and then kb::kbrequest inittab action which is triggered by + KeyboardSignal from console can be configured to issue system + shutdown. Steps for this configuration are: + + Add following lines to the /etc/console-setup/remap.inc file: + + # Key Power as special keypress + keycode 116 = KeyboardSignal + + Then add following lines to /etc/inittab file: + + # Action on special keypress (Key Power) + kb::kbrequest:/sbin/shutdown -t1 -a -h -P now + + And finally reload configuration by calling following commands: + + # dpkg-reconfigure console-setup + # service console-setup reload + # init q + This overlay only handles shutdown. After shutdown, the system can be powered up again by driving GPIO3 low. The default configuration uses GPIO3 with a pullup, so if you connect a -- Gitee From 945cfc490d3efae60185424da5303c1db0a84a21 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 30 Apr 2020 19:41:10 +0200 Subject: [PATCH 23/41] overlays: gpio-shutdown: Add information for Raspberry Pi 1 Model B rev 1 Raspberry Pi 1 Model B rev 1 uses GPIO1 for power-up instead of GPIO3. --- arch/arm/boot/dts/overlays/README | 10 ++++++++-- arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts | 6 ++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index a41b638456f4..54b195f52bb8 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -878,9 +878,14 @@ Info: Initiates a shutdown when GPIO pin changes. The given GPIO pin can be powered up again by driving GPIO3 low. The default configuration uses GPIO3 with a pullup, so if you connect a button between GPIO3 and GND (pin 5 and 6 on the 40-pin header), - you get a shutdown and power-up button. + you get a shutdown and power-up button. Please note that + Raspberry Pi 1 Model B rev 1 uses GPIO1 instead of GPIO3. Load: dtoverlay=gpio-shutdown,= Params: gpio_pin GPIO pin to trigger on (default 3) + For Raspberry Pi 1 Model B rev 1 set this + explicitly to value 1, e.g.: + + dtoverlay=gpio-shutdown,gpio_pin=1 active_low When this is 1 (active low), a falling edge generates a key down event and a @@ -892,7 +897,8 @@ Params: gpio_pin GPIO pin to trigger on (default 3) Default is "up". Note that the default pin (GPIO3) has an - external pullup. + external pullup. Same applies for GPIO1 + on Raspberry Pi 1 Model B rev 1. debounce Specify the debounce interval in milliseconds (default 100) diff --git a/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts index db07ba67781d..0a27595143ec 100644 --- a/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts +++ b/arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts @@ -4,7 +4,9 @@ // This overlay sets up an input device that generates KEY_POWER events // when a given GPIO pin changes. It defaults to using GPIO3, which can -// also be used to wake up (start) the Rpi again after shutdown. Since +// also be used to wake up (start) the Rpi again after shutdown. +// Raspberry Pi 1 Model B rev 1 can be wake up only by GPIO1 pin, so for +// these boards change default GPIO pin to 1 via gpio_pin parameter. Since // wakeup is active-low, this defaults to active-low with a pullup // enabled, but all of this can be changed using overlay parameters (but // note that GPIO3 has an external pullup on at least some boards). @@ -71,7 +73,7 @@ // Allow changing the internal pullup/down state. 0 = none, 1 = pulldown, 2 = pullup // Note that GPIO3 and GPIO2 are the I2c pins and have an external pullup (at least - // on some boards). + // on some boards). Same applies for GPIO1 on Raspberry Pi 1 Model B rev 1. gpio_pull = <&pin_state>,"brcm,pull:0"; // Allow setting the active_low flag. 0 = active high, 1 = active low -- Gitee From 787cecd86de4060a159c97a59ed433336d3c0428 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 30 Apr 2020 14:47:55 +0200 Subject: [PATCH 24/41] ALSA: usb-audio: Correct a typo of NuPrime DAC-10 USB ID commit 547d2c9cf4f1f72adfecacbd5b093681fb0e8b3e upstream. The USB vendor ID of NuPrime DAC-10 is not 16b0 but 16d0. Fixes: f656891c6619 ("ALSA: usb-audio: add more quirks for DSD interfaces") Cc: Link: https://lore.kernel.org/r/20200430124755.15940-1-tiwai@suse.de Signed-off-by: Takashi Iwai --- sound/usb/quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c index bc70212031df..257a38407ee2 100644 --- a/sound/usb/quirks.c +++ b/sound/usb/quirks.c @@ -1383,7 +1383,7 @@ u64 snd_usb_interface_dsd_format_quirks(struct snd_usb_audio *chip, case USB_ID(0x0d8c, 0x0316): /* Hegel HD12 DSD */ case USB_ID(0x10cb, 0x0103): /* The Bit Opus #3; with fp->dsd_raw */ - case USB_ID(0x16b0, 0x06b2): /* NuPrime DAC-10 */ + case USB_ID(0x16d0, 0x06b2): /* NuPrime DAC-10 */ case USB_ID(0x16d0, 0x09dd): /* Encore mDSD */ case USB_ID(0x16d0, 0x0733): /* Furutech ADL Stratos */ case USB_ID(0x16d0, 0x09db): /* NuPrime Audio DAC-9 */ -- Gitee From 2babc9bbb05b1c167025f0b2801b8d50ee3c333a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 1 May 2020 17:56:13 +0100 Subject: [PATCH 25/41] overlays: Make the i2c-gpio overlay safe again Like many overlays, the i2c-gpio overlay goes to efforts to avoid generating warnings about #address-cells and #size-cells not being defined, which it does by defining them. Unfortunately this is fatal if they don't match what the system requires, which is the case on BCM2711 with #address-cells = 2. In the absence of the knowledge of a clean way to fix this, just delete the declarations and suffer the warnings. Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts index e94053b55610..39e7bc5fa9d8 100644 --- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts @@ -9,9 +9,6 @@ target-path = "/"; __overlay__ { - #address-cells = <1>; - #size-cells = <0>; - i2c_gpio: i2c@0 { reg = <0xffffffff>; compatible = "i2c-gpio"; -- Gitee From bae33d0b87789387b865699eb881f2a3dc569b2d Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Sat, 2 May 2020 13:43:06 +0100 Subject: [PATCH 26/41] overlays: gpio-keys: Avoid open-drain warnings The i2c-gpio driver expects to use a GPIO in open-drain mode. Failure to configure it in that way causes alarming warnings in the kernel log. The BCM283x and BCM2711 GPIO blocks don't support open-drain mode, but i2c-gpio works anyway. Silence the warning by declaring that open-drain mode has been enabled by other means. See: https://github.com/raspberrypi/firmware/issues/1381 Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts index 39e7bc5fa9d8..def139db8bcb 100644 --- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts @@ -16,6 +16,8 @@ &gpio 24 0 /* scl */ >; i2c-gpio,delay-us = <2>; /* ~100 kHz */ + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; #address-cells = <1>; #size-cells = <0>; }; -- Gitee From 48b66ba594e03ea14dc00641b4922eccabe18d0d Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Wed, 6 May 2020 14:25:20 +0100 Subject: [PATCH 27/41] overlays: sc16is752-spi1: Add xtal parameter The other sc16is75x overlays have an xtal parameter to allow a different crystal frequency to be specified, but sc16is752-spi1 doesn't. Fix this omission. See: https://www.raspberrypi.org/forums/viewtopic.php?f=107&t=273234 Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/README | 1 + arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index 54b195f52bb8..fbbeb28e88ba 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -2143,6 +2143,7 @@ Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface Load: dtoverlay=sc16is752-spi1,= Params: int_pin GPIO used for IRQ (default 24) + xtal On-board crystal frequency (default 14745600) Name: sdhost diff --git a/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts index 4e33b14afc78..131d3ab43d3a 100644 --- a/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts +++ b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts @@ -56,6 +56,7 @@ }; __overrides__ { - int_pin = <&sc16is752>,"interrupts:0"; + int_pin = <&sc16is752>,"interrupts:0"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; }; }; -- Gitee From f38c6cb758ab1bf3761b39e3c2644e0a88ac4ab7 Mon Sep 17 00:00:00 2001 From: bjorn Date: Thu, 7 May 2020 05:11:43 +0200 Subject: [PATCH 28/41] overlays: Add spi0 overlay to support sc16is752 Signed-off-by: Bjorn --- arch/arm/boot/dts/overlays/Makefile | 1 + arch/arm/boot/dts/overlays/README | 8 ++++ .../dts/overlays/sc16is752-spi0-overlay.dts | 44 +++++++++++++++++++ 3 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile index d2e66ab46de5..9863b50ad6da 100644 --- a/arch/arm/boot/dts/overlays/Makefile +++ b/arch/arm/boot/dts/overlays/Makefile @@ -144,6 +144,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \ rra-digidac1-wm8741-audio.dtbo \ sc16is750-i2c.dtbo \ sc16is752-i2c.dtbo \ + sc16is752-spi0.dtbo \ sc16is752-spi1.dtbo \ sdhost.dtbo \ sdio.dtbo \ diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README index fbbeb28e88ba..aced2cd3c084 100644 --- a/arch/arm/boot/dts/overlays/README +++ b/arch/arm/boot/dts/overlays/README @@ -2135,6 +2135,14 @@ Params: int_pin GPIO used for IRQ (default 24) xtal On-board crystal frequency (default 14745600) +Name: sc16is752-spi0 +Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface + Enables the chip on SPI0. +Load: dtoverlay=sc16is752-spi0,= +Params: int_pin GPIO used for IRQ (default 24) + xtal On-board crystal frequency (default 14745600) + + Name: sc16is752-spi1 Info: Overlay for the NXP SC16IS752 Dual UART with SPI Interface Enables the chip on SPI1. diff --git a/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts new file mode 100644 index 000000000000..ccce7ad599bc --- /dev/null +++ b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts @@ -0,0 +1,44 @@ +/dts-v1/; +/plugin/; + +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { + target = <&spi0>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sc16is752: sc16is752@0 { + compatible = "nxp,sc16is752"; + reg = <0>; /* CE0 */ + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ + #gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <4000000>; + + sc16is752_clk: sc16is752_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <14745600>; + }; + }; + }; + }; + + fragment@1 { + target = <&spidev0>; + __overlay__ { + status = "disabled"; + }; + }; + + __overrides__ { + int_pin = <&sc16is752>,"interrupts:0"; + xtal = <&sc16is752_clk>, "clock-frequency:0"; + }; +}; -- Gitee From a9e95d3d0cde27e7af8b06ae7788fb71d5cf59d4 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Sun, 24 Nov 2019 16:40:48 -0600 Subject: [PATCH 29/41] net: rtl8192cu: fix gcc misleading whitespace warning This fixes a gcc warning about misleading whitespace. Signed-off-by: David Lechner --- .../wireless/realtek/rtl8192cu/core/rtw_security.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c b/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c index 8fa8ed51b721..bdd9c73cba3f 100644 --- a/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c +++ b/drivers/net/wireless/realtek/rtl8192cu/core/rtw_security.c @@ -1502,10 +1502,10 @@ _func_enter_; /* Insert MIC into payload */ for (j = 0; j < 8; j++) - pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; + pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; - payload_index = hdrlen + 8; - for (i=0; i< num_blocks; i++) + payload_index = hdrlen + 8; + for (i=0; i< num_blocks; i++) { construct_ctr_preload( ctr_preload, @@ -1876,10 +1876,10 @@ _func_enter_; /* Insert MIC into payload */ for (j = 0; j < 8; j++) - message[payload_index+j] = mic[j]; + message[payload_index+j] = mic[j]; - payload_index = hdrlen + 8; - for (i=0; i< num_blocks; i++) + payload_index = hdrlen + 8; + for (i=0; i< num_blocks; i++) { construct_ctr_preload( ctr_preload, -- Gitee From c01e7af4ab496eecd9c6d1b7c19367ee991f90fb Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 29 May 2020 14:41:13 +0100 Subject: [PATCH 30/41] overlays: i2c-rtc: Fix trickle-resistor-ohms param The abx80x implementation of the trickle-resistor-ohms parameter is missing the ":0" indicating that the target is an integer/cell value. See: https://github.com/raspberrypi/linux/issues/3642 Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts index 5df390b52a7b..24c86974b0db 100644 --- a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts @@ -229,7 +229,7 @@ <&m41t62>, "reg:0"; trickle-diode-type = <&abx80x>,"abracon,tc-diode"; trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0", - <&abx80x>,"abracon,tc-resistor", + <&abx80x>,"abracon,tc-resistor:0", <&rv3028>,"trickle-resistor-ohms:0"; backup-switchover-mode = <&rv3028>,"backup-switchover-mode:0"; wakeup-source = <&ds1339>,"wakeup-source?", -- Gitee From f47f0da1869cff62055fbe2faaef86de494d1073 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 29 May 2020 16:55:12 +0100 Subject: [PATCH 31/41] overlays: i2c-rtc-gpio: Fix trickle-resistor-ohms param The abx80x implementation of the trickle-resistor-ohms parameter is missing the ":0" indicating that the target is an integer/cell value. See: https://github.com/raspberrypi/linux/issues/3642 Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts index 44df77459520..125bd77fff0a 100644 --- a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts @@ -230,7 +230,7 @@ trickle-diode-type = <&abx80x>,"abracon,tc-diode"; trickle-resistor-ohms = <&ds1339>,"trickle-resistor-ohms:0", - <&abx80x>,"abracon,tc-resistor", + <&abx80x>,"abracon,tc-resistor:0", <&rv3028>,"trickle-resistor-ohms:0"; backup-switchover-mode = <&rv3028>,"backup-switchover-mode:0"; wakeup-source = <&ds1339>,"wakeup-source?", -- Gitee From ef310db4fdde7ce1f19c91dd031c134b319d18bd Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 5 Jun 2020 16:31:12 +0100 Subject: [PATCH 32/41] Revert "overlays: gpio-keys: Avoid open-drain warnings" This reverts commit 1d2d8a944f9dcbec9c64cc299c4b5e00d12dc098. --- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts index def139db8bcb..39e7bc5fa9d8 100644 --- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts @@ -16,8 +16,6 @@ &gpio 24 0 /* scl */ >; i2c-gpio,delay-us = <2>; /* ~100 kHz */ - i2c-gpio,sda-open-drain; - i2c-gpio,scl-open-drain; #address-cells = <1>; #size-cells = <0>; }; -- Gitee From 5d8761abb86105639a6323ce5649c3e98a1e52ac Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 5 Jun 2020 16:07:07 +0100 Subject: [PATCH 33/41] overlays: i2c-gpio: Avoid open-drain warnings The i2c-gpio driver expects to use a GPIO in open-drain mode. Failure to configure it in that way causes alarming warnings in the kernel log. The BCM283x and BCM2711 GPIO blocks don't support open-drain mode, but gpiolib can emulate it in software if configured correctly. Silence the warning by declaring the GPIOs as requiring open-drain mode, trusting gpiolib to manage the emulation. The previous incarnation of this patch took the other approach of telling the i2c-gpio driver that the GPIOs were configured for open-drain, but this had the effect of disabling the emulation. In some cases this appears to work, but examining the waveforms as analogue voltages shows contention, the success or failure depending on drive strengths. See: https://github.com/raspberrypi/firmware/issues/1381 See: https://github.com/raspberrypi/firmware/issues/1401 Signed-off-by: Phil Elwell --- arch/arm/boot/dts/overlays/balena-fin-overlay.dts | 5 ++++- arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts | 6 ++++-- arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts | 6 ++++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/overlays/balena-fin-overlay.dts b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts index 249c8202b2ed..e7ead7cdf5f5 100644 --- a/arch/arm/boot/dts/overlays/balena-fin-overlay.dts +++ b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts @@ -1,6 +1,8 @@ /dts-v1/; /plugin/; +#include + /{ compatible = "brcm,bcm2835"; @@ -48,7 +50,8 @@ i2c_soft: i2c@0 { compatible = "i2c-gpio"; - gpios = <&gpio 43 0 /* sda */ &gpio 42 0 /* scl */>; + gpios = <&gpio 43 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 42 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */>; i2c-gpio,delay-us = <5>; i2c-gpio,scl-open-drain; i2c-gpio,sda-open-drain; diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts index 39e7bc5fa9d8..63231b5d7c0c 100644 --- a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts @@ -2,6 +2,8 @@ /dts-v1/; /plugin/; +#include + / { compatible = "brcm,bcm2835"; @@ -12,8 +14,8 @@ i2c_gpio: i2c@0 { reg = <0xffffffff>; compatible = "i2c-gpio"; - gpios = <&gpio 23 0 /* sda */ - &gpio 24 0 /* scl */ + gpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */ >; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts index 125bd77fff0a..2ce968a5b2d6 100644 --- a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts +++ b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts @@ -3,6 +3,8 @@ /dts-v1/; /plugin/; +#include + / { compatible = "brcm,bcm2835"; @@ -11,8 +13,8 @@ __overlay__ { i2c_gpio: i2c-gpio-rtc@0 { compatible = "i2c-gpio"; - gpios = <&gpio 23 0 /* sda */ - &gpio 24 0 /* scl */ + gpios = <&gpio 23 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */ + &gpio 24 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */ >; i2c-gpio,delay-us = <2>; /* ~100 kHz */ #address-cells = <1>; -- Gitee From 93d9c960400686adbd359b70e7f5c2d48736844f Mon Sep 17 00:00:00 2001 From: Markus Proeller Date: Tue, 16 Jun 2020 13:24:31 +0200 Subject: [PATCH 34/41] media: irs1125: Using i2c_transfer for ic2 reads Reading data over i2c is done by using i2c_transfer to ensure that this operation can't be interrupted. Signed-off-by: Markus Proeller --- drivers/media/i2c/irs1125.c | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/drivers/media/i2c/irs1125.c b/drivers/media/i2c/irs1125.c index 25e1dd5a08ef..6680afea5894 100644 --- a/drivers/media/i2c/irs1125.c +++ b/drivers/media/i2c/irs1125.c @@ -248,27 +248,34 @@ static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val) static int irs1125_read(struct v4l2_subdev *sd, u16 reg, u16 *val) { - int ret; - unsigned char data_w[2] = { reg >> 8, reg & 0xff }; - char rdval[2]; - struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_msg msgs[2]; + u8 addr_buf[2] = { reg >> 8, reg & 0xff }; + u8 data_buf[2] = { 0, }; + int ret; - ret = i2c_master_send(client, data_w, 2); - if (ret < 0) { - dev_dbg(&client->dev, "%s: i2c write error, reg: %x\n", - __func__, reg); + /* Write register address */ + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = ARRAY_SIZE(addr_buf); + msgs[0].buf = addr_buf; + + /* Read data from register */ + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = 2; + msgs[1].buf = data_buf; + + ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs)); + if (ret != ARRAY_SIZE(msgs)) { + if (ret >= 0) + ret = -EIO; return ret; } - ret = i2c_master_recv(client, rdval, 2); - if (ret < 0) - dev_err(&client->dev, "%s: i2c read error, reg: %x\n", - __func__, reg); - - *val = rdval[1] | (rdval[0] << 8); + *val = data_buf[1] | (data_buf[0] << 8); - return ret; + return 0; } static int irs1125_write_array(struct v4l2_subdev *sd, -- Gitee From 705c78e998908a11db256e26c2d74b27edea3cc5 Mon Sep 17 00:00:00 2001 From: Markus Proeller Date: Tue, 16 Jun 2020 13:27:42 +0200 Subject: [PATCH 35/41] media: irs1125: Refactoring and debug messages Changed some variable names to comply with checkpatch --strict mode. Debug messages added. Signed-off-by: Markus Proeller --- drivers/media/i2c/irs1125.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/media/i2c/irs1125.c b/drivers/media/i2c/irs1125.c index 6680afea5894..289f0c25b141 100644 --- a/drivers/media/i2c/irs1125.c +++ b/drivers/media/i2c/irs1125.c @@ -15,6 +15,7 @@ #include "irs1125.h" #include #include +#include #include #include #include @@ -22,13 +23,13 @@ #include #include #include +#include #include -#include +#include #include #include #include #include -#include #define CHECK_BIT(val, pos) ((val) & BIT(pos)) @@ -38,18 +39,19 @@ #define IRS1125_ALTERNATE_FW "irs1125_af.bin" -#define IRS1125_REG_CSICFG 0xA882 -#define IRS1125_REG_DESIGN_STEP 0xB0AD -#define IRS1125_REG_EFUSEVAL2 0xB09F -#define IRS1125_REG_EFUSEVAL3 0xB0A0 -#define IRS1125_REG_EFUSEVAL4 0xB0A1 -#define IRS1125_REG_DMEM_SHADOW 0xC320 +#define IRS1125_REG_SAFE_RECONFIG 0xA850 +#define IRS1125_REG_CSICFG 0xA882 +#define IRS1125_REG_DESIGN_STEP 0xB0AD +#define IRS1125_REG_EFUSEVAL2 0xB09F +#define IRS1125_REG_EFUSEVAL3 0xB0A0 +#define IRS1125_REG_EFUSEVAL4 0xB0A1 +#define IRS1125_REG_DMEM_SHADOW 0xC320 -#define IRS1125_DESIGN_STEP_EXPECTED 0x0a12 +#define IRS1125_DESIGN_STEP_EXPECTED 0x0a12 #define IRS1125_ROW_START_DEF 0 #define IRS1125_COLUMN_START_DEF 0 -#define IRS1125_WINDOW_HEIGHT_DEF 288 +#define IRS1125_WINDOW_HEIGHT_DEF 288 #define IRS1125_WINDOW_WIDTH_DEF 352 struct regval_list { @@ -87,7 +89,7 @@ static inline struct irs1125 *to_state(struct v4l2_subdev *sd) return container_of(sd, struct irs1125, sd); } -static struct regval_list irs1125_26MHz[] = { +static struct regval_list irs1125_26mhz[] = { {0xB017, 0x0413}, {0xB086, 0x3535}, {0xB0AE, 0xEF02}, @@ -153,7 +155,7 @@ static struct regval_list irs1125_26MHz[] = { {0xFFFF, 100} }; -static struct regval_list irs1125_seq_cfg[] = { +static struct regval_list irs1125_seq_cfg_init[] = { {0xC3A0, 0x823D}, {0xC3A1, 0xB13B}, {0xC3A2, 0x0313}, @@ -243,6 +245,7 @@ static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val) dev_err(&client->dev, "%s: i2c write error, reg: %x\n", __func__, reg); + dev_dbg(&client->dev, "write addr 0x%04x, val 0x%04x\n", reg, val); return ret; } @@ -364,8 +367,8 @@ static int __sensor_init(struct v4l2_subdev *sd) cnt++; } - ret = irs1125_write_array(sd, irs1125_26MHz, - ARRAY_SIZE(irs1125_26MHz)); + ret = irs1125_write_array(sd, irs1125_26mhz, + ARRAY_SIZE(irs1125_26mhz)); if (ret < 0) { dev_err(&client->dev, "write sensor default regs error\n"); return ret; @@ -415,8 +418,8 @@ static int __sensor_init(struct v4l2_subdev *sd) } release_firmware(fw); - ret = irs1125_write_array(sd, irs1125_seq_cfg, - ARRAY_SIZE(irs1125_seq_cfg)); + ret = irs1125_write_array(sd, irs1125_seq_cfg_init, + ARRAY_SIZE(irs1125_seq_cfg_init)); if (ret < 0) { dev_err(&client->dev, "write default sequence failed\n"); return ret; @@ -1037,6 +1040,7 @@ static int irs1125_probe(struct i2c_client *client, } gpio_num = desc_to_gpio(sensor->reset); + dev_dbg(&client->dev, "reset on GPIO num %d\n", gpio_num); mutex_init(&sensor->lock); -- Gitee From 151b399c22474725a06fc0e84a1b95ab25028694 Mon Sep 17 00:00:00 2001 From: Markus Proeller Date: Tue, 16 Jun 2020 13:31:36 +0200 Subject: [PATCH 36/41] media: irs1125: Atomic access to imager reconfiguration Instead of changing the exposure and framerate settings for all sequences, they can be changed for every sequence individually now. Therefore the IRS1125_CID_SAFE_RECONFIG ctrl has been removed and replaced by IRS1125_CID_SAFE_RECONFIG_S_EXPO and *_FRAME ctrls. The consistency check in the sequence ctrl IRS1125_CID_SEQ_CONFIG is removed. Signed-off-by: Markus Proeller --- drivers/media/i2c/irs1125.c | 224 ++++++++++++++++++++++++------------ drivers/media/i2c/irs1125.h | 68 ++++++++--- 2 files changed, 204 insertions(+), 88 deletions(-) diff --git a/drivers/media/i2c/irs1125.c b/drivers/media/i2c/irs1125.c index 289f0c25b141..d59e05004a03 100644 --- a/drivers/media/i2c/irs1125.c +++ b/drivers/media/i2c/irs1125.c @@ -89,6 +89,52 @@ static inline struct irs1125 *to_state(struct v4l2_subdev *sd) return container_of(sd, struct irs1125, sd); } +static const char *expo_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = { + "safe reconfiguration of exposure of sequence 0", + "safe reconfiguration of exposure of sequence 1", + "safe reconfiguration of exposure of sequence 2", + "safe reconfiguration of exposure of sequence 3", + "safe reconfiguration of exposure of sequence 4", + "safe reconfiguration of exposure of sequence 5", + "safe reconfiguration of exposure of sequence 6", + "safe reconfiguration of exposure of sequence 7", + "safe reconfiguration of exposure of sequence 8", + "safe reconfiguration of exposure of sequence 9", + "safe reconfiguration of exposure of sequence 10", + "safe reconfiguration of exposure of sequence 11", + "safe reconfiguration of exposure of sequence 12", + "safe reconfiguration of exposure of sequence 13", + "safe reconfiguration of exposure of sequence 14", + "safe reconfiguration of exposure of sequence 15", + "safe reconfiguration of exposure of sequence 16", + "safe reconfiguration of exposure of sequence 17", + "safe reconfiguration of exposure of sequence 18", + "safe reconfiguration of exposure of sequence 19", +}; + +static const char *frame_ctrl_names[IRS1125_NUM_SEQ_ENTRIES] = { + "safe reconfiguration of framerate of sequence 0", + "safe reconfiguration of framerate of sequence 1", + "safe reconfiguration of framerate of sequence 2", + "safe reconfiguration of framerate of sequence 3", + "safe reconfiguration of framerate of sequence 4", + "safe reconfiguration of framerate of sequence 5", + "safe reconfiguration of framerate of sequence 6", + "safe reconfiguration of framerate of sequence 7", + "safe reconfiguration of framerate of sequence 8", + "safe reconfiguration of framerate of sequence 9", + "safe reconfiguration of framerate of sequence 10", + "safe reconfiguration of framerate of sequence 11", + "safe reconfiguration of framerate of sequence 12", + "safe reconfiguration of framerate of sequence 13", + "safe reconfiguration of framerate of sequence 14", + "safe reconfiguration of framerate of sequence 15", + "safe reconfiguration of framerate of sequence 16", + "safe reconfiguration of framerate of sequence 17", + "safe reconfiguration of framerate of sequence 18", + "safe reconfiguration of framerate of sequence 19", +}; + static struct regval_list irs1125_26mhz[] = { {0xB017, 0x0413}, {0xB086, 0x3535}, @@ -561,36 +607,57 @@ static int irs1125_s_ctrl(struct v4l2_ctrl *ctrl) struct irs1125 *dev = container_of(ctrl->handler, struct irs1125, ctrl_handler); struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); - int err, i; struct irs1125_mod_pll *mod_cur, *mod_new; - struct irs1125_seq_cfg *cfg_cur, *cfg_new; u16 addr, val; - - err = 0; + int err = 0, i; switch (ctrl->id) { - case IRS1125_CID_SAFE_RECONFIG: - { - struct irs1125_illu *illu_cur, *illu_new; - - illu_new = (struct irs1125_illu *)ctrl->p_new.p; - illu_cur = (struct irs1125_illu *)ctrl->p_cur.p; - for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { - if (illu_cur[i].exposure != illu_new[i].exposure) { - addr = 0xA850 + i * 2; - val = illu_new[i].exposure; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (illu_cur[i].framerate != illu_new[i].framerate) { - addr = 0xA851 + i * 2; - val = illu_new[i].framerate; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - } + case IRS1125_CID_SAFE_RECONFIG_S0_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S0_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S1_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S1_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S2_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S2_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S3_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S3_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S4_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S4_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S5_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S5_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S6_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S6_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S7_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S7_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S8_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S8_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S9_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S9_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S10_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S10_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S11_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S11_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S12_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S12_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S13_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S13_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S14_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S14_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S15_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S15_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S16_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S16_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S17_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S17_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S18_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S18_FRAME: + case IRS1125_CID_SAFE_RECONFIG_S19_EXPO: + case IRS1125_CID_SAFE_RECONFIG_S19_FRAME: { + unsigned int offset = ctrl->id - + IRS1125_CID_SAFE_RECONFIG_S0_EXPO; + + err = irs1125_write(&dev->sd, + IRS1125_REG_SAFE_RECONFIG + offset, + ctrl->val); break; } case IRS1125_CID_MOD_PLL: @@ -655,40 +722,40 @@ static int irs1125_s_ctrl(struct v4l2_ctrl *ctrl) } } break; - case IRS1125_CID_SEQ_CONFIG: + case IRS1125_CID_SEQ_CONFIG: { + struct irs1125_seq_cfg *cfg_new; + cfg_new = (struct irs1125_seq_cfg *)ctrl->p_new.p; - cfg_cur = (struct irs1125_seq_cfg *)ctrl->p_cur.p; for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { - if (cfg_cur[i].exposure != cfg_new[i].exposure) { - addr = IRS1125_REG_DMEM_SHADOW + i * 4; - val = cfg_new[i].exposure; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (cfg_cur[i].framerate != cfg_new[i].framerate) { - addr = IRS1125_REG_DMEM_SHADOW + 1 + i * 4; - val = cfg_new[i].framerate; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (cfg_cur[i].ps != cfg_new[i].ps) { - addr = IRS1125_REG_DMEM_SHADOW + 2 + i * 4; - val = cfg_new[i].ps; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (cfg_cur[i].pll != cfg_new[i].pll) { - addr = IRS1125_REG_DMEM_SHADOW + 3 + i * 4; - val = cfg_new[i].pll; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } + unsigned int seq_offset = i * 4; + u16 addr, val; + + addr = IRS1125_REG_DMEM_SHADOW + seq_offset; + val = cfg_new[i].exposure; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; + + addr = IRS1125_REG_DMEM_SHADOW + 1 + seq_offset; + val = cfg_new[i].framerate; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; + + addr = IRS1125_REG_DMEM_SHADOW + 2 + seq_offset; + val = cfg_new[i].ps; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; + + addr = IRS1125_REG_DMEM_SHADOW + 3 + seq_offset; + val = cfg_new[i].pll; + err = irs1125_write(&dev->sd, addr, val); + if (err < 0) + break; } break; + } case IRS1125_CID_NUM_SEQS: err = irs1125_write(&dev->sd, 0xA88D, ctrl->val - 1); if (err >= 0) @@ -758,19 +825,6 @@ static const struct v4l2_ctrl_config irs1125_custom_ctrls[] = { .elem_size = sizeof(u16), .dims = {sizeof(struct irs1125_mod_pll) / sizeof(u16), IRS1125_NUM_MOD_PLLS} - }, { - .ops = &irs1125_ctrl_ops, - .id = IRS1125_CID_SAFE_RECONFIG, - .name = "Change exposure and pause of single seq", - .type = V4L2_CTRL_TYPE_U16, - .flags = V4L2_CTRL_FLAG_HAS_PAYLOAD, - .min = 0, - .max = U16_MAX, - .step = 1, - .def = 0, - .elem_size = sizeof(u16), - .dims = {sizeof(struct irs1125_illu) / sizeof(u16), - IRS1125_NUM_SEQ_ENTRIES} }, { .ops = &irs1125_ctrl_ops, .id = IRS1125_CID_SEQ_CONFIG, @@ -900,9 +954,16 @@ static int irs1125_ctrls_init(struct irs1125 *sensor, struct device *dev) { struct v4l2_ctrl *ctrl; int err, i; - struct v4l2_ctrl_handler *hdl; + struct v4l2_ctrl_handler *hdl = &sensor->ctrl_handler; + struct v4l2_ctrl_config ctrl_cfg = { + .ops = &irs1125_ctrl_ops, + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = U16_MAX, + .step = 1, + .def = 0x1000 + }; - hdl = &sensor->ctrl_handler; v4l2_ctrl_handler_init(hdl, ARRAY_SIZE(irs1125_custom_ctrls)); for (i = 0; i < ARRAY_SIZE(irs1125_custom_ctrls); i++) { @@ -923,6 +984,27 @@ static int irs1125_ctrls_init(struct irs1125 *sensor, struct device *dev) goto error_ctrls; } + for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { + ctrl_cfg.name = expo_ctrl_names[i]; + ctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_EXPO + i * 2; + ctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg, + NULL); + if (!ctrl) + dev_err(dev, "Failed to init exposure control %s\n", + ctrl_cfg.name); + } + + ctrl_cfg.def = 0; + for (i = 0; i < IRS1125_NUM_SEQ_ENTRIES; i++) { + ctrl_cfg.name = frame_ctrl_names[i]; + ctrl_cfg.id = IRS1125_CID_SAFE_RECONFIG_S0_FRAME + i * 2; + ctrl = v4l2_ctrl_new_custom(hdl, &ctrl_cfg, + NULL); + if (!ctrl) + dev_err(dev, "Failed to init framerate control %s\n", + ctrl_cfg.name); + } + sensor->sd.ctrl_handler = hdl; return 0; diff --git a/drivers/media/i2c/irs1125.h b/drivers/media/i2c/irs1125.h index dccaca23aa76..96d676123d5e 100644 --- a/drivers/media/i2c/irs1125.h +++ b/drivers/media/i2c/irs1125.h @@ -21,18 +21,57 @@ #define IRS1125_NUM_SEQ_ENTRIES 20 #define IRS1125_NUM_MOD_PLLS 4 -#define IRS1125_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0xf000) -#define IRS1125_CID_SAFE_RECONFIG (IRS1125_CID_CUSTOM_BASE + 0) -#define IRS1125_CID_CONTINUOUS_TRIG (IRS1125_CID_CUSTOM_BASE + 1) -#define IRS1125_CID_TRIGGER (IRS1125_CID_CUSTOM_BASE + 2) -#define IRS1125_CID_RECONFIG (IRS1125_CID_CUSTOM_BASE + 3) -#define IRS1125_CID_ILLU_ON (IRS1125_CID_CUSTOM_BASE + 4) -#define IRS1125_CID_NUM_SEQS (IRS1125_CID_CUSTOM_BASE + 5) -#define IRS1125_CID_MOD_PLL (IRS1125_CID_CUSTOM_BASE + 6) -#define IRS1125_CID_SEQ_CONFIG (IRS1125_CID_CUSTOM_BASE + 7) -#define IRS1125_CID_IDENT0 (IRS1125_CID_CUSTOM_BASE + 8) -#define IRS1125_CID_IDENT1 (IRS1125_CID_CUSTOM_BASE + 9) -#define IRS1125_CID_IDENT2 (IRS1125_CID_CUSTOM_BASE + 10) +#define IRS1125_CID_CUSTOM_BASE (V4L2_CID_USER_BASE | 0xf000) +#define IRS1125_CID_CONTINUOUS_TRIG (IRS1125_CID_CUSTOM_BASE + 1) +#define IRS1125_CID_TRIGGER (IRS1125_CID_CUSTOM_BASE + 2) +#define IRS1125_CID_RECONFIG (IRS1125_CID_CUSTOM_BASE + 3) +#define IRS1125_CID_ILLU_ON (IRS1125_CID_CUSTOM_BASE + 4) +#define IRS1125_CID_NUM_SEQS (IRS1125_CID_CUSTOM_BASE + 5) +#define IRS1125_CID_MOD_PLL (IRS1125_CID_CUSTOM_BASE + 6) +#define IRS1125_CID_SEQ_CONFIG (IRS1125_CID_CUSTOM_BASE + 7) +#define IRS1125_CID_IDENT0 (IRS1125_CID_CUSTOM_BASE + 8) +#define IRS1125_CID_IDENT1 (IRS1125_CID_CUSTOM_BASE + 9) +#define IRS1125_CID_IDENT2 (IRS1125_CID_CUSTOM_BASE + 10) +#define IRS1125_CID_SAFE_RECONFIG_S0_EXPO (IRS1125_CID_CUSTOM_BASE + 11) +#define IRS1125_CID_SAFE_RECONFIG_S0_FRAME (IRS1125_CID_CUSTOM_BASE + 12) +#define IRS1125_CID_SAFE_RECONFIG_S1_EXPO (IRS1125_CID_CUSTOM_BASE + 13) +#define IRS1125_CID_SAFE_RECONFIG_S1_FRAME (IRS1125_CID_CUSTOM_BASE + 14) +#define IRS1125_CID_SAFE_RECONFIG_S2_EXPO (IRS1125_CID_CUSTOM_BASE + 15) +#define IRS1125_CID_SAFE_RECONFIG_S2_FRAME (IRS1125_CID_CUSTOM_BASE + 16) +#define IRS1125_CID_SAFE_RECONFIG_S3_EXPO (IRS1125_CID_CUSTOM_BASE + 17) +#define IRS1125_CID_SAFE_RECONFIG_S3_FRAME (IRS1125_CID_CUSTOM_BASE + 18) +#define IRS1125_CID_SAFE_RECONFIG_S4_EXPO (IRS1125_CID_CUSTOM_BASE + 19) +#define IRS1125_CID_SAFE_RECONFIG_S4_FRAME (IRS1125_CID_CUSTOM_BASE + 20) +#define IRS1125_CID_SAFE_RECONFIG_S5_EXPO (IRS1125_CID_CUSTOM_BASE + 21) +#define IRS1125_CID_SAFE_RECONFIG_S5_FRAME (IRS1125_CID_CUSTOM_BASE + 22) +#define IRS1125_CID_SAFE_RECONFIG_S6_EXPO (IRS1125_CID_CUSTOM_BASE + 23) +#define IRS1125_CID_SAFE_RECONFIG_S6_FRAME (IRS1125_CID_CUSTOM_BASE + 24) +#define IRS1125_CID_SAFE_RECONFIG_S7_EXPO (IRS1125_CID_CUSTOM_BASE + 25) +#define IRS1125_CID_SAFE_RECONFIG_S7_FRAME (IRS1125_CID_CUSTOM_BASE + 26) +#define IRS1125_CID_SAFE_RECONFIG_S8_EXPO (IRS1125_CID_CUSTOM_BASE + 27) +#define IRS1125_CID_SAFE_RECONFIG_S8_FRAME (IRS1125_CID_CUSTOM_BASE + 28) +#define IRS1125_CID_SAFE_RECONFIG_S9_EXPO (IRS1125_CID_CUSTOM_BASE + 29) +#define IRS1125_CID_SAFE_RECONFIG_S9_FRAME (IRS1125_CID_CUSTOM_BASE + 30) +#define IRS1125_CID_SAFE_RECONFIG_S10_EXPO (IRS1125_CID_CUSTOM_BASE + 31) +#define IRS1125_CID_SAFE_RECONFIG_S10_FRAME (IRS1125_CID_CUSTOM_BASE + 32) +#define IRS1125_CID_SAFE_RECONFIG_S11_EXPO (IRS1125_CID_CUSTOM_BASE + 33) +#define IRS1125_CID_SAFE_RECONFIG_S11_FRAME (IRS1125_CID_CUSTOM_BASE + 34) +#define IRS1125_CID_SAFE_RECONFIG_S12_EXPO (IRS1125_CID_CUSTOM_BASE + 35) +#define IRS1125_CID_SAFE_RECONFIG_S12_FRAME (IRS1125_CID_CUSTOM_BASE + 36) +#define IRS1125_CID_SAFE_RECONFIG_S13_EXPO (IRS1125_CID_CUSTOM_BASE + 37) +#define IRS1125_CID_SAFE_RECONFIG_S13_FRAME (IRS1125_CID_CUSTOM_BASE + 38) +#define IRS1125_CID_SAFE_RECONFIG_S14_EXPO (IRS1125_CID_CUSTOM_BASE + 39) +#define IRS1125_CID_SAFE_RECONFIG_S14_FRAME (IRS1125_CID_CUSTOM_BASE + 40) +#define IRS1125_CID_SAFE_RECONFIG_S15_EXPO (IRS1125_CID_CUSTOM_BASE + 41) +#define IRS1125_CID_SAFE_RECONFIG_S15_FRAME (IRS1125_CID_CUSTOM_BASE + 42) +#define IRS1125_CID_SAFE_RECONFIG_S16_EXPO (IRS1125_CID_CUSTOM_BASE + 43) +#define IRS1125_CID_SAFE_RECONFIG_S16_FRAME (IRS1125_CID_CUSTOM_BASE + 44) +#define IRS1125_CID_SAFE_RECONFIG_S17_EXPO (IRS1125_CID_CUSTOM_BASE + 45) +#define IRS1125_CID_SAFE_RECONFIG_S17_FRAME (IRS1125_CID_CUSTOM_BASE + 46) +#define IRS1125_CID_SAFE_RECONFIG_S18_EXPO (IRS1125_CID_CUSTOM_BASE + 47) +#define IRS1125_CID_SAFE_RECONFIG_S18_FRAME (IRS1125_CID_CUSTOM_BASE + 48) +#define IRS1125_CID_SAFE_RECONFIG_S19_EXPO (IRS1125_CID_CUSTOM_BASE + 49) +#define IRS1125_CID_SAFE_RECONFIG_S19_FRAME (IRS1125_CID_CUSTOM_BASE + 50) struct irs1125_seq_cfg { __u16 exposure; @@ -41,11 +80,6 @@ struct irs1125_seq_cfg { __u16 pll; }; -struct irs1125_illu { - __u16 exposure; - __u16 framerate; -}; - struct irs1125_mod_pll { __u16 pllcfg1; __u16 pllcfg2; -- Gitee From 4d7c8e1a571599e864ff7fa0c9054313d9529ff4 Mon Sep 17 00:00:00 2001 From: Markus Proeller Date: Tue, 16 Jun 2020 13:33:56 +0200 Subject: [PATCH 37/41] media: irs1125: Keep HW in sync after imager reset When closing the video device, the irs1125 is put in power down state. To keep V4L2 ctrls and the HW in sync, v4l2_ctrl_handler_setup is called after power up. The compound ctrl IRS1125_CID_MOD_PLL however has a default value of all zeros, which puts the imager into a non responding state. Thus, this ctrl is not written by the driver into HW after power up. The userspace has to take care to write senseful data. Signed-off-by: Markus Proeller --- drivers/media/i2c/irs1125.c | 121 +++++++++++++++++------------------- 1 file changed, 58 insertions(+), 63 deletions(-) diff --git a/drivers/media/i2c/irs1125.c b/drivers/media/i2c/irs1125.c index d59e05004a03..30c3d2640386 100644 --- a/drivers/media/i2c/irs1125.c +++ b/drivers/media/i2c/irs1125.c @@ -82,6 +82,7 @@ struct irs1125 { struct v4l2_ctrl *ctrl_numseq; int power_count; + bool mod_pll_init; }; static inline struct irs1125 *to_state(struct v4l2_subdev *sd) @@ -276,8 +277,7 @@ static struct regval_list irs1125_seq_cfg_init[] = { {0xC039, 0x0000}, {0xC401, 0x0002}, - {0xFFFF, 1}, - {0xA87C, 0x0001} + {0xFFFF, 1} }; static int irs1125_write(struct v4l2_subdev *sd, u16 reg, u16 val) @@ -471,7 +471,11 @@ static int __sensor_init(struct v4l2_subdev *sd) return ret; } - return 0; + irs1125->mod_pll_init = true; + v4l2_ctrl_handler_setup(&irs1125->ctrl_handler); + irs1125->mod_pll_init = false; + + return irs1125_write(sd, 0xA87C, 0x0001); } static int irs1125_sensor_power(struct v4l2_subdev *sd, int on) @@ -607,8 +611,6 @@ static int irs1125_s_ctrl(struct v4l2_ctrl *ctrl) struct irs1125 *dev = container_of(ctrl->handler, struct irs1125, ctrl_handler); struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); - struct irs1125_mod_pll *mod_cur, *mod_new; - u16 addr, val; int err = 0, i; switch (ctrl->id) { @@ -660,68 +662,61 @@ static int irs1125_s_ctrl(struct v4l2_ctrl *ctrl) ctrl->val); break; } - case IRS1125_CID_MOD_PLL: + case IRS1125_CID_MOD_PLL: { + struct irs1125_mod_pll *mod_new; + + if (dev->mod_pll_init) + break; + mod_new = (struct irs1125_mod_pll *)ctrl->p_new.p; - mod_cur = (struct irs1125_mod_pll *)ctrl->p_cur.p; for (i = 0; i < IRS1125_NUM_MOD_PLLS; i++) { - if (mod_cur[i].pllcfg1 != mod_new[i].pllcfg1) { - addr = 0xC3A0 + i * 3; - val = mod_new[i].pllcfg1; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg2 != mod_new[i].pllcfg2) { - addr = 0xC3A1 + i * 3; - val = mod_new[i].pllcfg2; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg3 != mod_new[i].pllcfg3) { - addr = 0xC3A2 + i * 3; - val = mod_new[i].pllcfg3; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg4 != mod_new[i].pllcfg4) { - addr = 0xC24C + i * 5; - val = mod_new[i].pllcfg4; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg5 != mod_new[i].pllcfg5) { - addr = 0xC24D + i * 5; - val = mod_new[i].pllcfg5; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg6 != mod_new[i].pllcfg6) { - addr = 0xC24E + i * 5; - val = mod_new[i].pllcfg6; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg7 != mod_new[i].pllcfg7) { - addr = 0xC24F + i * 5; - val = mod_new[i].pllcfg7; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } - if (mod_cur[i].pllcfg8 != mod_new[i].pllcfg8) { - addr = 0xC250 + i * 5; - val = mod_new[i].pllcfg8; - err = irs1125_write(&dev->sd, addr, val); - if (err < 0) - break; - } + unsigned int pll_offset, ssc_offset; + + pll_offset = i * 3; + ssc_offset = i * 5; + + err = irs1125_write(&dev->sd, 0xC3A0 + pll_offset, + mod_new[i].pllcfg1); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC3A1 + pll_offset, + mod_new[i].pllcfg2); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC3A2 + pll_offset, + mod_new[i].pllcfg3); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24C + ssc_offset, + mod_new[i].pllcfg4); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24D + ssc_offset, + mod_new[i].pllcfg5); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24E + ssc_offset, + mod_new[i].pllcfg6); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC24F + ssc_offset, + mod_new[i].pllcfg7); + if (err < 0) + break; + + err = irs1125_write(&dev->sd, 0xC250 + ssc_offset, + mod_new[i].pllcfg8); + if (err < 0) + break; } break; + } case IRS1125_CID_SEQ_CONFIG: { struct irs1125_seq_cfg *cfg_new; -- Gitee From 7a6ff62e987a90e32c855e44ad0ada710780d238 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Tue, 4 Feb 2020 15:50:41 +0100 Subject: [PATCH 38/41] irqchip/bcm2835: Quiesce IRQs left enabled by bootloader [ Upstream commit bd59b343a9c902c522f006e6d71080f4893bbf42 ] Per the spec, the BCM2835's IRQs are all disabled when coming out of power-on reset. Its IRQ driver assumes that's still the case when the kernel boots and does not perform any initialization of the registers. However the Raspberry Pi Foundation's bootloader leaves the USB interrupt enabled when handing over control to the kernel. Quiesce IRQs and the FIQ if they were left enabled and log a message to let users know that they should update the bootloader once a fixed version is released. If the USB interrupt is not quiesced and the USB driver later on claims the FIQ (as it does on the Raspberry Pi Foundation's downstream kernel), interrupt latency for all other peripherals increases and occasional lockups occur. That's because both the FIQ and the normal USB interrupt fire simultaneously: On a multicore Raspberry Pi, if normal interrupts are routed to CPU 0 and the FIQ to CPU 1 (hardcoded in the Foundation's kernel), then a USB interrupt causes CPU 0 to spin in bcm2836_chained_handle_irq() until the FIQ on CPU 1 has cleared it. Other peripherals' interrupts are starved as long. I've seen CPU 0 blocked for up to 2.9 msec. eMMC throughput on a Compute Module 3 irregularly dips to 23.0 MB/s without this commit but remains relatively constant at 23.5 MB/s with this commit. The lockups occur when CPU 0 receives a USB interrupt while holding a lock which CPU 1 is trying to acquire while the FIQ is temporarily disabled on CPU 1. At best users get RCU CPU stall warnings, but most of the time the system just freezes. Fixes: 89214f009c1d ("ARM: bcm2835: add interrupt controller driver") Signed-off-by: Lukas Wunner Signed-off-by: Marc Zyngier Reviewed-by: Florian Fainelli Reviewed-by: Nicolas Saenz Julienne Link: https://lore.kernel.org/r/f97868ba4e9b86ddad71f44ec9d8b3b7d8daa1ea.1582618537.git.lukas@wunner.de --- drivers/irqchip/irq-bcm2835.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c index 72abca2bac3a..1d8ceb2a4b90 100644 --- a/drivers/irqchip/irq-bcm2835.c +++ b/drivers/irqchip/irq-bcm2835.c @@ -76,8 +76,7 @@ #define ARM_LOCAL_GPU_INT_ROUTING 0x0c #define REG_FIQ_CONTROL 0x0c -#define REG_FIQ_ENABLE 0x80 -#define REG_FIQ_DISABLE 0 +#define FIQ_CONTROL_ENABLE BIT(7) #define NR_BANKS 3 #define IRQS_PER_BANK 32 @@ -125,7 +124,7 @@ static inline unsigned int hwirq_to_fiq(unsigned long hwirq) static void armctrl_mask_irq(struct irq_data *d) { if (d->hwirq >= NUMBER_IRQS) - writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); + writel_relaxed(0, intc.base + REG_FIQ_CONTROL); else writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); @@ -152,7 +151,7 @@ static void armctrl_unmask_irq(struct irq_data *d) ARM_LOCAL_GPU_INT_ROUTING); } - writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), + writel_relaxed(FIQ_CONTROL_ENABLE | hwirq_to_fiq(d->hwirq), intc.base + REG_FIQ_CONTROL); } else { writel_relaxed(HWIRQ_BIT(d->hwirq), @@ -210,6 +209,7 @@ static int __init armctrl_of_init(struct device_node *node, { void __iomem *base; int irq = 0, last_irq, b, i; + u32 reg; base = of_iomap(node, 0); if (!base) @@ -233,6 +233,19 @@ static int __init armctrl_of_init(struct device_node *node, handle_level_irq); irq_set_probe(irq); } + + reg = readl_relaxed(intc.enable[b]); + if (reg) { + writel_relaxed(reg, intc.disable[b]); + pr_err(FW_BUG "Bootloader left irq enabled: " + "bank %d irq %*pbl\n", b, IRQS_PER_BANK, ®); + } + } + + reg = readl_relaxed(base + REG_FIQ_CONTROL); + if (reg & FIQ_CONTROL_ENABLE) { + writel_relaxed(0, base + REG_FIQ_CONTROL); + pr_err(FW_BUG "Bootloader left fiq enabled\n"); } last_irq = irq; -- Gitee From 5a551a546efd67bfeba0cc8599889ebcc3d1b69c Mon Sep 17 00:00:00 2001 From: digital Date: Fri, 26 Jun 2020 17:30:49 +0200 Subject: [PATCH 39/41] Enable nf_tables support for aarch64 --- arch/arm64/configs/bcmrpi3_defconfig | 44 ++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig index 63e0cc8ab89f..d66d80f95c00 100644 --- a/arch/arm64/configs/bcmrpi3_defconfig +++ b/arch/arm64/configs/bcmrpi3_defconfig @@ -132,6 +132,33 @@ CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m CONFIG_NF_CT_NETLINK=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_SET=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m CONFIG_NETFILTER_XT_SET=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -220,6 +247,14 @@ CONFIG_IP_VS_SED=m CONFIG_IP_VS_NQ=m CONFIG_IP_VS_FTP=m CONFIG_IP_VS_PE_SIP=m +CONFIG_NFT_CHAIN_ROUTE_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=m +CONFIG_NFT_CHAIN_NAT_IPV4=m +CONFIG_NFT_MASQ_IPV4=m +CONFIG_NFT_REDIR_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -239,6 +274,12 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_CHAIN_ROUTE_IPV6=m +CONFIG_NFT_CHAIN_NAT_IPV6=m +CONFIG_NFT_MASQ_IPV6=m +CONFIG_NFT_REDIR_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m @@ -257,6 +298,9 @@ CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NF_LOG_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m -- Gitee From 7344ce8782698e80f17027814948025aea1b5dbc Mon Sep 17 00:00:00 2001 From: Matt Flax Date: Fri, 17 Jul 2020 08:38:10 +1000 Subject: [PATCH 40/41] Mute bug fix for Audioinjector.net isolated soundcard. --- .../bcm/audioinjector-isolated-soundcard.c | 27 +++---------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/sound/soc/bcm/audioinjector-isolated-soundcard.c b/sound/soc/bcm/audioinjector-isolated-soundcard.c index f71b426d880d..6b9ae9051bd2 100644 --- a/sound/soc/bcm/audioinjector-isolated-soundcard.c +++ b/sound/soc/bcm/audioinjector-isolated-soundcard.c @@ -42,41 +42,21 @@ static int audioinjector_isolated_dai_init(struct snd_soc_pcm_runtime *rtd) int ret=snd_soc_dai_set_sysclk(rtd->codec_dai, 0, 24576000, 0); if (ret) return ret; - return snd_soc_dai_set_bclk_ratio(rtd->cpu_dai, 64); } static int audioinjector_isolated_startup(struct snd_pcm_substream *substream) { + struct snd_soc_pcm_runtime *rtd = substream->private_data; snd_pcm_hw_constraint_list(substream->runtime, 0, - SNDRV_PCM_HW_PARAM_RATE, &audioinjector_isolated_constraints); - - return 0; -} + SNDRV_PCM_HW_PARAM_RATE, &audioinjector_isolated_constraints); -static int audioinjector_isolated_trigger(struct snd_pcm_substream *substream, - int cmd){ - - switch (cmd) { - case SNDRV_PCM_TRIGGER_STOP: - case SNDRV_PCM_TRIGGER_SUSPEND: - case SNDRV_PCM_TRIGGER_PAUSE_PUSH: - gpiod_set_value(mute_gpio, 0); - break; - case SNDRV_PCM_TRIGGER_START: - case SNDRV_PCM_TRIGGER_RESUME: - case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: - gpiod_set_value(mute_gpio, 1); - break; - default: - return -EINVAL; - } + gpiod_set_value(mute_gpio, 1); return 0; } static struct snd_soc_ops audioinjector_isolated_ops = { .startup = audioinjector_isolated_startup, - .trigger = audioinjector_isolated_trigger, }; static struct snd_soc_dai_link audioinjector_isolated_dai[] = { @@ -139,6 +119,7 @@ static int audioinjector_isolated_probe(struct platform_device *pdev) dev_err(&pdev->dev, "mute gpio not found in dt overlay\n"); return PTR_ERR(mute_gpio); } + gpiod_set_value(mute_gpio, 0); if (i2s_node && codec_node) { dai->cpu_dai_name = NULL; -- Gitee From 63963f830c821e538b3c5c01c9a8e96100851eab Mon Sep 17 00:00:00 2001 From: yafen Date: Mon, 9 Nov 2020 19:41:58 +0800 Subject: [PATCH 41/41] update for raspi 108 to 127 --- arch/arm64/configs/openeuler-raspi_defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/configs/openeuler-raspi_defconfig b/arch/arm64/configs/openeuler-raspi_defconfig index ffc3e8e132a6..4fa649be2878 100644 --- a/arch/arm64/configs/openeuler-raspi_defconfig +++ b/arch/arm64/configs/openeuler-raspi_defconfig @@ -5179,6 +5179,7 @@ CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m CONFIG_SND_AUDIOSENSE_PI=m CONFIG_SND_DIGIDAC1_SOUNDCARD=m CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m @@ -5255,7 +5256,6 @@ CONFIG_SND_SOC_AK4554=m CONFIG_SND_SOC_CS4265=m # CONFIG_SND_SOC_CS4270 is not set CONFIG_SND_SOC_CS4271=m -CONFIG_SND_SOC_CS4271_I2C=m # CONFIG_SND_SOC_CS4271_SPI is not set CONFIG_SND_SOC_CS42XX8=m CONFIG_SND_SOC_CS42XX8_I2C=m @@ -5272,8 +5272,8 @@ CONFIG_SND_SOC_HDMI_CODEC=m # CONFIG_SND_SOC_ES8328_SPI is not set # CONFIG_SND_SOC_GTM601 is not set CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m # CONFIG_SND_SOC_INNO_RK3036 is not set -# CONFIG_SND_SOC_MA120X0P is not set # CONFIG_SND_SOC_MAX98504 is not set # CONFIG_SND_SOC_MAX9867 is not set # CONFIG_SND_SOC_MAX98927 is not set -- Gitee