diff --git a/src/arch/aarch64/smmu.rs b/src/arch/aarch64/smmu.rs index 9011ae44acf821b7cbcf1aa7d0fbdda33f12b8ea..6c9f730f00851217a83d88c59c65999bb00ef1ae 100644 --- a/src/arch/aarch64/smmu.rs +++ b/src/arch/aarch64/smmu.rs @@ -356,7 +356,7 @@ impl SmmuV2 { /* Enable IOMMU. */ let mut cr0 = rs0.CR0.get() as usize; cr0 &= (0x3 << 30) | (0x1 << 11); - // fault and interrupt configration + // fault and interrupt configuration cr0 |= SMMUV2_CR0_USFCFG | SMMUV2_CR0_SMCFCFG; cr0 |= SMMUV2_CR0_GFRE | SMMUV2_CR0_GFIE | SMMUV2_CR0_GCFGFRE | SMMUV2_CR0_GCFGFIE; cr0 &= !SMMUV2_CR0_CLIENTPD; diff --git a/src/arch/aarch64/tlb.rs b/src/arch/aarch64/tlb.rs index f1970005b0e0f72b84ed02cc1456f4f325c49af2..9c70423284de9bad0b1786255a4b28cdab7e981f 100644 --- a/src/arch/aarch64/tlb.rs +++ b/src/arch/aarch64/tlb.rs @@ -10,7 +10,7 @@ use crate::arch::{dsb, isb}; -// Translation Look-a-side Buffer Instrution ('TLBI') operations. +// Translation Look-a-side Buffer Instruction ('TLBI') operations. // SAFETY: // TLBI operations can't trigger any side effects on the safety of the system. pub mod tlbi { diff --git a/src/arch/aarch64/vgicv3.rs b/src/arch/aarch64/vgicv3.rs index 290cfee9498c088ac180cf5c4fecd504d0120582..e84a93095a099457f93cd885266abb52b63045db 100644 --- a/src/arch/aarch64/vgicv3.rs +++ b/src/arch/aarch64/vgicv3.rs @@ -1566,7 +1566,7 @@ impl Vgic { let gic_lrs = gic_lrs(); // ICH_ELRSR_EL2:locate a usable List register when the hypervisor is delivering an interrupt to a Guest OS. let mut lr_idx_opt = bitmap_find_nth(GICH.elrsr(), 0, gic_lrs, 1, true); - // flag indicates that is no pending or not true:no pending flase:have pending,the we will look up active and pend + // flag indicates that is no pending or not true:no pending false:have pending,the we will look up active and pend let mut new_flags = flag; while lr_idx_opt.is_some() { match self.vgic_highest_proi_spilled(vcpu, new_flags) {