diff --git a/src/kernel/cpu.rs b/src/kernel/cpu.rs
index 510a723b4ee5c25479fa01544433a427f650e8bb..8393c946d5efd33753135dce64f775690e29097b 100644
--- a/src/kernel/cpu.rs
+++ b/src/kernel/cpu.rs
@@ -202,8 +202,8 @@ impl Cpu {
     pub fn schedule_to(&mut self, next_vcpu: Vcpu) {
         if let Some(prev_vcpu) = &self.active_vcpu {
             // On RISC-V, only one VM goes into this func also, since risc-v
-            // depends on traping to hypervisor to inject timer interrupt
-            // TODO: Use Sstc Extension to allow VS to receive its own timer interrupt without traping into hypervisor
+            // depends on trapping to hypervisor to inject timer interrupts
+            // TODO: Use Sstc Extension to allow VS to receive its own timer interrupts without trapping into hypervisor
 
             // This way, even when vm doesn't change, we should save prev_cpu's state
             prev_vcpu.set_state(VcpuState::Ready);