diff --git a/src/lib/cache.rs b/src/arch/aarch64/cache.rs similarity index 93% rename from src/lib/cache.rs rename to src/arch/aarch64/cache.rs index 616c383b739ea14a31c06492d820490fefec6d66..408e17e24d5547bffef4caaa73185143c791e720 100644 --- a/src/lib/cache.rs +++ b/src/arch/aarch64/cache.rs @@ -10,7 +10,7 @@ use core::arch::global_asm; -global_asm!(include_str!("../arch/aarch64/cache.S")); +global_asm!(include_str!("cache.S")); extern "C" { pub fn cache_invalidate_d(start: usize, len: usize); diff --git a/src/arch/aarch64/gic.rs b/src/arch/aarch64/gic.rs index 150a0ef9cc56c4cccb55f4bb36e10bc1a05b5b19..7d66c4c344c3bd2d3c15bebfdad761b4233243e4 100644 --- a/src/arch/aarch64/gic.rs +++ b/src/arch/aarch64/gic.rs @@ -15,7 +15,7 @@ use tock_registers::*; use tock_registers::interfaces::*; use tock_registers::registers::*; -use crate::board::{PLATFORM_GICC_BASE, PLATFORM_GICD_BASE, PLATFORM_GICH_BASE}; +use crate::board::{Platform, PlatOperation}; use crate::kernel::current_cpu; use crate::kernel::INTERRUPT_NUM_MAX; use crate::lib::{bit_extract, trace}; @@ -624,9 +624,9 @@ impl GicState { } } -pub static GICD: GicDistributor = GicDistributor::new(PLATFORM_GICD_BASE + 0x8_0000_0000); -pub static GICC: GicCpuInterface = GicCpuInterface::new(PLATFORM_GICC_BASE + 0x8_0000_0000); -pub static GICH: GicHypervisorInterface = GicHypervisorInterface::new(PLATFORM_GICH_BASE + 0x8_0000_0000); +pub static GICD: GicDistributor = GicDistributor::new(Platform::GICD_BASE + 0x8_0000_0000); +pub static GICC: GicCpuInterface = GicCpuInterface::new(Platform::GICC_BASE + 0x8_0000_0000); +pub static GICH: GicHypervisorInterface = GicHypervisorInterface::new(Platform::GICH_BASE + 0x8_0000_0000); #[inline(always)] pub fn gich_lrs_num() -> usize { diff --git a/src/arch/aarch64/interrupt.rs b/src/arch/aarch64/interrupt.rs index 8b0a940ca78089d27ae02207e2d528ebdebcc942..bb35cb89c610ce8fb86d70d79ca40efad8b56a1c 100644 --- a/src/arch/aarch64/interrupt.rs +++ b/src/arch/aarch64/interrupt.rs @@ -9,7 +9,7 @@ // See the Mulan PSL v2 for more details. use crate::arch::{gic_cpu_reset, gicc_clear_current_irq}; -use crate::board::platform_cpuid_to_cpuif; +use crate::board::{Platform, PlatOperation}; use crate::kernel::{current_cpu, Vcpu, Vm}; use super::GIC_SGIS_NUM; @@ -41,7 +41,7 @@ pub fn interrupt_arch_enable(int_id: usize, en: bool) { let cpu_id = current_cpu().id; if en { GICD.set_prio(int_id, 0x7f); - GICD.set_trgt(int_id, 1 << platform_cpuid_to_cpuif(cpu_id)); + GICD.set_trgt(int_id, 1 << Platform::cpuid_to_cpuif(cpu_id)); GICD.set_enable(int_id, en); } else { @@ -51,7 +51,7 @@ pub fn interrupt_arch_enable(int_id: usize, en: bool) { pub fn interrupt_arch_ipi_send(cpu_id: usize, ipi_id: usize) { if ipi_id < GIC_SGIS_NUM { - GICD.send_sgi(platform_cpuid_to_cpuif(cpu_id), ipi_id); + GICD.send_sgi(Platform::cpuid_to_cpuif(cpu_id), ipi_id); } } diff --git a/src/arch/aarch64/mod.rs b/src/arch/aarch64/mod.rs index 5d6d6b6f5b04321f140a91c77060d06fba35e255..813dc5f840b9d455f63ea9126f733b46b7fc86a7 100644 --- a/src/arch/aarch64/mod.rs +++ b/src/arch/aarch64/mod.rs @@ -19,6 +19,7 @@ pub use self::page_table::*; pub use self::psci::*; pub use self::regs::*; pub use self::smc::*; +pub use self::cache::*; pub use self::smmu::*; pub use self::sync::*; pub use self::timer::*; @@ -29,6 +30,7 @@ pub use self::vgic::*; #[macro_use] mod regs; +mod cache; mod context_frame; mod cpu; mod exception; diff --git a/src/arch/aarch64/vgic.rs b/src/arch/aarch64/vgic.rs index 1c0c84fa5560e65f0cad1370027c388984772e75..086851ae95e1bf27df43f124f4785cf8a380933c 100644 --- a/src/arch/aarch64/vgic.rs +++ b/src/arch/aarch64/vgic.rs @@ -15,8 +15,7 @@ use alloc::vec::Vec; use spin::Mutex; use crate::{arch::GICH, kernel::IpiInitcMessage}; -use crate::board::{PLATFORM_CPU_NUM_MAX, platform_cpuid_to_cpuif}; -use crate::board::PLATFORM_GICD_BASE; +use crate::board::{PLATFORM_CPU_NUM_MAX, Platform, PlatOperation}; use crate::device::EmuContext; use crate::device::EmuDevs; use crate::kernel::{ @@ -1399,7 +1398,7 @@ impl Vgic { let mut ptrgt = 0; for cpuid in 0..8 { if bit_get(trgt as usize, cpuid) != 0 { - ptrgt = bit_set(ptrgt, platform_cpuid_to_cpuif(cpuid)) + ptrgt = bit_set(ptrgt, Platform::cpuid_to_cpuif(cpuid)) } } if interrupt.hw() { @@ -1781,7 +1780,7 @@ impl Vgic { } }; - if bit_extract(emu_ctx.address, 0, 12) == bit_extract(PLATFORM_GICD_BASE + 0x0f00, 0, 12) { + if bit_extract(emu_ctx.address, 0, 12) == bit_extract(Platform::GICD_BASE + 0x0f00, 0, 12) { if emu_ctx.write { let sgir_trglstflt = bit_extract(val, 24, 2); let mut trgtlist = 0; @@ -2373,9 +2372,9 @@ pub fn partial_passthrough_intc_handler(_emu_dev_id: usize, emu_ctx: &EmuContext if emu_ctx.write { // todo: add offset match let val = current_cpu().get_gpr(emu_ctx.reg); - ptr_read_write(PLATFORM_GICD_BASE + 0x8_0000_0000 + offset, emu_ctx.width, val, false); + ptr_read_write(Platform::GICD_BASE + 0x8_0000_0000 + offset, emu_ctx.width, val, false); } else { - let res = ptr_read_write(PLATFORM_GICD_BASE + 0x8_0000_0000 + offset, emu_ctx.width, 0, true); + let res = ptr_read_write(Platform::GICD_BASE + 0x8_0000_0000 + offset, emu_ctx.width, 0, true); current_cpu().set_gpr(emu_ctx.reg, res); } diff --git a/src/board/mod.rs b/src/board/mod.rs index a9b7704860937749a2c1c36dd80112cff077ae2b..dbdae42e85609313a6f081cf5c04daf6eded21f5 100644 --- a/src/board/mod.rs +++ b/src/board/mod.rs @@ -8,13 +8,14 @@ // MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. // See the Mulan PSL v2 for more details. -#[cfg(feature = "pi4")] -pub use self::pi4::*; pub use self::platform_common::*; + +#[cfg(feature = "pi4")] +pub use self::pi4::{Pi4Platform as Platform, PLAT_DESC}; #[cfg(feature = "qemu")] -pub use self::qemu::*; +pub use self::qemu::{QemuPlatform as Platform, PLAT_DESC}; #[cfg(feature = "tx2")] -pub use self::tx2::*; +pub use self::tx2::{Tx2Platform as Platform, PLAT_DESC}; #[cfg(feature = "pi4")] mod pi4; diff --git a/src/board/pi4/platform.rs b/src/board/pi4/platform.rs index 4bf18d3de631b3cccd0dbd0f20ae096a46eb4442..824ddfd4b791828729243bba377eb6f556bf829c 100644 --- a/src/board/pi4/platform.rs +++ b/src/board/pi4/platform.rs @@ -10,60 +10,67 @@ use crate::arch::GicDesc; use crate::arch::SmmuDesc; -use crate::board::{ArchDesc, PlatCpuConfig, PlatformConfig, PlatMemoryConfig, PlatMemRegion, PlatCpuCoreConfig}; +use crate::board::{ + PlatOperation, Platform, PlatCpuCoreConfig, ArchDesc, PlatCpuConfig, PlatformConfig, PlatMemoryConfig, + PlatMemRegion, +}; use crate::board::SchedRule::RoundRobin; use crate::device::ARM_CORTEX_A57; #[allow(unused_imports)] use crate::device::ARM_NVIDIA_DENVER; -// pub const TIMER_FREQUENCY: usize = 62500000; +pub struct Pi4Platform; -pub const UART_0_ADDR: usize = 0xFE201000; -pub const UART_1_ADDR: usize = 0xFE201400; +impl PlatOperation for Pi4Platform { + const UART_0_ADDR: usize = 0xFE201000; + const UART_1_ADDR: usize = 0xFE201400; -pub const UART_0_INT: usize = 32 + 0x79; -pub const UART_1_INT: usize = 32 + 0x79; + const UART_0_INT: usize = 32 + 0x79; + const UART_1_INT: usize = 32 + 0x79; -pub const PLATFORM_GICD_BASE: usize = 0xFF841000; -pub const PLATFORM_GICC_BASE: usize = 0xFF842000; -pub const PLATFORM_GICH_BASE: usize = 0xFF844000; -pub const PLATFORM_GICV_BASE: usize = 0xFF846000; + const HYPERVISOR_UART_BASE: usize = Self::UART_0_ADDR; -// pub const DISK_PARTITION_1_ADDR_SIZE: usize = 0x400; -// pub const DISK_PARTITION_1_ADDR: usize = 0xa000000; -// pub const DISK_PARTITION_2_ADDR: usize = 0xa000400; -// pub const DISK_PARTITION_3_ADDR: usize = 0xa000800; -// pub const DISK_PARTITION_4_ADDR: usize = 0xa000c00; + const GICD_BASE: usize = 0xFF841000; + const GICC_BASE: usize = 0xFF842000; + const GICH_BASE: usize = 0xFF844000; + const GICV_BASE: usize = 0xFF846000; -pub const SHARE_MEM_BASE: usize = 0x7_0000_0000; + const SHARE_MEM_BASE: usize = 0x7_0000_0000; -// start sector number (LBA) -pub const DISK_PARTITION_0_START: usize = 2048; -pub const DISK_PARTITION_1_START: usize = 526336; -pub const DISK_PARTITION_2_START: usize = 17303552; -pub const DISK_PARTITION_3_START: usize = 34082816; -pub const DISK_PARTITION_4_START: usize = 50862080; + // start sector number (LBA) + const DISK_PARTITION_0_START: usize = 2048; + const DISK_PARTITION_1_START: usize = 526336; + const DISK_PARTITION_2_START: usize = 17303552; + const DISK_PARTITION_3_START: usize = 34082816; + const DISK_PARTITION_4_START: usize = 50862080; -// size in sector (512-byte) -// pub const DISK_PARTITION_TOTAL_SIZE: usize = 31457280; -pub const DISK_PARTITION_0_SIZE: usize = 524288; -pub const DISK_PARTITION_1_SIZE: usize = 16777216; -pub const DISK_PARTITION_2_SIZE: usize = 16777216; -pub const DISK_PARTITION_3_SIZE: usize = 16777216; -pub const DISK_PARTITION_4_SIZE: usize = 11471872; + // size in sector (512-byte) + const DISK_PARTITION_0_SIZE: usize = 524288; + const DISK_PARTITION_1_SIZE: usize = 16777216; + const DISK_PARTITION_2_SIZE: usize = 16777216; + const DISK_PARTITION_3_SIZE: usize = 16777216; + const DISK_PARTITION_4_SIZE: usize = 11471872; -// pub const DISK_PARTITION_1_INT: usize = 32 + 0x10; -// pub const DISK_PARTITION_2_INT: usize = 32 + 0x11; -// pub const DISK_PARTITION_3_INT: usize = 32 + 0x12; -// pub const DISK_PARTITION_4_INT: usize = 32 + 0x13; + fn cpuid_to_cpuif(cpuid: usize) -> usize { + cpuid + } -//end tx2 platform const + fn cpuif_to_cpuid(cpuif: usize) -> usize { + cpuif + } -// extern "C" { -// fn tegra_emmc_init(); -// fn tegra_emmc_blk_read(sector: usize, count: usize, buf: *mut u8); -// fn tegra_emmc_blk_write(sector: usize, count: usize, buf: *const u8); -// } + fn blk_init() { + todo!() + } + + fn blk_read(_sector: usize, _count: usize, _buf: usize) { + todo!() + } + + fn blk_write(_sector: usize, _count: usize, _buf: usize) { + todo!() + } +} pub static PLAT_DESC: PlatformConfig = PlatformConfig { cpu_desc: PlatCpuConfig { @@ -112,13 +119,12 @@ pub static PLAT_DESC: PlatformConfig = PlatformConfig { ], base: 0xf0000000, }, - uart_base: UART_0_ADDR, arch_desc: ArchDesc { gic_desc: GicDesc { - gicd_addr: PLATFORM_GICD_BASE, - gicc_addr: PLATFORM_GICC_BASE, - gich_addr: PLATFORM_GICH_BASE, - gicv_addr: PLATFORM_GICV_BASE, + gicd_addr: Platform::GICD_BASE, + gicc_addr: Platform::GICC_BASE, + gich_addr: Platform::GICH_BASE, + gicv_addr: Platform::GICV_BASE, maintenance_int_id: 25, }, smmu_desc: SmmuDesc { @@ -128,63 +134,3 @@ pub static PLAT_DESC: PlatformConfig = PlatformConfig { }, }, }; - -fn platform_cpu_on(arch_core_id: usize, entry: usize, ctx: usize) { - use crate::arch::power_arch_cpu_on; - power_arch_cpu_on(arch_core_id, entry, ctx); -} - -pub fn platform_cpu_shutdown() { - crate::arch::power_arch_cpu_shutdown(); -} - -pub fn platform_power_on_secondary_cores() { - extern "C" { - fn _image_start(); - } - for i in 1..PLAT_DESC.cpu_desc.num { - platform_cpu_on(PLAT_DESC.cpu_desc.core_list[i].mpidr, _image_start as usize, 0); - } -} - -pub fn platform_sys_reboot() { - println!("Hypervisor reset..."); - // mem_heap_reset(); - crate::arch::power_arch_sys_reset(); - loop {} -} - -pub fn platform_sys_shutdown() { - println!("Hypervisor shutdown..."); - // mem_heap_reset(); - crate::arch::power_arch_sys_shutdown(); - loop {} -} - -// TODO -// pub fn platform_blk_init() { -// unsafe { -// tegra_emmc_init(); -// } -// println!("Platform block driver init ok"); -// } -// -// pub fn platform_blk_read(sector: usize, count: usize, buf: usize) { -// unsafe { -// tegra_emmc_blk_read(sector, count, buf as *mut u8); -// } -// } -// -// pub fn platform_blk_write(sector: usize, count: usize, buf: usize) { -// unsafe { -// tegra_emmc_blk_write(sector, count, buf as *const u8); -// } -// } - -pub fn platform_cpuid_to_cpuif(cpuid: usize) -> usize { - cpuid -} - -pub fn platform_cpuif_to_cpuid(cpuif: usize) -> usize { - cpuif -} diff --git a/src/board/platform_common.rs b/src/board/platform_common.rs index a2f8c204344ea394d23a279de46bc811d52ac95e..91c63ffc62d239c7a99a3dab487b873f5d9422a5 100644 --- a/src/board/platform_common.rs +++ b/src/board/platform_common.rs @@ -54,6 +54,84 @@ pub struct ArchDesc { pub struct PlatformConfig { pub cpu_desc: PlatCpuConfig, pub mem_desc: PlatMemoryConfig, - pub uart_base: usize, pub arch_desc: ArchDesc, } + +pub trait PlatOperation { + // must offer UART_0 and UART_1 address + const UART_0_ADDR: usize; + const UART_1_ADDR: usize; + const UART_2_ADDR: usize = usize::MAX; + + // must offer hypervisor used uart + const HYPERVISOR_UART_BASE: usize; + + const UART_0_INT: usize = usize::MAX; + const UART_1_INT: usize = usize::MAX; + const UART_2_INT: usize = usize::MAX; + + // must offer interrupt controller + const GICD_BASE: usize; + const GICC_BASE: usize; + const GICH_BASE: usize; + const GICV_BASE: usize; + + const DISK_PARTITION_0_START: usize = usize::MAX; + const DISK_PARTITION_1_START: usize = usize::MAX; + const DISK_PARTITION_2_START: usize = usize::MAX; + const DISK_PARTITION_3_START: usize = usize::MAX; + const DISK_PARTITION_4_START: usize = usize::MAX; + + const DISK_PARTITION_TOTAL_SIZE: usize = usize::MAX; + const DISK_PARTITION_0_SIZE: usize = usize::MAX; + const DISK_PARTITION_1_SIZE: usize = usize::MAX; + const DISK_PARTITION_2_SIZE: usize = usize::MAX; + const DISK_PARTITION_3_SIZE: usize = usize::MAX; + const DISK_PARTITION_4_SIZE: usize = usize::MAX; + + const SHARE_MEM_BASE: usize; + + fn cpu_on(arch_core_id: usize, entry: usize, ctx: usize) { + crate::arch::power_arch_cpu_on(arch_core_id, entry, ctx); + } + + fn cpu_shutdown() { + crate::arch::power_arch_cpu_shutdown(); + } + + fn power_on_secondary_cores() { + use super::PLAT_DESC; + extern "C" { + fn _image_start(); + } + for i in 1..PLAT_DESC.cpu_desc.num { + Self::cpu_on(PLAT_DESC.cpu_desc.core_list[i].mpidr, _image_start as usize, 0); + } + } + + fn sys_reboot() -> ! { + println!("Hypervisor reset..."); + crate::arch::power_arch_sys_reset(); + loop { + core::hint::spin_loop(); + } + } + + fn sys_shutdown() -> ! { + println!("Hypervisor shutdown..."); + crate::arch::power_arch_sys_shutdown(); + loop { + core::hint::spin_loop(); + } + } + + fn cpuid_to_cpuif(cpuid: usize) -> usize; + + fn cpuif_to_cpuid(cpuif: usize) -> usize; + + fn blk_init(); + + fn blk_read(sector: usize, count: usize, buf: usize); + + fn blk_write(sector: usize, count: usize, buf: usize); +} diff --git a/src/board/qemu/platform.rs b/src/board/qemu/platform.rs index c73c9dd92cda6182471c941e4c5432047e8cf8ba..d9cde80fe695ed3db974bcce05f515b9825c8c03 100644 --- a/src/board/qemu/platform.rs +++ b/src/board/qemu/platform.rs @@ -11,38 +11,64 @@ // TODO: move these core name to device use crate::arch::GicDesc; use crate::arch::SmmuDesc; -use crate::board::{ArchDesc, PlatCpuConfig, PlatformConfig, PlatMemoryConfig, PlatMemRegion, PlatCpuCoreConfig}; +use crate::board::{ + PlatOperation, Platform, PlatCpuCoreConfig, ArchDesc, PlatCpuConfig, PlatformConfig, PlatMemoryConfig, + PlatMemRegion, +}; use crate::board::SchedRule::RoundRobin; use crate::device::ARM_CORTEX_A57; use crate::driver::{read, write}; -// pub const TIMER_FREQUENCY: usize = 62500000; +pub struct QemuPlatform; + +impl PlatOperation for QemuPlatform { + const UART_0_ADDR: usize = 0x9000000; + const UART_1_ADDR: usize = 0x9100000; + const UART_2_ADDR: usize = 0x9110000; -pub const UART_0_ADDR: usize = 0x9000000; -pub const UART_1_ADDR: usize = 0x9100000; -pub const UART_2_ADDR: usize = 0x9110000; + const UART_0_INT: usize = 32 + 0x70; + const UART_1_INT: usize = 32 + 0x72; -pub const UART_1_INT: usize = 42; -pub const UART_2_INT: usize = 43; + const HYPERVISOR_UART_BASE: usize = Self::UART_0_ADDR; -// Hardcode -pub const SHARE_MEM_BASE: usize = 0x7_0000_0000; + const GICD_BASE: usize = 0x08000000; + const GICC_BASE: usize = 0x08010000; + const GICH_BASE: usize = 0x08030000; + const GICV_BASE: usize = 0x08040000; -pub const PLATFORM_GICD_BASE: usize = 0x08000000; -pub const PLATFORM_GICC_BASE: usize = 0x08010000; -pub const PLATFORM_GICH_BASE: usize = 0x08030000; -pub const PLATFORM_GICV_BASE: usize = 0x08040000; + const SHARE_MEM_BASE: usize = 0x7_0000_0000; -pub const DISK_PARTITION_0_START: usize = 0; -pub const DISK_PARTITION_1_START: usize = 2097152; -pub const DISK_PARTITION_2_START: usize = 10289152; + const DISK_PARTITION_0_START: usize = 0; + const DISK_PARTITION_1_START: usize = 2097152; + const DISK_PARTITION_2_START: usize = 10289152; -pub const DISK_PARTITION_TOTAL_SIZE: usize = 18481152; -pub const DISK_PARTITION_0_SIZE: usize = 524288; -pub const DISK_PARTITION_1_SIZE: usize = 8192000; -pub const DISK_PARTITION_2_SIZE: usize = 8192000; + const DISK_PARTITION_TOTAL_SIZE: usize = 18481152; + const DISK_PARTITION_0_SIZE: usize = 524288; + const DISK_PARTITION_1_SIZE: usize = 8192000; + const DISK_PARTITION_2_SIZE: usize = 8192000; + + fn cpuid_to_cpuif(cpuid: usize) -> usize { + cpuid + } + + fn cpuif_to_cpuid(cpuif: usize) -> usize { + cpuif + } + + fn blk_init() { + println!("Platform block driver init ok"); + crate::driver::virtio_blk_init(); + } + + fn blk_read(sector: usize, count: usize, buf: usize) { + read(sector, count, buf); + } + + fn blk_write(sector: usize, count: usize, buf: usize) { + write(sector, count, buf); + } +} -// holy shit, need to recode later pub static PLAT_DESC: PlatformConfig = PlatformConfig { cpu_desc: PlatCpuConfig { num: 4, @@ -83,13 +109,12 @@ pub static PLAT_DESC: PlatformConfig = PlatformConfig { ], base: 0x40000000, }, - uart_base: UART_0_ADDR, arch_desc: ArchDesc { gic_desc: GicDesc { - gicd_addr: PLATFORM_GICD_BASE, - gicc_addr: PLATFORM_GICC_BASE, - gich_addr: PLATFORM_GICH_BASE, - gicv_addr: PLATFORM_GICV_BASE, + gicd_addr: Platform::GICD_BASE, + gicc_addr: Platform::GICC_BASE, + gich_addr: Platform::GICH_BASE, + gicv_addr: Platform::GICV_BASE, maintenance_int_id: 25, }, smmu_desc: SmmuDesc { @@ -99,49 +124,3 @@ pub static PLAT_DESC: PlatformConfig = PlatformConfig { }, }, }; - -fn platform_cpu_on(arch_core_id: usize, entry: usize, ctx: usize) { - use crate::arch::power_arch_cpu_on; - power_arch_cpu_on(arch_core_id, entry, ctx); -} - -pub fn platform_cpu_shutdown() { - crate::arch::power_arch_cpu_shutdown(); -} - -pub fn platform_power_on_secondary_cores() { - extern "C" { - fn _image_start(); - } - for i in 1..PLAT_DESC.cpu_desc.num { - platform_cpu_on(PLAT_DESC.cpu_desc.core_list[i].mpidr, _image_start as usize, 0); - } -} - -pub fn platform_sys_reboot() { - println!("Hypervisor reset..."); - // mem_heap_reset(); - crate::arch::power_arch_sys_reset(); - loop {} -} - -pub fn platform_blk_init() { - println!("Platform block driver init ok"); - crate::driver::virtio_blk_init(); -} - -pub fn platform_blk_read(sector: usize, count: usize, buf: usize) { - read(sector, count, buf); -} - -pub fn platform_blk_write(sector: usize, count: usize, buf: usize) { - write(sector, count, buf); -} - -pub fn platform_cpuid_to_cpuif(cpuid: usize) -> usize { - cpuid -} - -pub fn platform_cpuif_to_cpuid(cpuif: usize) -> usize { - cpuif -} diff --git a/src/board/tx2/platform.rs b/src/board/tx2/platform.rs index be334ecdb74426cb638ed7b29757152ccc6fa8f0..55ccd5583d439e06552abeaac3a06e2f56ab6275 100644 --- a/src/board/tx2/platform.rs +++ b/src/board/tx2/platform.rs @@ -10,56 +10,64 @@ use crate::arch::GicDesc; use crate::arch::SmmuDesc; -use crate::board::{ArchDesc, PlatCpuConfig, PlatformConfig, PlatMemoryConfig, PlatMemRegion, PlatCpuCoreConfig}; +use crate::board::{ + PlatOperation, Platform, PlatCpuCoreConfig, ArchDesc, PlatCpuConfig, PlatformConfig, PlatMemoryConfig, + PlatMemRegion, +}; use crate::board::SchedRule::RoundRobin; use crate::device::ARM_CORTEX_A57; #[allow(unused_imports)] use crate::device::ARM_NVIDIA_DENVER; -// pub const TIMER_FREQUENCY: usize = 62500000; +pub struct Tx2Platform; -pub const UART_0_ADDR: usize = 0x3100000; -pub const UART_1_ADDR: usize = 0xc280000; +impl PlatOperation for Tx2Platform { + const UART_0_ADDR: usize = 0x3100000; + const UART_1_ADDR: usize = 0xc280000; -pub const UART_0_INT: usize = 32 + 0x70; -pub const UART_1_INT: usize = 32 + 0x72; + const UART_0_INT: usize = 32 + 0x70; + const UART_1_INT: usize = 32 + 0x72; -pub const PLATFORM_GICD_BASE: usize = 0x3881000; -pub const PLATFORM_GICC_BASE: usize = 0x3882000; -pub const PLATFORM_GICH_BASE: usize = 0x3884000; -pub const PLATFORM_GICV_BASE: usize = 0x3886000; + const HYPERVISOR_UART_BASE: usize = Self::UART_1_ADDR; -// pub const DISK_PARTITION_1_ADDR_SIZE: usize = 0x400; -// pub const DISK_PARTITION_1_ADDR: usize = 0xa000000; -// pub const DISK_PARTITION_2_ADDR: usize = 0xa000400; -// pub const DISK_PARTITION_3_ADDR: usize = 0xa000800; -// pub const DISK_PARTITION_4_ADDR: usize = 0xa000c00; + const GICD_BASE: usize = 0x3881000; + const GICC_BASE: usize = 0x3882000; + const GICH_BASE: usize = 0x3884000; + const GICV_BASE: usize = 0x3886000; -// start sector number (LBA) -pub const DISK_PARTITION_0_START: usize = 43643256; -pub const DISK_PARTITION_1_START: usize = 4104; -pub const DISK_PARTITION_2_START: usize = 45740408; + // start sector number (LBA) + const DISK_PARTITION_0_START: usize = 43643256; + const DISK_PARTITION_1_START: usize = 4104; + const DISK_PARTITION_2_START: usize = 45740408; -// size in sector (512-byte) -// pub const DISK_PARTITION_TOTAL_SIZE: usize = 31457280; -pub const DISK_PARTITION_0_SIZE: usize = 2097152; -pub const DISK_PARTITION_1_SIZE: usize = 41943040; -pub const DISK_PARTITION_2_SIZE: usize = 8388608; + // size in sector (512-byte) + // pub const DISK_PARTITION_TOTAL_SIZE: usize = 31457280; + const DISK_PARTITION_0_SIZE: usize = 2097152; + const DISK_PARTITION_1_SIZE: usize = 41943040; + const DISK_PARTITION_2_SIZE: usize = 8388608; -// pub const DISK_PARTITION_1_INT: usize = 32 + 0x10; -// pub const DISK_PARTITION_2_INT: usize = 32 + 0x11; -// pub const DISK_PARTITION_3_INT: usize = 32 + 0x12; -// pub const DISK_PARTITION_4_INT: usize = 32 + 0x13; + const SHARE_MEM_BASE: usize = 0xd_0000_0000; -pub const SHARE_MEM_BASE: usize = 0xd_0000_0000; + fn cpuid_to_cpuif(cpuid: usize) -> usize { + cpuid + PLAT_DESC.cpu_desc.num + } -//end tx2 platform const + fn cpuif_to_cpuid(cpuif: usize) -> usize { + cpuif - PLAT_DESC.cpu_desc.num + } -// extern "C" { -// fn tegra_emmc_init(); -// fn tegra_emmc_blk_read(sector: usize, count: usize, buf: *mut u8); -// fn tegra_emmc_blk_write(sector: usize, count: usize, buf: *const u8); -// } + fn blk_init() { + todo!() + } + + fn blk_read(_sector: usize, _count: usize, _buf: usize) { + todo!() + } + + fn blk_write(_sector: usize, _count: usize, _buf: usize) { + todo!() + } +} pub static PLAT_DESC: PlatformConfig = PlatformConfig { cpu_desc: PlatCpuConfig { @@ -104,13 +112,12 @@ pub static PLAT_DESC: PlatformConfig = PlatformConfig { ], base: 0x80000000, }, - uart_base: UART_0_ADDR, arch_desc: ArchDesc { gic_desc: GicDesc { - gicd_addr: PLATFORM_GICD_BASE, - gicc_addr: PLATFORM_GICC_BASE, - gich_addr: PLATFORM_GICH_BASE, - gicv_addr: PLATFORM_GICV_BASE, + gicd_addr: Platform::GICD_BASE, + gicc_addr: Platform::GICC_BASE, + gich_addr: Platform::GICH_BASE, + gicv_addr: Platform::GICV_BASE, maintenance_int_id: 25, }, smmu_desc: SmmuDesc { @@ -120,63 +127,3 @@ pub static PLAT_DESC: PlatformConfig = PlatformConfig { }, }, }; - -fn platform_cpu_on(arch_core_id: usize, entry: usize, ctx: usize) { - use crate::arch::power_arch_cpu_on; - power_arch_cpu_on(arch_core_id, entry, ctx); -} - -pub fn platform_cpu_shutdown() { - crate::arch::power_arch_cpu_shutdown(); -} - -pub fn platform_power_on_secondary_cores() { - extern "C" { - fn _image_start(); - } - for i in 1..PLAT_DESC.cpu_desc.num { - platform_cpu_on(PLAT_DESC.cpu_desc.core_list[i].mpidr, _image_start as usize, 0); - } -} - -pub fn platform_sys_reboot() { - println!("Hypervisor reset..."); - // mem_heap_reset(); - crate::arch::power_arch_sys_reset(); - loop {} -} - -pub fn platform_sys_shutdown() { - println!("Hypervisor shutdown..."); - // mem_heap_reset(); - crate::arch::power_arch_sys_shutdown(); - loop {} -} - -// TODO -// pub fn platform_blk_init() { -// unsafe { -// tegra_emmc_init(); -// } -// println!("Platform block driver init ok"); -// } -// -// pub fn platform_blk_read(sector: usize, count: usize, buf: usize) { -// unsafe { -// tegra_emmc_blk_read(sector, count, buf as *mut u8); -// } -// } -// -// pub fn platform_blk_write(sector: usize, count: usize, buf: usize) { -// unsafe { -// tegra_emmc_blk_write(sector, count, buf as *const u8); -// } -// } - -pub fn platform_cpuid_to_cpuif(cpuid: usize) -> usize { - cpuid + PLAT_DESC.cpu_desc.num -} - -pub fn platform_cpuif_to_cpuid(cpuif: usize) -> usize { - cpuif - PLAT_DESC.cpu_desc.num -} diff --git a/src/config/pi4_def.rs b/src/config/pi4_def.rs index eba107ab72d69c9d9b1112fb88267373a993ea73..59afcefbeeed3b2a636d2ab14cb0f6eae00bce36 100644 --- a/src/config/pi4_def.rs +++ b/src/config/pi4_def.rs @@ -31,52 +31,53 @@ pub fn mvm_config_init() { vm_cfg_set_config_name("pi4-default"); // vm0 emu - let mut emu_dev_config: Vec = Vec::new(); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("interrupt-controller@fff841000")), - base_ipa: 0xFFF841000, - length: 0x1000, - irq_id: 0, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTGicd, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio_net@fa000800")), - base_ipa: 0xfa000800, - length: 0x400, - irq_id: 32 + 0x17, - cfg_list: vec![0x74, 0x56, 0xaa, 0x0f, 0x47, 0xd0], - emu_type: EmuDeviceType::EmuDeviceTVirtioNet, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio_console@fa000c00")), - base_ipa: 0xfa000c00, - length: 0x1000, - irq_id: 32 + 0x20, - cfg_list: vec![1, 0xa002000], - emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio_console@fa002000")), - base_ipa: 0xfa002000, - length: 0x1000, - irq_id: 32 + 0x18, - cfg_list: vec![2, 0xa002000], - emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("vm_service")), - base_ipa: 0, - length: 0, - irq_id: 32 + 0x10, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTShyper, - mediated: false, - }); + let emu_dev_config = vec![ + VmEmulatedDeviceConfig { + name: Some(String::from("interrupt-controller@fff841000")), + base_ipa: 0xFFF841000, + length: 0x1000, + irq_id: 0, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTGicd, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio_net@fa000800")), + base_ipa: 0xfa000800, + length: 0x400, + irq_id: 32 + 0x17, + cfg_list: vec![0x74, 0x56, 0xaa, 0x0f, 0x47, 0xd0], + emu_type: EmuDeviceType::EmuDeviceTVirtioNet, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio_console@fa000c00")), + base_ipa: 0xfa000c00, + length: 0x1000, + irq_id: 32 + 0x20, + cfg_list: vec![1, 0xa002000], + emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio_console@fa002000")), + base_ipa: 0xfa002000, + length: 0x1000, + irq_id: 32 + 0x18, + cfg_list: vec![2, 0xa002000], + emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("vm_service")), + base_ipa: 0, + length: 0, + irq_id: 32 + 0x10, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTShyper, + mediated: false, + } + ]; // vm0 passthrough let mut pt_dev_config: VmPassthroughDeviceConfig = VmPassthroughDeviceConfig::default(); @@ -88,7 +89,7 @@ pub fn mvm_config_init() { // fb PassthroughRegion { ipa: 0x3e000000, pa: 0x3e000000, length: 0x40000000 - 0x3e000000, dev_property: false }, // gicv - PassthroughRegion { ipa: PLATFORM_GICC_BASE + 0xF_0000_0000, pa: PLATFORM_GICV_BASE, length: 0x2000, dev_property: true }, + PassthroughRegion { ipa: Platform::GICC_BASE + 0xF_0000_0000, pa: Platform::GICV_BASE, length: 0x2000, dev_property: true }, ]; // 146 is UART_INT pt_dev_config.irqs = vec![ @@ -154,11 +155,12 @@ pub fn mvm_config_init() { pt_dev_config.streams_ids = vec![]; // vm0 vm_region - let mut vm_region: Vec = Vec::new(); - vm_region.push(VmRegion { - ipa_start: 0x200000, - length: 0x3e000000 - 0x200000, - }); + let vm_region = vec![ + VmRegion { + ipa_start: 0x200000, + length: 0x3e000000 - 0x200000, + } + ]; // vm_region.push(VmRegion { // ipa_start: 0xf0200000, // length: 0xc0000000, diff --git a/src/config/qemu_def.rs b/src/config/qemu_def.rs index a8e1d7f3f4238c698420a17361337276a5424dc3..26cd0bbeb6ae37f539fc131d11e5c4042a52fd73 100644 --- a/src/config/qemu_def.rs +++ b/src/config/qemu_def.rs @@ -29,49 +29,50 @@ pub fn mvm_config_init() { vm_cfg_set_config_name("qemu-default"); // vm0 emu - let mut emu_dev_config: Vec = Vec::new(); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("vgicd")), - base_ipa: PLATFORM_GICD_BASE, - length: 0x1000, - irq_id: 0, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTGicd, - mediated: false, - }); - // emu_dev_config.push(VmEmulatedDeviceConfig { - // name: Some(String::from("virtio-blk0")), - // base_ipa: 0xa000000, - // length: 0x1000, - // irq_id: 32 + 0x10, - // cfg_list: vec![DISK_PARTITION_1_START, DISK_PARTITION_1_SIZE], - // emu_type: EmuDeviceType::EmuDeviceTVirtioBlk, - // mediated: false, - // }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio-nic0")), - base_ipa: 0xa001000, - length: 0x1000, - irq_id: 32 + 0x11, - cfg_list: vec![0x74, 0x56, 0xaa, 0x0f, 0x47, 0xd0], - emu_type: EmuDeviceType::EmuDeviceTVirtioNet, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("shyper")), - base_ipa: 0, - length: 0, - irq_id: HVC_IRQ, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTShyper, - mediated: false, - }); + let emu_dev_config = vec![ + VmEmulatedDeviceConfig { + name: Some(String::from("vgicd")), + base_ipa: Platform::GICD_BASE, + length: 0x1000, + irq_id: 0, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTGicd, + mediated: false, + }, + // VmEmulatedDeviceConfig { + // name: Some(String::from("virtio-blk0")), + // base_ipa: 0xa000000, + // length: 0x1000, + // irq_id: 32 + 0x10, + // cfg_list: vec![DISK_PARTITION_1_START, DISK_PARTITION_1_SIZE], + // emu_type: EmuDeviceType::EmuDeviceTVirtioBlk, + // mediated: false, + // }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio-nic0")), + base_ipa: 0xa001000, + length: 0x1000, + irq_id: 32 + 0x11, + cfg_list: vec![0x74, 0x56, 0xaa, 0x0f, 0x47, 0xd0], + emu_type: EmuDeviceType::EmuDeviceTVirtioNet, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("shyper")), + base_ipa: 0, + length: 0, + irq_id: HVC_IRQ, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTShyper, + mediated: false, + } + ]; // vm0 passthrough let mut pt_dev_config: VmPassthroughDeviceConfig = VmPassthroughDeviceConfig::default(); pt_dev_config.regions = vec![ - PassthroughRegion { ipa: UART_0_ADDR, pa: UART_0_ADDR, length: 0x1000, dev_property: true }, - PassthroughRegion { ipa: PLATFORM_GICC_BASE, pa: PLATFORM_GICV_BASE, length: 0x2000, dev_property: true }, + PassthroughRegion { ipa: Platform::UART_0_ADDR, pa: Platform::UART_0_ADDR, length: 0x1000, dev_property: true }, + PassthroughRegion { ipa: Platform::GICC_BASE, pa: Platform::GICV_BASE, length: 0x2000, dev_property: true }, // pass-througn virtio blk/net PassthroughRegion { ipa: 0x0a003000, pa: 0x0a003000, length: 0x1000, dev_property: true }, ]; @@ -102,11 +103,12 @@ pub fn mvm_config_init() { // }); // vm0 vm_region - let mut vm_region: Vec = Vec::new(); - vm_region.push(VmRegion { - ipa_start: 0x50000000, - length: 0x80000000, - }); + let vm_region = vec![ + VmRegion { + ipa_start: 0x50000000, + length: 0x80000000, + } + ]; // vm0 config let mvm_config_entry =VmConfigEntry { diff --git a/src/config/tx2_def.rs b/src/config/tx2_def.rs index 3a0ae832c938253e9c8421d5626d796fb9855cff..d363639c96dd0f6d30d8052fc2bbf38166326aab 100644 --- a/src/config/tx2_def.rs +++ b/src/config/tx2_def.rs @@ -14,8 +14,7 @@ use alloc::vec::Vec; use spin::Mutex; -use crate::board::*; -// self.mem_map_cache = None; +use crate::board::{Platform, PlatOperation}; use crate::config::vm_cfg_add_vm_entry; use crate::device::EmuDeviceType; use crate::kernel::{HVC_IRQ, INTERRUPT_IRQ_GUEST_TIMER, VmType}; @@ -32,61 +31,62 @@ pub fn mvm_config_init() { vm_cfg_set_config_name("tx2-default"); // vm0 emu - let mut emu_dev_config: Vec = Vec::new(); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("interrupt-controller@3881000")), - base_ipa: PLATFORM_GICD_BASE, - length: 0x1000, - irq_id: 0, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTGicd, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio_net@a001000")), - base_ipa: 0xa001000, - length: 0x1000, - irq_id: 32 + 0x100, - cfg_list: vec![0x74, 0x56, 0xaa, 0x0f, 0x47, 0xd0], - emu_type: EmuDeviceType::EmuDeviceTVirtioNet, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio_console@a002000")), - base_ipa: 0xa002000, - length: 0x1000, - irq_id: 32 + 0x101, - cfg_list: vec![1, 0xa002000], - emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("virtio_console@a003000")), - base_ipa: 0xa003000, - length: 0x1000, - irq_id: 32 + 0x102, - cfg_list: vec![2, 0xa002000], - emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("iommu")), - base_ipa: 0x12000000, - length: 0x1000000, - irq_id: 0, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTIOMMU, - mediated: false, - }); - emu_dev_config.push(VmEmulatedDeviceConfig { - name: Some(String::from("vm_service")), - base_ipa: 0, - length: 0, - irq_id: HVC_IRQ, - cfg_list: Vec::new(), - emu_type: EmuDeviceType::EmuDeviceTShyper, - mediated: false, - }); + let emu_dev_config = vec![ + VmEmulatedDeviceConfig { + name: Some(String::from("interrupt-controller@3881000")), + base_ipa: Platform::GICD_BASE, + length: 0x1000, + irq_id: 0, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTGicd, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio_net@a001000")), + base_ipa: 0xa001000, + length: 0x1000, + irq_id: 32 + 0x100, + cfg_list: vec![0x74, 0x56, 0xaa, 0x0f, 0x47, 0xd0], + emu_type: EmuDeviceType::EmuDeviceTVirtioNet, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio_console@a002000")), + base_ipa: 0xa002000, + length: 0x1000, + irq_id: 32 + 0x101, + cfg_list: vec![1, 0xa002000], + emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("virtio_console@a003000")), + base_ipa: 0xa003000, + length: 0x1000, + irq_id: 32 + 0x102, + cfg_list: vec![2, 0xa002000], + emu_type: EmuDeviceType::EmuDeviceTVirtioConsole, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("iommu")), + base_ipa: 0x12000000, + length: 0x1000000, + irq_id: 0, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTIOMMU, + mediated: false, + }, + VmEmulatedDeviceConfig { + name: Some(String::from("vm_service")), + base_ipa: 0, + length: 0, + irq_id: HVC_IRQ, + cfg_list: Vec::new(), + emu_type: EmuDeviceType::EmuDeviceTShyper, + mediated: false, + } + ]; // vm0 passthrough let mut pt_dev_config: VmPassthroughDeviceConfig = VmPassthroughDeviceConfig::default(); @@ -148,7 +148,7 @@ pub fn mvm_config_init() { PassthroughRegion { ipa: 0x03ad0000, pa: 0x03ad0000, length: 0x20000, dev_property: true }, // PassthroughRegion { ipa: 0x03b41000, pa: 0x03b41000, length: 0x1000 }, PassthroughRegion { ipa: 0x03c00000, pa: 0x03c00000, length: 0xa0000, dev_property: true }, - PassthroughRegion { ipa: PLATFORM_GICC_BASE, pa: PLATFORM_GICV_BASE, length: 0x2000, dev_property: true }, + PassthroughRegion { ipa: Platform::GICC_BASE, pa: Platform::GICV_BASE, length: 0x2000, dev_property: true }, PassthroughRegion { ipa: 0x8010000, pa: 0x8010000, length: 0x1000, dev_property: true }, PassthroughRegion { ipa: 0x08030000, pa: 0x08030000, length: 0x1000, dev_property: true }, PassthroughRegion { ipa: 0x08050000, pa: 0x08050000, length: 0x1000, dev_property: true }, @@ -204,7 +204,7 @@ pub fn mvm_config_init() { INTERRUPT_IRQ_GUEST_TIMER, 32, 33, 34, 35, 36, 37, 38, 39, 40, 48, 49, 56, 57, 58, 59, 60, 62, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 76, 79, 82, 85, 88, 91, 92, 94, 95, 96, 97, 102, 103, 104, 105, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, - 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, UART_0_INT, 151, 152, + 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, Platform::UART_0_INT, 151, 152, 153, 154, 155, 156, 157, 158, 159, 165, 166, 167, 168, 173, 174, 175, 176, 177, 178, 179, 185, 186, 187, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 208, 212, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 229, 230, 233, 234, 235, 237, 238, @@ -217,11 +217,12 @@ pub fn mvm_config_init() { ]; // vm0 vm_region - let mut vm_region: Vec = Vec::new(); - vm_region.push(VmRegion { - ipa_start: 0xa0000000, - length: 0x60000000, - }); + let vm_region = vec![ + VmRegion { + ipa_start: 0xa0000000, + length: 0x60000000, + } + ]; // vm_region.push(VmRegion { // ipa_start: 0xf0200000, // length: 0xc0000000, diff --git a/src/config/vm_def.rs b/src/config/vm_def.rs index 7f869573b3503f794a076581a4a52570081bd96d..7508e404fd9f6ca82b7da0a504822473b590cf31 100644 --- a/src/config/vm_def.rs +++ b/src/config/vm_def.rs @@ -53,18 +53,18 @@ pub fn init_tmp_config_for_bma1() { pt_dev_config.regions = vec![ PassthroughRegion { ipa: 0x9000000, - pa: UART_1_ADDR, + pa: Platform::UART_1_ADDR, length: 0x1000, dev_property: true, }, PassthroughRegion { ipa: 0x8010000, - pa: PLATFORM_GICV_BASE, + pa: Platform::GICV_BASE, length: 0x2000, dev_property: true, }, ]; - pt_dev_config.irqs = vec![UART_1_INT]; + pt_dev_config.irqs = vec![Platform::UART_1_INT]; // bma vm_region let mut vm_region: Vec = Vec::new(); @@ -133,13 +133,13 @@ pub fn init_tmp_config_for_bma2() { pt_dev_config.regions = vec![ PassthroughRegion { ipa: 0x9000000, - pa: UART_1_ADDR, + pa: Platform::UART_1_ADDR, length: 0x1000, dev_property: true, }, PassthroughRegion { ipa: 0x8010000, - pa: PLATFORM_GICV_BASE, + pa: Platform::GICV_BASE, length: 0x2000, dev_property: true, }, @@ -250,7 +250,7 @@ pub fn init_tmp_config_for_vm1() { // }, PassthroughRegion { ipa: 0x8010000, - pa: PLATFORM_GICV_BASE, + pa: Platform::GICV_BASE, length: 0x2000, dev_property: true, }, @@ -382,7 +382,7 @@ pub fn init_tmp_config_for_vm2() { // }, PassthroughRegion { ipa: 0x8010000, - pa: PLATFORM_GICV_BASE, + pa: Platform::GICV_BASE, length: 0x2000, dev_property: true, }, diff --git a/src/device/virtio/blk.rs b/src/device/virtio/blk.rs index 47584c502134ceeb7360dfef29ecb19cbe3ab8b6..5a5dd1034cca6fb19cf1ce10faa2c862ff6ced81 100644 --- a/src/device/virtio/blk.rs +++ b/src/device/virtio/blk.rs @@ -492,9 +492,9 @@ pub fn generate_blk_req(req: VirtioBlkReq, vq: Virtq, dev: VirtioMmio, cache: us // update used ring if !req.mediated() { todo!("reset num to vq size"); - if !vq.update_used_ring(req_node.iov_total as u32, req_node.desc_chain_head_idx as u32) { - println!("blk_req_handler: fail to update used ring"); - } + // if !vq.update_used_ring(req_node.iov_total as u32, req_node.desc_chain_head_idx as u32) { + // println!("blk_req_handler: fail to update used ring"); + // } } else { push_used_info(req_node.desc_chain_head_idx, req_node.iov_total as u32, vm.id()); } diff --git a/src/driver/aarch64/uart.rs b/src/driver/aarch64/uart.rs index d0fd3e73299284f4ca92af9e447a221110d62132..81adab2720f6417b9459ea12b7bf0bfd708d808b 100644 --- a/src/driver/aarch64/uart.rs +++ b/src/driver/aarch64/uart.rs @@ -10,32 +10,30 @@ use core::ptr; +use crate::board::{Platform, PlatOperation}; + pub fn putc(byte: u8) { + const UART_BASE: usize = Platform::HYPERVISOR_UART_BASE + 0x8_0000_0000; #[cfg(feature = "qemu")] unsafe { - use crate::board::UART_0_ADDR; - ptr::write_volatile(UART_0_ADDR as *mut u8, byte); + ptr::write_volatile(UART_BASE as *mut u8, byte); } // ns16550 #[cfg(feature = "tx2")] unsafe { - use crate::board::UART_1_ADDR; if byte == '\n' as u8 { putc('\r' as u8); } - while ptr::read_volatile((UART_1_ADDR + 0x8_0000_0000 + 20) as *const u8) & 0x20 == 0 {} - ptr::write_volatile((UART_1_ADDR + 0x8_0000_0000) as *mut u8, byte); - // while ptr::read_volatile((UART_1_ADDR + 20) as *const u8) & 0x20 == 0 {} - // ptr::write_volatile(UART_1_ADDR as *mut u8, byte); + while ptr::read_volatile((UART_BASE + 20) as *const u8) & 0x20 == 0 {} + ptr::write_volatile(UART_BASE as *mut u8, byte); } // pl011 #[cfg(feature = "pi4")] unsafe { - use crate::board::UART_0_ADDR; if byte == '\n' as u8 { putc('\r' as u8); } - while (ptr::read_volatile((UART_0_ADDR as usize + 24) as *const u32) & (1 << 5)) != 0 {} - ptr::write_volatile(UART_0_ADDR as *mut u32, byte as u32); + while (ptr::read_volatile((UART_BASE as usize + 24) as *const u32) & (1 << 5)) != 0 {} + ptr::write_volatile(UART_BASE as *mut u32, byte as u32); } } diff --git a/src/kernel/cpu.rs b/src/kernel/cpu.rs index cd69b77e1b36c2952892bfdf12e717a86370c06b..6c0547b5ffad7882c540a8508f166c3ba8d80d5e 100644 --- a/src/kernel/cpu.rs +++ b/src/kernel/cpu.rs @@ -287,8 +287,8 @@ pub fn cpu_init() { let cpu_id = current_cpu().id; if cpu_id == 0 { use crate::arch::power_arch_init; - use crate::board::platform_power_on_secondary_cores; - platform_power_on_secondary_cores(); + use crate::board::{Platform, PlatOperation}; + Platform::power_on_secondary_cores(); power_arch_init(); cpu_if_init(); } diff --git a/src/kernel/vcpu.rs b/src/kernel/vcpu.rs index 3cd23301e986096863b5366d77607b13c5d7b8af..409a0726a39bdf458895ef335db3638949483a4e 100644 --- a/src/kernel/vcpu.rs +++ b/src/kernel/vcpu.rs @@ -17,7 +17,7 @@ use crate::arch::{ ContextFrame, ContextFrameTrait, cpu_interrupt_unmask, GIC_INTS_MAX, GIC_SGI_REGS_NUM, GICC, GicContext, GICD, GICH, VmContext, timer_arch_get_counter, }; -use crate::board::{platform_cpuid_to_cpuif, PLATFORM_GICV_BASE, PLATFORM_VCPU_NUM_MAX}; +use crate::board::{Platform, PlatOperation, PLATFORM_VCPU_NUM_MAX}; use crate::kernel::{current_cpu, interrupt_vm_inject, vm_if_set_state}; use crate::kernel::{active_vcpu_id, active_vm_id}; use crate::lib::memcpy_safe; @@ -60,7 +60,7 @@ impl Vcpu { active_vm_id(), active_vcpu_id() ); - crate::board::platform_cpu_shutdown(); + crate::board::Platform::cpu_shutdown(); } pub fn migrate_vm_ctx_save(&self, cache_pa: usize) { @@ -134,9 +134,9 @@ impl Vcpu { inner.gic_ctx.add_irq(irq as u64); } inner.gic_ctx.add_irq(25); - let gicv_ctlr = unsafe { &*((PLATFORM_GICV_BASE + 0x8_0000_0000) as *const u32) }; + let gicv_ctlr = unsafe { &*((Platform::GICV_BASE + 0x8_0000_0000) as *const u32) }; inner.gic_ctx.set_gicv_ctlr(*gicv_ctlr); - let gicv_pmr = unsafe { &*((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0x4) as *const u32) }; + let gicv_pmr = unsafe { &*((Platform::GICV_BASE + 0x8_0000_0000 + 0x4) as *const u32) }; inner.gic_ctx.set_gicv_pmr(*gicv_pmr); } @@ -147,14 +147,14 @@ impl Vcpu { if irq_state.id != 0 { GICD.set_enable(irq_state.id as usize, irq_state.enable != 0); GICD.set_prio(irq_state.id as usize, irq_state.priority); - GICD.set_trgt(irq_state.id as usize, 1 << platform_cpuid_to_cpuif(current_cpu().id)); + GICD.set_trgt(irq_state.id as usize, 1 << Platform::cpuid_to_cpuif(current_cpu().id)); } } - let gicv_pmr = unsafe { &mut *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0x4) as *mut u32) }; + let gicv_pmr = unsafe { &mut *((Platform::GICV_BASE + 0x8_0000_0000 + 0x4) as *mut u32) }; *gicv_pmr = inner.gic_ctx.gicv_pmr(); // println!("Core[{}] save gic context", current_cpu().id); - let gicv_ctlr = unsafe { &mut *((PLATFORM_GICV_BASE + 0x8_0000_0000) as *mut u32) }; + let gicv_ctlr = unsafe { &mut *((Platform::GICV_BASE + 0x8_0000_0000) as *mut u32) }; *gicv_ctlr = inner.gic_ctx.gicv_ctlr(); // show_vcpu_reg_context(); } @@ -608,25 +608,25 @@ pub fn show_vcpu_reg_context() { println!("GICH_MISR {:x}", GICH.misr()); println!("GICV_CTLR {:x}", unsafe { - *((PLATFORM_GICV_BASE + 0x8_0000_0000) as *const u32) + *((Platform::GICV_BASE + 0x8_0000_0000) as *const u32) }); println!("GICV_PMR {:x}", unsafe { - *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0x4) as *const u32) + *((Platform::GICV_BASE + 0x8_0000_0000 + 0x4) as *const u32) }); println!("GICV_BPR {:x}", unsafe { - *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0x8) as *const u32) + *((Platform::GICV_BASE + 0x8_0000_0000 + 0x8) as *const u32) }); println!("GICV_ABPR {:x}", unsafe { - *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0x1c) as *const u32) + *((Platform::GICV_BASE + 0x8_0000_0000 + 0x1c) as *const u32) }); println!("GICV_STATUSR {:x}", unsafe { - *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0x2c) as *const u32) + *((Platform::GICV_BASE + 0x8_0000_0000 + 0x2c) as *const u32) }); println!( "GICV_APR[0] {:x}, GICV_APR[1] {:x}, GICV_APR[2] {:x}, GICV_APR[3] {:x}", - unsafe { *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0xd0) as *const u32) }, - unsafe { *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0xd4) as *const u32) }, - unsafe { *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0xd8) as *const u32) }, - unsafe { *((PLATFORM_GICV_BASE + 0x8_0000_0000 + 0xdc) as *const u32) }, + unsafe { *((Platform::GICV_BASE + 0x8_0000_0000 + 0xd0) as *const u32) }, + unsafe { *((Platform::GICV_BASE + 0x8_0000_0000 + 0xd4) as *const u32) }, + unsafe { *((Platform::GICV_BASE + 0x8_0000_0000 + 0xd8) as *const u32) }, + unsafe { *((Platform::GICV_BASE + 0x8_0000_0000 + 0xdc) as *const u32) }, ); } diff --git a/src/kernel/vm.rs b/src/kernel/vm.rs index 0e6a6ba4b08f736af4cedbbd355a8724c9640955..03975867f3da0e05ead388a54b03995a11ef9d41 100644 --- a/src/kernel/vm.rs +++ b/src/kernel/vm.rs @@ -19,7 +19,7 @@ use crate::arch::{PAGE_SIZE, PTE_S2_FIELD_AP_RO, PTE_S2_NORMAL, PTE_S2_RO}; use crate::arch::{GICC_CTLR_EN_BIT, GICC_CTLR_EOIMODENS_BIT}; use crate::arch::PageTable; use crate::arch::Vgic; -use crate::board::SHARE_MEM_BASE; +use crate::board::{Platform, PlatOperation}; use crate::config::VmConfigEntry; use crate::device::EmuDevs; use crate::kernel::{ @@ -943,7 +943,7 @@ impl VmInner { intc_dev_id: 0, int_bitmap: Some(BitAlloc4K::default()), // migration_state: false, - share_mem_base: SHARE_MEM_BASE, // hard code + share_mem_base: Platform::SHARE_MEM_BASE, // hard code migrate_save_pf: vec![], migrate_restore_pf: vec![], @@ -972,7 +972,7 @@ impl VmInner { intc_dev_id: 0, int_bitmap: Some(BitAlloc4K::default()), // migration_state: false, - share_mem_base: SHARE_MEM_BASE, // hard code + share_mem_base: Platform::SHARE_MEM_BASE, // hard code migrate_save_pf: vec![], migrate_restore_pf: vec![], iommu_ctx_id: None, diff --git a/src/lib/mod.rs b/src/lib/mod.rs index fa2d5eb278eda09c99bc4f5e2786bfb5c92a1f40..38a59c91107ccaa3ab1155f88924f56a344d49c9 100644 --- a/src/lib/mod.rs +++ b/src/lib/mod.rs @@ -10,7 +10,6 @@ pub use self::barrier::*; pub use self::bitmap::*; -pub use self::cache::*; // pub use self::fatfs::*; pub use self::print::*; pub use self::string::*; @@ -20,7 +19,6 @@ pub use self::util::*; mod barrier; mod bitmap; // mod fatfs; -mod cache; mod print; mod string; mod time; diff --git a/src/vmm/init.rs b/src/vmm/init.rs index 80646e9591f0eb5d0aafa566e967a22a02606de2..3640eb57205a9a00b9555d4626fbf3313ad1af2e 100644 --- a/src/vmm/init.rs +++ b/src/vmm/init.rs @@ -382,15 +382,15 @@ pub unsafe fn vmm_setup_fdt(vm: Vm) { #[cfg(any(feature = "tx2", feature = "qemu"))] fdt_setup_gic( dtb, - PLATFORM_GICD_BASE as u64, - PLATFORM_GICC_BASE as u64, + Platform::GICD_BASE as u64, + Platform::GICC_BASE as u64, emu_cfg.name.unwrap().as_ptr(), ); #[cfg(feature = "pi4")] let _r = fdt_setup_gic( dtb, - (PLATFORM_GICD_BASE | 0xF_0000_0000) as u64, - (PLATFORM_GICC_BASE | 0xF_0000_0000) as u64, + (Platform::GICD_BASE | 0xF_0000_0000) as u64, + (Platform::GICC_BASE | 0xF_0000_0000) as u64, emu_cfg.name.unwrap().as_ptr(), ); } diff --git a/src/vmm/manager.rs b/src/vmm/manager.rs index 9c3a7d4f2bf8de7d097d1014ddbf9bf6238c58e0..1c50bb320a22d7e51881c8425b33938a7fb73049 100644 --- a/src/vmm/manager.rs +++ b/src/vmm/manager.rs @@ -272,7 +272,8 @@ pub fn vmm_reboot() { // If running MVM, reboot the whole system. if vm.id() == 0 { vmm_shutdown_secondary_vm(); - crate::board::platform_sys_reboot(); + use crate::board::{PlatOperation, Platform}; + Platform::sys_reboot(); } // Reset GVM.