From a13d5ac0e810dbe22f272e717ef562c01a037cec Mon Sep 17 00:00:00 2001 From: wangyouwang Date: Tue, 25 Jul 2023 00:16:15 +0800 Subject: [PATCH 1/2] eth i210 driver for mcs Signed-off-by: wangyouwang-hw --- drivers/i210/Makefile | 21 ++ drivers/i210/README.md | 16 + drivers/i210/i210_drv.c | 602 ++++++++++++++++++++++++++++++++++++++ drivers/i210/i210_eth.h | 170 +++++++++++ drivers/i210/i210_intel.h | 227 ++++++++++++++ drivers/i210/i210_main.c | 163 +++++++++++ 6 files changed, 1199 insertions(+) create mode 100644 drivers/i210/Makefile create mode 100644 drivers/i210/README.md create mode 100644 drivers/i210/i210_drv.c create mode 100644 drivers/i210/i210_eth.h create mode 100644 drivers/i210/i210_intel.h create mode 100644 drivers/i210/i210_main.c diff --git a/drivers/i210/Makefile b/drivers/i210/Makefile new file mode 100644 index 00000000..116a1aa8 --- /dev/null +++ b/drivers/i210/Makefile @@ -0,0 +1,21 @@ +KERNELDIR := ${KERNEL_SRC} +CURRENT_PATH := $(shell pwd) + +MK_DIR := $(abspath $(lastword $(MAKEFILE_LIST))) +PWD_DIR := $(shell dirname $(MK_DIR)) +PATH_TO_ANOTHER := $(abspath $(PWD_DIR)/../) +KBUILD_EXTRA_SYMBOLS += $(PATH_TO_ANOTHER)/Module.symvers +# KBUILD_EXTRA_SYMBOLS += /home/wyw/gitee/mcs/mcs/mcs_km/Module.symvers + +target := eth_i210 +obj-m := $(target).o + +$(target)-objs := i210_main.o +$(target)-objs += i210_drv.o ## 非module模块的.c文件 + +build := kernel_modules + +kernel_modules: + $(MAKE) -C $(KERNELDIR) M=$(CURRENT_PATH) modules +clean: + $(MAKE) -C $(KERNELDIR) M=$(CURRENT_PATH) clean \ No newline at end of file diff --git a/drivers/i210/README.md b/drivers/i210/README.md new file mode 100644 index 00000000..7277073f --- /dev/null +++ b/drivers/i210/README.md @@ -0,0 +1,16 @@ +## i210 linux侧驱动 + +### 介绍 + +i210 linux侧驱动（编译产物eth_i210.ko）完成i210网卡的初始化，并将配置基地址告知 uniproton侧， 这样uniproton侧可以直接用于控制i210进行收发包。由于bar的物理地址需要通过mmu进行映射到uniproton，因此编译以来mcs_km.ko，构建流程如下： + +1. mcs_km 按照 https://gitee.com/openeuler/mcs 指导进行构建，生成mcs_km.ko、Module.symvers +2. 将i210目录整体复制到mcs工程的mcs/mcs_km/i210，运行make，得到eth_i210.ko +3. insmod mcs_km.ko +4. insmod eth_i210.ko +5. ./rpmsg_main 加载 uniproton.bin + +### 注意事项 + +1. i210_drv.c 中 clientos_map_info 数组应该和 mcs/mcs_km/mmu_map.c 中的页表clientos_map_info保持一致 +2. i210_eth.h 中 RESERVE_MEM_BASE_CK 宏定义值应该和./rpmsg_main 部署 uniproton.bin 的地址保持一致 diff --git a/drivers/i210/i210_drv.c b/drivers/i210/i210_drv.c new file mode 100644 index 00000000..51721ff8 --- /dev/null +++ b/drivers/i210/i210_drv.c @@ -0,0 +1,602 @@ + +#include +#include +#include +#include +#include +#include "i210_eth.h" +#include "i210_intel.h" + +extern void set_bar_addr(unsigned long phy_addr); + +/* 物理地址基址 */ +u64 g_rxRingBase; +u64 g_rxDmaBase; +u64 g_txRingBase; +u64 g_txDmaBase; +u64 g_macDevBase; + +/* (LINUX侧视角)虚拟地址基址 */ +u64 g_rxRingHostVirtBase; +u64 g_rxDmaHostVirtBase; +u64 g_txRingHostVirtBase; +u64 g_txDmaHostVirtBase; +u64 g_macDevHostVirtBase; + +/* (RTOS侧视角)虚拟地址基址 */ +u64 g_rxRingVirtBase; +u64 g_rxDmaVirtBase; +u64 g_txRingVirtBase; +u64 g_txDmaVirtBase; +u64 g_macDevVirtBase; + +/* (设备侧视角)总线地址基址 */ +u64 g_rxRingBusBase; +u64 g_rxDmaBusBase; +u64 g_txRingBusBase; +u64 g_txDmaBusBase; +u64 g_macDevBusBase; + +int bus_addr_init(void) +{ + const PCI_DEV_INFO_S* i210_dev; + struct pci_dev *pdev; + dma_addr_t dma; + + i210_dev = get_mac_dev_info(0); + pdev = (struct pci_dev *)(i210_dev->pdev); + + dma = dma_map_resource(&(pdev->dev), g_rxRingBase, TOTAL_SIZE, DMA_BIDIRECTIONAL, 0); + if (dma_mapping_error(&(pdev->dev), dma)) { + return -EAGAIN; + } + + g_rxRingBusBase = dma; + g_rxDmaBusBase = g_rxRingBusBase + RX_RING_SIZE; + g_txRingBusBase = g_rxDmaBusBase + RX_DMA_SIZE; + g_txDmaBusBase = g_txRingBusBase + TX_RING_SIZE; + g_macDevBusBase = g_txDmaBusBase + TX_DMA_SIZE; + + return 0; +} + +void bus_addr_destory(u32 dev_id) +{ + const PCI_DEV_INFO_S* i210_dev; + struct pci_dev *pdev; + + i210_dev = get_mac_dev_info(dev_id); + pdev = (struct pci_dev *)(i210_dev->pdev); + if (g_rxRingBusBase != 0) { + dma_unmap_resource(&(pdev->dev), g_rxRingBusBase, TOTAL_SIZE, DMA_BIDIRECTIONAL, 0); + g_rxRingBusBase = 0; + } +} + +#define MEM_ATTR_UNCACHE_RWX (_PAGE_PRESENT | _PAGE_RW | _PAGE_PCD | _PAGE_ACCESSED | _PAGE_DIRTY) +#define MEM_ATTR_CACHE_RWX (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) +#define MEM_ATTR_CACHE_RX (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY) +#define MEM_ATTR_WC_RWX (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PWT) + +#define PAGE_SIZE_2M 0x200000 +#define PAGE_SIZE_4K 0x1000 +enum { + BOOT_TABLE = 0, + PAGE_TABLE, + BAR_TABLE, + DMA_TABLE, + SHAREMEM_TABLE, + LOG_TABLE, + TEXT_TABLE, + DATA_TABLE, + TABLE_MAX +}; + +typedef struct { + unsigned long va; + unsigned long pa; + unsigned long size; + unsigned long attr; + unsigned long page_size; +} mmu_map_info; + +static mmu_map_info clientos_map_info[TABLE_MAX] = { /* 注意: 这里要和 mmu_map.c 中的页表保持一致 */ + { + // boottable + .va = 0x0, + .pa = 0x0, + .size = 0x1000, + .attr = MEM_ATTR_CACHE_RWX, + .page_size = PAGE_SIZE_4K, + }, { + // pagetable + .va = 0xa0000, + .pa = 0xa0000, + .size = 0x6000, + .attr = MEM_ATTR_CACHE_RWX, + .page_size = PAGE_SIZE_4K, + },{ + // bar + .va = 0xf00008000, + .pa = 0x0, + .size = 0x100000, + .attr = MEM_ATTR_UNCACHE_RWX, + .page_size = PAGE_SIZE_4K, + }, { + // dma + .va = 0xf00200000, + .pa = 0x0, + .size = 0x200000, + .attr = MEM_ATTR_UNCACHE_RWX, + .page_size = PAGE_SIZE_2M, + }, { + // sharemem + .va = 0xf00400000, + .pa = 0x0, + .size = 0x2000000, + .attr = MEM_ATTR_UNCACHE_RWX, + .page_size = PAGE_SIZE_2M, + }, { + // log + .va = 0xf02400000, + .pa = 0x0, + .size = 0x200000, + .attr = MEM_ATTR_UNCACHE_RWX, + .page_size = PAGE_SIZE_2M, + }, { + // text + .va = 0xf02600000, + .pa = 0x0, + .size = 0x400000, + .attr = MEM_ATTR_CACHE_RX, + .page_size = PAGE_SIZE_2M, + }, { + // data + .va = 0xf02a00000, + .pa = 0x0, + .size = 0x1000000, + .attr = MEM_ATTR_CACHE_RWX, + .page_size = PAGE_SIZE_2M, + } +}; + +unsigned long calc_dma_phy_addr(unsigned long loadaddr) +{ + int i; + unsigned long phy_addr = loadaddr; + for(i = TEXT_TABLE - 1; i >= DMA_TABLE; i--) { + phy_addr -= (clientos_map_info[i].size >= PAGE_SIZE_2M) ? clientos_map_info[i].size : PAGE_SIZE_2M; + clientos_map_info[i].pa = phy_addr; + } + printk(KERN_INFO "dma_phy_addr:%llx\n", clientos_map_info[DMA_TABLE].pa); + return clientos_map_info[DMA_TABLE].pa; +} + +int net_addr_init(void) +{ + g_rxRingBase = calc_dma_phy_addr(RESERVE_MEM_BASE_CK); /* == clientos_map_info[DMA_TABLE].pa */ + g_rxDmaBase = g_rxRingBase + RX_RING_SIZE; + g_txRingBase = g_rxDmaBase + RX_DMA_SIZE; + g_txDmaBase = g_txRingBase + TX_RING_SIZE; + g_macDevBase = g_txDmaBase + TX_DMA_SIZE; + + g_rxRingVirtBase = clientos_map_info[DMA_TABLE].va; /* == 0xf00200000 */ + g_rxDmaVirtBase = g_rxRingVirtBase + RX_RING_SIZE; + g_txRingVirtBase = g_rxDmaVirtBase + RX_DMA_SIZE; + g_txDmaVirtBase = g_txRingVirtBase + TX_RING_SIZE; + g_macDevVirtBase = g_txDmaVirtBase + TX_DMA_SIZE; + + g_rxRingHostVirtBase = (u64)memremap(g_rxRingBase, TOTAL_SIZE, MEMREMAP_WT); + g_rxDmaHostVirtBase = g_rxRingHostVirtBase + RX_RING_SIZE; + g_txRingHostVirtBase = g_rxDmaHostVirtBase + RX_DMA_SIZE; + g_txDmaHostVirtBase = g_txRingHostVirtBase + TX_RING_SIZE; + g_macDevHostVirtBase = g_txDmaHostVirtBase + TX_DMA_SIZE; + if (g_rxRingHostVirtBase == 0) { + return -ENOMEM; + } + + CALLFUNC(bus_addr_init()); + mac_dev_func_hook(0, bus_addr_destory); + + printk(KERN_INFO "base_addr(phy virt bus host):0x(%llx %llx %llx %llx)\n" + "size(rx_ring rx_dma tx_ring tx_dma):0x(%lx %lx %lx %lx)", + g_rxRingBase, g_rxRingVirtBase, g_rxRingBusBase, g_rxRingHostVirtBase, + RX_RING_SIZE, RX_DMA_SIZE, TX_RING_SIZE, TX_DMA_SIZE); + return 0; +} + +void mac_addr_print(struct mac_dev *macdev) +{ + // 尝试打印网卡的MAC地址 + unsigned char *pmac_addr = (unsigned char*)(macdev->mac_base + 0x5400); + printk(KERN_INFO "i210: MAC address = 0x%llx (%02x:%02x:%02x:%02x:%02x:%02x)", + pmac_addr, pmac_addr[0], pmac_addr[1], pmac_addr[2], pmac_addr[3], pmac_addr[4], pmac_addr[5]); +} + +int net_dma_init(struct mac_dev *dev) +{ + struct mac_queue *q = &dev->queue; + int i; + + q->rx_desc = (struct mac_rx_desc *)g_rxRingHostVirtBase; + ASSERT_INT(q->rx_desc != NULL); + for (i = 0; i < NR_DESC; i++) { + q->rx_desc[i].buffer_addr = g_rxDmaBusBase + i * DMA_SIZE; + q->rx_desc[i].writeback = 0; + } + q->rx_desc = (struct mac_rx_desc *)g_rxRingVirtBase; + q->rx_ring_dma = g_rxRingBusBase; + q->rx_size = RX_RING_SIZE; + + q->tx_desc = (struct mac_tx_desc *)g_txRingHostVirtBase; + ASSERT_INT(q->tx_desc != NULL); + for (i = 0; i < NR_DESC; i++) { + q->tx_desc[i].buffer_addr = g_txDmaBusBase + i * DMA_SIZE; + q->tx_desc[i].lower.data = 0; + q->tx_desc[i].upper.data = 0; + } + q->tx_desc = (struct mac_tx_desc *)g_txRingVirtBase; + q->tx_ring_dma = g_txRingBusBase; + q->tx_size = TX_RING_SIZE; + + q->virt_addr_offset = g_rxRingVirtBase - g_rxRingBase; + q->bus_addr_offset = g_rxRingBusBase - g_rxRingBase; + return 0; +} + +int mac_irq_disable(struct mac_dev *dev) +{ + u32 val; + mac_clear(dev, INTEL_E1000_EIAM, 0); + mac_write(dev, INTEL_E1000_EIMC, 0); + mac_clear(dev, INTEL_E1000_EIAC, 0); + mac_write(dev, INTEL_E1000_IAM, 0); + mac_write(dev, INTEL_E1000_IMC, ~0); + mac_read(dev, INTEL_E1000_STATUS, &val); + + return 0; +} + +#define MASTER_DISABLE_TIMEOUT 800 +int mac_disable_pcie_master(struct mac_dev *dev) +{ + int ret; + mac_set(dev, INTEL_E1000_CTRL, INTEL_E1000_CTRL_GIO_MASTER_DISABLE); + ret = mac_wait(dev, INTEL_E1000_STATUS, INTEL_E1000_STATUS_GIO_MASTER_ENABLE, 0, MASTER_DISABLE_TIMEOUT); + if (ret) { + printk(KERN_INFO "PCI-E Master disable polling has failed. \n"); /* 仅记录即可 */ + } + + return 0; +} + +inline void mac_flush(struct mac_dev *dev) +{ + unsigned int status; + mac_read(dev, INTEL_E1000_STATUS, &status); +} + +int mac_wait_cfg_done(struct mac_dev *dev) +{ + unsigned int mask = INTEL_E1000_STATUS_LAN_INIT_DONE | INTEL_E1000_STATUS_PHYRA; + + CALLFUNC(mac_wait(dev, INTEL_E1000_STATUS, mask, mask, INTEL_E1000_ICH8_LAN_INIT_TIMEOUT)); + mac_clear(dev, INTEL_E1000_STATUS, mask); + + return 0; +} + +int mac_reset(struct mac_dev *dev) +{ + CALLFUNC(mac_disable_pcie_master(dev)); + + mac_write(dev, INTEL_E1000_IMC, 0xffffffff); + mac_write(dev, INTEL_E1000_RCTL, 0); + mac_write(dev, INTEL_E1000_TCTL, INTEL_E1000_TCTL_PSP); + mac_flush(dev); + mdelay(20); + + mac_set(dev, INTEL_E1000_CTRL, INTEL_E1000_CTRL_RST | INTEL_E1000_CTRL_PHY_RST); + mdelay(20); + + CALLFUNC(mac_wait_cfg_done(dev)); + + mac_write(dev, INTEL_E1000_IMC, 0xffffffff); + mac_set(dev, INTEL_E1000_CTRL_EXT, INTEL_E1000_CTRL_EXT_DRV_LOAD); + + return 0; +} + +int rxqueue_i210_init(struct mac_dev *dev) +{ + struct mac_queue *q = &dev->queue; + int reg; + + ASSERT_INT(q->rx_ring_dma != 0); + ASSERT_INT(q->rx_desc != NULL); + q->rx_desc_nr = q->rx_size / sizeof(struct mac_rx_desc); + q->rx_head = 0; + q->rx_tail = q->rx_desc_nr - 1; + + mac_read(dev, E1000_I210_RXDCTL(0), ®); + reg &= ~(1 << 25); + mac_write(dev, E1000_I210_RXDCTL(0), reg); + mdelay(10); + + mac_read(dev, E1000_I210_RXDCTL(0), ®); + printk(KERN_INFO "E1000_RXDCTL after 0x%x\n", reg); + + reg = 0; + mac_read(dev, INTEL_E1000_RCTL, ®); + reg &= ~(3 << 12); + reg &= ~(3 << 16); + reg &= ~(3 << 6); + reg |= ((1 << 1) | (1 << 15) | (1 << 26)); + mac_set(dev, INTEL_E1000_RCTL, reg); + + mac_write(dev, E1000_I210_RDBAL(0), (unsigned int)q->rx_ring_dma); + mac_write(dev, E1000_I210_RDBAH(0), (unsigned int)(q->rx_ring_dma >> 32)); + mac_write(dev, E1000_I210_RDLEN(0), q->rx_size); + mac_write(dev, E1000_I210_RDH(0), q->rx_head); + mac_write(dev, E1000_I210_RDT(0), q->rx_tail); + + mac_read(dev, E1000_I210_RXDCTL(0), ®); + reg |= (1 << 25); + mac_write(dev, E1000_I210_RXDCTL(0), reg); + mac_read(dev, E1000_I210_RXDCTL(0), ®); + printk(KERN_INFO "E1000_RXDCTL after 0x%x\n", reg); + mac_write(dev, E1000_I210_RDT(0), q->rx_tail); + + return 0; +} + +int txqueue_i210_init(struct mac_dev *dev) +{ + struct mac_queue *q = &dev->queue; + int reg; + + ASSERT_INT(q->tx_ring_dma != 0); + ASSERT_INT(q->tx_desc != NULL); + q->tx_desc_nr = q->tx_size / sizeof(struct mac_tx_desc); + q->tx_head = q->tx_tail = 0; + + mac_read(dev, E1000_I210_TXDCTL(0), ®); + printk(KERN_INFO "E1000_TXDCTL before 0x%x\n", reg); + reg &= ~(1 << 25); + mac_write(dev, E1000_I210_TXDCTL(0), reg); + mac_read(dev, E1000_I210_TXDCTL(0), ®); + printk(KERN_INFO "E1000_TXDCTL after 0x%x\n", reg); + + mac_write(dev, E1000_I210_TDBAL(0), (unsigned int)(q->tx_ring_dma & 0xffffffff)); + mac_write(dev, E1000_I210_TDBAH(0), (unsigned int)((q->tx_ring_dma >> 32) & 0xffffffff)); + mac_write(dev, E1000_I210_TDLEN(0), q->tx_size); + + mac_read(dev, E1000_I210_TXDCTL(0), ®); + printk(KERN_INFO "E1000_TXDCTL before 0x%x\n", reg); + reg &= ~(0x1f << 16); + reg |= (1 << 16); + mac_write(dev, E1000_I210_TXDCTL(0), reg); + mac_read(dev, E1000_I210_TXDCTL(0), ®); + printk(KERN_INFO "E1000_TXDCTL after 0x%x\n", reg); + + mac_write(dev, E1000_I210_TDH(0), 0); + mac_write(dev, E1000_I210_TDT(0), 0); + + mac_read(dev, E1000_I210_TXDCTL(0), ®); + printk(KERN_INFO "E1000_TXDCTL before 0x%x\n", reg); + reg |= (1 << 25); + mac_write(dev, E1000_I210_TXDCTL(0), reg); + mac_read(dev, E1000_I210_TXDCTL(0), ®); + printk(KERN_INFO "E1000_TXDCTL after 0x%x\n", reg); + + mac_set(dev, INTEL_E1000_TCTL, INTEL_E1000_TCTL_EN | INTEL_E1000_TCTL_RTLC); + + return 0; +} + +int queue_i210_init(struct mac_dev *dev) +{ + CALLFUNC(rxqueue_i210_init(dev)); + CALLFUNC(txqueue_i210_init(dev)); + return 0; +} + +void put_hw_semaphore(struct mac_dev *dev) +{ + u32 swsm; + mac_read(dev, INTEL_E1000_SWSM, &swsm); + swsm &= ~(INTEL_E1000_SWSM_SMBI | INTEL_E1000_SWSM_SWESMBI); + mac_write(dev, INTEL_E1000_SWSM, swsm); +} + +int get_hw_semaphore(struct mac_dev *dev) +{ + static u32 clear_semaphore_once = 0; + u32 i = 0; + u32 swsm; + s32 timeout = 0x8000; + + /* Get the SW semaphore */ + while (i < timeout) { + mac_read(dev, INTEL_E1000_SWSM, &swsm); + if (!(swsm & INTEL_E1000_SWSM_SMBI)) + break; + + udelay(50); + i++; + } + + if (i == timeout && clear_semaphore_once == 0) { + printk(KERN_INFO "get_hw_semaphore timeout once.\n"); + clear_semaphore_once++; + put_hw_semaphore(dev); + + for (i = 0; i < timeout; i++) { + mac_read(dev, INTEL_E1000_SWSM, &swsm); + if (!(swsm & INTEL_E1000_SWSM_SMBI)) + break; + + udelay(50); + } + + if (i == timeout) { + printk(KERN_INFO "get_hw_semaphore Driver can't access device - SMBI bit is set.\n"); + return -1; + } + } + + /* Get the FW semaphore. */ + for (i = 0; i < timeout; i++) { + mac_read(dev, INTEL_E1000_SWSM, &swsm); + mac_write(dev, INTEL_E1000_SWSM, swsm | INTEL_E1000_SWSM_SWESMBI); + + /* Semaphore acquired if bit latched */ + mac_read(dev, INTEL_E1000_SWSM, &swsm); + if (swsm & INTEL_E1000_SWSM_SWESMBI) + break; + + udelay(50); + } + + if (i == timeout) { + /* Release semaphores */ + put_hw_semaphore(dev); + printk(KERN_INFO "get_hw_semaphore Driver can't access the NVM\n"); + return -1; + } + + return 0; +} + +int release_swfw_sync(struct mac_dev *dev, u32 mask) +{ + u32 swfw_sync; + while (get_hw_semaphore(dev)) + ; /* Empty */ + + mac_read(dev, INTEL_E1000_SW_FW_SYNC, &swfw_sync); + swfw_sync &= ~mask; + mac_write(dev, INTEL_E1000_SW_FW_SYNC, swfw_sync); + + put_hw_semaphore(dev); + return 0; +} + +int mac_init(struct mac_dev *dev) +{ + u32 val; + mac_read(dev, INTEL_E1000_CTRL_EXT, &val); + mac_read(dev, INTEL_E1000_FWSM, &val); + mac_read(dev, INTEL_E1000_EECD, &val); + mac_read(dev, INTEL_E1000_CTRL_EXT, &val); + mac_write(dev, INTEL_E1000_CTRL_EXT, val); + mac_read(dev, INTEL_E1000_STATUS, &val); + + release_swfw_sync(dev, 0xffffffff); + + mac_irq_disable(dev); + mac_reset(dev); + queue_i210_init(dev); + + return 0; +} + +int mac_dev_info_init(void) +{ + struct mac_dev *macdev; + const PCI_DEV_INFO_S* mac_dev_info = get_mac_dev_info(0); + if (mac_dev_info == NULL) { + printk(KERN_INFO "mac_dev_info_init mac_dev_info is null\n"); + return -1; + } + + /* 1. 全局变量初始化：几种基地址的初始化 */ + CALLFUNC(net_addr_init()); + + /* 2. macdev指向存储空间结构体，并初始化pci设备的基地址 */ + macdev = (struct mac_dev *)g_macDevHostVirtBase; + macdev->mac_base = (u64)(mac_dev_info->io_virt); + + /* 3. pci设备软、硬件的初始化：mac地址打印, dma相关空间配置, 硬件初始化 */ + mac_addr_print(macdev); + CALLFUNC(net_dma_init(macdev)); + CALLFUNC(mac_init(macdev)); + mdelay(1000); + + /* 4. 将pci设备的物理地址传递给mcs_km.ko, 配置rtos.bin运行页表时使用 */ + set_bar_addr((unsigned long)mac_dev_info->io_phy); + macdev->mac_base = clientos_map_info[BAR_TABLE].va; /* rtos侧的访问pci设备使用的虚拟地址 */ + + /* 5. dump mac_dev, 用于比较rtos侧是否正确获取信息 */ + mac_dev_dump(macdev); + return 0; +} + +#ifdef MACDEV_OPERATE +static inline void plat_writel(u32 val, u32 *addr) +{ + *addr = val; +} + +static inline u32 plat_readl(u32 *addr) +{ + return *addr; +} + +int mac_read(struct mac_dev *dev, int offset, u32 *val) +{ + *val = plat_readl((u32*)(size_t)(dev->mac_base + offset)); + return 0; +} + +int mac_write(struct mac_dev *dev, int offset, u32 val) +{ + plat_writel(val, (u32*)(size_t)(dev->mac_base + offset)); + return 0; +} + +int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, unsigned int expect, int timeout) +{ + unsigned int val; + while (timeout--) { + mdelay(10); + CALLFUNC(mac_read(dev, offset, &val)); + if ((val & bitmask) == expect) + return 0; + } + printk(KERN_INFO "offset=%x bitmask=%x expect=%x timeout=%d val=%x\n", offset, bitmask, expect, timeout, val); + return -1; +} + +int mac_op(struct mac_dev *dev, int offset, unsigned int clear, unsigned int set) +{ + unsigned int val; + CALLFUNC(mac_read(dev, offset, &val)); + val &= ~clear; + val |= set; + CALLFUNC(mac_write(dev, offset, val)); + return 0; +} + +int mac_set(struct mac_dev *dev, int offset, unsigned int bits) +{ + return mac_op(dev, offset, 0, bits); +} + +int mac_clear(struct mac_dev *dev, int offset, unsigned int bits) +{ + return mac_op(dev, offset, bits, 0); +} +#endif + +void mac_dev_dump(struct mac_dev *macdev) +{ + if (macdev == NULL) + return; + + printk(KERN_INFO "macdev: queue{%llx %llx %llx %x %llx %x,\n 0x%llx, %x %x %x,\n 0x%llx, %x %x %x}\n 0x%llx 0x%llx %x %x %x", + macdev->queue.virt_addr_offset, macdev->queue.bus_addr_offset, macdev->queue.rx_ring_dma, macdev->queue.rx_size, macdev->queue.tx_ring_dma, macdev->queue.tx_size, + (long long unsigned int)macdev->queue.rx_desc, macdev->queue.rx_desc_nr, macdev->queue.rx_head, macdev->queue.rx_tail, + (long long unsigned int)macdev->queue.tx_desc, macdev->queue.tx_desc_nr, macdev->queue.tx_head, macdev->queue.tx_tail, + macdev->mac_base, macdev->pci_cfg_base, macdev->pm_cap, macdev->msi_cap, macdev->locked); +} \ No newline at end of file diff --git a/drivers/i210/i210_eth.h b/drivers/i210/i210_eth.h new file mode 100644 index 00000000..54d60e43 --- /dev/null +++ b/drivers/i210/i210_eth.h @@ -0,0 +1,170 @@ +#ifndef _I210_ETH_H_ +#define _I210_ETH_H_ + +/********这里涉及多个地址概念，如下图示******** + * 本驱动代码需要将rtos侧的地址预配置好 + * linux/oe | rtos_ck + * ↓↓↓ | ↓↓↓ + * virt_addr_host | virt_addr_guest + *---------------------|--------------------- + * phy_addr + *------------------------------------------- + * bus_addr(dma_addr) + * ↑↑↑ + * i210_eth + */ + +#define RESERVE_MEM_BASE_CK 0x400000000ULL + +#define RESERVE_MEM_BASE 0x400200000ULL +#define NR_DESC 128 +#define DMA_SIZE 2048 + +#define RX_RING_BASE RESERVE_MEM_BASE +#define RX_RING_SIZE (sizeof(struct mac_rx_desc) * NR_DESC) +#define RX_DMA_BASE (RX_RING_BASE + RX_RING_SIZE) +#define RX_DMA_SIZE (DMA_SIZE * NR_DESC) + +#define TX_RING_BASE (RX_DMA_BASE + RX_DMA_SIZE) +#define TX_RING_SIZE (sizeof(struct mac_tx_desc) * NR_DESC) +#define TX_DMA_BASE (TX_RING_BASE + TX_RING_SIZE) +#define TX_DMA_SIZE (DMA_SIZE * NR_DESC) + +#define MAC_DEV_BASE (TX_DMA_BASE + TX_DMA_SIZE) +#define MAC_DEV_SIZE (sizeof(struct mac_dev)) +#define TOTAL_SIZE (MAC_DEV_BASE + MAC_DEV_SIZE - RESERVE_MEM_BASE) + +#define E1000_I210_RDBAL(_n) (0x0c000 + ((_n) * 0x40)) +#define E1000_I210_RDBAH(_n) (0x0c004 + ((_n) * 0x40)) +#define E1000_I210_RDLEN(_n) (0x0c008 + ((_n) * 0x40)) +#define E1000_I210_RDH(_n) (0x0c010 + ((_n) * 0x40)) +#define E1000_I210_RDT(_n) (0x0c018 + ((_n) * 0x40)) +#define E1000_I210_RXDCTL(_n) (0x0c028 + ((_n) * 0x40)) + +#define E1000_I210_TDBAL(_n) (0x0e000 + ((_n) * 0x40)) +#define E1000_I210_TDBAH(_n) (0x0e004 + ((_n) * 0x40)) +#define E1000_I210_TDLEN(_n) (0x0e008 + ((_n) * 0x40)) +#define E1000_I210_TDH(_n) (0x0e010 + ((_n) * 0x40)) +#define E1000_I210_TDT(_n) (0x0e018 + ((_n) * 0x40)) +#define E1000_I210_TXDCTL(_n) (0x0e028 + ((_n) * 0x40)) + +#define E1000_RDBAL(_n) E1000_I210_RDBAL(_n) +#define E1000_RDBAH(_n) E1000_I210_RDBAH(_n) +#define E1000_RDLEN(_n) E1000_I210_RDLEN(_n) +#define E1000_RDH(_n) E1000_I210_RDH(_n) +#define E1000_RDT(_n) E1000_I210_RDT(_n) +#define E1000_RXDCTL(_n) E1000_I210_RXDCTL(_n) + +#define E1000_TDBAL(_n) E1000_I210_TDBAL(_n) +#define E1000_TDBAH(_n) E1000_I210_TDBAH(_n) +#define E1000_TDLEN(_n) E1000_I210_TDLEN(_n) +#define E1000_TDH(_n) E1000_I210_TDH(_n) +#define E1000_TDT(_n) E1000_I210_TDT(_n) + +typedef void (*pfn_free_dma_map_t)(unsigned int dev_id); +typedef struct { + unsigned int dev_id; + void __iomem* io_phy; + void __iomem* io_virt; + void *pdev; /* struct pci_dev */ + pfn_free_dma_map_t pfn_free_dma_map; +} PCI_DEV_INFO_S; + +#define I210_DEV_MAX_NUM 4 /* 最大支持i210设备个数 */ +const PCI_DEV_INFO_S* get_mac_dev_info(u32 dev_id); +void mac_dev_func_hook(u32 dev_id, pfn_free_dma_map_t fn_free_dma_map); + +/* Transmit Descriptor */ +struct mac_tx_desc { + unsigned long long buffer_addr; /* Address of the descriptor's data buffer */ + union { + unsigned int data; + struct { + unsigned short length; /* Data buffer length */ + unsigned char cso; /* Checksum offset */ + unsigned char cmd; /* Descriptor control */ +#define E1000_TXD_CMD_EOP 0x01 /* End of Packet */ +#define E1000_TXD_CMD_IFCS 0x02 /* Insert FCS (Ethernet CRC) */ +#define E1000_TXD_CMD_IC 0x04 /* Insert Checksum */ +#define E1000_TXD_CMD_RS 0x08 /* Report Status */ +#define E1000_TXD_CMD_RPS 0x10 /* Report Packet Sent */ +#define E1000_TXD_CMD_DEXT 0x20 /* Desc extension (0 = legacy) */ +#define E1000_TXD_CMD_VLE 0x40 /* Add VLAN tag */ +#define E1000_TXD_CMD_IDE 0x80 /* Interrupt Delay Enable */ + } flags; + } lower; + union { + unsigned int data; + struct { + unsigned char status; /* Descriptor status */ + unsigned char css; /* Checksum start */ + unsigned short speial; + } fields; + } upper; +}; + +/* Receive Descriptor - Extended */ +struct mac_rx_desc { + unsigned long long buffer_addr; + unsigned long long writeback; /* writeback */ +}; + +struct mac_queue { + unsigned long long virt_addr_offset; + unsigned long long bus_addr_offset; + unsigned long long rx_ring_dma; + unsigned int rx_size; + unsigned long long tx_ring_dma; + unsigned int tx_size; + struct mac_rx_desc *rx_desc; + int rx_desc_nr; + int rx_head; + int rx_tail; + struct mac_tx_desc *tx_desc; + int tx_desc_nr; + int tx_head; + int tx_tail; +}; + +typedef struct mac_dev { + struct mac_queue queue; + unsigned long long mac_base; + unsigned long long pci_cfg_base; + unsigned int pm_cap; + unsigned int msi_cap; + int locked; +} MAC_DEV_S; + +#if 1 /* comm func */ +#define ASSERT_INT(exp) do { \ + if (!(exp)) { \ + printk(KERN_INFO "assert int "#exp" false!!"); \ + return -1;\ + } \ +} while(0) + +#define __CALLFUNC(func, op, val) do { \ + int ret = func;\ + if (ret) { \ + printk(KERN_INFO "call "#func" faild err=%d\n", ret); \ + op val;\ + } \ + } while(0) + +#define CALLFUNC(func) __CALLFUNC(func, return, ret) +#endif /* comm func */ + +#define MACDEV_OPERATE +#ifdef MACDEV_OPERATE +int mac_read(struct mac_dev *dev, int offset, u32 *val); +int mac_write(struct mac_dev *dev, int offset, u32 val); +int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, unsigned int expect, int timeout); +int mac_op(struct mac_dev *dev, int offset, unsigned int clear, unsigned int set); +int mac_set(struct mac_dev *dev, int offset, unsigned int bits); +int mac_clear(struct mac_dev *dev, int offset, unsigned int bits); +#endif + +void mac_dev_dump(struct mac_dev *macdev); +int mac_dev_info_init(void); + +#endif \ No newline at end of file diff --git a/drivers/i210/i210_intel.h b/drivers/i210/i210_intel.h new file mode 100644 index 00000000..9d1657a1 --- /dev/null +++ b/drivers/i210/i210_intel.h @@ -0,0 +1,227 @@ +#ifndef _I210_INTEL_H_ +#define _I210_INTEL_H_ + +#define INTEL_E1000_CTRL 0x00000 /* Device Control - RW */ +/* Device Control */ +#define INTEL_E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define INTEL_E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ +#define INTEL_E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define INTEL_E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define INTEL_E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define INTEL_E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define INTEL_E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define INTEL_E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define INTEL_E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define INTEL_E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define INTEL_E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define INTEL_E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define INTEL_E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANDPHYPC */ +#define INTEL_E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANDPHYPC */ +#define INTEL_E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ +#define INTEL_E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define INTEL_E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define INTEL_E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ +#define INTEL_E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ +#define INTEL_E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define INTEL_E1000_CTRL_RST 0x04000000 /* Global reset */ +#define INTEL_E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define INTEL_E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define INTEL_E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define INTEL_E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +#define INTEL_E1000_STATUS 0x00008 /* Device Status - RO */ +/* Device Status */ +#define INTEL_E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define INTEL_E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define INTEL_E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define INTEL_E1000_STATUS_FUNC_SHIFT 2 +#define INTEL_E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define INTEL_E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define INTEL_E1000_STATUS_SPEED_MASK 0x000000C0 +#define INTEL_E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define INTEL_E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define INTEL_E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define INTEL_E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ +#define INTEL_E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ +#define INTEL_E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ +#define INTEL_E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ +#define INTEL_E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ +#define INTEL_E1000_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ + +#define INTEL_E1000_STRAP 0x0000C +#define INTEL_E1000_STRAP_SMBUS_ADDRESS_MASK 0x00fe0000 +#define INTEL_E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 +#define INTEL_E1000_STRAP_SMT_FREQ_MASK 0x00003000 +#define INTEL_E1000_STRAP_SMT_FREQ_SHIFT 12 + +#define INTEL_E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define INTEL_E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define INTEL_E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +#define INTEL_E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ +#define INTEL_E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ +#define INTEL_E1000_CTRL_EXT_FORCE_SMBUS 0x000800 /* Force SMBus mode */ +#define INTEL_E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define INTEL_E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +#define INTEL_E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ +#define INTEL_E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ +#define INTEL_E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define INTEL_E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00c00000 +#define INTEL_E1000_CTRL_EXT_EIAME 0x01000000 +#define INTEL_E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ +#define INTEL_E1000_CTRL_EXT_IAME 0x08000000 /* Int Ack Auto-mask */ +#define INTEL_E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ +#define INTEL_E1000_CTRL_EXT_LSECCK 0x00001000 +#define INTEL_E1000_CTRL_EXT_PHYPDEN 0x00100000 + +#define INTEL_E1000_FLA 0x0001C /* Flash Access - RW */ +#define INTEL_E1000_MDIC 0x00020 /* MDI Control - RW */ +#define INTEL_E1000_SCTL 0x00024 /* SerDes Control - RW */ +#define INTEL_E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +#define INTEL_E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +#define INTEL_E1000_FEXT 0x0002C /* Future Externed - RW */ +#define INTEL_E1000_FEXTNVM 0x00028 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM3 0x0003C /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM4 0x00024 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM5 0x00014 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM6 0x00010 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM7 0x000E4 /* Future Externed NVM - RW */ + +#define INTEL_E1000_FEXTNVM8 0x05bb0 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM9 0x05bb4 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM11 0x05bbc /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM12 0x05bc0 /* Future Externed NVM - RW */ +#define INTEL_E1000_PCIEANACFG 0x00F18 /* PCIE Analog config */ +#define INTEL_E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */ +#define INTEL_E1000_FCT 0x00030 /* Flow Control Type - RW */ +#define INTEL_E1000_VET 0x00038 /* VLAN Ether Type - RW */ +#define INTEL_E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +#define INTEL_E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +#define INTEL_E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +#define INTEL_E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +#define INTEL_E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define INTEL_E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ +#define INTEL_E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ +#define INTEL_E1000_SVCR 0x000F0 +#define INTEL_E1000_SVT 0x000F4 +#define INTEL_E1000_LPIC 0x000FC /* Low Power IDLE control */ +#define INTEL_E1000_RCTL 0x00100 /* RX Control - RW */ +#define INTEL_E1000_RCTL_EN 0x00000002 /* enable */ +#define INTEL_E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define INTEL_E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define INTEL_E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define INTEL_E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define INTEL_E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define INTEL_E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define INTEL_E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define INTEL_E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ +#define INTEL_E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define INTEL_E1000_RCTL_RDMTS_HEX 0x00010000 +#define INTEL_E1000_RCTL_RDMTS1_HEX INTEL_E1000_RCTL_RDMTS_HEX +#define INTEL_E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define INTEL_E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define INTEL_E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +/* these buff sizes are valid if E1000_RCTL_BSEX is 0 */ +#define INTEL_E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define INTEL_E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define INTEL_E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define INTEL_E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +/* these buff sizes are valid if E1000_RCTL_BSEX is 1 */ +#define INTEL_E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define INTEL_E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define INTEL_E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define INTEL_E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define INTEL_E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define INTEL_E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define INTEL_E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ +#define INTEL_E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define INTEL_E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ +#define INTEL_E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ + +#define INTEL_E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +#define INTEL_E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +#define INTEL_E1000_RXCW 0x00180 /* RX Configuration Word - RW */ +#define INTEL_E1000_PBA_ECC 0x01100 /* PBA ECC register */ +#define INTEL_E1000_TCTL 0x00400 /* TX Control - RW */ +/* Transmit Control */ +#define INTEL_E1000_TCTL_EN 0x00000002 /* enable tx */ +#define INTEL_E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define INTEL_E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define INTEL_E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define INTEL_E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define INTEL_E1000_TCTL_MULR 0x10000000 /* Multiple request support */ + +#define INTEL_E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ +#define INTEL_E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +#define INTEL_E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define INTEL_E1000_LEDCTL 0x00E00 /* LED Control - RW */ +#define INTEL_E1000_LEDMUX 0x08130 /* LED MUX Control */ +#define INTEL_E1000_EXTCNF_CTRL 0x00f00 /* Extended Configuration Control */ +#define INTEL_E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x20 +#define INTEL_E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x1 +#define INTEL_E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x8 +#define INTEL_E1000_EXTCNF_CTRL_SWFLAG 0x20 +#define INTEL_E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x80 + +/* Low Power IDLE Control */ +#define INTEL_E1000_LPIC_LPIET_SHIFT 24 + +#define INTEL_E1000_EXTCNF_SIZE 0x00f08 +#define INTEL_E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00ff0000 +#define INTEL_E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 +#define INTEL_E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 +#define INTEL_E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 + +#define INTEL_E1000_PHY_CTRL 0xf10 +#define INTEL_E1000_PHY_CTRL_D0A_LPLU 0x2 +#define INTEL_E1000_PHY_CTRL_NOND0A_LPLU 0x4 +#define INTEL_E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x8 +#define INTEL_E1000_PHY_CTRL_GBE_DISABLE 0x40 + +#define INTEL_E1000_POEMB E1000_PHY_CTRL /* Packet Buffer Allocation - RW */ +#define INTEL_E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +#define INTEL_E1000_PBS 0x01008 /* Packet Buffer Size */ +#define INTEL_E1000_PBECCSTS 0x0100C /* Packet Buffer ECC status - RW */ +#define INTEL_E1000_IOSFPC 0x0f28 /* tx corrupted data */ +#define INTEL_E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +#define INTEL_E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define INTEL_E1000_FLOP 0x0103C /* Flash Opcode Register - RW */ +#define INTEL_E1000_ERT 0x02008 /* */ +#define INTEL_E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +#define INTEL_E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define INTEL_E1000_PSRCTL 0x02170 /* */ +#define INTEL_E1000_RDFH 0x02410 /* */ +#define INTEL_E1000_RDFT 0x02418 /* */ +#define INTEL_E1000_RDFHS 0x02420 /* */ +#define INTEL_E1000_RDFTS 0x02428 /* */ +#define INTEL_E1000_RDFPC 0x02430 /* */ +/* */ +#define INTEL_E1000_RDTR 0x02820 /* */ +#define INTEL_E1000_RADV 0x0282C /* */ + +#define INTEL_E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +#define INTEL_E1000_RFCTL 0x05008 /* Receive Filter Control*/ + +#define INTEL_E1000_KABGTXD 0x03004 /* */ +#define INTEL_E1000_KABGTXD_BGSQLBIAS 0x050000 /* */ + +#define INTEL_E1000_H2ME 0x05b50 /* */ +#define INTEL_E1000_H2ME_ULP 0x0800 /* */ +#define INTEL_E1000_H2ME_ENFORCE_SETTINGS 0x01000 /* */ + +#define INTEL_E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ +#define INTEL_E1000_SWSM 0x05B50 /* SW Semaphore */ +#define INTEL_E1000_FWSM 0x05B54 /* FW Semaphore */ +#define INTEL_E1000_FWSM_ULP_CFG_DONE 0x0400 /* FW Semaphore */ +#define INTEL_E1000_PCS_LCTL_FORCE_FCTRL 0x080 /* */ +#define INTEL_E1000_PCS_LSTS_AN_COMPLETE 0x010000 /* */ +#define INTEL_E1000_ICH8_LAN_INIT_TIMEOUT 1500 /* */ + +/* SW Semaphore Register */ +#define INTEL_E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define INTEL_E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ + +#define INTEL_E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ +#define INTEL_E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ +#define INTEL_E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ + +#endif diff --git a/drivers/i210/i210_main.c b/drivers/i210/i210_main.c new file mode 100644 index 00000000..505f2738 --- /dev/null +++ b/drivers/i210/i210_main.c @@ -0,0 +1,163 @@ +#include +#include +#include +#include "i210_eth.h" + +const char g_i210_driver_name[] = "i210_eth"; +#define E1000_DEV_ID_I210_COPPER 0x1533 +#define E1000_DEV_ID_I210_FIBER 0x1536 +#define E1000_DEV_ID_I210_SERDES 0x1537 +#define E1000_DEV_ID_I210_SGMII 0x1538 +#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B +#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C + +static struct pci_device_id i210_pci_tbl[] = { + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS) }, + { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS) }, + { 0, } /* required last entry */ +}; + +MODULE_DEVICE_TABLE(pci, i210_pci_tbl); + +u32 global_dev_num_i210 = 0; +PCI_DEV_INFO_S global_mac_dev_info[I210_DEV_MAX_NUM] = { {0} }; + +const PCI_DEV_INFO_S* get_mac_dev_info(u32 dev_id) +{ + if ((dev_id >= global_dev_num_i210) || (dev_id >= I210_DEV_MAX_NUM)) { + return NULL; + } + return &(global_mac_dev_info[dev_id]); +} + +void mac_dev_func_hook(u32 dev_id, pfn_free_dma_map_t fn_free_dma_map) +{ + if ((dev_id >= global_dev_num_i210) || (dev_id >= I210_DEV_MAX_NUM)) { + return; + } + global_mac_dev_info[dev_id].pfn_free_dma_map = fn_free_dma_map; +} + +static int i210_probe(struct pci_dev *pdev, const struct pci_device_id *ent) +{ + int err; + u8 __iomem *bar_addr; + u32 bar_size; + void __iomem *bar; + unsigned char *pmac_addr; + const char *eth_dev_name = pci_name(to_pci_dev(&pdev->dev)); + printk(KERN_INFO "%s probe func: eth_dev_name:%s\n", g_i210_driver_name, eth_dev_name); + if (global_dev_num_i210 >= I210_DEV_MAX_NUM) { + return -E2BIG; + } + global_dev_num_i210++; + + err = pci_enable_device(pdev); + if (err != 0) { + printk(KERN_INFO "pci enable device failed\n"); + return err; + } + + err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (err != 0) { + err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (err) { + dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); + goto err_dma; + } + } + + err = pci_request_regions(pdev, g_i210_driver_name); + if (err) + goto err_dma; + + pci_set_master(pdev); + pci_save_state(pdev); + + /* 打印设备的BAR地址和大小 */ + bar_addr = (u8 __iomem *)pci_resource_start(pdev, 0); + bar_size = pci_resource_len(pdev, 0); + printk(KERN_INFO "i210: BAR0 address = 0x%llx, size = %u", (u64)bar_addr, bar_size); + + /* 映射BAR空间 */ + bar = pci_iomap(pdev, 0, bar_size); + if (!bar) { + printk(KERN_INFO "i210: Failed to map BAR0"); + err = -ENOMEM; + goto err_pci_reg; + } + + global_mac_dev_info[global_dev_num_i210 - 1].dev_id = global_dev_num_i210 - 1; + global_mac_dev_info[global_dev_num_i210 - 1].pdev = (struct pci_dev *)pdev; + global_mac_dev_info[global_dev_num_i210 - 1].io_phy = bar_addr; + global_mac_dev_info[global_dev_num_i210 - 1].io_virt = bar; + pci_set_drvdata(pdev, &(global_mac_dev_info[global_dev_num_i210 - 1])); + printk(KERN_INFO "eth_i210[%u]: io_addr:pa=0x%llx va=0x%llx\n", (global_dev_num_i210 - 1), + (u64)global_mac_dev_info[global_dev_num_i210 - 1].io_phy, + (u64)global_mac_dev_info[global_dev_num_i210 - 1].io_virt); + + /* 尝试打印网卡的MAC地址 */ + pmac_addr = (unsigned char*)(bar + 0x5400); + printk(KERN_INFO "i210: MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", + pmac_addr[0], pmac_addr[1], pmac_addr[2], pmac_addr[3], pmac_addr[4], pmac_addr[5]); + + /* 初始化mac_dev_info */ + err = mac_dev_info_init(); + if (err != 0) { + printk(KERN_INFO "mac_dev_info_init fail, ret:0x%x", err); + } + + return 0; + +err_pci_reg: + pci_release_regions(pdev); +err_dma: + pci_disable_device(pdev); + return err; +} + +static void i210_remove(struct pci_dev *pdev) +{ + PCI_DEV_INFO_S *mac_dev; + printk(KERN_INFO "remove %s\n", g_i210_driver_name); + + mac_dev = (PCI_DEV_INFO_S *)pci_get_drvdata(pdev); + if (mac_dev->io_virt) { + pci_iounmap(pdev, mac_dev->io_virt); + } + if (mac_dev->pfn_free_dma_map != NULL) { + mac_dev->pfn_free_dma_map(mac_dev->dev_id); + } + pci_release_regions(pdev); + pci_disable_device(pdev); +} + +static struct pci_driver i210_driver = { + .name = g_i210_driver_name, + .id_table = i210_pci_tbl, + .probe = i210_probe, + .remove = i210_remove, +}; + +static int __init i210_init(void) +{ + printk(KERN_INFO "Hello, i210_init!\n"); + return pci_register_driver(&i210_driver); +} + +static void __exit i210_exit(void) +{ + pci_unregister_driver(&i210_driver); + printk(KERN_INFO "Byebye!"); +} + +module_init(i210_init); +module_exit(i210_exit); + +MODULE_AUTHOR("OpenEuler Embedded"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_DESCRIPTION("Intel i210 Gigabit Ethernet driver"); \ No newline at end of file -- Gitee From 9e4519dcafc48dd4f4317b905ffb6e587ba449ea Mon Sep 17 00:00:00 2001 From: wangyouwang Date: Wed, 26 Jul 2023 13:18:40 +0800 Subject: [PATCH 2/2] I210: driver for mcs Signed-off-by: wangyouwang-hw --- drivers/i210/i210_drv.c | 87 +++++---- drivers/i210/i210_eth.h | 8 +- drivers/i210/i210_intel.h | 360 +++++++++++++++++++------------------- drivers/i210/i210_main.c | 42 +++-- 4 files changed, 264 insertions(+), 233 deletions(-) diff --git a/drivers/i210/i210_drv.c b/drivers/i210/i210_drv.c index 51721ff8..ea6b7f4d 100644 --- a/drivers/i210/i210_drv.c +++ b/drivers/i210/i210_drv.c @@ -46,7 +46,8 @@ int bus_addr_init(void) i210_dev = get_mac_dev_info(0); pdev = (struct pci_dev *)(i210_dev->pdev); - dma = dma_map_resource(&(pdev->dev), g_rxRingBase, TOTAL_SIZE, DMA_BIDIRECTIONAL, 0); + dma = dma_map_resource(&(pdev->dev), g_rxRingBase, TOTAL_SIZE, + DMA_BIDIRECTIONAL, 0); if (dma_mapping_error(&(pdev->dev), dma)) { return -EAGAIN; } @@ -68,15 +69,20 @@ void bus_addr_destory(u32 dev_id) i210_dev = get_mac_dev_info(dev_id); pdev = (struct pci_dev *)(i210_dev->pdev); if (g_rxRingBusBase != 0) { - dma_unmap_resource(&(pdev->dev), g_rxRingBusBase, TOTAL_SIZE, DMA_BIDIRECTIONAL, 0); + dma_unmap_resource(&(pdev->dev), g_rxRingBusBase, TOTAL_SIZE, + DMA_BIDIRECTIONAL, 0); g_rxRingBusBase = 0; } } -#define MEM_ATTR_UNCACHE_RWX (_PAGE_PRESENT | _PAGE_RW | _PAGE_PCD | _PAGE_ACCESSED | _PAGE_DIRTY) -#define MEM_ATTR_CACHE_RWX (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) -#define MEM_ATTR_CACHE_RX (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY) -#define MEM_ATTR_WC_RWX (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PWT) +#define MEM_ATTR_UNCACHE_RWX \ + (_PAGE_PRESENT | _PAGE_RW | _PAGE_PCD | _PAGE_ACCESSED | _PAGE_DIRTY) +#define MEM_ATTR_CACHE_RWX \ + (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) +#define MEM_ATTR_CACHE_RX \ + (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY) +#define MEM_ATTR_WC_RWX \ + (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PWT) #define PAGE_SIZE_2M 0x200000 #define PAGE_SIZE_4K 0x1000 @@ -99,8 +105,8 @@ typedef struct { unsigned long attr; unsigned long page_size; } mmu_map_info; - -static mmu_map_info clientos_map_info[TABLE_MAX] = { /* 注意: 这里要和 mmu_map.c 中的页表保持一致 */ +/* 注意: 这里要和 mmu_map.c 中的页表保持一致 */ +static mmu_map_info clientos_map_info[TABLE_MAX] = { { // boottable .va = 0x0, @@ -165,7 +171,8 @@ unsigned long calc_dma_phy_addr(unsigned long loadaddr) int i; unsigned long phy_addr = loadaddr; for(i = TEXT_TABLE - 1; i >= DMA_TABLE; i--) { - phy_addr -= (clientos_map_info[i].size >= PAGE_SIZE_2M) ? clientos_map_info[i].size : PAGE_SIZE_2M; + phy_addr -= (clientos_map_info[i].size >= PAGE_SIZE_2M) ? + (clientos_map_info[i].size) : (PAGE_SIZE_2M); clientos_map_info[i].pa = phy_addr; } printk(KERN_INFO "dma_phy_addr:%llx\n", clientos_map_info[DMA_TABLE].pa); @@ -174,13 +181,13 @@ unsigned long calc_dma_phy_addr(unsigned long loadaddr) int net_addr_init(void) { - g_rxRingBase = calc_dma_phy_addr(RESERVE_MEM_BASE_CK); /* == clientos_map_info[DMA_TABLE].pa */ + g_rxRingBase = calc_dma_phy_addr(RESERVE_MEM_BASE_CK); g_rxDmaBase = g_rxRingBase + RX_RING_SIZE; g_txRingBase = g_rxDmaBase + RX_DMA_SIZE; g_txDmaBase = g_txRingBase + TX_RING_SIZE; g_macDevBase = g_txDmaBase + TX_DMA_SIZE; - g_rxRingVirtBase = clientos_map_info[DMA_TABLE].va; /* == 0xf00200000 */ + g_rxRingVirtBase = clientos_map_info[DMA_TABLE].va; g_rxDmaVirtBase = g_rxRingVirtBase + RX_RING_SIZE; g_txRingVirtBase = g_rxDmaVirtBase + RX_DMA_SIZE; g_txDmaVirtBase = g_txRingVirtBase + TX_RING_SIZE; @@ -209,8 +216,9 @@ void mac_addr_print(struct mac_dev *macdev) { // 尝试打印网卡的MAC地址 unsigned char *pmac_addr = (unsigned char*)(macdev->mac_base + 0x5400); - printk(KERN_INFO "i210: MAC address = 0x%llx (%02x:%02x:%02x:%02x:%02x:%02x)", - pmac_addr, pmac_addr[0], pmac_addr[1], pmac_addr[2], pmac_addr[3], pmac_addr[4], pmac_addr[5]); + printk(KERN_INFO "i210: MAC address = %02x:%02x:%02x:%02x:%02x:%02x", + pmac_addr[0], pmac_addr[1], pmac_addr[2], pmac_addr[3], + pmac_addr[4], pmac_addr[5]); } int net_dma_init(struct mac_dev *dev) @@ -262,9 +270,10 @@ int mac_disable_pcie_master(struct mac_dev *dev) { int ret; mac_set(dev, INTEL_E1000_CTRL, INTEL_E1000_CTRL_GIO_MASTER_DISABLE); - ret = mac_wait(dev, INTEL_E1000_STATUS, INTEL_E1000_STATUS_GIO_MASTER_ENABLE, 0, MASTER_DISABLE_TIMEOUT); - if (ret) { - printk(KERN_INFO "PCI-E Master disable polling has failed. \n"); /* 仅记录即可 */ + ret = mac_wait(dev, INTEL_E1000_STATUS, + INTEL_E1000_STATUS_GIO_MASTER_ENABLE, 0, MASTER_DISABLE_TIMEOUT); + if (ret) { /* 仅记录即可 */ + printk(KERN_INFO "PCI-E Master disable polling has failed. \n"); } return 0; @@ -278,9 +287,11 @@ inline void mac_flush(struct mac_dev *dev) int mac_wait_cfg_done(struct mac_dev *dev) { - unsigned int mask = INTEL_E1000_STATUS_LAN_INIT_DONE | INTEL_E1000_STATUS_PHYRA; + unsigned int mask = + INTEL_E1000_STATUS_LAN_INIT_DONE | INTEL_E1000_STATUS_PHYRA; - CALLFUNC(mac_wait(dev, INTEL_E1000_STATUS, mask, mask, INTEL_E1000_ICH8_LAN_INIT_TIMEOUT)); + CALLFUNC(mac_wait(dev, INTEL_E1000_STATUS, mask, mask, + INTEL_E1000_ICH8_LAN_INIT_TIMEOUT)); mac_clear(dev, INTEL_E1000_STATUS, mask); return 0; @@ -296,7 +307,8 @@ int mac_reset(struct mac_dev *dev) mac_flush(dev); mdelay(20); - mac_set(dev, INTEL_E1000_CTRL, INTEL_E1000_CTRL_RST | INTEL_E1000_CTRL_PHY_RST); + mac_set(dev, INTEL_E1000_CTRL, + INTEL_E1000_CTRL_RST | INTEL_E1000_CTRL_PHY_RST); mdelay(20); CALLFUNC(mac_wait_cfg_done(dev)); @@ -367,8 +379,10 @@ int txqueue_i210_init(struct mac_dev *dev) mac_read(dev, E1000_I210_TXDCTL(0), ®); printk(KERN_INFO "E1000_TXDCTL after 0x%x\n", reg); - mac_write(dev, E1000_I210_TDBAL(0), (unsigned int)(q->tx_ring_dma & 0xffffffff)); - mac_write(dev, E1000_I210_TDBAH(0), (unsigned int)((q->tx_ring_dma >> 32) & 0xffffffff)); + mac_write(dev, E1000_I210_TDBAL(0), + (unsigned int)(q->tx_ring_dma & 0xffffffff)); + mac_write(dev, E1000_I210_TDBAH(0), + (unsigned int)((q->tx_ring_dma >> 32) & 0xffffffff)); mac_write(dev, E1000_I210_TDLEN(0), q->tx_size); mac_read(dev, E1000_I210_TXDCTL(0), ®); @@ -440,7 +454,8 @@ int get_hw_semaphore(struct mac_dev *dev) } if (i == timeout) { - printk(KERN_INFO "get_hw_semaphore Driver can't access device - SMBI bit is set.\n"); + printk(KERN_INFO "get_hw_semaphore Driver can't access device" + " - SMBI bit is set.\n"); return -1; } } @@ -525,7 +540,8 @@ int mac_dev_info_init(void) /* 4. 将pci设备的物理地址传递给mcs_km.ko, 配置rtos.bin运行页表时使用 */ set_bar_addr((unsigned long)mac_dev_info->io_phy); - macdev->mac_base = clientos_map_info[BAR_TABLE].va; /* rtos侧的访问pci设备使用的虚拟地址 */ + /* rtos侧的访问pci设备使用的虚拟地址 */ + macdev->mac_base = clientos_map_info[BAR_TABLE].va; /* 5. dump mac_dev, 用于比较rtos侧是否正确获取信息 */ mac_dev_dump(macdev); @@ -555,7 +571,8 @@ int mac_write(struct mac_dev *dev, int offset, u32 val) return 0; } -int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, unsigned int expect, int timeout) +int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, + unsigned int expect, int timeout) { unsigned int val; while (timeout--) { @@ -564,11 +581,13 @@ int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, unsigned int if ((val & bitmask) == expect) return 0; } - printk(KERN_INFO "offset=%x bitmask=%x expect=%x timeout=%d val=%x\n", offset, bitmask, expect, timeout, val); + printk(KERN_INFO "offset=%x bitmask=%x expect=%x timeout=%d val=%x\n", + offset, bitmask, expect, timeout, val); return -1; } -int mac_op(struct mac_dev *dev, int offset, unsigned int clear, unsigned int set) +int mac_op(struct mac_dev *dev, int offset, unsigned int clear, + unsigned int set) { unsigned int val; CALLFUNC(mac_read(dev, offset, &val)); @@ -594,9 +613,15 @@ void mac_dev_dump(struct mac_dev *macdev) if (macdev == NULL) return; - printk(KERN_INFO "macdev: queue{%llx %llx %llx %x %llx %x,\n 0x%llx, %x %x %x,\n 0x%llx, %x %x %x}\n 0x%llx 0x%llx %x %x %x", - macdev->queue.virt_addr_offset, macdev->queue.bus_addr_offset, macdev->queue.rx_ring_dma, macdev->queue.rx_size, macdev->queue.tx_ring_dma, macdev->queue.tx_size, - (long long unsigned int)macdev->queue.rx_desc, macdev->queue.rx_desc_nr, macdev->queue.rx_head, macdev->queue.rx_tail, - (long long unsigned int)macdev->queue.tx_desc, macdev->queue.tx_desc_nr, macdev->queue.tx_head, macdev->queue.tx_tail, - macdev->mac_base, macdev->pci_cfg_base, macdev->pm_cap, macdev->msi_cap, macdev->locked); + printk(KERN_INFO "macdev: queue{%llx %llx %llx %x %llx %x,\n" + " 0x%llx, %x %x %x,\n 0x%llx, %x %x %x}\n 0x%llx 0x%llx %x %x %x", + macdev->queue.virt_addr_offset, macdev->queue.bus_addr_offset, + macdev->queue.rx_ring_dma, macdev->queue.rx_size, + macdev->queue.tx_ring_dma, macdev->queue.tx_size, + (long long unsigned int)macdev->queue.rx_desc, + macdev->queue.rx_desc_nr, macdev->queue.rx_head, macdev->queue.rx_tail, + (long long unsigned int)macdev->queue.tx_desc, + macdev->queue.tx_desc_nr, macdev->queue.tx_head, macdev->queue.tx_tail, + macdev->mac_base, macdev->pci_cfg_base, macdev->pm_cap, macdev->msi_cap, + macdev->locked); } \ No newline at end of file diff --git a/drivers/i210/i210_eth.h b/drivers/i210/i210_eth.h index 54d60e43..921b7956 100644 --- a/drivers/i210/i210_eth.h +++ b/drivers/i210/i210_eth.h @@ -76,7 +76,7 @@ void mac_dev_func_hook(u32 dev_id, pfn_free_dma_map_t fn_free_dma_map); /* Transmit Descriptor */ struct mac_tx_desc { - unsigned long long buffer_addr; /* Address of the descriptor's data buffer */ + unsigned long long buffer_addr; /* Address of the descriptor's data buf */ union { unsigned int data; struct { @@ -158,8 +158,10 @@ typedef struct mac_dev { #ifdef MACDEV_OPERATE int mac_read(struct mac_dev *dev, int offset, u32 *val); int mac_write(struct mac_dev *dev, int offset, u32 val); -int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, unsigned int expect, int timeout); -int mac_op(struct mac_dev *dev, int offset, unsigned int clear, unsigned int set); +int mac_wait(struct mac_dev *dev, int offset, unsigned int bitmask, + unsigned int expect, int timeout); +int mac_op(struct mac_dev *dev, int offset, unsigned int clear, + unsigned int set); int mac_set(struct mac_dev *dev, int offset, unsigned int bits); int mac_clear(struct mac_dev *dev, int offset, unsigned int bits); #endif diff --git a/drivers/i210/i210_intel.h b/drivers/i210/i210_intel.h index 9d1657a1..fc1e877a 100644 --- a/drivers/i210/i210_intel.h +++ b/drivers/i210/i210_intel.h @@ -1,161 +1,161 @@ #ifndef _I210_INTEL_H_ #define _I210_INTEL_H_ -#define INTEL_E1000_CTRL 0x00000 /* Device Control - RW */ +#define INTEL_E1000_CTRL 0x00000 /* Device Control - RW */ /* Device Control */ -#define INTEL_E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ +#define INTEL_E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ #define INTEL_E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ -#define INTEL_E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ -#define INTEL_E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ -#define INTEL_E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ -#define INTEL_E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ -#define INTEL_E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ -#define INTEL_E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ -#define INTEL_E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ -#define INTEL_E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ -#define INTEL_E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ -#define INTEL_E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ +#define INTEL_E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ +#define INTEL_E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ +#define INTEL_E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ +#define INTEL_E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ +#define INTEL_E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ +#define INTEL_E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ +#define INTEL_E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ +#define INTEL_E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ +#define INTEL_E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ +#define INTEL_E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ #define INTEL_E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANDPHYPC */ #define INTEL_E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANDPHYPC */ #define INTEL_E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ -#define INTEL_E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ -#define INTEL_E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ -#define INTEL_E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ +#define INTEL_E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ +#define INTEL_E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ +#define INTEL_E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ #define INTEL_E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ -#define INTEL_E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ -#define INTEL_E1000_CTRL_RST 0x04000000 /* Global reset */ -#define INTEL_E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ -#define INTEL_E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ -#define INTEL_E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ -#define INTEL_E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ - -#define INTEL_E1000_STATUS 0x00008 /* Device Status - RO */ +#define INTEL_E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ +#define INTEL_E1000_CTRL_RST 0x04000000 /* Global reset */ +#define INTEL_E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ +#define INTEL_E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ +#define INTEL_E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ +#define INTEL_E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ + +#define INTEL_E1000_STATUS 0x00008 /* Device Status - RO */ /* Device Status */ -#define INTEL_E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ -#define INTEL_E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ -#define INTEL_E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ +#define INTEL_E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ +#define INTEL_E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ +#define INTEL_E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ #define INTEL_E1000_STATUS_FUNC_SHIFT 2 -#define INTEL_E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ -#define INTEL_E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ -#define INTEL_E1000_STATUS_SPEED_MASK 0x000000C0 -#define INTEL_E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ -#define INTEL_E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ -#define INTEL_E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ -#define INTEL_E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ -#define INTEL_E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ +#define INTEL_E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ +#define INTEL_E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ +#define INTEL_E1000_STATUS_SPEED_MASK 0x000000C0 +#define INTEL_E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ +#define INTEL_E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ +#define INTEL_E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ +#define INTEL_E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Compltn by NVM */ +#define INTEL_E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ #define INTEL_E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master request status */ -#define INTEL_E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ -#define INTEL_E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ -#define INTEL_E1000_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ +#define INTEL_E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ +#define INTEL_E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ +#define INTEL_E1000_STATUS_PCIM_STATE 0x40000000 /* PCIm function state */ #define INTEL_E1000_STRAP 0x0000C -#define INTEL_E1000_STRAP_SMBUS_ADDRESS_MASK 0x00fe0000 -#define INTEL_E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 -#define INTEL_E1000_STRAP_SMT_FREQ_MASK 0x00003000 -#define INTEL_E1000_STRAP_SMT_FREQ_SHIFT 12 - -#define INTEL_E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ -#define INTEL_E1000_EERD 0x00014 /* EEPROM Read - RW */ -#define INTEL_E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ -#define INTEL_E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ +#define INTEL_E1000_STRAP_SMBUS_ADDRESS_MASK 0x00fe0000 +#define INTEL_E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 +#define INTEL_E1000_STRAP_SMT_FREQ_MASK 0x00003000 +#define INTEL_E1000_STRAP_SMT_FREQ_SHIFT 12 + +#define INTEL_E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ +#define INTEL_E1000_EERD 0x00014 /* EEPROM Read - RW */ +#define INTEL_E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ +#define INTEL_E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ #define INTEL_E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ -#define INTEL_E1000_CTRL_EXT_FORCE_SMBUS 0x000800 /* Force SMBus mode */ -#define INTEL_E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ -#define INTEL_E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ -#define INTEL_E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ +#define INTEL_E1000_CTRL_EXT_FORCE_SMBUS 0x000800 /* Force SMBus mode */ +#define INTEL_E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ +#define INTEL_E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ +#define INTEL_E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ #define INTEL_E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */ -#define INTEL_E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 +#define INTEL_E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define INTEL_E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00c00000 -#define INTEL_E1000_CTRL_EXT_EIAME 0x01000000 -#define INTEL_E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ +#define INTEL_E1000_CTRL_EXT_EIAME 0x01000000 +#define INTEL_E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ #define INTEL_E1000_CTRL_EXT_IAME 0x08000000 /* Int Ack Auto-mask */ -#define INTEL_E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ -#define INTEL_E1000_CTRL_EXT_LSECCK 0x00001000 -#define INTEL_E1000_CTRL_EXT_PHYPDEN 0x00100000 - -#define INTEL_E1000_FLA 0x0001C /* Flash Access - RW */ -#define INTEL_E1000_MDIC 0x00020 /* MDI Control - RW */ -#define INTEL_E1000_SCTL 0x00024 /* SerDes Control - RW */ -#define INTEL_E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ -#define INTEL_E1000_FCAH 0x0002C /* Flow Control Address High -RW */ -#define INTEL_E1000_FEXT 0x0002C /* Future Externed - RW */ -#define INTEL_E1000_FEXTNVM 0x00028 /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM3 0x0003C /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM4 0x00024 /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM5 0x00014 /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM6 0x00010 /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM7 0x000E4 /* Future Externed NVM - RW */ - -#define INTEL_E1000_FEXTNVM8 0x05bb0 /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM9 0x05bb4 /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM11 0x05bbc /* Future Externed NVM - RW */ -#define INTEL_E1000_FEXTNVM12 0x05bc0 /* Future Externed NVM - RW */ -#define INTEL_E1000_PCIEANACFG 0x00F18 /* PCIE Analog config */ -#define INTEL_E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */ -#define INTEL_E1000_FCT 0x00030 /* Flow Control Type - RW */ -#define INTEL_E1000_VET 0x00038 /* VLAN Ether Type - RW */ -#define INTEL_E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ -#define INTEL_E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ -#define INTEL_E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ -#define INTEL_E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ -#define INTEL_E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ -#define INTEL_E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ -#define INTEL_E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ -#define INTEL_E1000_SVCR 0x000F0 -#define INTEL_E1000_SVT 0x000F4 -#define INTEL_E1000_LPIC 0x000FC /* Low Power IDLE control */ -#define INTEL_E1000_RCTL 0x00100 /* RX Control - RW */ -#define INTEL_E1000_RCTL_EN 0x00000002 /* enable */ -#define INTEL_E1000_RCTL_SBP 0x00000004 /* store bad packet */ -#define INTEL_E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ -#define INTEL_E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ -#define INTEL_E1000_RCTL_LPE 0x00000020 /* long packet enable */ -#define INTEL_E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ -#define INTEL_E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ -#define INTEL_E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ -#define INTEL_E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ -#define INTEL_E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ -#define INTEL_E1000_RCTL_RDMTS_HEX 0x00010000 -#define INTEL_E1000_RCTL_RDMTS1_HEX INTEL_E1000_RCTL_RDMTS_HEX -#define INTEL_E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ -#define INTEL_E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ -#define INTEL_E1000_RCTL_BAM 0x00008000 /* broadcast enable */ +#define INTEL_E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ +#define INTEL_E1000_CTRL_EXT_LSECCK 0x00001000 +#define INTEL_E1000_CTRL_EXT_PHYPDEN 0x00100000 + +#define INTEL_E1000_FLA 0x0001C /* Flash Access - RW */ +#define INTEL_E1000_MDIC 0x00020 /* MDI Control - RW */ +#define INTEL_E1000_SCTL 0x00024 /* SerDes Control - RW */ +#define INTEL_E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ +#define INTEL_E1000_FCAH 0x0002C /* Flow Control Address High -RW */ +#define INTEL_E1000_FEXT 0x0002C /* Future Externed - RW */ +#define INTEL_E1000_FEXTNVM 0x00028 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM3 0x0003C /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM4 0x00024 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM5 0x00014 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM6 0x00010 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM7 0x000E4 /* Future Externed NVM - RW */ + +#define INTEL_E1000_FEXTNVM8 0x05bb0 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM9 0x05bb4 /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM11 0x05bbc /* Future Externed NVM - RW */ +#define INTEL_E1000_FEXTNVM12 0x05bc0 /* Future Externed NVM - RW */ +#define INTEL_E1000_PCIEANACFG 0x00F18 /* PCIE Analog config */ +#define INTEL_E1000_DPGFR 0x00FAC /* Dynamic Power Gate Force Control Register */ +#define INTEL_E1000_FCT 0x00030 /* Flow Control Type - RW */ +#define INTEL_E1000_VET 0x00038 /* VLAN Ether Type - RW */ +#define INTEL_E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ +#define INTEL_E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ +#define INTEL_E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ +#define INTEL_E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ +#define INTEL_E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ +#define INTEL_E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ +#define INTEL_E1000_IVAR 0x000E4 /* Interrupt Vector Allocation Register - RW */ +#define INTEL_E1000_SVCR 0x000F0 +#define INTEL_E1000_SVT 0x000F4 +#define INTEL_E1000_LPIC 0x000FC /* Low Power IDLE control */ +#define INTEL_E1000_RCTL 0x00100 /* RX Control - RW */ +#define INTEL_E1000_RCTL_EN 0x00000002 /* enable */ +#define INTEL_E1000_RCTL_SBP 0x00000004 /* store bad packet */ +#define INTEL_E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ +#define INTEL_E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ +#define INTEL_E1000_RCTL_LPE 0x00000020 /* long packet enable */ +#define INTEL_E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ +#define INTEL_E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ +#define INTEL_E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ +#define INTEL_E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ +#define INTEL_E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ +#define INTEL_E1000_RCTL_RDMTS_HEX 0x00010000 +#define INTEL_E1000_RCTL_RDMTS1_HEX INTEL_E1000_RCTL_RDMTS_HEX +#define INTEL_E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ +#define INTEL_E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ +#define INTEL_E1000_RCTL_BAM 0x00008000 /* broadcast enable */ /* these buff sizes are valid if E1000_RCTL_BSEX is 0 */ -#define INTEL_E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ -#define INTEL_E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ -#define INTEL_E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ -#define INTEL_E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ +#define INTEL_E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ +#define INTEL_E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ +#define INTEL_E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ +#define INTEL_E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ /* these buff sizes are valid if E1000_RCTL_BSEX is 1 */ -#define INTEL_E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ -#define INTEL_E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ -#define INTEL_E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ -#define INTEL_E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ -#define INTEL_E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ -#define INTEL_E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ -#define INTEL_E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ -#define INTEL_E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ -#define INTEL_E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ -#define INTEL_E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ - -#define INTEL_E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ -#define INTEL_E1000_TXCW 0x00178 /* TX Configuration Word - RW */ -#define INTEL_E1000_RXCW 0x00180 /* RX Configuration Word - RW */ -#define INTEL_E1000_PBA_ECC 0x01100 /* PBA ECC register */ -#define INTEL_E1000_TCTL 0x00400 /* TX Control - RW */ +#define INTEL_E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ +#define INTEL_E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ +#define INTEL_E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ +#define INTEL_E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ +#define INTEL_E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ +#define INTEL_E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ +#define INTEL_E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ +#define INTEL_E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ +#define INTEL_E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ +#define INTEL_E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ + +#define INTEL_E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ +#define INTEL_E1000_TXCW 0x00178 /* TX Configuration Word - RW */ +#define INTEL_E1000_RXCW 0x00180 /* RX Configuration Word - RW */ +#define INTEL_E1000_PBA_ECC 0x01100 /* PBA ECC register */ +#define INTEL_E1000_TCTL 0x00400 /* TX Control - RW */ /* Transmit Control */ -#define INTEL_E1000_TCTL_EN 0x00000002 /* enable tx */ -#define INTEL_E1000_TCTL_PSP 0x00000008 /* pad short packets */ -#define INTEL_E1000_TCTL_CT 0x00000ff0 /* collision threshold */ -#define INTEL_E1000_TCTL_COLD 0x003ff000 /* collision distance */ -#define INTEL_E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ -#define INTEL_E1000_TCTL_MULR 0x10000000 /* Multiple request support */ - -#define INTEL_E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ -#define INTEL_E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ -#define INTEL_E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ -#define INTEL_E1000_LEDCTL 0x00E00 /* LED Control - RW */ -#define INTEL_E1000_LEDMUX 0x08130 /* LED MUX Control */ -#define INTEL_E1000_EXTCNF_CTRL 0x00f00 /* Extended Configuration Control */ +#define INTEL_E1000_TCTL_EN 0x00000002 /* enable tx */ +#define INTEL_E1000_TCTL_PSP 0x00000008 /* pad short packets */ +#define INTEL_E1000_TCTL_CT 0x00000ff0 /* collision threshold */ +#define INTEL_E1000_TCTL_COLD 0x003ff000 /* collision distance */ +#define INTEL_E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ +#define INTEL_E1000_TCTL_MULR 0x10000000 /* Multiple request support */ + +#define INTEL_E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ +#define INTEL_E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ +#define INTEL_E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ +#define INTEL_E1000_LEDCTL 0x00E00 /* LED Control - RW */ +#define INTEL_E1000_LEDMUX 0x08130 /* LED MUX Control */ +#define INTEL_E1000_EXTCNF_CTRL 0x00f00 /* Extended Configuration Control */ #define INTEL_E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x20 #define INTEL_E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x1 #define INTEL_E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x8 @@ -177,51 +177,51 @@ #define INTEL_E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x8 #define INTEL_E1000_PHY_CTRL_GBE_DISABLE 0x40 -#define INTEL_E1000_POEMB E1000_PHY_CTRL /* Packet Buffer Allocation - RW */ -#define INTEL_E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ -#define INTEL_E1000_PBS 0x01008 /* Packet Buffer Size */ -#define INTEL_E1000_PBECCSTS 0x0100C /* Packet Buffer ECC status - RW */ -#define INTEL_E1000_IOSFPC 0x0f28 /* tx corrupted data */ -#define INTEL_E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ -#define INTEL_E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ -#define INTEL_E1000_FLOP 0x0103C /* Flash Opcode Register - RW */ -#define INTEL_E1000_ERT 0x02008 /* */ -#define INTEL_E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ -#define INTEL_E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ -#define INTEL_E1000_PSRCTL 0x02170 /* */ -#define INTEL_E1000_RDFH 0x02410 /* */ -#define INTEL_E1000_RDFT 0x02418 /* */ -#define INTEL_E1000_RDFHS 0x02420 /* */ -#define INTEL_E1000_RDFTS 0x02428 /* */ -#define INTEL_E1000_RDFPC 0x02430 /* */ -/* */ -#define INTEL_E1000_RDTR 0x02820 /* */ -#define INTEL_E1000_RADV 0x0282C /* */ - -#define INTEL_E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ -#define INTEL_E1000_RFCTL 0x05008 /* Receive Filter Control*/ - -#define INTEL_E1000_KABGTXD 0x03004 /* */ -#define INTEL_E1000_KABGTXD_BGSQLBIAS 0x050000 /* */ - -#define INTEL_E1000_H2ME 0x05b50 /* */ -#define INTEL_E1000_H2ME_ULP 0x0800 /* */ -#define INTEL_E1000_H2ME_ENFORCE_SETTINGS 0x01000 /* */ - -#define INTEL_E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ -#define INTEL_E1000_SWSM 0x05B50 /* SW Semaphore */ -#define INTEL_E1000_FWSM 0x05B54 /* FW Semaphore */ -#define INTEL_E1000_FWSM_ULP_CFG_DONE 0x0400 /* FW Semaphore */ -#define INTEL_E1000_PCS_LCTL_FORCE_FCTRL 0x080 /* */ -#define INTEL_E1000_PCS_LSTS_AN_COMPLETE 0x010000 /* */ -#define INTEL_E1000_ICH8_LAN_INIT_TIMEOUT 1500 /* */ +#define INTEL_E1000_POEMB E1000_PHY_CTRL /* Packet Buffer Allocation - RW */ +#define INTEL_E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ +#define INTEL_E1000_PBS 0x01008 /* Packet Buffer Size */ +#define INTEL_E1000_PBECCSTS 0x0100C /* Packet Buffer ECC status - RW */ +#define INTEL_E1000_IOSFPC 0x0f28 /* tx corrupted data */ +#define INTEL_E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ +#define INTEL_E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ +#define INTEL_E1000_FLOP 0x0103C /* Flash Opcode Register - RW */ +#define INTEL_E1000_ERT 0x02008 +#define INTEL_E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ +#define INTEL_E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ +#define INTEL_E1000_PSRCTL 0x02170 +#define INTEL_E1000_RDFH 0x02410 +#define INTEL_E1000_RDFT 0x02418 +#define INTEL_E1000_RDFHS 0x02420 +#define INTEL_E1000_RDFTS 0x02428 +#define INTEL_E1000_RDFPC 0x02430 + +#define INTEL_E1000_RDTR 0x02820 +#define INTEL_E1000_RADV 0x0282C + +#define INTEL_E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ +#define INTEL_E1000_RFCTL 0x05008 /* Receive Filter Control*/ + +#define INTEL_E1000_KABGTXD 0x03004 +#define INTEL_E1000_KABGTXD_BGSQLBIAS 0x050000 + +#define INTEL_E1000_H2ME 0x05b50 +#define INTEL_E1000_H2ME_ULP 0x0800 +#define INTEL_E1000_H2ME_ENFORCE_SETTINGS 0x01000 + +#define INTEL_E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ +#define INTEL_E1000_SWSM 0x05B50 /* SW Semaphore */ +#define INTEL_E1000_FWSM 0x05B54 /* FW Semaphore */ +#define INTEL_E1000_FWSM_ULP_CFG_DONE 0x0400 /* FW Semaphore */ +#define INTEL_E1000_PCS_LCTL_FORCE_FCTRL 0x080 +#define INTEL_E1000_PCS_LSTS_AN_COMPLETE 0x010000 +#define INTEL_E1000_ICH8_LAN_INIT_TIMEOUT 1500 /* SW Semaphore Register */ -#define INTEL_E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ -#define INTEL_E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ +#define INTEL_E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ +#define INTEL_E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ -#define INTEL_E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ -#define INTEL_E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ -#define INTEL_E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ +#define INTEL_E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ +#define INTEL_E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ +#define INTEL_E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ #endif diff --git a/drivers/i210/i210_main.c b/drivers/i210/i210_main.c index 505f2738..4af5a995 100644 --- a/drivers/i210/i210_main.c +++ b/drivers/i210/i210_main.c @@ -23,23 +23,23 @@ static struct pci_device_id i210_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, i210_pci_tbl); -u32 global_dev_num_i210 = 0; -PCI_DEV_INFO_S global_mac_dev_info[I210_DEV_MAX_NUM] = { {0} }; +u32 g_dev_num_i210 = 0; +PCI_DEV_INFO_S g_mac_dev_info[I210_DEV_MAX_NUM] = { {0} }; const PCI_DEV_INFO_S* get_mac_dev_info(u32 dev_id) { - if ((dev_id >= global_dev_num_i210) || (dev_id >= I210_DEV_MAX_NUM)) { + if ((dev_id >= g_dev_num_i210) || (dev_id >= I210_DEV_MAX_NUM)) { return NULL; } - return &(global_mac_dev_info[dev_id]); + return &(g_mac_dev_info[dev_id]); } void mac_dev_func_hook(u32 dev_id, pfn_free_dma_map_t fn_free_dma_map) { - if ((dev_id >= global_dev_num_i210) || (dev_id >= I210_DEV_MAX_NUM)) { + if ((dev_id >= g_dev_num_i210) || (dev_id >= I210_DEV_MAX_NUM)) { return; } - global_mac_dev_info[dev_id].pfn_free_dma_map = fn_free_dma_map; + g_mac_dev_info[dev_id].pfn_free_dma_map = fn_free_dma_map; } static int i210_probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -50,11 +50,12 @@ static int i210_probe(struct pci_dev *pdev, const struct pci_device_id *ent) void __iomem *bar; unsigned char *pmac_addr; const char *eth_dev_name = pci_name(to_pci_dev(&pdev->dev)); - printk(KERN_INFO "%s probe func: eth_dev_name:%s\n", g_i210_driver_name, eth_dev_name); - if (global_dev_num_i210 >= I210_DEV_MAX_NUM) { + printk(KERN_INFO "%s probe func: eth_dev_name:%s\n", g_i210_driver_name, + eth_dev_name); + if (g_dev_num_i210 >= I210_DEV_MAX_NUM) { return -E2BIG; } - global_dev_num_i210++; + g_dev_num_i210++; err = pci_enable_device(pdev); if (err != 0) { @@ -81,7 +82,8 @@ static int i210_probe(struct pci_dev *pdev, const struct pci_device_id *ent) /* 打印设备的BAR地址和大小 */ bar_addr = (u8 __iomem *)pci_resource_start(pdev, 0); bar_size = pci_resource_len(pdev, 0); - printk(KERN_INFO "i210: BAR0 address = 0x%llx, size = %u", (u64)bar_addr, bar_size); + printk(KERN_INFO "i210: BAR0 address = 0x%llx, size = %u", (u64)bar_addr, + bar_size); /* 映射BAR空间 */ bar = pci_iomap(pdev, 0, bar_size); @@ -91,19 +93,21 @@ static int i210_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto err_pci_reg; } - global_mac_dev_info[global_dev_num_i210 - 1].dev_id = global_dev_num_i210 - 1; - global_mac_dev_info[global_dev_num_i210 - 1].pdev = (struct pci_dev *)pdev; - global_mac_dev_info[global_dev_num_i210 - 1].io_phy = bar_addr; - global_mac_dev_info[global_dev_num_i210 - 1].io_virt = bar; - pci_set_drvdata(pdev, &(global_mac_dev_info[global_dev_num_i210 - 1])); - printk(KERN_INFO "eth_i210[%u]: io_addr:pa=0x%llx va=0x%llx\n", (global_dev_num_i210 - 1), - (u64)global_mac_dev_info[global_dev_num_i210 - 1].io_phy, - (u64)global_mac_dev_info[global_dev_num_i210 - 1].io_virt); + g_mac_dev_info[g_dev_num_i210 - 1].dev_id = g_dev_num_i210 - 1; + g_mac_dev_info[g_dev_num_i210 - 1].pdev = (struct pci_dev *)pdev; + g_mac_dev_info[g_dev_num_i210 - 1].io_phy = bar_addr; + g_mac_dev_info[g_dev_num_i210 - 1].io_virt = bar; + pci_set_drvdata(pdev, &(g_mac_dev_info[g_dev_num_i210 - 1])); + printk(KERN_INFO "eth_i210[%u]: io_addr:pa=0x%llx va=0x%llx\n", + (g_dev_num_i210 - 1), + (u64)g_mac_dev_info[g_dev_num_i210 - 1].io_phy, + (u64)g_mac_dev_info[g_dev_num_i210 - 1].io_virt); /* 尝试打印网卡的MAC地址 */ pmac_addr = (unsigned char*)(bar + 0x5400); printk(KERN_INFO "i210: MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", - pmac_addr[0], pmac_addr[1], pmac_addr[2], pmac_addr[3], pmac_addr[4], pmac_addr[5]); + pmac_addr[0], pmac_addr[1], pmac_addr[2], pmac_addr[3], pmac_addr[4], + pmac_addr[5]); /* 初始化mac_dev_info */ err = mac_dev_info_init(); -- Gitee