diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..f6c26977bbb993b180afd759658dcf5ea6619cd0 --- /dev/null +++ b/LICENSE @@ -0,0 +1,194 @@ +木兰宽松许可证，第2版 + +木兰宽松许可证，第2版 + +2020年1月 http://license.coscl.org.cn/MulanPSL2 + +您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束： + +0. 定义 + +“软件” 是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。 + +“贡献” 是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。 + +“贡献者” 是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。 + +“法人实体” 是指提交贡献的机构及其“关联实体”。 + +“关联实体” 是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是 +指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。 + +1. 授予版权许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可 +以复制、使用、修改、分发其“贡献”，不论修改与否。 + +2. 授予专利许可 + +每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定 +撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡 +献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软 +件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“ +关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或 +其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权 +行动之日终止。 + +3. 无商标许可 + +“本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定 +的声明义务而必须使用除外。 + +4. 分发限制 + +您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“ +本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。 + +5. 免责声明与责任限制 + +“软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对 +任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于 +何种法律理论，即使其曾被建议有此种损失的可能性。 + +6. 语言 + +“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文 +版为准。 + +条款结束 + +如何将木兰宽松许可证，第2版，应用到您的软件 + +如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步： + +1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字； + +2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中； + +3， 请将如下声明文本放入每个源文件的头部注释中。 + +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan +PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY +KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO +NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. + +Mulan Permissive Software License，Version 2 + +Mulan Permissive Software License，Version 2 (Mulan PSL v2) + +January 2020 http://license.coscl.org.cn/MulanPSL2 + +Your reproduction, use, modification and distribution of the Software shall +be subject to Mulan PSL v2 (this License) with the following terms and +conditions: + +0. Definition + +Software means the program and related documents which are licensed under +this License and comprise all Contribution(s). + +Contribution means the copyrightable work licensed by a particular +Contributor under this License. + +Contributor means the Individual or Legal Entity who licenses its +copyrightable work under this License. + +Legal Entity means the entity making a Contribution and all its +Affiliates. + +Affiliates means entities that control, are controlled by, or are under +common control with the acting entity under this License, ‘control’ means +direct or indirect ownership of at least fifty percent (50%) of the voting +power, capital or other securities of controlled or commonly controlled +entity. + +1. Grant of Copyright License + +Subject to the terms and conditions of this License, each Contributor hereby +grants to you a perpetual, worldwide, royalty-free, non-exclusive, +irrevocable copyright license to reproduce, use, modify, or distribute its +Contribution, with modification or not. + +2. Grant of Patent License + +Subject to the terms and conditions of this License, each Contributor hereby +grants to you a perpetual, worldwide, royalty-free, non-exclusive, +irrevocable (except for revocation under this Section) patent license to +make, have made, use, offer for sale, sell, import or otherwise transfer its +Contribution, where such patent license is only limited to the patent claims +owned or controlled by such Contributor now or in future which will be +necessarily infringed by its Contribution alone, or by combination of the +Contribution with the Software to which the Contribution was contributed. +The patent license shall not apply to any modification of the Contribution, +and any other combination which includes the Contribution. If you or your +Affiliates directly or indirectly institute patent litigation (including a +cross claim or counterclaim in a litigation) or other patent enforcement +activities against any individual or entity by alleging that the Software or +any Contribution in it infringes patents, then any patent license granted to +you under this License for the Software shall terminate as of the date such +litigation or activity is filed or taken. + +3. No Trademark License + +No trademark license is granted to use the trade names, trademarks, service +marks, or product names of Contributor, except as required to fulfill notice +requirements in section 4. + +4. Distribution Restriction + +You may distribute the Software in any medium with or without modification, +whether in source or executable forms, provided that you provide recipients +with a copy of this License and retain copyright, patent, trademark and +disclaimer statements in the Software. + +5. Disclaimer of Warranty and Limitation of Liability + +THE SOFTWARE AND CONTRIBUTION IN IT ARE PROVIDED WITHOUT WARRANTIES OF ANY +KIND, EITHER EXPRESS OR IMPLIED. IN NO EVENT SHALL ANY CONTRIBUTOR OR +COPYRIGHT HOLDER BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING, BUT NOT +LIMITED TO ANY DIRECT, OR INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING +FROM YOUR USE OR INABILITY TO USE THE SOFTWARE OR THE CONTRIBUTION IN IT, NO +MATTER HOW IT’S CAUSED OR BASED ON WHICH LEGAL THEORY, EVEN IF ADVISED OF +THE POSSIBILITY OF SUCH DAMAGES. + +6. Language + +THIS LICENSE IS WRITTEN IN BOTH CHINESE AND ENGLISH, AND THE CHINESE VERSION +AND ENGLISH VERSION SHALL HAVE THE SAME LEGAL EFFECT. IN THE CASE OF +DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION +SHALL PREVAIL. + +END OF THE TERMS AND CONDITIONS + +How to Apply the Mulan Permissive Software License，Version 2 +(Mulan PSL v2) to Your Software + +To apply the Mulan PSL v2 to your work, for easy identification by +recipients, you are suggested to complete following three steps: + +i. Fill in the blanks in following statement, including insert your software +name, the year of the first publication of your software, and your name +identified as the copyright owner; + +ii. Create a file named "LICENSE" which contains the whole context of this +License in the first directory of your software package; + +iii. Attach the statement to the appropriate annotated syntax at the +beginning of each source file. + +Copyright (c) [Year] [name of copyright holder] +[Software Name] is licensed under Mulan PSL v2. +You can use this software according to the terms and conditions of the Mulan +PSL v2. +You may obtain a copy of Mulan PSL v2 at: + http://license.coscl.org.cn/MulanPSL2 +THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY +KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO +NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. +See the Mulan PSL v2 for more details. diff --git a/hi-vision/Demo/create_live_channel.py b/hi-vision/Demo/create_live_channel.py new file mode 100644 index 0000000000000000000000000000000000000000..a1a849d3571dfb9ddbdc07135c031d362aaa0c8f --- /dev/null +++ b/hi-vision/Demo/create_live_channel.py @@ -0,0 +1,25 @@ +import os +import oss2 + +# access_key_id = os.getenv('OSS_TEST_ACCESS_KEY_ID', '**') +# access_key_secret = os.getenv('OSS_TEST_ACCESS_KEY_SECRET', '***') +# bucket_name = os.getenv('OSS_TEST_BUCKET', '********') +# endpoint = os.getenv('OSS_TEST_ENDPOINT', '***') + +# 创建Bucket实例。 +bucket = oss2.Bucket(oss2.Auth(access_key_id, access_key_secret), endpoint, bucket_name) + +# 创建并配置流频道。 +# 频道的名称是test_rtmp_live。直播生成的m3u8文件叫做test.m3u8，该索引文件包含3片ts文件，每片ts文件的时长为5秒（这只是一个建议值，具体的时长取决于关键帧）。 +channel_name = "test_rtmp_live" +playlist_name = "test.m3u8" + +create_result = bucket.create_live_channel( + channel_name, + oss2.models.LiveChannelInfo( + status = 'enabled', + description = '测试使用的直播频道', + target = oss2.models.LiveChannelInfoTarget( + playlist_name = playlist_name, + frag_count = 3, + frag_duration = 5))) diff --git a/hi-vision/Demo/get_push_url.py b/hi-vision/Demo/get_push_url.py new file mode 100644 index 0000000000000000000000000000000000000000..56244836769f50fd62aea95aa109afbdb4e65ee9 --- /dev/null +++ b/hi-vision/Demo/get_push_url.py @@ -0,0 +1,31 @@ +# -*- coding: utf-8 -*- +import oss2 +from oss2.credentials import EnvironmentVariableCredentialsProvider + +# 从环境变量中获取访问凭证。运行本代码示例之前，请确保已设置环境变量OSS_ACCESS_KEY_ID和OSS_ACCESS_KEY_SECRET。 +auth = oss2.ProviderAuth(EnvironmentVariableCredentialsProvider()) +# 填写Bucket所在地域对应的Endpoint。 +# 填写存储空间名称。 +bucket = oss2.Bucket(auth, 'https://oss-cn-nanjing.aliyuncs.com', 'redcap2') + +# 填写LiveChannel名称，例如test-channel。 +channel_name = "redcap_camera" +playlist_name = "playlist.m3u8" + +channel = bucket.create_live_channel( + channel_name, + oss2.models.LiveChannelInfo( + status = 'enabled', + description = '测试使用的直播频道', + target = oss2.models.LiveChannelInfoTarget( + playlist_name = playlist_name, + frag_count = 3, + frag_duration = 4))) + +publish_url = channel.publish_url +# 生成RTMP推流的签名URL，并设置过期时间为3600秒。 +signed_publish_url = bucket.sign_rtmp_url(channel_name, "playlist.m3u8", 3600) +# 打印未签名推流地址。 +print('publish_url='+publish_url) +# 打印签名推流地址。 +# print('signed_publish_url='+signed_publish_url) diff --git a/hi-vision/Demo/redcap2.py b/hi-vision/Demo/redcap2.py new file mode 100644 index 0000000000000000000000000000000000000000..8ec7cb5a44602c3818d3da95bfa6dfe04e1f8cdf --- /dev/null +++ b/hi-vision/Demo/redcap2.py @@ -0,0 +1,50 @@ +import cv2 +import subprocess + +# HLS推流地址，这需要一个服务器或者本地文件系统的路径 +hls_out_path = 'rtmp://redcap2.oss-cn-nanjing.aliyuncs.com/live/redcap_camera' + +# 使用OpenCV捕获摄像头视频 +cap = cv2.VideoCapture(0) # 0表示默认摄像头 + +# 定义FFmpeg命令，将视频转换为HLS格式 +ffmpeg_command = [ + 'ffmpeg', + '-y', # 覆盖已有文件 + '-f', 'rawvideo', # 输入格式为原始视频 + '-pixel_format', 'bgr24', # 像素格式 + '-video_size', '640x480', # 视频大小 + '-i', '-', # 从标准输入读取 + '-c:v', 'libx264', # 使用H.264编码 + '-preset', 'veryfast', # 编码速度 + '-hls_time', '2', # 每个片段的长度（秒） + '-hls_list_size', '3', # 播放列表中的最大片段数量 + '-hls_flags', 'delete_segments+append_list', # 删除旧片段并持续更新播放列表 + '-start_number', '1', # 起始片段序号 + hls_out_path # HLS输出路径 +] + +# 启动FFmpeg进程 +process = subprocess.Popen(ffmpeg_command, stdin=subprocess.PIPE) + +while True: + # 从摄像头读取帧 + ret, frame = cap.read() + if not ret: + break + + # 将帧写入FFmpeg的标准输入 + process.stdin.write(frame.tobytes()) + + # 显示捕获的视频（可选） + cv2.imshow("Camera Feed", frame) + + # 按下'q'键退出 + if cv2.waitKey(1) & 0xFF == ord('q'): + break + +# 释放资源 +cap.release() +process.stdin.close() +process.wait() +cv2.destroyAllWindows() diff --git a/hi-vision/Demo/redcap_rtmp.py b/hi-vision/Demo/redcap_rtmp.py new file mode 100644 index 0000000000000000000000000000000000000000..9da371137240f3b91a3fcba7a45aaddaf1651e97 --- /dev/null +++ b/hi-vision/Demo/redcap_rtmp.py @@ -0,0 +1,90 @@ +import subprocess +import os +import psutil +import time +import cv2 + +def get_system_params(): + """获取CPU和内存使用情况""" + cpu_usage = psutil.cpu_percent(interval=1) + memory_info = psutil.virtual_memory() + memory_usage = memory_info.percent + return cpu_usage, memory_usage + +def optimize_ffmpeg_command(cpu_usage, memory_usage): + """根据系统参数优化FFmpeg命令""" + if cpu_usage > 80: + # 如果CPU使用率高，降低帧率 + frame_rate = 15 + scale = '640:480' + elif memory_usage > 80: + # 如果内存使用率高，减少视频分辨率 + frame_rate = 20 + scale = '320:240' + else: + frame_rate = 20 + scale = '640:480' + + command = [ + 'ffmpeg', + '-f', 'rawvideo', + '-pixel_format', 'bgr24', + '-video_size', scale, + '-framerate', str(frame_rate), + '-i', '-', # 从标准输入读取 + '-c:v', 'libx264', + '-preset', 'ultrafast', + '-tune', 'zerolatency', + '-f', 'flv', + 'rtmp://rtmp.dd33.net/live/9fb3c888b037?91F116049D064C38' + ] + + return command + +def main(): + cap = cv2.VideoCapture(0) # 打开默认摄像头 + if not cap.isOpened(): + print("无法打开摄像头") + return + + while True: + cpu_usage, memory_usage = get_system_params() + print(f"CPU Usage: {cpu_usage}%, Memory Usage: {memory_usage}%") + + command = optimize_ffmpeg_command(cpu_usage, memory_usage) + + try: + # 启动FFmpeg进程 + process = subprocess.Popen(command, stdin=subprocess.PIPE, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + while True: + ret, frame = cap.read() + if not ret: + print("无法读取摄像头帧") + break + + # 将帧写入FFmpeg的标准输入 + process.stdin.write(frame.tobytes()) + + # 显示捕获的视频（可选） + cv2.imshow("Camera Feed", frame) + + # 检查退出条件 + if cv2.waitKey(1) & 0xFF == ord('q'): + break + + except Exception as e: + print(f"Error occurred: {e}") + finally: + # 释放资源 + cap.release() + process.stdin.close() + process.wait() + cv2.destroyAllWindows() + print("释放资源并退出.") + + # 每隔5秒检查一次系统参数 + time.sleep(5) + +if __name__ == "__main__": + main() diff --git a/hi-vision/Picture/1.png b/hi-vision/Picture/1.png new file mode 100644 index 0000000000000000000000000000000000000000..58f0a43f2456b465ec23c3936e3b8c0bb3f768b3 Binary files /dev/null and b/hi-vision/Picture/1.png differ diff --git a/hi-vision/Picture/10.png b/hi-vision/Picture/10.png new file mode 100644 index 0000000000000000000000000000000000000000..891c9638ad91bc62d323707645f22c47ee01c375 Binary files /dev/null and b/hi-vision/Picture/10.png differ diff --git a/hi-vision/Picture/11.png b/hi-vision/Picture/11.png new file mode 100644 index 0000000000000000000000000000000000000000..f1fe3ed3b545f7c574d36b2b9faff3806982c63a Binary files /dev/null and b/hi-vision/Picture/11.png differ diff --git a/hi-vision/Picture/12.png b/hi-vision/Picture/12.png new file mode 100644 index 0000000000000000000000000000000000000000..71a7112c92a7ace6da1a1fd4e969ec760c707d05 Binary files /dev/null and b/hi-vision/Picture/12.png differ diff --git a/hi-vision/Picture/13.png b/hi-vision/Picture/13.png new file mode 100644 index 0000000000000000000000000000000000000000..5066046fe3a55b9d8d3c2dd6b0d719e8c7bd0c00 Binary files /dev/null and b/hi-vision/Picture/13.png differ diff --git a/hi-vision/Picture/14.png b/hi-vision/Picture/14.png new file mode 100644 index 0000000000000000000000000000000000000000..a87d8767c0624945ed555a609b6ace8a00611d23 Binary files /dev/null and b/hi-vision/Picture/14.png differ diff --git a/hi-vision/Picture/2.1.png b/hi-vision/Picture/2.1.png new file mode 100644 index 0000000000000000000000000000000000000000..27541cbb4d9dba3619acf75c2b055a6f66b2fbbb Binary files /dev/null and b/hi-vision/Picture/2.1.png differ diff --git a/hi-vision/Picture/2.2.png b/hi-vision/Picture/2.2.png new file mode 100644 index 0000000000000000000000000000000000000000..e1f263c717fe50873a27c33f762e3bddb5ba2b3a Binary files /dev/null and b/hi-vision/Picture/2.2.png differ diff --git a/hi-vision/Picture/2.png b/hi-vision/Picture/2.png new file mode 100644 index 0000000000000000000000000000000000000000..5a19b64d57c0fa032843a13cc4e5e176adb3efe4 Binary files /dev/null and b/hi-vision/Picture/2.png differ diff --git a/hi-vision/Picture/3.png b/hi-vision/Picture/3.png new file mode 100644 index 0000000000000000000000000000000000000000..69dbe2d5d8768b10898ae8d59f213b682e1f4294 Binary files /dev/null and b/hi-vision/Picture/3.png differ diff --git a/hi-vision/Picture/4.png b/hi-vision/Picture/4.png new file mode 100644 index 0000000000000000000000000000000000000000..5027f9d443212fce56b0c3a26a4bb0eab9a8cded Binary files /dev/null and b/hi-vision/Picture/4.png differ diff --git a/hi-vision/Picture/5.png b/hi-vision/Picture/5.png new file mode 100644 index 0000000000000000000000000000000000000000..189f34e715e1e61e3fc442281ec2aa17577a8e5f Binary files /dev/null and b/hi-vision/Picture/5.png differ diff --git a/hi-vision/Picture/6.png b/hi-vision/Picture/6.png new file mode 100644 index 0000000000000000000000000000000000000000..249f889efbadb2b50ca1858d6578f94cb28e2d0d Binary files /dev/null and b/hi-vision/Picture/6.png differ diff --git a/hi-vision/Picture/7.png b/hi-vision/Picture/7.png new file mode 100644 index 0000000000000000000000000000000000000000..50c00b9fbd8ca4ba694f564b597bc70ae9ee4b8f Binary files /dev/null and b/hi-vision/Picture/7.png differ diff --git a/hi-vision/Picture/8.png b/hi-vision/Picture/8.png new file mode 100644 index 0000000000000000000000000000000000000000..c3cc0f7b62588a82539241b9ddaf8398e853e31c Binary files /dev/null and b/hi-vision/Picture/8.png differ diff --git a/hi-vision/Picture/9.png b/hi-vision/Picture/9.png new file mode 100644 index 0000000000000000000000000000000000000000..ff12e245720172a1929e0f0c3130761d1f98e94e Binary files /dev/null and b/hi-vision/Picture/9.png differ diff --git a/hi-vision/README.md b/hi-vision/README.md index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..49bf6ac8776353813f40fceb620e654e8b71ed34 100644 --- a/hi-vision/README.md +++ b/hi-vision/README.md @@ -0,0 +1,231 @@ +

海鸥派和RedCap初始化

+1. 烧录镜像，详细操作步骤在/hi-vision/[openeuler_v1.1.1](https://gitee.com/xiongsonglin/yocto-embedded-tools/tree/hieuler/hi-vision/openeuler_v1.1.1)/Readme.md中 + +2. 重新上电启动海鸥派，使用xshell连接串口，等待初始化后，即可看到OpenEuler的命令行，输入用户名root，密码（第一次使用需要设置密码），当看到用户名变成绿色时，表示已经成功进入系统 + +![](./Picture/1.png) + +3. 在鼎桥Redcap MT5710 模组反面插入5G sim卡，并将该模组插入海鸥派的USB中，上电后该模组会亮3s蓝色的灯，等待近10s启动后，串口会有如下打印 + +![](./Picture/2.png) + +![](./Picture/3.png) + +4. 在命令行中输入 ifconfig -a ，即可看到新增名为usb1的网口 + +![](./Picture/4.png) + +**PS：若ifconfig -a 找不到usb1，可能是因为下载的镜像中没有redcap驱动，请使用/hi-vision/patch中的**`5.10.0-153.28.0.patch`**和**`readcap_vendor_id.patch`**打热补丁** + +5. 可在当前目录下创建编辑测试拨号脚本dial.sh + +```bash +touch dial.sh +vi dial.sh +``` + + 具体内容如下，“udhcpc-i 网卡名称（对应修改）”： + +```bash +#!/bin/bash +echo -e "AT^NDISDUP=1,1\r\n" > /dev/ttyUSB1 +sleep 1 +udhcpc-i usb1 +``` + +![](./Picture/11.png) + +6. 修改文件执行权限并执行脚本dial.sh,命令行显示成功得到DNS + +```bash +chmod 777 dial.sh +./dial.sh +``` + +![](./Picture/6.png) + +**PS: 若./dial.sh一直卡在udhcpc: broadcasting discover，尝试重新插拔redcap** + +7. route发现有两个默认网关，其中一个是与电脑连接的网口，将这个默认网关删掉 + +```bash +route +route del default gw 192.168.10.1 +``` + +![](./Picture/7.png) + +8. 添加DNS服务器，编辑 `/etc/resolv.conf`文件如下： + +```bash +nameserver 8.8.8.8 +nameserver 8.8.4.4 +``` + +9. ping百度，发现能够正常上网，表示该usb网络已调试完成 + +![](./Picture/8.png) + +10. 接下来，为了能够让海鸥派与服务器协作，我们需要校准海鸥派的时间 + +```bash +# 同步时区 +cp /usr/share/zoneinfo/Asia/Shanghai /etc/localtime +# 校准具体时间，以实际时间为准 +date -s "2024-09-27 17:48:00" +``` + +至此，海鸥派和RedCap的初始化全部完成 + +

部署ubuntu环境

+在Windows中安装Ubuntu22.04系统，使用VMware软件，在此略过 + +

下载项目代码

+在Ubuntu中运行/hi_vision/download.sh脚本，安装需要的4个环境包 + +```plain +chmod 777 ./download.sh +./download.sh +``` + +将项目中的5个文件夹拷贝到docker容器中 + +1. opencv +2. opencv_contrib +3. pyserial +4. psutil +5. numpy + +我们电脑中的docker容器目录为：/home/robot/hieuler/build_3403/build/hieulerpi + +命令类似如下： + +```plain +cp -rf opencv /home/robot/hieuler/build_3403/build/hieulerpi +``` + +

下载安装SDK

+进入docker容器目录： + +```plain +cd /home/robot/hieuler/build_3403/build/hieulerpi +``` + +下载SDK + +```plain +wget https://mirrors.dotsrc.org/openeuler/openEuler-24.03-LTS/embedded_img/aarch64/hieulerpi1-ros/openeuler-glibc-x86_64-openeuler-image-aarch64-hieulerpi1-toolchain-24.03-LTS.sh +``` + +增加可执行权限 + +```plain +ls -l chmod +x openeuler-glibc-x86_64-openeuler-image-aarch64-hieulerpi1-toolchain-24.03-LTS.sh +``` + +执行下面命令，切换到openEuler交互环境，用户切换为openeuler： + +```plain +oebuild bitbake +``` + +安装刚刚下载的SDK: + +```plain +./openeuler-glibc-x86_64-openeuler-image-aarch64-hieulerpi1-toolchain-24.03-LTS.sh +``` + +使SDK生效 + +```plain +. /opt/openeuler/oecore-x86_64/environment-setup-aarch64-openeuler-linux +``` + +退出openEuler交互环境 + +```plain +exit +``` + +

编译项目代码

+```plain +进入docker容器目录： + +cd /home/robot/hieuler/build_3403/build/hieulerpi + + + +执行下面命令，切换到openEuler交互环境，用户切换为openeuler： + +oebuild bitbake + +执行下面命令，加载SDK（注意.后面的空格） + +. /opt/openeuler/oecore-x86_64/environment-setup-aarch64-openeuler-linux + +依次编译上面第二步拷贝过来的文件夹，例如编译hi_vision项目(禁止BUILD_TESTING)： + +cd hi_vision +colcon build --cmake-args -DBUILD_TESTING=False + +编译完成后，生成的可执行文件在install目录中 + +退出openEuler交叉编译环境 + +exit +``` + +

下载

+使用VMware的共享文件夹或下载VMware tools实现将所有生成的可执行文件从Ubuntu系统中拷贝至Windows桌面。 + +然后使用xftp软件，将所有的可执行文件拷贝进入OpenEuler系统。 + +```plain +在开发板的openEuler环境，进入install目录，修改setup.sh： + +cd vision_install +vi setup.sh + +第十行为colcon的编译目录名， +_colcon_prefix_chain_sh_COLCON_CURRENT_PREFIX=/home/openeuler/build/sd3403/eulercar/install +. +我们需要将install目录下的所有文件中，该目录名，替换为，开发板的工作目录名/root/install。类似如下 + +_colcon_prefix_chain_sh_COLCON_CURRENT_PREFIX=/root/vision_install + +这里手动修改，点击i进入编辑模式，修改好后按Esc键退出编辑模式，然后输入:wq保存退出文件 +``` + +

推流

+1. 依照RTMP服务器制作.md搭建RTMP服务器，并将.py中的RTMP URL切换为自己搭建的服务器的URL +2. 该项目的运行还需要ffmpeg库，因此需要在ffmpeg官网上下载ARM64架构的ffmpeg库，进入网页[https://johnvansickle.com/ffmpeg/](https://johnvansickle.com/ffmpeg/)，找到ffmpeg-release-arm64-static.tar.xz，点击下载 + +![](./Picture/12.png) + +将ffmpeg-release-arm64-static.tar.xz移动至主目录解压缩，并和/Demo/redcap_rtmp.py在同一目录下 + +3. 插入usb摄像头，能看到检测到video + +![](./Picture/13.png) + +4. 以上配置全部正确后，运行以下命令开始推流 + +```plain +python redcap_rtmp.py +``` + +

Windows端拉流

+1. windows端下载ffplay，进入网站[https://www.gyan.dev/ffmpeg/builds/](https://www.gyan.dev/ffmpeg/builds/)，点击release版本下载 + +![](./Picture/14.png) + +下载后解压，进入bin目录，打开Windows Shell，并输入以下指令 + +```plain +./ffplay -fflags nobuffer rtmp://rtmp.dd33.net/live/80e07838e6ce?45CE2282FCC6454A（修改为自己的RTMP URL） +``` + +运行后测试视频帧率23fps，延迟在2秒以内。 + +![](./Picture/10.png) + diff --git "a/hi-vision/RTMP\346\234\215\345\212\241\345\231\250\345\210\266\344\275\234README.md" "b/hi-vision/RTMP\346\234\215\345\212\241\345\231\250\345\210\266\344\275\234README.md" new file mode 100644 index 0000000000000000000000000000000000000000..d8f52ac125da4f412d9ce9acf56edd130c7996c2 --- /dev/null +++ "b/hi-vision/RTMP\346\234\215\345\212\241\345\231\250\345\210\266\344\275\234README.md" @@ -0,0 +1,127 @@ +我们使用RTMP服务器进行视频流的传输，协议流程如下： + +![](./Picture/2.1.png) + +用RTMP协议的流媒体推流还需要经过以下几个步骤： + +```plain +握手（RTMP连接都是以握手作为开始） +建立连接 （建立客户端与服务器之间的“网络连接”） +建立流 （建立客户端与服务器之间的“网络流”） +推流&播放 +``` + +

gcc-c++ 编译环境

+```plain +sudo apt-get install build-essential +sudo apt-get install gcc +sudo apt-get install g++ +``` + +

openssl插件

+```plain +wget https://www.openssl.org/source/openssl-1.1.1d.tar.gz +tar -zxvf tar -zxvf openssl-1.1.1d.tar.gz +cd openssl-1.1.1d +sudo ./config --prefix=/home/env/openssl-1.1.1d #prefix指定安装目录(自定义) +sudo make +sudo make install +``` + +

pcre插件

+```plain +wget https://ftp.pcre.org/pub/pcre/pcre-8.35.tar.gz +tar -zxvf pcre-8.35.tar.gz +cd pcre-8.35 +sudo ./configure --prefix=/home/env/pcre-8.35 #prefix指定安装目录(自定义) +sudo make +sudo make install +``` + +

zlib插件

+```plain +wget https://zlib.net/zlib-1.2.8.tar.gz +tar -zxvf zlib-1.2.8.tar.gz +cd zlib-1.2.8 +sudo ./configure --prefix=/home/env/zlib-1.2.8 #prefix指定安装目录(自定义) +sudo make +sudo make install +``` + +

nginx-rtmp-module 流

+```plain +git clone https://github.com/arut/nginx-rtmp-module.git +unzip nginx-rtmp-module-master.zip +``` + +

安装nginx

+```plain +#cd nginx-1.14.0/ +源码路径(非安装目录): --with--xxx=DIR DIR一定是源码路径(解压后的路径) +add-module=DIR DIR是unzip解压rtmp的的路径 +#./configure --prefix=/usr/local/nginx-1.14.0 --with-openssl=/home/env/openssl-1.1.1d --with-pcre=/home/env/pcre-8.35 --with-zlib=/home/env/zlib-1.2.8 --add-module=/home/env/nginx-rtmp-module-master --with-http_ssl_module +#sudo make +#sudo make install +``` + +

配置nginx

+```plain +vi /usr/local/nginx-1.14.0/conf/nginx.conf +``` + +增加如下配置 + +```plain +rtmp { + server { + listen 1935; #监听的端口 + chunk_size 4096; + application hls { #rtmp推流请求路径 + live on; + hls on; + hls_path /你的流存放路径; #hls_path需要可读可写的权限。 + hls_fragment 5s; #一个片段含5秒内容，也就是1给文件含有5秒的内容进行保存 + } + } +} +``` + +修改http中的server模块： + +```plain +server { + listen 81; + server_name localhost; + + #charset koi8-r; + + #access_log logs/host.access.log main; + + location / { + root /usr/share/nginx/html; + index index.html index.htm; + } + + #error_page 404 /404.html; + + # redirect server error pages to the static page /50x.html + # + error_page 500 502 503 504 /50x.html; + location = /50x.html { + root html; + } +``` + +启动nginx + +```plain + ps-ef |grep nginx +``` + +

使用obs推流

+打开OBS Studio进行推流 + +![](./Picture/2.2.png) + +去配置的 hls_path(刚刚nginx.conf里面配置的存放流文件的路径） 目录查看是否产生了文件，cd到对应的路径能够看到路径下产生了.ts和.m3u8文件。 + diff --git a/hi-vision/download.sh b/hi-vision/download.sh new file mode 100644 index 0000000000000000000000000000000000000000..efbdbd8a73609e4d0a8f8fce8e27f5980bfb733a --- /dev/null +++ b/hi-vision/download.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +# ҪصĴַ +REPOS=( + "https://github.com/opencv/opencv.git" + "https://github.com/opencv/opencv_contrib.git" + "https://github.com/pyserial/pyserial.git" + "https://github.com/giampaolo/psutil.git" + "https://github.com/numpy/numpy.git" +) + +# ȡűĿ¼ +SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)" + +# űĿ¼ +cd $SCRIPT_DIR + +# ο¡ÿ +for REPO in "${REPOS[@]}"; do + git clone $REPO +done diff --git a/hi-vision/openeuler_v1.1.1/1.JPG b/hi-vision/openeuler_v1.1.1/1.JPG new file mode 100644 index 0000000000000000000000000000000000000000..d81a74f5b5b838e7096284fb1117c810aae444e8 Binary files /dev/null and b/hi-vision/openeuler_v1.1.1/1.JPG differ diff --git a/hi-vision/openeuler_v1.1.1/2.png b/hi-vision/openeuler_v1.1.1/2.png new file mode 100644 index 0000000000000000000000000000000000000000..4ca256037a8eae75788a80107974e4e7203029db Binary files /dev/null and b/hi-vision/openeuler_v1.1.1/2.png differ diff --git a/hi-vision/openeuler_v1.1.1/3.png b/hi-vision/openeuler_v1.1.1/3.png new file mode 100644 index 0000000000000000000000000000000000000000..2a6b6d104fefb34ac9a5ee3d20c745936a5428dd Binary files /dev/null and b/hi-vision/openeuler_v1.1.1/3.png differ diff --git a/hi-vision/openeuler_v1.1.1/Readme.md b/hi-vision/openeuler_v1.1.1/Readme.md new file mode 100644 index 0000000000000000000000000000000000000000..ff57c8b15f738868c417725247ec54589ffd8e52 --- /dev/null +++ b/hi-vision/openeuler_v1.1.1/Readme.md @@ -0,0 +1,15 @@ +1. 为海鸥派上电，插入网口和串口（debug），并连接电脑，当海鸥派亮起红灯时表示正常启动 + +![](1.JPG) + +2. 进入网址：https://gitee.com/HiEuler/doc/blob/master/EulerPi%20Compile%20using%20One%20Finger%20Zen.md，并按照教程下载ROS版本镜像文件和Uboot镜像 + +![](2.png) + +3. 打开toolplatform软件 +4. 选择串口和网口，在烧写eMMC选项处加载eMMC分区表文件parttable.xml，看到下方文件加载正常 + +![](3.png) + +5. 点击烧写，按欧拉派网口旁的RST按键一次，看到下方命令行出现*************，即表示一切正常，等待烧录完成即可。 + diff --git a/hi-vision/patch/5.10.0-153.28.0.patch b/hi-vision/patch/5.10.0-153.28.0.patch new file mode 100644 index 0000000000000000000000000000000000000000..0353a06ca187db209c914bdd9becdedff3cb1a07 --- /dev/null +++ b/hi-vision/patch/5.10.0-153.28.0.patch @@ -0,0 +1,68213 @@ +From cd8ca2fc8fbccb9afbab7b090e7595c2075cf09f Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?=E6=98=93=E5=B0=8F=E6=B5=B7?= + <14510022+e-xiaohai@user.noreply.gitee.com> +Date: Thu, 5 Sep 2024 06:47:30 +0000 +Subject: [PATCH] add redcap + +--- + arch/arm/Makefile | 5 + + arch/arm64/Kconfig.platforms | 71 + + arch/arm64/boot/dts/Makefile | 1 + + arch/arm64/boot/dts/vendor/Makefile | 2 + + arch/arm64/boot/dts/vendor/ss928v100-demo.dts | 415 ++ + arch/arm64/boot/dts/vendor/ss928v100.dtsi | 1107 ++++ + arch/arm64/configs/hieulerpi1_defconfig | 5630 +++++++++++++++++ + arch/arm64/configs/ss928v100_defconfig | 3665 +++++++++++ + arch/arm64/configs/ss928v100_emmc_defconfig | 4137 ++++++++++++ + arch/arm64/configs/ss928v100_nand_defconfig | 3669 +++++++++++ + arch/arm64/kernel/pci.c | 12 + + arch/arm64/mm/init.c | 4 + + drivers/Kconfig | 2 + + drivers/Makefile | 1 + + drivers/clk/Kconfig | 1 + + drivers/clk/Makefile | 1 + + drivers/clk/vendor/Kconfig | 12 + + drivers/clk/vendor/Makefile | 8 + + drivers/clk/vendor/clk.c | 288 + + drivers/clk/vendor/clk.h | 127 + + drivers/clk/vendor/clk_hi3519dv500.c | 507 ++ + drivers/clk/vendor/clk_ss928v100.c | 693 ++ + drivers/clk/vendor/clkgate_separated.c | 108 + + drivers/clk/vendor/crg.h | 24 + + drivers/clk/vendor/reset.c | 145 + + drivers/clk/vendor/reset.h | 29 + + drivers/dma/Makefile | 1 + + drivers/dma/edmacv310.c | 1450 +++++ + drivers/dma/edmacv310.h | 147 + + drivers/gpio/gpio-pl061.c | 15 + + drivers/i2c/busses/Kconfig | 27 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-bsp.c | 1534 +++++ + drivers/i2c/i2c-dev.c | 55 + + drivers/iio/adc/Kconfig | 10 + + drivers/iio/adc/Makefile | 1 + + drivers/iio/adc/bsp_lsadc.c | 473 ++ + drivers/iio/industrialio-core.c | 48 + + drivers/iommu/Kconfig | 72 +- + drivers/iommu/Makefile | 5 +- + drivers/iommu/amd/amd_iommu.h | 1 - + drivers/iommu/amd/amd_iommu_types.h | 1 - + drivers/iommu/amd/init.c | 193 +- + drivers/iommu/amd/iommu.c | 13 +- + drivers/iommu/amd/iommu_v2.c | 7 +- + drivers/iommu/arm/arm-smmu-v3/Makefile | 1 - + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 18 +- + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1785 ++---- + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 98 +- + drivers/iommu/arm/arm-smmu-v3/ascend_smmu.c | 434 -- + drivers/iommu/arm/arm-smmu/arm-smmu.c | 47 +- + drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +- + drivers/iommu/dma-iommu.c | 6 +- + drivers/iommu/exynos-iommu.c | 6 +- + drivers/iommu/fsl_pamu.c | 2 +- + drivers/iommu/intel/Kconfig | 1 - + drivers/iommu/intel/dmar.c | 86 +- + drivers/iommu/intel/iommu.c | 355 +- + drivers/iommu/intel/irq_remapping.c | 13 +- + drivers/iommu/intel/pasid.c | 32 +- + drivers/iommu/intel/pasid.h | 16 +- + drivers/iommu/intel/svm.c | 383 +- + drivers/iommu/io-pgfault.c | 6 + + drivers/iommu/io-pgtable-arm-v7s.c | 6 +- + drivers/iommu/io-pgtable-arm.c | 409 +- + drivers/iommu/ioasid.c | 38 +- + drivers/iommu/iommu-sva-lib.c | 39 +- + drivers/iommu/iommu-sva-lib.h | 7 +- + drivers/iommu/iommu.c | 321 +- + drivers/iommu/iova.c | 39 +- + drivers/iommu/ipmmu-vmsa.c | 4 +- + drivers/iommu/msm_iommu.c | 11 +- + drivers/iommu/mtk_iommu.c | 3 +- + drivers/iommu/mtk_iommu_v1.c | 26 +- + drivers/iommu/omap-iommu-debug.c | 6 +- + drivers/iommu/omap-iommu.c | 2 +- + drivers/iommu/sun50i-iommu.c | 16 +- + drivers/iommu/sw64/Kconfig | 9 - + drivers/iommu/sw64/Makefile | 2 - + drivers/iommu/sw64/sunway_iommu.c | 1693 ----- + drivers/iommu/sw64/sunway_iommu.h | 77 - + drivers/iommu/virtio-iommu.c | 3 +- + drivers/media/usb/uvc/uvc_ctrl.c | 30 +- + drivers/media/usb/uvc/uvc_driver.c | 71 +- + drivers/media/usb/uvc/uvc_entity.c | 2 +- + drivers/media/usb/uvc/uvc_status.c | 40 +- + drivers/media/usb/uvc/uvc_video.c | 15 +- + drivers/media/usb/uvc/uvcvideo.h | 9 +- + drivers/mfd/Makefile | 1 + + drivers/mfd/bsp_fmc.c | 134 + + drivers/mmc/core/core.c | 37 +- + drivers/mmc/core/mmc.c | 7 +- + drivers/mmc/core/sd.c | 1 + + drivers/mmc/core/sdio.c | 46 +- + drivers/mmc/host/Kconfig | 7 + + drivers/mmc/host/Makefile | 2 + + drivers/mmc/host/bsp_quirk_ids.h | 67 + + drivers/mmc/host/cqhci.c | 58 +- + drivers/mmc/host/cqhci.h | 8 + + drivers/mmc/host/mci_proc.c | 338 + + drivers/mmc/host/mci_proc.h | 41 + + drivers/mmc/host/sdhci-bsp.c | 950 +++ + drivers/mmc/host/sdhci-bsp.h | 135 + + drivers/mmc/host/sdhci-ss928v100.c | 931 +++ + drivers/mmc/host/sdhci.c | 34 +- + drivers/mmc/host/sdhci.h | 30 +- + drivers/net/ethernet/Kconfig | 1 + + drivers/net/ethernet/Makefile | 1 + + drivers/net/ethernet/vendor/Kconfig | 20 + + drivers/net/ethernet/vendor/Makefile | 6 + + drivers/net/ethernet/vendor/gmac/Kconfig | 106 + + drivers/net/ethernet/vendor/gmac/Makefile | 2 + + .../ethernet/vendor/gmac/autoeee/autoeee.c | 137 + + .../ethernet/vendor/gmac/autoeee/autoeee.h | 49 + + .../vendor/gmac/autoeee/phy_id_table.c | 181 + + drivers/net/ethernet/vendor/gmac/gmac.c | 2289 +++++++ + drivers/net/ethernet/vendor/gmac/gmac.h | 779 +++ + .../ethernet/vendor/gmac/gmac_ethtool_ops.c | 401 ++ + .../ethernet/vendor/gmac/gmac_ethtool_ops.h | 35 + + .../ethernet/vendor/gmac/gmac_netdev_ops.c | 730 +++ + .../ethernet/vendor/gmac/gmac_netdev_ops.h | 22 + + .../net/ethernet/vendor/gmac/gmac_phy_fixup.c | 154 + + .../net/ethernet/vendor/gmac/gmac_phy_fixup.h | 13 + + drivers/net/ethernet/vendor/gmac/gmac_pm.c | 340 + + drivers/net/ethernet/vendor/gmac/gmac_pm.h | 56 + + drivers/net/ethernet/vendor/gmac/gmac_proc.c | 80 + + drivers/net/ethernet/vendor/gmac/gmac_proc.h | 21 + + drivers/net/phy/Kconfig | 6 + + drivers/net/phy/Makefile | 2 + + drivers/net/phy/mdio_bsp_gemac.c | 232 + + drivers/net/phy/mdio_bsp_gemac.h | 28 + + drivers/phy/Kconfig | 1 + + drivers/phy/Makefile | 1 + + drivers/phy/vendor/Kconfig | 23 + + drivers/phy/vendor/Makefile | 5 + + drivers/phy/vendor/phy-bsp-sata.c | 175 + + drivers/phy/vendor/phy-bsp-sata.h | 39 + + drivers/phy/vendor/phy-ss524v100-sata.c | 684 ++ + drivers/phy/vendor/phy-ss528v100-sata.c | 1043 +++ + drivers/phy/vendor/phy-ss625v100-sata.c | 732 +++ + drivers/phy/vendor/usb/Kconfig | 88 + + drivers/phy/vendor/usb/Makefile | 21 + + drivers/phy/vendor/usb/phy-bsp-usb.c | 142 + + drivers/phy/vendor/usb/phy-bsp-usb.h | 66 + + drivers/phy/vendor/usb/phy-ss524v100-usb.c | 449 ++ + drivers/phy/vendor/usb/phy-ss528v100-usb.c | 584 ++ + drivers/phy/vendor/usb/phy-ss928v100-usb.c | 358 ++ + drivers/phy/vendor/usb/phy-xvp-bsp-usb.c | 798 +++ + drivers/pwm/Kconfig | 9 + + drivers/pwm/Makefile | 1 + + drivers/pwm/pwm-bsp.c | 434 ++ + drivers/pwm/sysfs.c | 114 +- + drivers/spi/spi-pl022.c | 237 +- + drivers/usb/dwc3/Makefile | 4 +- + drivers/usb/dwc3/core.c | 51 +- + drivers/usb/dwc3/core.h | 47 + + drivers/usb/dwc3/dwc3-bsp.c | 441 ++ + drivers/usb/dwc3/dwc3-bsp.h | 47 + + drivers/usb/dwc3/ep0.c | 46 + + drivers/usb/dwc3/gadget.c | 211 +- + drivers/usb/dwc3/proc.c | 132 + + drivers/usb/gadget/Kconfig | 8 + + drivers/usb/gadget/configfs.c | 4 + + drivers/usb/gadget/epautoconf.c | 18 +- + drivers/usb/gadget/function/f_mass_storage.c | 8 +- + drivers/usb/gadget/function/f_uac1.c | 58 +- + drivers/usb/gadget/function/f_uvc.c | 463 +- + drivers/usb/gadget/function/u_audio.c | 2 +- + drivers/usb/gadget/function/u_serial.c | 23 +- + drivers/usb/gadget/function/u_uvc.h | 5 +- + drivers/usb/gadget/function/uvc.h | 46 +- + drivers/usb/gadget/function/uvc_configfs.c | 857 ++- + drivers/usb/gadget/function/uvc_v4l2.c | 28 +- + drivers/usb/gadget/function/uvc_video.c | 490 +- + drivers/usb/gadget/udc/renesas_usb3.c | 1 - + drivers/usb/serial/option.c | 104 + + drivers/vendor/Kconfig | 5 + + drivers/vendor/Makefile | 3 + + drivers/vendor/cma/Kconfig | 16 + + drivers/vendor/cma/Makefile | 2 + + drivers/vendor/cma/cma.c | 176 + + drivers/vendor/npu/Kconfig | 7 + + drivers/vendor/npu/Makefile | 6 + + drivers/vendor/npu/npu_misc.c | 770 +++ + drivers/vendor/npu/npu_svm.c | 1370 ++++ + drivers/vendor/npu/smmu_power_on.c | 91 + + drivers/vendor/peri/Makefile | 2 + + drivers/vendor/peri/peri_io_ss928v100.c | 46 + + fs/read_write.c | 2 + + include/dt-bindings/clock/ss928v100_clock.h | 146 + + include/linux/bsp_cma.h | 52 + + include/linux/clk-provider.h | 1 + + include/linux/edmac.h | 80 + + include/linux/i2c.h | 17 + + include/linux/iio/iio.h | 7 + + include/linux/io-pgtable.h | 34 +- + include/linux/ioasid.h | 21 +- + include/linux/iommu.h | 128 +- + include/linux/iova.h | 5 +- + include/linux/iprec.h | 51 + + include/linux/mfd/bsp_fmc.h | 480 ++ + include/linux/mm_types.h | 3 + + include/linux/mmc/host.h | 14 +- + include/linux/pwm.h | 4 + + include/linux/securec.h | 629 ++ + include/linux/securectype.h | 585 ++ + include/linux/vendor/peri_io.h | 57 + + include/linux/vendor/sva_ext.h | 93 + + include/uapi/linux/i2c-dev.h | 2 + + include/uapi/linux/i2c.h | 3 + + include/uapi/linux/usb/g_uvc.h | 15 + + include/uapi/linux/usb/video.h | 90 + + include/uapi/linux/videodev2.h | 1 + + kernel/Makefile | 2 + + kernel/dma/contiguous.c | 16 + + kernel/fork.c | 8 + + kernel/iprec.c | 410 ++ + kernel/kallsyms.c | 1 + + kernel/sched/core.c | 1 + + lib/Kconfig | 4 + + lib/Makefile | 2 + + lib/securec/LICENSE | 124 + + lib/securec/Makefile | 1 + + lib/securec/README.en.md | 59 + + lib/securec/README.md | 56 + + lib/securec/src/Makefile | 17 + + lib/securec/src/input.inl | 2229 +++++++ + lib/securec/src/memcpy_s.c | 555 ++ + lib/securec/src/memmove_s.c | 123 + + lib/securec/src/memset_s.c | 510 ++ + lib/securec/src/output.inl | 1720 +++++ + lib/securec/src/scanf_s.c | 51 + + lib/securec/src/secinput.h | 181 + + lib/securec/src/securecutil.c | 81 + + lib/securec/src/securecutil.h | 574 ++ + lib/securec/src/secureinput_a.c | 38 + + lib/securec/src/secureprintoutput.h | 146 + + lib/securec/src/secureprintoutput_a.c | 112 + + lib/securec/src/snprintf_s.c | 110 + + lib/securec/src/sprintf_s.c | 58 + + lib/securec/src/sscanf_s.c | 58 + + lib/securec/src/strcat_s.c | 101 + + lib/securec/src/strcpy_s.c | 353 ++ + lib/securec/src/strncat_s.c | 119 + + lib/securec/src/strncpy_s.c | 145 + + lib/securec/src/strtok_s.c | 116 + + lib/securec/src/vscanf_s.c | 63 + + lib/securec/src/vsnprintf_s.c | 138 + + lib/securec/src/vsprintf_s.c | 67 + + lib/securec/src/vsscanf_s.c | 87 + + 250 files changed, 56505 insertions(+), 5453 deletions(-) + create mode 100644 arch/arm64/boot/dts/vendor/Makefile + create mode 100644 arch/arm64/boot/dts/vendor/ss928v100-demo.dts + create mode 100644 arch/arm64/boot/dts/vendor/ss928v100.dtsi + create mode 100644 arch/arm64/configs/hieulerpi1_defconfig + create mode 100644 arch/arm64/configs/ss928v100_defconfig + create mode 100644 arch/arm64/configs/ss928v100_emmc_defconfig + create mode 100644 arch/arm64/configs/ss928v100_nand_defconfig + create mode 100644 drivers/clk/vendor/Kconfig + create mode 100644 drivers/clk/vendor/Makefile + create mode 100644 drivers/clk/vendor/clk.c + create mode 100644 drivers/clk/vendor/clk.h + create mode 100644 drivers/clk/vendor/clk_hi3519dv500.c + create mode 100644 drivers/clk/vendor/clk_ss928v100.c + create mode 100644 drivers/clk/vendor/clkgate_separated.c + create mode 100644 drivers/clk/vendor/crg.h + create mode 100644 drivers/clk/vendor/reset.c + create mode 100644 drivers/clk/vendor/reset.h + create mode 100644 drivers/dma/edmacv310.c + create mode 100644 drivers/dma/edmacv310.h + create mode 100644 drivers/i2c/busses/i2c-bsp.c + create mode 100644 drivers/iio/adc/bsp_lsadc.c + delete mode 100644 drivers/iommu/arm/arm-smmu-v3/ascend_smmu.c + delete mode 100644 drivers/iommu/sw64/Kconfig + delete mode 100644 drivers/iommu/sw64/Makefile + delete mode 100644 drivers/iommu/sw64/sunway_iommu.c + delete mode 100644 drivers/iommu/sw64/sunway_iommu.h + create mode 100644 drivers/mfd/bsp_fmc.c + create mode 100644 drivers/mmc/host/bsp_quirk_ids.h + create mode 100644 drivers/mmc/host/mci_proc.c + create mode 100644 drivers/mmc/host/mci_proc.h + create mode 100644 drivers/mmc/host/sdhci-bsp.c + create mode 100644 drivers/mmc/host/sdhci-bsp.h + create mode 100644 drivers/mmc/host/sdhci-ss928v100.c + create mode 100644 drivers/net/ethernet/vendor/Kconfig + create mode 100644 drivers/net/ethernet/vendor/Makefile + create mode 100644 drivers/net/ethernet/vendor/gmac/Kconfig + create mode 100644 drivers/net/ethernet/vendor/gmac/Makefile + create mode 100644 drivers/net/ethernet/vendor/gmac/autoeee/autoeee.c + create mode 100644 drivers/net/ethernet/vendor/gmac/autoeee/autoeee.h + create mode 100644 drivers/net/ethernet/vendor/gmac/autoeee/phy_id_table.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac.h + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.h + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.h + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.h + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_pm.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_pm.h + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_proc.c + create mode 100644 drivers/net/ethernet/vendor/gmac/gmac_proc.h + create mode 100644 drivers/net/phy/mdio_bsp_gemac.c + create mode 100644 drivers/net/phy/mdio_bsp_gemac.h + create mode 100644 drivers/phy/vendor/Kconfig + create mode 100644 drivers/phy/vendor/Makefile + create mode 100644 drivers/phy/vendor/phy-bsp-sata.c + create mode 100644 drivers/phy/vendor/phy-bsp-sata.h + create mode 100644 drivers/phy/vendor/phy-ss524v100-sata.c + create mode 100644 drivers/phy/vendor/phy-ss528v100-sata.c + create mode 100644 drivers/phy/vendor/phy-ss625v100-sata.c + create mode 100644 drivers/phy/vendor/usb/Kconfig + create mode 100644 drivers/phy/vendor/usb/Makefile + create mode 100644 drivers/phy/vendor/usb/phy-bsp-usb.c + create mode 100644 drivers/phy/vendor/usb/phy-bsp-usb.h + create mode 100644 drivers/phy/vendor/usb/phy-ss524v100-usb.c + create mode 100644 drivers/phy/vendor/usb/phy-ss528v100-usb.c + create mode 100644 drivers/phy/vendor/usb/phy-ss928v100-usb.c + create mode 100644 drivers/phy/vendor/usb/phy-xvp-bsp-usb.c + create mode 100644 drivers/pwm/pwm-bsp.c + create mode 100644 drivers/usb/dwc3/dwc3-bsp.c + create mode 100644 drivers/usb/dwc3/dwc3-bsp.h + create mode 100644 drivers/usb/dwc3/proc.c + create mode 100644 drivers/vendor/Kconfig + create mode 100644 drivers/vendor/Makefile + create mode 100644 drivers/vendor/cma/Kconfig + create mode 100644 drivers/vendor/cma/Makefile + create mode 100644 drivers/vendor/cma/cma.c + create mode 100644 drivers/vendor/npu/Kconfig + create mode 100644 drivers/vendor/npu/Makefile + create mode 100644 drivers/vendor/npu/npu_misc.c + create mode 100644 drivers/vendor/npu/npu_svm.c + create mode 100644 drivers/vendor/npu/smmu_power_on.c + create mode 100644 drivers/vendor/peri/Makefile + create mode 100644 drivers/vendor/peri/peri_io_ss928v100.c + create mode 100644 include/dt-bindings/clock/ss928v100_clock.h + create mode 100644 include/linux/bsp_cma.h + create mode 100644 include/linux/edmac.h + create mode 100755 include/linux/iprec.h + create mode 100644 include/linux/mfd/bsp_fmc.h + create mode 100644 include/linux/securec.h + create mode 100644 include/linux/securectype.h + create mode 100644 include/linux/vendor/peri_io.h + create mode 100644 include/linux/vendor/sva_ext.h + create mode 100755 kernel/iprec.c + create mode 100644 lib/securec/LICENSE + create mode 100644 lib/securec/Makefile + create mode 100644 lib/securec/README.en.md + create mode 100644 lib/securec/README.md + create mode 100644 lib/securec/src/Makefile + create mode 100644 lib/securec/src/input.inl + create mode 100644 lib/securec/src/memcpy_s.c + create mode 100644 lib/securec/src/memmove_s.c + create mode 100644 lib/securec/src/memset_s.c + create mode 100644 lib/securec/src/output.inl + create mode 100644 lib/securec/src/scanf_s.c + create mode 100644 lib/securec/src/secinput.h + create mode 100644 lib/securec/src/securecutil.c + create mode 100644 lib/securec/src/securecutil.h + create mode 100644 lib/securec/src/secureinput_a.c + create mode 100644 lib/securec/src/secureprintoutput.h + create mode 100644 lib/securec/src/secureprintoutput_a.c + create mode 100644 lib/securec/src/snprintf_s.c + create mode 100644 lib/securec/src/sprintf_s.c + create mode 100644 lib/securec/src/sscanf_s.c + create mode 100644 lib/securec/src/strcat_s.c + create mode 100644 lib/securec/src/strcpy_s.c + create mode 100644 lib/securec/src/strncat_s.c + create mode 100644 lib/securec/src/strncpy_s.c + create mode 100644 lib/securec/src/strtok_s.c + create mode 100644 lib/securec/src/vscanf_s.c + create mode 100644 lib/securec/src/vsnprintf_s.c + create mode 100644 lib/securec/src/vsprintf_s.c + create mode 100644 lib/securec/src/vsscanf_s.c + +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index d6817de42f24..07acfc5380cb 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_FOOTBRIDGE) += footbridge + machine-$(CONFIG_ARCH_GEMINI) += gemini + machine-$(CONFIG_ARCH_HIGHBANK) += highbank + machine-$(CONFIG_ARCH_HISI) += hisi ++machine-$(CONFIG_ARCH_BSP) += bsp + machine-$(CONFIG_ARCH_INTEGRATOR) += integrator + machine-$(CONFIG_ARCH_IOP32X) += iop32x + machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx +@@ -271,6 +272,10 @@ KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs)) + endif + endif + ++ifeq ($(CONFIG_ARCH_BSP),y) ++KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs)) ++endif ++ + export TEXT_OFFSET GZFLAGS MMUEXT + + core-y += arch/arm/ +diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms +index c924fce750f1..63cb3695098e 100644 +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -136,6 +136,77 @@ config ARCH_HISI + help + This enables support for Hisilicon ARMv8 SoC family + ++config ARCH_BSP ++ bool "Vendor SoC Family" ++ select ARM_TIMER_SP804 ++ select PINCTRL ++ help ++ This enables support for Vendor ARMv8 SoC family ++ ++config ARCH_SS528V100 ++ bool "SS528V100 family" ++ depends on ARCH_BSP ++ select ARM_TIMER_SP804 ++ select PINCTRL ++ help ++ Support for SS528V100 Soc family ++ ++ ++config ARCH_SS625V100 ++ bool "SS625V100 family" ++ depends on ARCH_BSP ++ select ARM_TIMER_SP804 ++ select PINCTRL ++ help ++ Support for SS625V100 Soc family ++ ++config ARCH_SS919V100 ++ bool "SS919V100 family" ++ depends on ARCH_BSP ++ select ARM_TIMER_SP804 ++ select PINCTRL ++ help ++ Support for SS919V100 Soc family ++ ++config ARCH_SS015V100 ++ bool "SS015V100 family" ++ depends on ARCH_BSP ++ select ARM_TIMER_SP804 ++ select PINCTRL ++ help ++ Support for SS015V100 Soc family ++ ++config ARCH_SS928V100 ++ bool "Vendor ss928v100 family" ++ depends on ARCH_BSP ++ select ARM_TIMER_SP804 ++ select HISILICON_IRQ_MBIGEN if PCI ++ select PINCTRL ++ help ++ Support for Vendor SS928V100 Soc family ++ ++config ARCH_SS927V100 ++ bool "Vendor ss927v100 family" ++ depends on ARCH_BSP ++ select ARM_TIMER_SP804 ++ select HISILICON_IRQ_MBIGEN if PCI ++ select PINCTRL ++ help ++ Support for Vendor SS927V100 Soc family ++ ++config ACCESS_M7_DEV ++ bool "Enable to access the devices of m7" ++ depends on (ARCH_SS919V100 || ARCH_SS015V100) ++ help ++ supprot to access the devices of M7 ++ ++config ARCH_BSP_AMP ++ bool "Vendor AMP solution" ++ select DMA_SHARED_BUFFER ++ depends on (ARCH_SS919V100 || ARCH_SS015V100) ++ help ++ Support for SS919V100 and SS015V100 AMP ++ + config ARCH_KEEMBAY + bool "Keem Bay SoC" + help +diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile +index 9b1170658d60..33a2db38af67 100644 +--- a/arch/arm64/boot/dts/Makefile ++++ b/arch/arm64/boot/dts/Makefile +@@ -30,3 +30,4 @@ subdir-y += ti + subdir-y += toshiba + subdir-y += xilinx + subdir-y += zte ++subdir-y += vendor +diff --git a/arch/arm64/boot/dts/vendor/Makefile b/arch/arm64/boot/dts/vendor/Makefile +new file mode 100644 +index 000000000000..bf71c96d6346 +--- /dev/null ++++ b/arch/arm64/boot/dts/vendor/Makefile +@@ -0,0 +1,2 @@ ++# SPDX-License-Identifier: GPL-2.0 ++dtb-$(CONFIG_ARCH_BSP) += ss928v100-demo.dtb +diff --git a/arch/arm64/boot/dts/vendor/ss928v100-demo.dts b/arch/arm64/boot/dts/vendor/ss928v100-demo.dts +new file mode 100644 +index 000000000000..9ebd9255895c +--- /dev/null ++++ b/arch/arm64/boot/dts/vendor/ss928v100-demo.dts +@@ -0,0 +1,415 @@ ++/* Copyright (c) 2017 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++/dts-v1/; ++/* reserved for warmreset */ ++/* reserved for arm trustedfirmware */ ++/* Modify this configuration according to the system framework */ ++/memreserve/ 0x0000000052fff000 0x0000000001a02000; ++#include "ss928v100.dtsi" ++ ++/ { ++ model = "Vendor SS928V100 DEMO Board"; ++ compatible = "vendor,ss928v100"; ++ ++ aliases { ++ serial0 = &uart0; ++ ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ ++ i2c0 = &i2c_bus0; ++ i2c1 = &i2c_bus1; ++ i2c2 = &i2c_bus2; ++ i2c3 = &i2c_bus3; ++ i2c4 = &i2c_bus4; ++ i2c5 = &i2c_bus5; ++ ++ spi0 = &spi_bus0; ++ spi1 = &spi_bus1; ++ spi2 = &spi_bus2; ++ spi3 = &spi_bus3; ++ ++ gpio0 = &gpio_chip0; ++ gpio1 = &gpio_chip1; ++ gpio2 = &gpio_chip2; ++ gpio3 = &gpio_chip3; ++ gpio4 = &gpio_chip4; ++ gpio5 = &gpio_chip5; ++ gpio6 = &gpio_chip6; ++ gpio7 = &gpio_chip7; ++ gpio8 = &gpio_chip8; ++ gpio9 = &gpio_chip9; ++ gpio10 = &gpio_chip10; ++ gpio11 = &gpio_chip11; ++ gpio12 = &gpio_chip12; ++ gpio13 = &gpio_chip13; ++ gpio14 = &gpio_chip14; ++ gpio15 = &gpio_chip15; ++ gpio16 = &gpio_chip16; ++ gpio17 = &gpio_chip17; ++ }; ++ hi110x { ++ compatible = "hisilicon,hi110x"; ++ hi110x,subchip_type="hi1102a"; ++ hi110x,gpio_power_on = <&gpio_chip2 2 0>; ++ hi110x,gpio_bfgx_power_on = <&gpio_chip2 0 0>; ++ hi110x,gpio_wlan_power_on = <&gpio_chip1 7 0>; ++ huawei,pmu_clk32b = "clk_pmu32kb"; ++ hi110x,asic_version; ++ }; ++ ++ hisi_wifi { ++ compatible = "hisilicon,hisi_wifi"; ++ hi110x,gpio_wlan_wakeup_host = <&gpio_chip2 1 0>; ++ hi110x,gpio_host_wakeup_wlan = <&gpio_chip8 6 0>; ++ ++ hisi_wifi_firmware { ++ compatible = "hisi,wifi_firmware"; ++ firmware_type_num="1"; ++ }; ++ }; ++ ++ hisi_bfgx { ++ compatible = "hisilicon,hisi_bfgx"; ++ hi110x,gpio_bfgx_wakeup_host = <&gpio_chip9 6 0>; ++ hi110x,uart_port = "/dev/ttyAMA5"; ++ }; ++ ++ hisi_cust_cfg { ++ compatible = "hi110x,customize"; ++ ini_file_name = "/vendor/etc/cfg_hi1102a.ini"; ++ }; ++ ++ chosen { ++ bootargs = "yt8521_phy_fix=enable earlycon=pl011,0x11040000 mem=512M console=ttyAMA0,115200 clk_ignore_unused root=/dev/mtdblock2 rootfstype=yaffs2 rw mtdparts=bspnand:1M(boot),9M(kernel),32M(rootfs),1M(this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!_this_bootargs_string_is_reserved_for_bootargs_form_uboot!!!_it_must_be_longer_than_bootargs_form_uboot!!!)"; ++ ++ linux,initrd-start = <0x60000040>; ++ linux,initrd-end = <0x61000000>; ++ }; ++ clocks { ++ clk20m: clk20m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <20000000>; ++ clock-output-names = "clk20m"; ++ }; ++ }; ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ compatible = "arm,cortex-a55"; ++ device_type = "cpu"; ++ reg = <0x0 0x0>; ++ enable-method = "psci"; ++ //clock-latency = <100000>; /* From legacy driver */ ++ }; ++ ++ cpu@1 { ++ compatible = "arm,cortex-a55"; ++ device_type = "cpu"; ++ reg = <0x0 0x100>; ++ enable-method = "psci"; ++ //clock-latency = <200000>; /* From legacy driver */ ++ }; ++ ++ cpu@2 { ++ compatible = "arm,cortex-a55"; ++ device_type = "cpu"; ++ reg = <0x0 0x200>; ++ enable-method = "psci"; ++ }; ++ ++ cpu@3 { ++ compatible = "arm,cortex-a55"; ++ device_type = "cpu"; ++ reg = <0x0 0x300>; ++ enable-method = "psci"; ++ }; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ reg = <0x0 0x50000000 0x1 0xf0000000>; /* system memory base */ ++ }; ++}; ++ ++&ipcm { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&uart3 { ++ status = "okay"; ++}; ++ ++&uart4 { ++ status = "okay"; ++}; ++&uart5 { ++ status = "okay"; ++}; ++ ++&i2c_bus0 { ++ status = "okay"; ++}; ++ ++&i2c_bus1 { ++ status = "okay"; ++}; ++ ++&i2c_bus2 { ++ status = "okay"; ++}; ++ ++&i2c_bus3 { ++ status = "okay"; ++}; ++ ++&i2c_bus4 { ++ status = "okay"; ++}; ++ ++&i2c_bus5 { ++ status = "okay"; ++}; ++ ++&spi_bus0{ ++ status = "okay"; ++ /* ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ pl022,interface = <0>; ++ pl022,com-mode = <0>; ++ spi-max-frequency = <25000000>; ++ }; ++ */ ++ can0: can@0 { ++ compatible = "microchip,mcp2515"; ++ reg = <0>; ++ clocks = <&clk20m>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&gpio_chip1>; ++ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; ++ status = "okay"; ++ }; ++}; ++ ++&spi_bus1{ ++ status = "okay"; ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ pl022,interface = <0>; ++ pl022,com-mode = <0>; ++ spi-max-frequency = <25000000>; ++ }; ++ spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ reg = <1>; ++ pl022,interface = <0>; ++ pl022,com-mode = <0>; ++ spi-max-frequency = <25000000>; ++ }; ++}; ++ ++&spi_bus2{ ++ status = "okay"; ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ pl022,interface = <0>; ++ pl022,com-mode = <0>; ++ spi-max-frequency = <25000000>; ++ }; ++}; ++ ++&spi_bus3{ ++ status = "okay"; ++ ++ spidev@0 { ++ compatible = "rohm,dh2228fv"; ++ reg = <0>; ++ pl022,interface = <0>; ++ pl022,com-mode = <0>; ++ spi-max-frequency = <25000000>; ++ }; ++}; ++ ++&gpio_chip0 { ++ status = "okay"; ++}; ++ ++&gpio_chip1 { ++ status = "okay"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++}; ++ ++&gpio_chip2 { ++ status = "okay"; ++}; ++ ++&gpio_chip3 { ++ status = "okay"; ++}; ++ ++&gpio_chip4 { ++ status = "okay"; ++}; ++ ++&gpio_chip5 { ++ status = "okay"; ++}; ++ ++&gpio_chip6 { ++ status = "okay"; ++}; ++ ++&gpio_chip7 { ++ status = "okay"; ++}; ++ ++&gpio_chip8 { ++ status = "okay"; ++}; ++ ++&gpio_chip9 { ++ status = "okay"; ++}; ++ ++&gpio_chip10 { ++ status = "okay"; ++}; ++ ++&gpio_chip11 { ++ status = "okay"; ++}; ++ ++&gpio_chip12 { ++ status = "okay"; ++}; ++ ++&gpio_chip13 { ++ status = "okay"; ++}; ++ ++&gpio_chip14 { ++ status = "okay"; ++}; ++ ++&gpio_chip15 { ++ status = "okay"; ++}; ++&gpio_chip16 { ++ status = "okay"; ++}; ++&gpio_chip17 { ++ status = "okay"; ++}; ++ ++&sfc { ++ sfc { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <160000000>; ++ m25p,fast-read; ++ }; ++}; ++ ++&snfc { ++ nand { ++ compatible = "jedec,spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <160000000>; ++ }; ++}; ++ ++&nfc { ++ nand { ++ compatible = "jedec,nand"; ++ reg = <0>; ++ nand-max-frequency = <200000000>; ++ }; ++}; ++ ++&mdio { ++ ethphy: ethernet-phy@1 { ++ reg = <1>; ++ }; ++}; ++&mdio1 { ++ ethphy1: ethernet-phy@3 { ++ reg = <3>; ++ }; ++}; ++ ++&gmac { ++ phy-handle = <ðphy>; ++ phy-mode = "rgmii"; ++}; ++ ++&gmac1 { ++ phy-handle = <ðphy1>; ++ phy-mode = "rgmii"; ++}; ++ ++&pcie0 { ++ status = "okay"; ++}; ++ ++&edmacv310_0 { ++ status = "disabled"; ++}; ++ ++&adc { ++ status = "okay"; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&mmc1 { ++ status = "okay"; ++}; ++ ++&mmc2 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ status = "okay"; ++}; ++ +diff --git a/arch/arm64/boot/dts/vendor/ss928v100.dtsi b/arch/arm64/boot/dts/vendor/ss928v100.dtsi +new file mode 100644 +index 000000000000..5174c39d4923 +--- /dev/null ++++ b/arch/arm64/boot/dts/vendor/ss928v100.dtsi +@@ -0,0 +1,1107 @@ ++/* Copyright (c) 2017 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++/* reserved for arm trustedfirmware */ ++#include ++#include ++#include ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gic>; ++ ++ gic: interrupt-controller@12400000 { ++ compatible = "arm,gic-v3"; ++ #interrupt-cells = <3>; ++ #address-cells = <0>; ++ interrupt-controller; ++ reg = <0x0 0x12400000 0x0 0x10000>, /* gic distributor base */ ++ <0x0 0x12440000 0x0 0x140000>; /* gic redistributor base */ ++ }; ++ ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = ; ++ }; ++ ++ clock: clock0 { ++ compatible = "vendor,ss928v100_clock", "syscon"; ++ #clock-cells = <1>; ++ #reset-cells = <2>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x0 0x11010000 0x0 0x44a0>; ++ }; ++ ++ smmu0: smmu_npu@14040000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x0 0x14040000 0x0 0x40000>; //SMMU TCU ++ interrupts = ; ++ interrupt-names = "combined"; ++ #iommu-cells = <0x1>; ++ vendor,broken-prefetch-cmd; ++ }; ++ ++ svm0: svm_npu@14020000 { ++ compatible = "vendor,svm"; ++ crg-base = <0x11010000>; ++ crg-size = <0x10000>; ++ npu_crg_6560 = <0x6680>; ++ ranges; ++ #size-cells = <0x2>; ++ #address-cells = <0x2>; ++ ++ svm_aicore { ++ reg = <0x0 0x14020000 0x0 0x10000>; ++ iommus = <&smmu0 0x1>; ++ dma-can-stall; ++ pasid-num-bits = <16>; ++ }; ++ }; ++ ++ smmu1: smmu_pqp@0x15410000 { ++ compatible = "arm,smmu-v3"; ++ reg = <0x0 0x15410000 0x0 0x40000>; /*SMMU TCU*/ ++ ++ interrupts = ; ++ interrupt-names = "combined"; ++ #iommu-cells = <0x1>; ++ vendor,broken-prefetch-cmd; ++ }; ++ ++ svm1: svm_pqp@15400000 { ++ compatible = "vendor,svm"; ++ ranges; ++ #size-cells = <0x2>; ++ #address-cells = <0x2>; ++ crg-base = <0x11010000>; ++ crg-size = <0x10000>; ++ pqp_crg_6592 = <0x6700>; ++ svm_aicore { ++ reg = <0x0 0x15400000 0x0 0x10000>; ++ iommus = <&smmu1 0x1>; ++ dma-can-stall; ++ pasid-num-bits = <16>; ++ }; ++ ++ svm_hwts { ++ iommus = <&smmu1 0x2>; ++ dma-can-stall; ++ pasid-bits = <0x10>; ++ vendor,smmu_bypass; ++ }; ++ }; ++ ++ firmware { ++ optee { ++ compatible = "linaro,optee-tz"; ++ method = "smc"; ++ }; ++ }; ++ ++ ipcm: ipcm@11031000 { ++ compatible = "vendor,ipcm-interrupt"; ++ interrupt-parent = <&gic>; ++ interrupts = , <0 27 IRQ_TYPE_LEVEL_HIGH>; ++ reg = <0x0 0x11031000 0x0 0x1000>; ++ status = "disabled"; ++ ++ }; ++ ++ soc { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "simple-bus"; ++ device_type = "soc"; ++ ranges = <0x0 0x00000000 0x0 0xffffffff>; ++ ++ clk_3m: clk_3m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <3000000>; ++ }; ++ ++ amba { ++ compatible = "arm,amba-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ arm-timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ ; ++ clock-frequency = <24000000>; ++ always-on; ++ }; ++ ++ timer@11000000 { ++ compatible = "vendor,bsp_sp804"; ++ reg = <0x11000000 0x1000>, /* clocksource */ ++ <0x11001000 0x1000>, ++ <0x11002000 0x1000>, ++ <0x11003000 0x1000>, ++ <0x11004000 0x1000>; ++ ++ interrupts = , ++ , ++ , ++ ; ++ ++ clocks = <&clk_3m>; ++ clock-names = "apb_pclk"; ++ }; ++ ++ uart0: uart@11040000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x11040000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_UART0_CLK>; ++ clock-names = "apb_pclk"; ++ /* dmas = <&edmacv310_0 20 20>, <&edmacv310_0 21 21>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ uart1: uart@11041000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x11041000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_UART1_CLK>; ++ clock-names = "apb_pclk"; ++ /* dmas = <&edmacv310_0 22 22>, <&edmacv310_0 23 23>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ uart2: uart@11042000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x11042000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_UART2_CLK>; ++ clock-names = "apb_pclk"; ++ /* dmas = <&edmacv310_0 24 24>, <&edmacv310_0 25 25>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ uart3: uart@11043000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x11043000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_UART3_CLK>; ++ clock-names = "apb_pclk"; ++ /* dmas = <&edmacv310_0 26 26>, <&edmacv310_0 27 27>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ uart4: uart@11044000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x11044000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_UART4_CLK>; ++ clock-names = "apb_pclk"; ++ /* dmas = <&edmacv310_0 28 28>, <&edmacv310_0 29 29>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ uart5: uart@11045000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x11045000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_UART5_CLK>; ++ clock-names = "apb_pclk"; ++ /* dmas = <&edmacv310_0 30 30>, <&edmacv310_0 31 31>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ i2c_bus0: i2c@11060000 { ++ compatible = "vendor,i2c"; ++ reg = <0x11060000 0x1000>; ++ clocks = <&clock SS928V100_I2C0_CLK>; ++ clock-frequency = <100000>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ /* dmas = <&edmacv310_0 0 0>, <&edmacv310_0 1 1>; */ ++ /* dma-names = "rx","tx"; */ ++ rtc: rtc@32 { ++ compatible = "epson,rx8900"; ++ reg = <0x32>; ++ epson,vdet-disable; ++ trickle-diode-disable; ++ }; ++ gt911: gt911@5d { ++ compatible = "goodix,gt911"; ++ reg = <0x5d>; ++ interrupt-parent = <&gpio_chip8>; ++ interrupts = <7 IRQ_TYPE_EDGE_FALLING>; ++ irq-gpios = <&gpio_chip8 7 0>; ++ reset-gpios = <&gpio_chip9 1 0>; ++ status = "okay"; ++ }; ++ }; ++ ++ i2c_bus1: i2c@11061000 { ++ compatible = "vendor,i2c"; ++ reg = <0x11061000 0x1000>; ++ clocks = <&clock SS928V100_I2C1_CLK>; ++ clock-frequency = <100000>; ++ /* dmas = <&edmacv310_0 2 2>, <&edmacv310_0 3 3>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ i2c_bus2: i2c@11062000 { ++ compatible = "vendor,i2c"; ++ reg = <0x11062000 0x1000>; ++ clocks = <&clock SS928V100_I2C2_CLK>; ++ clock-frequency = <100000>; ++ /* dmas = <&edmacv310_0 4 4>, <&edmacv310_0 5 5>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ i2c_bus3: i2c@11063000 { ++ compatible = "vendor,i2c"; ++ reg = <0x11063000 0x1000>; ++ clocks = <&clock SS928V100_I2C3_CLK>; ++ clock-frequency = <100000>; ++ /* dmas = <&edmacv310_0 6 6>, <&edmacv310_0 7 7>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ i2c_bus4: i2c@11064000 { ++ compatible = "vendor,i2c"; ++ reg = <0x11064000 0x1000>; ++ clocks = <&clock SS928V100_I2C4_CLK>; ++ clock-frequency = <100000>; ++ /* dmas = <&edmacv310_0 8 8>, <&edmacv310_0 9 9>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ i2c_bus5: i2c@11065000 { ++ compatible = "vendor,i2c"; ++ reg = <0x11065000 0x1000>; ++ clocks = <&clock SS928V100_I2C5_CLK>; ++ clock-frequency = <100000>; ++ /* dmas = <&edmacv310_0 10 10>, <&edmacv310_0 11 11>; */ ++ /* dma-names = "rx","tx"; */ ++ status = "disabled"; ++ }; ++ ++ spi_bus0: spi@11070000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ arm,primecell-periphid = <0x00800022>; ++ reg = <0x11070000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_SPI0_CLK>; ++ clock-names = "apb_pclk"; ++ #address-cells = <1>; ++ spi,slave_mode = <0>; ++ #size-cells = <0>; ++ status = "disabled"; ++ num-cs = <1>; ++ /* dmas = <&edmacv310_0 12 12>, <&edmacv310_0 13 13>; */ ++ /* dma-names = "rx","tx"; */ ++ }; ++ ++ spi_bus1: spi@11071000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ arm,primecell-periphid = <0x00800022>; ++ reg = <0x11071000 0x1000>, <0x110d2100 0x4>; ++ interrupts = ; ++ clocks = <&clock SS928V100_SPI1_CLK>; ++ clock-names = "apb_pclk"; ++ #address-cells = <1>; ++ spi,slave_mode = <0>; ++ #size-cells = <0>; ++ status = "disabled"; ++ num-cs = <2>; ++ spi_cs_sb = <2>; ++ spi_cs_mask_bit = <0x4>; ++ /* dmas = <&edmacv310_0 14 14>, <&edmacv310_0 15 15>; */ ++ /* dma-names = "rx","tx"; */ ++ }; ++ ++ spi_bus2: spi@11073000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ arm,primecell-periphid = <0x00800022>; ++ reg = <0x11073000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_SPI2_CLK>; ++ clock-names = "apb_pclk"; ++ #address-cells = <1>; ++ spi,slave_mode = <0>; ++ #size-cells = <0>; ++ status = "disabled"; ++ num-cs = <1>; ++ /* dmas = <&edmacv310_0 16 16>, <&edmacv310_0 17 17>; */ ++ /* dma-names = "rx","tx"; */ ++ }; ++ ++ spi_bus3: spi@11074000 { ++ compatible = "arm,pl022", "arm,primecell"; ++ arm,primecell-periphid = <0x00800022>; ++ reg = <0x11074000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_SPI3_CLK>; ++ clock-names = "apb_pclk"; ++ spi,slave_mode = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ num-cs = <1>; ++ /* dmas = <&edmacv310_0 18 18>, <&edmacv310_0 19 19>; */ ++ /* dma-names = "rx","tx"; */ ++ }; ++ ++ gpio_chip0: gpio_chip@11090000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11090000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip1: gpio_chip@11091000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11091000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip2: gpio_chip@11092000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11092000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip3: gpio_chip@11093000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11093000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip4: gpio_chip@11094000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11094000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip5: gpio_chip@11095000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11095000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip6: gpio_chip@11096000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11096000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip7: gpio_chip@11097000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11097000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip8: gpio_chip@11098000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11098000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip9: gpio_chip@11099000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x11099000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip10: gpio_chip@1109A000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x1109A000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip11: gpio_chip@1109B000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x1109B000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip12: gpio_chip@1109C000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x1109C000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip13: gpio_chip@1109D000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x1109D000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip14: gpio_chip@1109E000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x1109E000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip15: gpio_chip@1109F000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x1109F000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip16: gpio_chip@110a0000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x110a0000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ gpio_chip17: gpio_chip@110a1000 { ++ compatible = "arm,pl061", "arm,primecell"; ++ reg = <0x110a1000 0x1000>; ++ interrupts = ; ++ #gpio-cells = <2>; ++ clocks = <&clock SS928V100_FIXED_50M>; ++ clock-names = "apb_pclk"; ++ status = "disabled"; ++ }; ++ ++ }; ++ ++ misc_ctrl: misc-controller@11024000 { ++ compatible = "vendor,miscctrl", "syscon"; ++ reg = <0x11024000 0x5000>; ++ }; ++ ++ ioconfig0: ioconfig0@10230000 { ++ compatible = "vendor,ioconfig", "syscon"; ++ reg = <0x10230000 0x10000>; ++ }; ++ ++ ioconfig1: ioconfig1@102f0000 { ++ compatible = "vendor,ioconfig", "syscon"; ++ reg = <0x102f0000 0x10000>; ++ }; ++ ++ /*FLASH DTS nodes*/ ++ fmc: flash-memory-controller@10000000 { ++ compatible = "vendor,fmc"; ++ reg = <0x10000000 0x1000>, <0x0f000000 0x1000000>; ++ reg-names = "control", "memory"; ++ clocks = <&clock SS928V100_FMC_CLK>; ++ max-dma-size = <0x2000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ sfc:spi_nor_controller { ++ compatible = "vendor,fmc-spi-nor"; ++ assigned-clocks = <&clock SS928V100_FMC_CLK>; ++ assigned-clock-rates = <24000000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ snfc:spi_nand_controller { ++ compatible = "vendor,fmc-spi-nand"; ++ assigned-clocks = <&clock SS928V100_FMC_CLK>; ++ assigned-clock-rates = <24000000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ nfc:parallel-nand-controller { ++ compatible = "vendor,fmc-nand"; ++ assigned-clocks = <&clock SS928V100_FMC_CLK>; ++ assigned-clock-rates = <200000000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ ++ /*ethernet DTS nodes*/ ++ mdio: mdio@102903c0 { ++ compatible = "vendor,gemac-mdio"; ++ reg = <0x102903c0 0x20>; ++ clocks = <&clock SS928V100_ETH_CLK>; ++ resets = <&clock 0x37cc 0>; ++ reset-names = "phy_reset"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio1: mdio@102a03c0 { ++ compatible = "vendor,gemac-mdio"; ++ reg = <0x102a03c0 0x20>; ++ clocks = <&clock SS928V100_ETH1_CLK>; ++ resets = <&clock 0x380c 0>; ++ reset-names = "phy_reset"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ gmac: ethernet@10290000 { ++ compatible = "vendor,gmac-v5"; ++ reg = <0x10290000 0x1000>,<0x1029300c 0x4>; ++ interrupts = , , ++ , ; ++ ++ clocks = <&clock SS928V100_ETH_CLK>, ++ <&clock SS928V100_ETH_MACIF_CLK>; ++ clock-names = "gmac_clk", ++ "macif_clk"; ++ ++ resets = <&clock 0x37c4 0>, ++ <&clock 0x37c0 0>; ++ reset-names = "port_reset", ++ "macif_reset"; ++ ++ mac-address = [00 00 00 00 00 00]; ++ }; ++ ++ gmac1: ethernet@102a0000 { ++ compatible = "vendor,gmac-v5"; ++ reg = <0x102a0000 0x1000>,<0x102a300c 0x4>; ++ interrupts =, , ++ , ; ++ ++ clocks = <&clock SS928V100_ETH1_CLK>, ++ <&clock SS928V100_ETH1_MACIF_CLK>; ++ clock-names = "gmac_clk", ++ "macif_clk"; ++ ++ resets = <&clock 0x3804 0>, ++ <&clock 0x3800 0>; ++ reset-names = "port_reset", ++ "macif_reset"; ++ ++ mac-address = [00 00 00 00 00 00]; ++ }; ++ ++ /*USB DTS nodes*/ ++ usb3_phy: phy3 { ++ compatible = "vendor,usb-phy"; ++ reg = <0x11010000 0x10000>, <0x11024000 0x5000>, <0x11020000 0x4000>; ++ phyid = <0>; ++ }; ++ ++ ++ xhci_0:xhci_0@0x10300000 { ++ compatible = "generic-xhci"; ++ reg = <0x10300000 0x10000>; ++ interrupts = ; ++ usb2-lpm-disable; ++ }; ++ ++ xhci_1:xhci_1@0x10320000 { ++ compatible = "generic-xhci"; ++ reg = <0x10320000 0x10000>; ++ interrupts = ; ++ usb2-lpm-disable; ++ }; ++ ++/* ++ bspdwc3:bspudc3@0x10320000 { ++ compatible = "snps,dwc3"; ++ reg = <0x10320000 0x10000>, <0x11010000 0x10000>, <0x11020000 0x4000>; ++ interrupts = ; ++ port_speed = <0>; ++ interrupt-names = "peripheral"; ++ maximum-speed = "super-speed"; ++ dr_mode = "peripheral"; ++ snps,dis_initiate_u1; ++ snps,dis_initiate_u2; ++ }; ++*/ ++ ++ /*EMMC/SD/SDIO DTS nodes*/ ++ mmc0: eMMC@0x10020000 { ++ compatible = "vendor,sdhci"; ++ reg = <0x10020000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_MMC0_CLK>; ++ clock-names = "mmc_clk"; ++ resets = <&clock 0x34c0 16>, <&clock 0x34c4 1>; ++ reset-names = "crg_reset", "dll_reset"; ++ max-frequency = <200000000>; ++ crg_regmap = <&clock>; ++ non-removable; ++ iocfg_regmap = <&ioconfig0>; ++ bus-width = <8>; ++ mmc-cmd-queue; ++ cap-mmc-highspeed; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++ cap-mmc-hw-reset; ++ no-sdio; ++ no-sd; ++ devid = <0>; ++ status = "okay"; ++ }; ++ ++ mmc1: SDIO@0x10030000 { ++ compatible = "vendor,sdhci"; ++ reg = <0x10030000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_MMC1_CLK>; ++ clock-names = "mmc_clk"; ++ resets = <&clock 0x35c0 16>, <&clock 0x35c4 1>; ++ reset-names = "crg_reset", "dll_reset"; ++ max-frequency = <200000000>; ++ crg_regmap = <&clock>; ++ iocfg_regmap = <&ioconfig1>; ++ bus-width = ; ++ cap-sd-highspeed; ++ sd-uhs-sdr104; ++ sd-uhs-sdr50; ++ full-pwr-cycle; ++ disable-wp; ++ no-emmc; ++ no-sdio; ++ devid = <1>; ++ status = "okay"; ++ }; ++ ++ mmc2: SDIO1@0x10040000 { ++ compatible = "vendor,sdhci"; ++ reg = <0x10040000 0x1000>; ++ interrupts = ; ++ clocks = <&clock SS928V100_MMC2_CLK>; ++ clock-names = "mmc_clk"; ++ resets = <&clock 0x36c0 16>, <&clock 0x36c4 1>; ++ reset-names = "crg_reset", "dll_reset"; ++ max-frequency = <200000000>; ++ crg_regmap = <&clock>; ++ iocfg_regmap = <&ioconfig1>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ sd-uhs-sdr104; ++ no-emmc; ++ no-sd; ++ devid = <2>; ++ status = "okay"; ++ }; ++ ++ pcie0: pcie@0x103d0000 { ++ device_type = "pci"; ++ compatible = "vendor,pcie"; ++ #size-cells = <2>; ++ #address-cells = <3>; ++ #interrupt-cells = <1>; ++ bus-range = <0x0 0xff>; ++ reg = <0x00 0x103d0000 0x00 0x2000>; ++ ranges = <0x02000000 0x00 0x30000000 0x30000000 0x00 0x10000000>; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0x0 0x0 0x0 0x1 &gic GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH ++ 0x0 0x0 0x0 0x2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH ++ 0x0 0x0 0x0 0x3 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH ++ 0x0 0x0 0x0 0x4 &gic GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; ++ /* msi interrupts */ ++ interrupts = ; ++ interrupt-names = "msi"; ++ ++ pcie_controller = <0>; ++ dev_mem_size = <0x10000000>; ++ dev_conf_size = <0x10000000>; ++ sys_ctrl_base = <0x11020000>; ++ pcie_dbi_base = <0x103d0000>; ++ ep_conf_base = <0x20000000>; ++ pcie_clk_rest_reg = <0x3a40>; ++ }; ++ ++ pcie_mcc: pcie_mcc@0x0 { ++ compatible = "vendor,pcie_mcc"; ++ interrupts = , /* pcie0 inta */ ++ , /* pcie0 intb */ ++ , /* pcie0 intc */ ++ , /* pcie0 intd */ ++ , /* pcie0 dma*/ ++ ; /* global soft irq */ ++ }; ++ ++ ++ edmacv310_0: edma-controller@10280000 { ++ compatible = "vendor,edmacv310"; ++ reg = <0x10280000 0x1000>, <0x102e0024 0x4>; ++ reg-names = "dmac", "dma_peri_channel_req_sel"; ++ interrupts = ; ++ clocks = <&clock SS928V100_EDMAC_CLK>, ++ <&clock SS928V100_EDMAC_AXICLK>; ++ clock-names = "apb_pclk", "axi_aclk"; ++ #clock-cells = <2>; ++ resets = <&clock 0x2A80 0>; ++ reset-names = "dma-reset"; ++ dma-requests = <32>; ++ dma-channels = <8>; ++ devid = <0>; ++ #dma-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ /*SDK DTS nodes*/ ++ sys: sys@11010000 { ++ compatible = "vendor,sys"; ++ reg = <0x11014500 0xBB00>, ++ <0x11020000 0x4000>, ++ <0x11140000 0x20000>, ++ <0X11024000 0x5000>; ++ reg-names = "crg", "sys", "ddr", "misc"; ++ }; ++ ++ mipi_rx: mipi_rx@0x173c0000 { ++ compatible = "vendor,mipi_rx"; ++ reg = <0x173c0000 0x10000>; ++ reg-names = "mipi_rx"; ++ interrupts = ; ++ interrupt-names = "mipi_rx"; ++ }; ++ ++ vi: vi@0x17400000 { ++ compatible = "vendor,vi"; ++ reg = <0x17400000 0x200000>, ++ <0x17800000 0x40000>, ++ <0x17840000 0x40000>; ++ reg-names = "vi_cap0", "vi_proc0", "vi_proc1"; ++ interrupts = , , ++ ; ++ interrupt-names = "vi_cap0", "vi_proc0", "vi_proc1"; ++ }; ++ ++ vpss: vpss@0x17900000 { ++ compatible = "vendor,vpss"; ++ reg = <0x17900000 0x10000>; ++ reg-names = "vpss0"; ++ interrupts = ; ++ interrupt-names = "vpss0"; ++ }; ++ ++ vo: vo@0x17A00000 { ++ compatible = "vendor,vo"; ++ reg = <0x17A00000 0x40000>; ++ reg-names = "vo"; ++ interrupts = ; ++ interrupt-names = "vo"; ++ }; ++ ++ gfbg: gfbg@0x17A00000 { ++ compatible = "vendor,gfbg"; ++ reg = <0x17A00000 0x40000>; ++ reg-names = "gfbg"; ++ interrupts = ; ++ interrupt-names = "gfbg"; ++ }; ++ ++ hdmi: hdmi@0x17B40000 { ++ compatible = "vendor,hdmi"; ++ reg = <0x17B40000 0x20000>,<0x17BC0000 0x10000>; ++ reg-names = "hdmi0","phy"; ++ interrupts = ,, ++ ; ++ interrupt-names = "tx_aon","tx_sec","tx_pwd"; ++ }; ++ ++ mipi_tx: mipi_tx@0x17A80000 { ++ compatible = "vendor,mipi_tx"; ++ reg = <0x17A80000 0x10000>; ++ reg-names = "mipi_tx"; ++ interrupts = ; ++ interrupt-names = "mipi_tx"; ++ }; ++ ++ vgs: vgs@0x17240000 { ++ compatible = "vendor,vgs"; ++ reg = <0x17240000 0x10000>, <0x17250000 0x10000>; ++ reg-names = "vgs0", "vgs1"; ++ interrupts = , ; ++ interrupt-names = "vgs0", "vgs1"; ++ }; ++ ++ vdh: vdh@0x17100000 { ++ compatible = "vendor,vdh"; ++ reg = <0x17100000 0x10000>; ++ reg-names = "vdh_scd"; ++ interrupts = ,, ++ ,; ++ interrupt-names = "vdh_bsp","vdh_pxp","scd","vdh_mdma"; ++ }; ++ ++ gdc: gdc@0x172c0000 { ++ compatible = "vendor,gdc"; ++ reg = <0x172c0000 0x10000>; ++ reg-names = "gdc"; ++ interrupts = ; ++ interrupt-names = "gdc"; ++ }; ++ ++ tde: tde@0x17280000 { ++ compatible = "vendor,tde"; ++ reg = <0x17280000 0x10000>; ++ reg-names = "tde"; ++ interrupts = ; ++ interrupt-names = "tde_osr_isr"; ++ }; ++ ++ jpegd: jpegd@0x17180000 { ++ compatible = "vendor,jpegd"; ++ reg = <0x17180000 0x10000>; ++ reg-names = "jpegd"; ++ interrupts = ; ++ interrupt-names = "jpegd"; ++ }; ++ ++ venc: venc@0x17140000 { ++ compatible = "vendor,vedu"; ++ reg = <0x17140000 0x10000>,<0x171c0000 0x10000>; ++ reg-names = "vedu0","jpge"; ++ interrupts = ,; ++ interrupt-names = "vedu0","jpge"; ++ }; ++ ++ npu: npu@0x14000000 { ++ compatible = "vendor,npu"; ++ reg = <0x14000000 0x100000>, ++ <0x14100000 0x200000>,<0x14300000 0x200000>, ++ <0x17150000 0x10000>,<0x11010000 0x10000>; ++ reg-names = "npu_top","npu_htws","npu_aicore", ++ "npu_peri","crg"; ++ interrupts = ,, ++ ,, ++ ,, ++ ,, ++ ; ++ interrupt-names = "hwts_dfx","hwts_normal_s","hwts_debug_s", ++ "hwts_error_s","hwts_normal_ns","hwts_debug_ns", ++ "hwts_error_ns","hwts_aicpu_s","hwts_aicpu_ns"; ++ }; ++ ++ pqp: pqp@0x15000000 { ++ compatible = "vendor,pqp"; ++ reg = <0x15000000 0x10000>; ++ reg-names = "pqp"; ++ interrupts = , ; ++ interrupt-names = "pqp_ns","pqp_s"; ++ }; ++ ++ svp_npu: svp_npu@0x15000000 { ++ compatible = "vendor,svp_npu"; ++ reg = <0x15000000 0x10000>; ++ reg-names = "svp_npu"; ++ interrupts = , ; ++ interrupt-names = "svp_npu_ns","svp_npu_s"; ++ }; ++ ++ ive: ive@0x17000000 { ++ compatible = "vendor,ive"; ++ reg = <0x17000000 0x10000>; ++ reg-names = "ive"; ++ interrupts = ; ++ interrupt-names = "ive"; ++ }; ++ ++ mau: mau@0x17030000 { ++ compatible = "vendor,mau"; ++ reg = <0x17030000 0x10000>; ++ reg-names = "mau0"; ++ interrupts = ; ++ interrupt-names = "mau0"; ++ }; ++ ++ dpu_rect: dpu_rect@0x17030000 { ++ compatible = "vendor,dpu_rect"; ++ reg = <0x17030000 0x10000>; ++ reg-names = "dpu_rect"; ++ interrupts = ; ++ interrupt-names = "rect"; ++ }; ++ ++ dpu_match: dpu_match@0x17030000 { ++ compatible = "vendor,dpu_match"; ++ reg = <0x17030000 0x10000>; ++ reg-names = "dpu_match"; ++ interrupts = ; ++ interrupt-names = "match"; ++ }; ++ ++ dsp: dsp@0x16110000 { ++ compatible = "vendor,dsp"; ++ reg = <0x16110000 0x20000>,<0x16310000 0x20000>; ++ reg-names = "dsp0","dsp1"; ++ }; ++ ++ avs: avs@0x17930000 { ++ compatible = "vendor,avs"; ++ reg = <0x17930000 0x10000>; ++ reg-names = "avs"; ++ interrupts = ; ++ interrupt-names = "avs"; ++ }; ++ ++ aiao: aiao@17c00000 { ++ compatible = "vendor,aiao"; ++ reg = <0x17c00000 0x10000>,<0x17c40000 0x10000>; ++ reg-names = "aiao","acodec"; ++ interrupts = ; ++ interrupt-names = "AIO"; ++ }; ++ ++ cipher: cipher@0x10100000 { ++ compatible = "vendor,cipher"; ++ reg = <0x10100000 0x10000>; ++ reg-names = "cipher"; ++ interrupts = ,, ++ ,; ++ interrupt-names = "nsec_spacc","sec_spacc","nsec_pke","sec_pke"; ++ }; ++ ++ klad: klad@0x10110000 { ++ compatible = "vendor,klad"; ++ reg = <0x10110000 0x1000>; ++ reg-names = "klad"; ++ interrupts = ,, ++ ,; ++ interrupt-names = "nsec_rkp","sec_rkp","nsec_klad","sec_klad"; ++ }; ++ ++ otp: otp@0x10120000 { ++ compatible = "vendor,otp"; ++ reg = <0x10120000 0x1000>; ++ reg-names = "otp"; ++ }; ++ ++ adc: adc@0x11080000 { ++ compatible = "vendor,lsadc"; ++ reg = <0x11080000 0x1000>; ++ reg-names = "lsadc"; ++ interrupts = <0 72 4>; ++ interrupt-names = "lsadc"; ++ clocks = <&clock SS928V100_LSADC_CLK>; ++ clock-names = "lsadc-clk"; ++ resets = <&clock 0x46c0 0>; ++ reset-names = "lsadc-crg"; ++ status = "disabled"; ++ }; ++ ++ ir: ir@0x110F0000 { ++ compatible = "vendor,ir"; ++ reg = <0x110F0000 0x10000>; ++ reg-names = "ir"; ++ interrupts = ; ++ interrupt-names = "ir"; ++ }; ++ ++ wdg: wdg@0x11030000 { ++ compatible = "vendor,wdg"; ++ reg = <0x11030000 0x1000>; ++ reg-names = "wdg0"; ++ interrupts = ; ++ interrupt-names = "wdg"; ++ }; ++ ++ pwm: pwm@0x1102D000 { ++ compatible = "vendor,pwm"; ++ reg = <0x110B0000 0x1000>, <0x1102D000 0x1000>; ++ reg-names = "pwm0", "pwm1"; ++ clocks = <&clock SS928V100_PWM0_CLK>, <&clock SS928V100_PWM1_CLK>; ++ clock-names = "pwm0", "pwm1"; ++ resets = <&clock 0x4588 0>, <&clock 0x4590 0>; ++ reset-names = "pwm0", "pwm1"; ++ status = "disabled"; ++ }; ++ ++ }; ++}; ++ +diff --git a/arch/arm64/configs/hieulerpi1_defconfig b/arch/arm64/configs/hieulerpi1_defconfig +new file mode 100644 +index 000000000000..481993463b25 +--- /dev/null ++++ b/arch/arm64/configs/hieulerpi1_defconfig +@@ -0,0 +1,5630 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm64 5.10.0 Kernel Configuration ++# ++CONFIG_CC_VERSION_TEXT="aarch64-openeuler-linux-gnu-gcc (crosstool-NG 1.26.0) 12.3.1" ++CONFIG_CC_IS_GCC=y ++CONFIG_GCC_VERSION=120301 ++CONFIG_LD_VERSION=241000000 ++CONFIG_CLANG_VERSION=0 ++CONFIG_LLD_VERSION=0 ++CONFIG_CC_HAS_ASM_GOTO=y ++CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y ++CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y ++CONFIG_CC_HAS_ASM_INLINE=y ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_TABLE_SORT=y ++CONFIG_THREAD_INFO_IN_TASK=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="-openeuler" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_BUILD_SALT="" ++CONFIG_DEFAULT_INIT="" ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_WATCH_QUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y ++CONFIG_GENERIC_IRQ_MIGRATION=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_GENERIC_IRQ_IPI=y ++CONFIG_GENERIC_MSI_IRQ=y ++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y ++CONFIG_IRQ_MSI_IOMMU=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++# CONFIG_GENERIC_IRQ_DEBUGFS is not set ++# end of IRQ subsystem ++ ++CONFIG_GENERIC_IRQ_MULTI_HANDLER=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_HZ_PERIODIC=y ++# CONFIG_NO_HZ_IDLE is not set ++# CONFIG_NO_HZ_FULL is not set ++# CONFIG_NO_HZ is not set ++CONFIG_HIGH_RES_TIMERS=y ++# CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE is not set ++# end of Timers subsystem ++ ++CONFIG_PREEMPT_NONE=y ++# CONFIG_PREEMPT_VOLUNTARY is not set ++# CONFIG_PREEMPT is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++CONFIG_PSI=y ++# CONFIG_PSI_DEFAULT_DISABLED is not set ++# end of CPU/Task time and stats accounting ++ ++CONFIG_CPU_ISOLATION=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++CONFIG_TREE_SRCU=y ++CONFIG_TASKS_RCU_GENERIC=y ++CONFIG_TASKS_TRACE_RCU=y ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_NEED_SEGCBLIST=y ++# end of RCU Subsystem ++ ++# CONFIG_IKCONFIG is not set ++# CONFIG_IKHEADERS is not set ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++ ++# ++# Scheduler features ++# ++# end of Scheduler features ++ ++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y ++CONFIG_CC_HAS_INT128=y ++CONFIG_ARCH_SUPPORTS_INT128=y ++CONFIG_CGROUPS=y ++CONFIG_PAGE_COUNTER=y ++CONFIG_MEMCG=y ++CONFIG_MEMCG_KMEM=y ++CONFIG_MEMCG_MEMFS_INFO=y ++CONFIG_BLK_CGROUP=y ++CONFIG_CGROUP_WRITEBACK=y ++CONFIG_CGROUP_V1_WRITEBACK=y ++CONFIG_CGROUP_SCHED=y ++CONFIG_QOS_SCHED=y ++CONFIG_QOS_SCHED_MULTILEVEL=y ++CONFIG_QOS_SCHED_SMT_EXPELLER=y ++CONFIG_QOS_SCHED_PRIO_LB=y ++CONFIG_FAIR_GROUP_SCHED=y ++CONFIG_CFS_BANDWIDTH=y ++# CONFIG_RT_GROUP_SCHED is not set ++# CONFIG_QOS_SCHED_DYNAMIC_AFFINITY is not set ++CONFIG_CGROUP_PIDS=y ++CONFIG_CGROUP_RDMA=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CPUSETS=y ++CONFIG_PROC_PID_CPUSET=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++# CONFIG_CGROUP_PERF is not set ++CONFIG_CGROUP_BPF=y ++# CONFIG_CGROUP_DEBUG is not set ++CONFIG_SOCK_CGROUP_DATA=y ++CONFIG_CGROUP_FILES=y ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_TIME_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++CONFIG_SCHED_STEAL=y ++# CONFIG_CHECKPOINT_RESTORE is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++CONFIG_RELAY=y ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_BOOT_CONFIG is not set ++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_LD_ORPHAN_WARN=y ++CONFIG_SYSCTL=y ++CONFIG_SYSCTL_EXCEPTION_TRACE=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_FHANDLE is not set ++CONFIG_POSIX_TIMERS=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_FUTEX_PI=y ++CONFIG_HAVE_FUTEX_CMPXCHG=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_IO_URING=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_MEMBARRIER=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y ++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set ++# CONFIG_BPF_PRELOAD is not set ++CONFIG_USERFAULTFD=y ++CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y ++# CONFIG_KCMP is not set ++CONFIG_RSEQ=y ++# CONFIG_DEBUG_RSEQ is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++# CONFIG_PC104 is not set ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++# end of Kernel Performance Events And Counters ++ ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_SLUB_MEMCG_SYSFS_ON is not set ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++CONFIG_SLAB_MERGE_DEFAULT=y ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SLAB_FREELIST_HARDENED is not set ++# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++CONFIG_SYSTEM_DATA_VERIFICATION=y ++# CONFIG_PROFILING is not set ++CONFIG_KABI_RESERVE=y ++CONFIG_KABI_SIZE_ALIGN_CHECKS=y ++# end of General setup ++ ++CONFIG_ARM64=y ++CONFIG_64BIT=y ++CONFIG_MMU=y ++CONFIG_ARM64_PAGE_SHIFT=12 ++CONFIG_ARM64_CONT_PTE_SHIFT=4 ++CONFIG_ARM64_CONT_PMD_SHIFT=4 ++CONFIG_ARCH_MMAP_RND_BITS_MIN=18 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=24 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CSUM=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_ZONE_DMA32=y ++CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y ++CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y ++CONFIG_SMP=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_PGTABLE_LEVELS=3 ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_ARCH_PROC_KCORE_TEXT=y ++CONFIG_ARCH_HAS_CPU_RELAX=y ++ ++# ++# Platform selection ++# ++# CONFIG_ARCH_ACTIONS is not set ++# CONFIG_ARCH_AGILEX is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_BCM2835 is not set ++# CONFIG_ARCH_BCM_IPROC is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_BITMAIN is not set ++# CONFIG_ARCH_BRCMSTB is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SPARX5 is not set ++# CONFIG_ARCH_K3 is not set ++# CONFIG_ARCH_LAYERSCAPE is not set ++# CONFIG_ARCH_LG1K is not set ++# CONFIG_ARCH_HISI is not set ++CONFIG_ARCH_BSP=y ++# CONFIG_ARCH_SS528V100 is not set ++# CONFIG_ARCH_SS625V100 is not set ++# CONFIG_ARCH_SS919V100 is not set ++# CONFIG_ARCH_SS015V100 is not set ++CONFIG_ARCH_SS928V100=y ++# CONFIG_ARCH_SS927V100 is not set ++# CONFIG_ARCH_KEEMBAY is not set ++# CONFIG_ARCH_MEDIATEK is not set ++# CONFIG_ARCH_MESON is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_PHYTIUM is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALTEK is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_S32 is not set ++# CONFIG_ARCH_SEATTLE is not set ++# CONFIG_ARCH_STRATIX10 is not set ++# CONFIG_ARCH_SYNQUACER is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_SPRD is not set ++# CONFIG_ARCH_THUNDER is not set ++# CONFIG_ARCH_THUNDER2 is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_VISCONTI is not set ++# CONFIG_ARCH_XGENE is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQMP is not set ++# end of Platform selection ++ ++CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y ++ ++# ++# Enable Livepatch ++# ++# end of Enable Livepatch ++ ++# ++# Kernel Features ++# ++ ++# ++# ARM errata workarounds via the alternatives framework ++# ++CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y ++CONFIG_ARM64_ERRATUM_826319=y ++CONFIG_ARM64_ERRATUM_827319=y ++CONFIG_ARM64_ERRATUM_824069=y ++CONFIG_ARM64_ERRATUM_819472=y ++CONFIG_ARM64_ERRATUM_832075=y ++CONFIG_ARM64_ERRATUM_843419=y ++CONFIG_ARM64_ERRATUM_1024718=y ++CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y ++CONFIG_ARM64_ERRATUM_1165522=y ++CONFIG_ARM64_ERRATUM_1319367=y ++CONFIG_ARM64_ERRATUM_1530923=y ++CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y ++CONFIG_ARM64_ERRATUM_1286807=y ++CONFIG_ARM64_ERRATUM_1463225=y ++CONFIG_ARM64_ERRATUM_1542419=y ++CONFIG_ARM64_ERRATUM_1508412=y ++CONFIG_CAVIUM_ERRATUM_22375=y ++CONFIG_CAVIUM_ERRATUM_23154=y ++CONFIG_CAVIUM_ERRATUM_27456=y ++CONFIG_CAVIUM_ERRATUM_30115=y ++CONFIG_CAVIUM_TX2_ERRATUM_219=y ++CONFIG_FUJITSU_ERRATUM_010001=y ++CONFIG_HISILICON_ERRATUM_161600802=y ++# CONFIG_HISILICON_ERRATUM_1980005 is not set ++CONFIG_HISILICON_ERRATUM_162100801=y ++CONFIG_HISILICON_ERRATUM_162100125=y ++CONFIG_QCOM_FALKOR_ERRATUM_1003=y ++CONFIG_QCOM_FALKOR_ERRATUM_1009=y ++CONFIG_QCOM_QDF2400_ERRATUM_0065=y ++CONFIG_QCOM_FALKOR_ERRATUM_E1041=y ++CONFIG_SOCIONEXT_SYNQUACER_PREITS=y ++CONFIG_HISILICON_ERRATUM_HIP08_RU_PREFETCH=y ++# CONFIG_HISILICON_HIP08_RU_PREFETCH_DEFAULT_OFF is not set ++# end of ARM errata workarounds via the alternatives framework ++ ++CONFIG_ARM64_4K_PAGES=y ++# CONFIG_ARM64_16K_PAGES is not set ++# CONFIG_ARM64_64K_PAGES is not set ++CONFIG_ARM64_VA_BITS_39=y ++# CONFIG_ARM64_VA_BITS_48 is not set ++CONFIG_ARM64_VA_BITS=39 ++CONFIG_ARM64_PA_BITS_48=y ++CONFIG_ARM64_PA_BITS=48 ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_CPU_LITTLE_ENDIAN=y ++CONFIG_SCHED_MC=y ++CONFIG_SCHED_CLUSTER=y ++CONFIG_SCHED_SMT=y ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM64_BOOTPARAM_HOTPLUG_CPU0 is not set ++# CONFIG_NUMA is not set ++CONFIG_HZ_100=y ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_ARCH_SPARSEMEM_DEFAULT=y ++CONFIG_ARCH_SELECT_MEMORY_MODEL=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_SYS_SUPPORTS_HUGETLBFS=y ++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y ++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y ++CONFIG_ARCH_LLC_128_LINE_SIZE=y ++CONFIG_ARCH_HAS_FILTER_PGPROT=y ++CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y ++CONFIG_CC_HAVE_SHADOW_CALL_STACK=y ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_KEXEC is not set ++# CONFIG_KEXEC_FILE is not set ++# CONFIG_CRASH_DUMP is not set ++# CONFIG_XEN is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_UNMAP_KERNEL_AT_EL0=y ++CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY=y ++CONFIG_RODATA_FULL_DEFAULT_ENABLED=y ++# CONFIG_ARM64_PMEM_LEGACY is not set ++# CONFIG_ARM64_SW_TTBR0_PAN is not set ++CONFIG_ARM64_TAGGED_ADDR_ABI=y ++# CONFIG_AARCH32_EL0 is not set ++ ++# ++# ARMv8.1 architectural features ++# ++CONFIG_ARM64_HW_AFDBM=y ++CONFIG_ARM64_PAN=y ++CONFIG_AS_HAS_LSE_ATOMICS=y ++CONFIG_ARM64_VHE=y ++# end of ARMv8.1 architectural features ++ ++# ++# ARMv8.2 architectural features ++# ++# CONFIG_ARM64_PMEM is not set ++CONFIG_ARM64_RAS_EXTN=y ++CONFIG_ARM64_CNP=y ++# end of ARMv8.2 architectural features ++ ++# ++# ARMv8.3 architectural features ++# ++CONFIG_ARM64_PTR_AUTH=y ++CONFIG_CC_HAS_BRANCH_PROT_PAC_RET=y ++CONFIG_CC_HAS_SIGN_RETURN_ADDRESS=y ++CONFIG_AS_HAS_PAC=y ++CONFIG_AS_HAS_CFI_NEGATE_RA_STATE=y ++# end of ARMv8.3 architectural features ++ ++# ++# ARMv8.4 architectural features ++# ++CONFIG_ARM64_AMU_EXTN=y ++CONFIG_AS_HAS_ARMV8_4=y ++CONFIG_ARM64_TLB_RANGE=y ++# end of ARMv8.4 architectural features ++ ++# ++# ARMv8.5 architectural features ++# ++# CONFIG_ARM64_BTI is not set ++CONFIG_CC_HAS_BRANCH_PROT_PAC_RET_BTI=y ++CONFIG_ARM64_E0PD=y ++CONFIG_ARCH_RANDOM=y ++CONFIG_ARM64_AS_HAS_MTE=y ++# CONFIG_ARM64_MTE is not set ++# end of ARMv8.5 architectural features ++ ++# ++# ARMv8.6 architectural features ++# ++CONFIG_ARM64_TWED=y ++# end of ARMv8.6 architectural features ++ ++# ++# ARMv8.7 architectural features ++# ++CONFIG_ARM64_EPAN=y ++# end of ARMv8.7 architectural features ++ ++CONFIG_ARM64_SVE=y ++CONFIG_ARM64_MODULE_PLTS=y ++# CONFIG_ARM64_PSEUDO_NMI is not set ++CONFIG_RELOCATABLE=y ++# CONFIG_RANDOMIZE_BASE is not set ++CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y ++CONFIG_STACKPROTECTOR_PER_TASK=y ++# CONFIG_ASCEND_FEATURES is not set ++# end of Kernel Features ++ ++# ++# Boot options ++# ++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox" ++# CONFIG_CMDLINE_FORCE is not set ++# CONFIG_EFI is not set ++# end of Boot options ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++# CONFIG_PM_WAKELOCKS is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++# CONFIG_ENERGY_MODEL is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# end of Power management options ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# end of CPU Idle ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++CONFIG_CPUFREQ_DT=y ++CONFIG_CPUFREQ_DT_PLATDEV=y ++# end of CPU Frequency scaling ++# end of CPU Power Management ++ ++# ++# Firmware Drivers ++# ++# CONFIG_ARM_SCMI_PROTOCOL is not set ++# CONFIG_ARM_SDE_INTERFACE is not set ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++# CONFIG_GOOGLE_FIRMWARE is not set ++CONFIG_ARM_PSCI_FW=y ++CONFIG_HAVE_ARM_SMCCC=y ++CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y ++CONFIG_ARM_SMCCC_SOC_ID=y ++ ++# ++# Tegra firmware driver ++# ++# end of Tegra firmware driver ++# end of Firmware Drivers ++ ++# CONFIG_VIRTUALIZATION is not set ++# CONFIG_ARM64_CRYPTO is not set ++ ++# ++# General architecture-dependent options ++# ++# CONFIG_KPROBES is not set ++# CONFIG_JUMP_LABEL is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y ++CONFIG_ARCH_HAS_KEEPINITRD=y ++CONFIG_ARCH_HAS_SET_MEMORY=y ++CONFIG_ARCH_HAS_SET_DIRECT_MAP=y ++CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y ++CONFIG_HAVE_ASM_MODVERSIONS=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_RSEQ=y ++CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y ++CONFIG_MMU_GATHER_TABLE_FREE=y ++CONFIG_MMU_GATHER_RCU_TABLE_FREE=y ++CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y ++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y ++CONFIG_HAVE_CMPXCHG_LOCAL=y ++CONFIG_HAVE_CMPXCHG_DOUBLE=y ++CONFIG_HAVE_ARCH_SECCOMP=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++# CONFIG_SECCOMP is not set ++CONFIG_HAVE_ARCH_STACKLEAK=y ++CONFIG_HAVE_STACKPROTECTOR=y ++CONFIG_STACKPROTECTOR=y ++CONFIG_STACKPROTECTOR_STRONG=y ++CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOVE_PUD=y ++CONFIG_HAVE_MOVE_PMD=y ++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y ++CONFIG_HAVE_ARCH_HUGE_VMAP=y ++CONFIG_HAVE_ARCH_HUGE_VMALLOC=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_ARCH_MMAP_RND_BITS=18 ++CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_COMPAT_32BIT_TIME=y ++CONFIG_HAVE_ARCH_VMAP_STACK=y ++CONFIG_VMAP_STACK=y ++CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y ++CONFIG_RANDOMIZE_KSTACK_OFFSET=y ++# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set ++CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y ++CONFIG_STRICT_KERNEL_RWX=y ++CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y ++CONFIG_STRICT_MODULE_RWX=y ++CONFIG_HAVE_ARCH_COMPILER_H=y ++CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y ++# CONFIG_LOCK_EVENT_COUNTS is not set ++CONFIG_ARCH_HAS_RELR=y ++CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++# end of GCOV-based kernel profiling ++ ++CONFIG_HAVE_GCC_PLUGINS=y ++CONFIG_GCC_PLUGINS=y ++# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set ++# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set ++# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set ++# end of General architecture-dependent options ++ ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_MODULES_TREE_LOOKUP=y ++CONFIG_BLOCK=y ++CONFIG_BLK_SCSI_REQUEST=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_DEV_ZONED is not set ++# CONFIG_BLK_DEV_THROTTLING is not set ++CONFIG_BLK_CMDLINE_PARSER=y ++# CONFIG_BLK_WBT is not set ++# CONFIG_BLK_CGROUP_IOLATENCY is not set ++# CONFIG_BLK_CGROUP_IOCOST is not set ++CONFIG_BLK_DEBUG_FS=y ++# CONFIG_BLK_SED_OPAL is not set ++# CONFIG_BLK_INLINE_ENCRYPTION is not set ++# CONFIG_BLK_DEV_DUMPINFO is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_AIX_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_CMDLINE_PARTITION=y ++# end of Partition Types ++ ++CONFIG_BLK_MQ_PCI=y ++CONFIG_BLK_PM=y ++ ++# ++# IO Schedulers ++# ++CONFIG_MQ_IOSCHED_DEADLINE=y ++CONFIG_MQ_IOSCHED_KYBER=y ++# CONFIG_IOSCHED_BFQ is not set ++# end of IO Schedulers ++ ++CONFIG_ASN1=y ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_READ_LOCK=y ++CONFIG_ARCH_INLINE_READ_LOCK_BH=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_READ_UNLOCK=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_WRITE_LOCK=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_SPIN_TRYLOCK=y ++CONFIG_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK=y ++CONFIG_INLINE_SPIN_LOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_READ_LOCK=y ++CONFIG_INLINE_READ_LOCK_BH=y ++CONFIG_INLINE_READ_LOCK_IRQ=y ++CONFIG_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_INLINE_READ_UNLOCK=y ++CONFIG_INLINE_READ_UNLOCK_BH=y ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_WRITE_LOCK=y ++CONFIG_INLINE_WRITE_LOCK_BH=y ++CONFIG_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_INLINE_WRITE_UNLOCK=y ++CONFIG_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y ++CONFIG_QUEUED_SPINLOCKS=y ++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y ++CONFIG_QUEUED_RWLOCKS=y ++CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y ++CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y ++CONFIG_FREEZER=y ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_STATE=y ++CONFIG_ARCH_HAVE_ELF_PROT=y ++CONFIG_ARCH_USE_GNU_PROPERTY=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++# end of Executable file formats ++ ++# ++# Memory Management options ++# ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_SPARSEMEM_EXTREME=y ++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y ++CONFIG_SPARSEMEM_VMEMMAP=y ++CONFIG_HAVE_FAST_GUP=y ++CONFIG_HOLES_IN_ZONE=y ++CONFIG_ARCH_KEEP_MEMBLOCK=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_MEMORY_HOTPLUG is not set ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++# CONFIG_PAGE_REPORTING is not set ++CONFIG_MIGRATION=y ++# CONFIG_HUGE_VMALLOC_DEFAULT_ENABLED is not set ++CONFIG_CONTIG_ALLOC=y ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_BOUNCE=y ++CONFIG_MMU_NOTIFIER=y ++CONFIG_KSM=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y ++# CONFIG_MEMORY_FAILURE is not set ++# CONFIG_TRANSPARENT_HUGEPAGE is not set ++# CONFIG_CLEANCACHE is not set ++CONFIG_MEMCG_QOS=y ++# CONFIG_ETMEM is not set ++# CONFIG_USERSWAP is not set ++# CONFIG_PAGE_CACHE_LIMIT is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_ARCH_HAS_PTE_DEVMAP=y ++CONFIG_FRAME_VECTOR=y ++# CONFIG_PERCPU_STATS is not set ++# CONFIG_GUP_BENCHMARK is not set ++CONFIG_ARCH_HAS_PTE_SPECIAL=y ++# CONFIG_PIN_MEMORY is not set ++# CONFIG_CLEAR_FREELIST_PAGE is not set ++# CONFIG_EXTEND_HUGEPAGE_MAPPING is not set ++ ++# ++# Data Access Monitoring ++# ++# CONFIG_DAMON is not set ++# end of Data Access Monitoring ++# end of Memory Management options ++ ++CONFIG_NET=y ++CONFIG_NET_INGRESS=y ++CONFIG_SKB_EXTENSIONS=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++CONFIG_UNIX_SCM=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_TLS is not set ++CONFIG_XFRM=y ++CONFIG_XFRM_ALGO=m ++CONFIG_XFRM_USER=m ++# CONFIG_XFRM_INTERFACE is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_XDP_SOCKETS is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++CONFIG_NET_IP_TUNNEL=m ++# CONFIG_IP_MROUTE is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++CONFIG_NET_UDP_TUNNEL=m ++# CONFIG_NET_FOU is not set ++# CONFIG_NET_FOU_IP_TUNNELS is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++CONFIG_INET_TABLE_PERTURB_ORDER=16 ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_INET_RAW_DIAG is not set ++# CONFIG_INET_DIAG_DESTROY is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=y ++CONFIG_IPV6_ROUTER_PREF=y ++# CONFIG_IPV6_ROUTE_INFO is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++# CONFIG_IPV6_ILA is not set ++# CONFIG_IPV6_VTI is not set ++CONFIG_IPV6_SIT=m ++# CONFIG_IPV6_SIT_6RD is not set ++CONFIG_IPV6_NDISC_NODETYPE=y ++# CONFIG_IPV6_TUNNEL is not set ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_IPV6_SEG6_LWTUNNEL is not set ++# CONFIG_IPV6_SEG6_HMAC is not set ++# CONFIG_IPV6_RPL_LWTUNNEL is not set ++# CONFIG_MPTCP is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++CONFIG_NETFILTER=y ++CONFIG_NETFILTER_ADVANCED=y ++CONFIG_BRIDGE_NETFILTER=m ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_INGRESS=y ++CONFIG_NETFILTER_NETLINK=m ++CONFIG_NETFILTER_FAMILY_BRIDGE=y ++# CONFIG_NETFILTER_NETLINK_ACCT is not set ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++CONFIG_NETFILTER_NETLINK_LOG=m ++# CONFIG_NETFILTER_NETLINK_OSF is not set ++CONFIG_NF_CONNTRACK=m ++# CONFIG_NF_LOG_NETDEV is not set ++CONFIG_NF_CONNTRACK_MARK=y ++# CONFIG_NF_CONNTRACK_ZONES is not set ++# CONFIG_NF_CONNTRACK_PROCFS is not set ++CONFIG_NF_CONNTRACK_EVENTS=y ++# CONFIG_NF_CONNTRACK_TIMEOUT is not set ++# CONFIG_NF_CONNTRACK_TIMESTAMP is not set ++# CONFIG_NF_CONNTRACK_LABELS is not set ++CONFIG_NF_CT_PROTO_DCCP=y ++CONFIG_NF_CT_PROTO_SCTP=y ++CONFIG_NF_CT_PROTO_UDPLITE=y ++# CONFIG_NF_CONNTRACK_AMANDA is not set ++CONFIG_NF_CONNTRACK_FTP=m ++# CONFIG_NF_CONNTRACK_H323 is not set ++# CONFIG_NF_CONNTRACK_IRC is not set ++# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set ++# CONFIG_NF_CONNTRACK_SNMP is not set ++# CONFIG_NF_CONNTRACK_PPTP is not set ++# CONFIG_NF_CONNTRACK_SANE is not set ++# CONFIG_NF_CONNTRACK_SIP is not set ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_NETLINK_GLUE_CT=y ++CONFIG_NF_NAT=m ++CONFIG_NF_NAT_FTP=m ++CONFIG_NF_NAT_TFTP=m ++CONFIG_NF_NAT_MASQUERADE=y ++CONFIG_NF_TABLES=m ++# CONFIG_NF_TABLES_INET is not set ++# CONFIG_NF_TABLES_NETDEV is not set ++# CONFIG_NFT_NUMGEN is not set ++# CONFIG_NFT_CT is not set ++CONFIG_NFT_COUNTER=m ++# CONFIG_NFT_CONNLIMIT is not set ++# CONFIG_NFT_LOG is not set ++# CONFIG_NFT_LIMIT is not set ++# CONFIG_NFT_MASQ is not set ++# CONFIG_NFT_REDIR is not set ++CONFIG_NFT_NAT=m ++# CONFIG_NFT_TUNNEL is not set ++# CONFIG_NFT_OBJREF is not set ++# CONFIG_NFT_QUOTA is not set ++# CONFIG_NFT_REJECT is not set ++CONFIG_NFT_COMPAT=m ++# CONFIG_NFT_HASH is not set ++# CONFIG_NFT_XFRM is not set ++# CONFIG_NFT_SOCKET is not set ++# CONFIG_NFT_OSF is not set ++# CONFIG_NFT_TPROXY is not set ++# CONFIG_NFT_SYNPROXY is not set ++# CONFIG_NF_FLOW_TABLE is not set ++CONFIG_NETFILTER_XTABLES=m ++ ++# ++# Xtables combined modules ++# ++CONFIG_NETFILTER_XT_MARK=m ++CONFIG_NETFILTER_XT_CONNMARK=m ++ ++# ++# Xtables targets ++# ++# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set ++# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set ++# CONFIG_NETFILTER_XT_TARGET_HMARK is not set ++# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set ++# CONFIG_NETFILTER_XT_TARGET_LOG is not set ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_NAT=m ++# CONFIG_NETFILTER_XT_TARGET_NETMAP is not set ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set ++# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set ++# CONFIG_NETFILTER_XT_TARGET_REDIRECT is not set ++CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m ++# CONFIG_NETFILTER_XT_TARGET_TEE is not set ++# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set ++ ++# ++# Xtables matches ++# ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++# CONFIG_NETFILTER_XT_MATCH_BPF is not set ++# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set ++# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set ++# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set ++# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set ++# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++# CONFIG_NETFILTER_XT_MATCH_CPU is not set ++# CONFIG_NETFILTER_XT_MATCH_DCCP is not set ++# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set ++# CONFIG_NETFILTER_XT_MATCH_DSCP is not set ++# CONFIG_NETFILTER_XT_MATCH_ECN is not set ++# CONFIG_NETFILTER_XT_MATCH_ESP is not set ++# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set ++# CONFIG_NETFILTER_XT_MATCH_HELPER is not set ++# CONFIG_NETFILTER_XT_MATCH_HL is not set ++# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set ++# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++# CONFIG_NETFILTER_XT_MATCH_L2TP is not set ++# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++# CONFIG_NETFILTER_XT_MATCH_MAC is not set ++# CONFIG_NETFILTER_XT_MATCH_MARK is not set ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set ++# CONFIG_NETFILTER_XT_MATCH_OSF is not set ++# CONFIG_NETFILTER_XT_MATCH_OWNER is not set ++# CONFIG_NETFILTER_XT_MATCH_POLICY is not set ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set ++# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set ++# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set ++# CONFIG_NETFILTER_XT_MATCH_REALM is not set ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++# CONFIG_NETFILTER_XT_MATCH_SCTP is not set ++# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set ++# CONFIG_NETFILTER_XT_MATCH_STATE is not set ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++# CONFIG_NETFILTER_XT_MATCH_STRING is not set ++# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set ++# CONFIG_NETFILTER_XT_MATCH_TIME is not set ++# CONFIG_NETFILTER_XT_MATCH_U32 is not set ++# end of Core Netfilter Configuration ++ ++# CONFIG_IP_SET is not set ++CONFIG_IP_VS=m ++# CONFIG_IP_VS_IPV6 is not set ++# CONFIG_IP_VS_DEBUG is not set ++CONFIG_IP_VS_TAB_BITS=12 ++ ++# ++# IPVS transport protocol load balancing support ++# ++# CONFIG_IP_VS_PROTO_TCP is not set ++# CONFIG_IP_VS_PROTO_UDP is not set ++# CONFIG_IP_VS_PROTO_ESP is not set ++# CONFIG_IP_VS_PROTO_AH is not set ++# CONFIG_IP_VS_PROTO_SCTP is not set ++ ++# ++# IPVS scheduler ++# ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++# CONFIG_IP_VS_LC is not set ++# CONFIG_IP_VS_WLC is not set ++# CONFIG_IP_VS_FO is not set ++# CONFIG_IP_VS_OVF is not set ++# CONFIG_IP_VS_LBLC is not set ++# CONFIG_IP_VS_LBLCR is not set ++# CONFIG_IP_VS_DH is not set ++CONFIG_IP_VS_SH=m ++# CONFIG_IP_VS_MH is not set ++# CONFIG_IP_VS_SED is not set ++# CONFIG_IP_VS_NQ is not set ++ ++# ++# IPVS SH scheduler ++# ++CONFIG_IP_VS_SH_TAB_BITS=8 ++ ++# ++# IPVS MH scheduler ++# ++CONFIG_IP_VS_MH_TAB_INDEX=12 ++ ++# ++# IPVS application helper ++# ++# CONFIG_IP_VS_NFCT is not set ++ ++# ++# IP: Netfilter Configuration ++# ++CONFIG_NF_DEFRAG_IPV4=m ++# CONFIG_NF_SOCKET_IPV4 is not set ++# CONFIG_NF_TPROXY_IPV4 is not set ++CONFIG_NF_TABLES_IPV4=y ++# CONFIG_NFT_DUP_IPV4 is not set ++# CONFIG_NFT_FIB_IPV4 is not set ++# CONFIG_NF_TABLES_ARP is not set ++# CONFIG_NF_DUP_IPV4 is not set ++# CONFIG_NF_LOG_ARP is not set ++# CONFIG_NF_LOG_IPV4 is not set ++# CONFIG_NF_REJECT_IPV4 is not set ++CONFIG_IP_NF_IPTABLES=m ++# CONFIG_IP_NF_MATCH_AH is not set ++# CONFIG_IP_NF_MATCH_ECN is not set ++# CONFIG_IP_NF_MATCH_TTL is not set ++# CONFIG_IP_NF_FILTER is not set ++# CONFIG_IP_NF_TARGET_SYNPROXY is not set ++CONFIG_IP_NF_NAT=m ++# CONFIG_IP_NF_TARGET_MASQUERADE is not set ++# CONFIG_IP_NF_TARGET_NETMAP is not set ++# CONFIG_IP_NF_TARGET_REDIRECT is not set ++# CONFIG_IP_NF_MANGLE is not set ++# CONFIG_IP_NF_RAW is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++# end of IP: Netfilter Configuration ++ ++# ++# IPv6: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV6 is not set ++# CONFIG_NF_TPROXY_IPV6 is not set ++CONFIG_NF_TABLES_IPV6=y ++# CONFIG_NFT_DUP_IPV6 is not set ++# CONFIG_NFT_FIB_IPV6 is not set ++# CONFIG_NF_DUP_IPV6 is not set ++# CONFIG_NF_REJECT_IPV6 is not set ++# CONFIG_NF_LOG_IPV6 is not set ++# CONFIG_IP6_NF_IPTABLES is not set ++# end of IPv6: Netfilter Configuration ++ ++CONFIG_NF_DEFRAG_IPV6=m ++# CONFIG_NF_TABLES_BRIDGE is not set ++# CONFIG_NF_CONNTRACK_BRIDGE is not set ++# CONFIG_BRIDGE_NF_EBTABLES is not set ++# CONFIG_BPFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++CONFIG_STP=m ++CONFIG_BRIDGE=m ++CONFIG_BRIDGE_IGMP_SNOOPING=y ++# CONFIG_BRIDGE_MRP is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++CONFIG_LLC=m ++# CONFIG_LLC2 is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_6LOWPAN is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++CONFIG_NETLINK_DIAG=m ++# CONFIG_MPLS is not set ++# CONFIG_NET_NSH is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++CONFIG_NET_L3_MASTER_DEV=y ++# CONFIG_QRTR is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++# CONFIG_BPF_STREAM_PARSER is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# end of Network testing ++# end of Networking options ++ ++# CONFIG_HAMRADIO is not set ++CONFIG_CAN=y ++CONFIG_CAN_RAW=y ++CONFIG_CAN_BCM=y ++CONFIG_CAN_GW=y ++# CONFIG_CAN_J1939 is not set ++# CONFIG_CAN_ISOTP is not set ++ ++# ++# CAN Device Drivers ++# ++# CONFIG_CAN_VCAN is not set ++# CONFIG_CAN_VXCAN is not set ++# CONFIG_CAN_SLCAN is not set ++CONFIG_CAN_DEV=y ++CONFIG_CAN_CALC_BITTIMING=y ++# CONFIG_CAN_FLEXCAN is not set ++# CONFIG_CAN_GRCAN is not set ++# CONFIG_CAN_KVASER_PCIEFD is not set ++# CONFIG_CAN_XILINXCAN is not set ++# CONFIG_CAN_C_CAN is not set ++# CONFIG_CAN_CC770 is not set ++# CONFIG_CAN_IFI_CANFD is not set ++# CONFIG_CAN_M_CAN is not set ++# CONFIG_CAN_PEAK_PCIEFD is not set ++# CONFIG_CAN_SJA1000 is not set ++# CONFIG_CAN_SOFTING is not set ++ ++# ++# CAN SPI interfaces ++# ++# CONFIG_CAN_HI311X is not set ++CONFIG_CAN_MCP251X=y ++# CONFIG_CAN_MCP251XFD is not set ++# end of CAN SPI interfaces ++ ++# ++# CAN USB interfaces ++# ++# CONFIG_CAN_8DEV_USB is not set ++# CONFIG_CAN_EMS_USB is not set ++# CONFIG_CAN_ESD_USB2 is not set ++# CONFIG_CAN_GS_USB is not set ++# CONFIG_CAN_KVASER_USB is not set ++# CONFIG_CAN_MCBA_USB is not set ++# CONFIG_CAN_PEAK_USB is not set ++# CONFIG_CAN_UCAN is not set ++# end of CAN USB interfaces ++ ++# CONFIG_CAN_DEBUG_DEVICES is not set ++# end of CAN Device Drivers ++ ++CONFIG_BT=y ++CONFIG_BT_BREDR=y ++# CONFIG_BT_RFCOMM is not set ++# CONFIG_BT_BNEP is not set ++# CONFIG_BT_HIDP is not set ++# CONFIG_BT_HS is not set ++CONFIG_BT_LE=y ++# CONFIG_BT_MSFTEXT is not set ++CONFIG_BT_DEBUGFS=y ++# CONFIG_BT_SELFTEST is not set ++# CONFIG_BT_FEATURE_DEBUG is not set ++ ++# ++# Bluetooth device drivers ++# ++# CONFIG_BT_HCIBTUSB is not set ++# CONFIG_BT_HCIBTSDIO is not set ++# CONFIG_BT_HCIUART is not set ++# CONFIG_BT_HCIBCM203X is not set ++# CONFIG_BT_HCIBPA10X is not set ++# CONFIG_BT_HCIBFUSB is not set ++# CONFIG_BT_HCIVHCI is not set ++# CONFIG_BT_MRVL is not set ++# CONFIG_BT_MTKSDIO is not set ++# end of Bluetooth device drivers ++ ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++CONFIG_WIRELESS=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_CFG80211=y ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y ++CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++CONFIG_CFG80211_CRDA_SUPPORT=y ++CONFIG_CFG80211_WEXT=y ++CONFIG_MAC80211=y ++CONFIG_MAC80211_HAS_RC=y ++CONFIG_MAC80211_RC_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y ++CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" ++# CONFIG_MAC80211_MESH is not set ++# CONFIG_MAC80211_DEBUGFS is not set ++# CONFIG_MAC80211_MESSAGE_TRACING is not set ++# CONFIG_MAC80211_DEBUG_MENU is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_PSAMPLE is not set ++# CONFIG_NET_IFE is not set ++# CONFIG_LWTUNNEL is not set ++CONFIG_DST_CACHE=y ++CONFIG_GRO_CELLS=y ++# CONFIG_FAILOVER is not set ++CONFIG_ETHTOOL_NETLINK=y ++CONFIG_HAVE_EBPF_JIT=y ++ ++# ++# Device Drivers ++# ++CONFIG_ARM_AMBA=y ++CONFIG_HAVE_PCI=y ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++CONFIG_PCI_DOMAINS_GENERIC=y ++CONFIG_PCI_SYSCALL=y ++CONFIG_PCIEPORTBUS=y ++# CONFIG_PCIEAER is not set ++# CONFIG_PCIEASPM is not set ++CONFIG_PCIE_PME=y ++# CONFIG_PCIE_PTM is not set ++CONFIG_PCI_MSI=y ++CONFIG_PCI_MSI_IRQ_DOMAIN=y ++CONFIG_PCI_QUIRKS=y ++# CONFIG_PCI_DEBUG is not set ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++# CONFIG_PCI_PRI is not set ++# CONFIG_PCI_PASID is not set ++# CONFIG_PCIE_BUS_TUNE_OFF is not set ++CONFIG_PCIE_BUS_DEFAULT=y ++# CONFIG_PCIE_BUS_SAFE is not set ++# CONFIG_PCIE_BUS_PERFORMANCE is not set ++# CONFIG_PCIE_BUS_PEER2PEER is not set ++# CONFIG_HOTPLUG_PCI is not set ++ ++# ++# PCI controller drivers ++# ++# CONFIG_PCI_FTPCI100 is not set ++# CONFIG_PCI_HOST_GENERIC is not set ++# CONFIG_PCIE_XILINX is not set ++# CONFIG_PCI_XGENE is not set ++# CONFIG_PCIE_ALTERA is not set ++# CONFIG_PCI_HOST_THUNDER_PEM is not set ++# CONFIG_PCI_HOST_THUNDER_ECAM is not set ++ ++# ++# DesignWare PCI Core Support ++# ++# CONFIG_PCIE_DW_PLAT_HOST is not set ++# CONFIG_PCI_HISI is not set ++# CONFIG_PCIE_KIRIN is not set ++# CONFIG_PCI_MESON is not set ++# CONFIG_PCIE_AL is not set ++# end of DesignWare PCI Core Support ++ ++# ++# Mobiveil PCIe Core Support ++# ++# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set ++# end of Mobiveil PCIe Core Support ++ ++# ++# Cadence PCIe controllers support ++# ++# CONFIG_PCIE_CADENCE_PLAT_HOST is not set ++# CONFIG_PCI_J721E_HOST is not set ++# end of Cadence PCIe controllers support ++# end of PCI controller drivers ++ ++# ++# PCI Endpoint ++# ++# CONFIG_PCI_ENDPOINT is not set ++# end of PCI Endpoint ++ ++# ++# PCI switch controller drivers ++# ++# CONFIG_PCI_SW_SWITCHTEC is not set ++# end of PCI switch controller drivers ++ ++# CONFIG_PCCARD is not set ++# CONFIG_RAPIDIO is not set ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++ ++# ++# Firmware loader ++# ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER is not set ++# CONFIG_FW_LOADER_COMPRESS is not set ++CONFIG_FW_CACHE=y ++# end of Firmware loader ++ ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set ++CONFIG_GENERIC_CPU_AUTOPROBE=y ++CONFIG_GENERIC_CPU_VULNERABILITIES=y ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_MMIO=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_DMA_FENCE_TRACE is not set ++CONFIG_GENERIC_ARCH_TOPOLOGY=y ++# end of Generic Driver Options ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_MOXTET is not set ++# CONFIG_SIMPLE_PM_BUS is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_MHI_BUS is not set ++# end of Bus devices ++ ++# CONFIG_CONNECTOR is not set ++# CONFIG_GNSS is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_KOBJ=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set ++# CONFIG_BLK_DEV_UMEM is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SKD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=65536 ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++# CONFIG_BLK_DEV_RSXX is not set ++ ++# ++# NVME Support ++# ++# CONFIG_BLK_DEV_NVME is not set ++# CONFIG_NVME_FC is not set ++# CONFIG_NVME_TCP is not set ++# CONFIG_NVME_TARGET is not set ++# end of NVME Support ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_PHANTOM is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_PCI_ENDPOINT_TEST is not set ++# CONFIG_XILINX_SDFEC is not set ++# CONFIG_PVPANIC is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++# CONFIG_EEPROM_IDT_89HPESX is not set ++# CONFIG_EEPROM_EE1004 is not set ++# end of EEPROM support ++ ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# end of Texas Instruments shared transport line discipline ++ ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++# CONFIG_ALTERA_STAPL is not set ++# CONFIG_GENWQE is not set ++# CONFIG_ECHO is not set ++# CONFIG_MISC_ALCOR_PCI is not set ++# CONFIG_MISC_RTSX_PCI is not set ++# CONFIG_MISC_RTSX_USB is not set ++# CONFIG_HABANA_AI is not set ++# CONFIG_UACCE is not set ++# end of Misc devices ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# end of SCSI Transports ++ ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_CXGB3_ISCSI is not set ++# CONFIG_SCSI_CXGB4_ISCSI is not set ++# CONFIG_SCSI_BNX2_ISCSI is not set ++# CONFIG_BE2ISCSI is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_HPSA is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_3W_SAS is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_MVUMI is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_SCSI_ESAS2R is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_3SNIC_SSSRAID is not set ++# CONFIG_SCSI_MPT3SAS is not set ++# CONFIG_SCSI_MPT2SAS is not set ++# CONFIG_SCSI_SMARTPQI is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_SCSI_MYRB is not set ++# CONFIG_SCSI_MYRS is not set ++# CONFIG_SCSI_SNIC is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_FDOMAIN_PCI is not set ++# CONFIG_SCSI_GDTH is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_AM53C974 is not set ++# CONFIG_SCSI_WD719X is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_PMCRAID is not set ++# CONFIG_SCSI_PM8001 is not set ++# CONFIG_SCSI_DH is not set ++# end of SCSI device support ++ ++CONFIG_HAVE_PATA_PLATFORM=y ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_FIREWIRE_NOSY is not set ++# end of IEEE 1394 (FireWire) support ++ ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++CONFIG_NET_CORE=y ++# CONFIG_BONDING is not set ++CONFIG_DUMMY=m ++# CONFIG_WIREGUARD is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NET_TEAM is not set ++# CONFIG_MACVLAN is not set ++CONFIG_IPVLAN_L3S=y ++CONFIG_IPVLAN=m ++# CONFIG_IPVTAP is not set ++CONFIG_VXLAN=m ++# CONFIG_GENEVE is not set ++# CONFIG_BAREUDP is not set ++# CONFIG_GTP is not set ++# CONFIG_MACSEC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_TUN is not set ++# CONFIG_TUN_VNET_CROSS_LE is not set ++CONFIG_VETH=m ++# CONFIG_NLMON is not set ++# CONFIG_ARCNET is not set ++ ++# ++# Distributed Switch Architecture drivers ++# ++# end of Distributed Switch Architecture drivers ++ ++CONFIG_ETHERNET=y ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_3SNIC is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++# CONFIG_NET_VENDOR_AGERE is not set ++# CONFIG_NET_VENDOR_ALACRITECH is not set ++# CONFIG_NET_VENDOR_ALTEON is not set ++# CONFIG_ALTERA_TSE is not set ++# CONFIG_NET_VENDOR_AMAZON is not set ++# CONFIG_NET_VENDOR_AMD is not set ++# CONFIG_NET_VENDOR_AQUANTIA is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_VENDOR_ATHEROS is not set ++# CONFIG_NET_VENDOR_AURORA is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_BROCADE is not set ++# CONFIG_NET_VENDOR_CADENCE is not set ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++# CONFIG_NET_VENDOR_CORTINA is not set ++CONFIG_NET_VENDOR_VENDOR=y ++CONFIG_ETH_GMAC=y ++# CONFIG_GMAC_DDR_64BIT is not set ++CONFIG_GMAC_DESC_4WORD=y ++CONFIG_GMAC_RXCSUM=y ++CONFIG_RX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF ++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF ++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16 ++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32 ++# CONFIG_DNET is not set ++# CONFIG_NET_VENDOR_DEC is not set ++# CONFIG_NET_VENDOR_DLINK is not set ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++CONFIG_NET_VENDOR_GOOGLE=y ++# CONFIG_GVE is not set ++# CONFIG_NET_VENDOR_HISILICON is not set ++# CONFIG_NET_VENDOR_HUAWEI is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++CONFIG_NET_VENDOR_NETSWIFT=y ++# CONFIG_NGBE is not set ++# CONFIG_TXGBE is not set ++# CONFIG_JME is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MELLANOX is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_MICROSEMI is not set ++# CONFIG_NET_VENDOR_MYRI is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_NETERION is not set ++# CONFIG_NET_VENDOR_NETRONOME is not set ++# CONFIG_NET_VENDOR_NI is not set ++# CONFIG_NET_VENDOR_NVIDIA is not set ++# CONFIG_NET_VENDOR_OKI is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_PACKET_ENGINES is not set ++CONFIG_NET_VENDOR_PENSANDO=y ++# CONFIG_IONIC is not set ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++# CONFIG_NET_VENDOR_RDC is not set ++# CONFIG_NET_VENDOR_REALTEK is not set ++# CONFIG_NET_VENDOR_RENESAS is not set ++# CONFIG_NET_VENDOR_ROCKER is not set ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SOLARFLARE is not set ++# CONFIG_NET_VENDOR_SILAN is not set ++# CONFIG_NET_VENDOR_SIS is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_SOCIONEXT is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++# CONFIG_NET_VENDOR_SUN is not set ++# CONFIG_NET_VENDOR_SYNOPSYS is not set ++# CONFIG_NET_VENDOR_TEHUTI is not set ++# CONFIG_NET_VENDOR_TI is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++CONFIG_NET_VENDOR_XILINX=y ++# CONFIG_XILINX_AXI_EMAC is not set ++# CONFIG_XILINX_LL_TEMAC is not set ++# CONFIG_NET_VENDOR_NEBULA_MATRIX is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++CONFIG_FIXED_PHY=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_ADIN_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AX88796B_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM54140_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM84881_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_CORTINA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MARVELL_10G_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROCHIP_T1_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_RENESAS_PHY is not set ++# CONFIG_ROCKCHIP_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_DP83822_PHY is not set ++# CONFIG_DP83TC811_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++# CONFIG_DP83869_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++CONFIG_SS928V100_PHY=y ++CONFIG_MDIO_DEVICE=y ++CONFIG_MDIO_BUS=y ++CONFIG_OF_MDIO=y ++CONFIG_MDIO_DEVRES=y ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++# CONFIG_MDIO_MVUSB is not set ++# CONFIG_MDIO_MSCC_MIIM is not set ++# CONFIG_MDIO_OCTEON is not set ++# CONFIG_MDIO_IPQ4019 is not set ++# CONFIG_MDIO_IPQ8064 is not set ++# CONFIG_MDIO_THUNDER is not set ++ ++# ++# MDIO Multiplexers ++# ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++ ++# ++# PCS device drivers ++# ++# CONFIG_PCS_XPCS is not set ++# end of PCS device drivers ++ ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++CONFIG_USB_NET_DRIVERS=y ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++CONFIG_USB_RTL8152=y ++# CONFIG_USB_LAN78XX is not set ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=y ++CONFIG_USB_NET_AX88179_178A=y ++CONFIG_USB_NET_CDCETHER=y ++# CONFIG_USB_NET_CDC_EEM is not set ++CONFIG_USB_NET_CDC_NCM=y ++# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set ++# CONFIG_USB_NET_CDC_MBIM is not set ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SR9700 is not set ++# CONFIG_USB_NET_SR9800 is not set ++# CONFIG_USB_NET_SMSC75XX is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++# CONFIG_USB_NET_GL620A is not set ++CONFIG_USB_NET_NET1080=y ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++CONFIG_USB_NET_RNDIS_HOST=y ++CONFIG_USB_NET_CDC_SUBSET_ENABLE=y ++CONFIG_USB_NET_CDC_SUBSET=y ++# CONFIG_USB_ALI_M5632 is not set ++# CONFIG_USB_AN2720 is not set ++CONFIG_USB_BELKIN=y ++CONFIG_USB_ARMLINUX=y ++# CONFIG_USB_EPSON2888 is not set ++# CONFIG_USB_KC2190 is not set ++CONFIG_USB_NET_ZAURUS=y ++# CONFIG_USB_NET_CX82310_ETH is not set ++# CONFIG_USB_NET_KALMIA is not set ++CONFIG_USB_NET_QMI_WWAN=y ++# CONFIG_USB_NET_INT51X1 is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_USB_SIERRA_NET is not set ++# CONFIG_USB_VL600 is not set ++# CONFIG_USB_NET_CH9200 is not set ++# CONFIG_USB_NET_AQC111 is not set ++CONFIG_WLAN=y ++# CONFIG_WIRELESS_WDS is not set ++# CONFIG_WLAN_VENDOR_ADMTEK is not set ++# CONFIG_WLAN_VENDOR_ATH is not set ++# CONFIG_WLAN_VENDOR_ATMEL is not set ++# CONFIG_WLAN_VENDOR_BROADCOM is not set ++# CONFIG_WLAN_VENDOR_CISCO is not set ++# CONFIG_WLAN_VENDOR_INTEL is not set ++# CONFIG_WLAN_VENDOR_INTERSIL is not set ++# CONFIG_WLAN_VENDOR_MARVELL is not set ++# CONFIG_WLAN_VENDOR_MEDIATEK is not set ++CONFIG_WLAN_VENDOR_MICROCHIP=y ++# CONFIG_WILC1000_SDIO is not set ++# CONFIG_WILC1000_SPI is not set ++# CONFIG_WLAN_VENDOR_RALINK is not set ++# CONFIG_WLAN_VENDOR_REALTEK is not set ++# CONFIG_WLAN_VENDOR_RSI is not set ++# CONFIG_WLAN_VENDOR_ST is not set ++# CONFIG_WLAN_VENDOR_TI is not set ++# CONFIG_WLAN_VENDOR_ZYDAS is not set ++# CONFIG_WLAN_VENDOR_QUANTENNA is not set ++# CONFIG_MAC80211_HWSIM is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_VIRT_WIFI is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_VMXNET3 is not set ++# CONFIG_NETDEVSIM is not set ++# CONFIG_NET_FAILOVER is not set ++# CONFIG_NET_LOCALIP_LST is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++CONFIG_INPUT_JOYDEV=y ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADC is not set ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_QT1050 is not set ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_DLINK_DIR685 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++CONFIG_MOUSE_PS2_SMBUS=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++CONFIG_INPUT_JOYSTICK=y ++# CONFIG_JOYSTICK_ANALOG is not set ++# CONFIG_JOYSTICK_A3D is not set ++# CONFIG_JOYSTICK_ADC is not set ++# CONFIG_JOYSTICK_ADI is not set ++# CONFIG_JOYSTICK_COBRA is not set ++# CONFIG_JOYSTICK_GF2K is not set ++# CONFIG_JOYSTICK_GRIP is not set ++# CONFIG_JOYSTICK_GRIP_MP is not set ++# CONFIG_JOYSTICK_GUILLEMOT is not set ++# CONFIG_JOYSTICK_INTERACT is not set ++# CONFIG_JOYSTICK_SIDEWINDER is not set ++# CONFIG_JOYSTICK_TMDC is not set ++# CONFIG_JOYSTICK_IFORCE is not set ++# CONFIG_JOYSTICK_WARRIOR is not set ++# CONFIG_JOYSTICK_MAGELLAN is not set ++# CONFIG_JOYSTICK_SPACEORB is not set ++# CONFIG_JOYSTICK_SPACEBALL is not set ++# CONFIG_JOYSTICK_STINGER is not set ++# CONFIG_JOYSTICK_TWIDJOY is not set ++# CONFIG_JOYSTICK_ZHENHUA is not set ++# CONFIG_JOYSTICK_AS5011 is not set ++# CONFIG_JOYSTICK_JOYDUMP is not set ++# CONFIG_JOYSTICK_XPAD is not set ++# CONFIG_JOYSTICK_PSXPAD_SPI is not set ++# CONFIG_JOYSTICK_PXRC is not set ++# CONFIG_JOYSTICK_FSIA6B is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_ADC is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_BU21029 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_EXC3000 is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_HIDEEP is not set ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_S6SY761 is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SUR40 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZET6223 is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++# CONFIG_TOUCHSCREEN_IQS5XX is not set ++# CONFIG_TOUCHSCREEN_ZINITIX is not set ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_AD714X is not set ++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set ++# CONFIG_INPUT_BMA150 is not set ++# CONFIG_INPUT_E3X0_BUTTON is not set ++# CONFIG_INPUT_MMA8450 is not set ++# CONFIG_INPUT_GPIO_BEEPER is not set ++# CONFIG_INPUT_GPIO_DECODER is not set ++# CONFIG_INPUT_GPIO_VIBRA is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_KXTJ9 is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++# CONFIG_INPUT_REGULATOR_HAPTIC is not set ++CONFIG_INPUT_UINPUT=y ++# CONFIG_INPUT_PCF8574 is not set ++# CONFIG_INPUT_PWM_BEEPER is not set ++# CONFIG_INPUT_PWM_VIBRA is not set ++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set ++# CONFIG_INPUT_ADXL34X is not set ++# CONFIG_INPUT_IQS269A is not set ++# CONFIG_INPUT_CMA3000 is not set ++# CONFIG_INPUT_DRV260X_HAPTICS is not set ++# CONFIG_INPUT_DRV2665_HAPTICS is not set ++# CONFIG_INPUT_DRV2667_HAPTICS is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_AMBAKMI is not set ++# CONFIG_SERIO_PCIPS2 is not set ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_SERIO_GPIO_PS2 is not set ++# CONFIG_USERIO is not set ++CONFIG_GAMEPORT=y ++# CONFIG_GAMEPORT_NS558 is not set ++# CONFIG_GAMEPORT_L4 is not set ++# CONFIG_GAMEPORT_EMU10K1 is not set ++# CONFIG_GAMEPORT_FM801 is not set ++# end of Hardware I/O ports ++# end of Input device support ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_VT_CONSOLE_SLEEP=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_LDISC_AUTOLOAD=y ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_EARLYCON=y ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_AMBA_PL010 is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_SIFIVE is not set ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_RP2 is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_FSL_LINFLEXUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_SPRD is not set ++# end of Serial drivers ++ ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_NOZOMI is not set ++# CONFIG_NULL_TTY is not set ++# CONFIG_TRACE_SINK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_SERIAL_DEV_BUS is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_VIRTIO_CONSOLE is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_APPLICOM is not set ++CONFIG_DEVMEM=y ++# CONFIG_RAW_DRIVER is not set ++CONFIG_DEVPORT=y ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++# CONFIG_RANDOM_TRUST_CPU is not set ++# CONFIG_RANDOM_TRUST_BOOTLOADER is not set ++# end of Character devices ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_GPMUX is not set ++# CONFIG_I2C_MUX_LTC4306 is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_PINCTRL is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_DEMUX_PINCTRL is not set ++# CONFIG_I2C_MUX_MLXCPLD is not set ++# end of Multiplexer I2C Chip support ++ ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++# end of I2C Algorithms ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_NVIDIA_GPU is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CADENCE is not set ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_DESIGNWARE_PCI is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++CONFIG_I2C_BSP=y ++# CONFIG_I2C_HISI is not set ++# CONFIG_I2C_NOMADIK is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_THUNDERX is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++CONFIG_DMA_MSG_MIN_LEN=5 ++CONFIG_DMA_MSG_MAX_LEN=4090 ++# end of I2C Hardware Bus support ++ ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# end of I2C support ++ ++# CONFIG_I3C is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++# CONFIG_SPI_MEM is not set ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_CADENCE_QUADSPI is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_NXP_FLEXSPI is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++CONFIG_SPI_PL022=y ++# CONFIG_SPI_PXA2XX is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_SIFIVE is not set ++# CONFIG_SPI_MXIC is not set ++# CONFIG_SPI_THUNDERX is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++# CONFIG_SPI_AMD is not set ++ ++# ++# SPI Multiplexer support ++# ++# CONFIG_SPI_MUX is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPI_SLAVE is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++# CONFIG_PPS is not set ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++# CONFIG_PTP_HISI is not set ++# end of PTP clock support ++ ++CONFIG_PINCTRL=y ++CONFIG_GENERIC_PINCTRL_GROUPS=y ++CONFIG_PINMUX=y ++CONFIG_GENERIC_PINMUX_FUNCTIONS=y ++CONFIG_PINCONF=y ++CONFIG_GENERIC_PINCONF=y ++# CONFIG_DEBUG_PINCTRL is not set ++# CONFIG_PINCTRL_MCP23S08 is not set ++CONFIG_PINCTRL_SINGLE=y ++# CONFIG_PINCTRL_SX150X is not set ++# CONFIG_PINCTRL_STMFX is not set ++# CONFIG_PINCTRL_OCELOT is not set ++ ++# ++# Renesas pinctrl drivers ++# ++# end of Renesas pinctrl drivers ++ ++CONFIG_GPIOLIB=y ++CONFIG_GPIOLIB_FASTPATH_LIMIT=512 ++CONFIG_OF_GPIO=y ++CONFIG_GPIOLIB_IRQCHIP=y ++CONFIG_DEBUG_GPIO=y ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_CDEV=y ++CONFIG_GPIO_CDEV_V1=y ++CONFIG_GPIO_GENERIC=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_CADENCE is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_FTGPIO010 is not set ++CONFIG_GPIO_GENERIC_PLATFORM=y ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_HLWD is not set ++# CONFIG_GPIO_LOGICVC is not set ++# CONFIG_GPIO_MB86S7X is not set ++CONFIG_GPIO_PL061=y ++# CONFIG_GPIO_SAMA5D2_PIOBU is not set ++# CONFIG_GPIO_SIFIVE is not set ++# CONFIG_GPIO_SYSCON is not set ++# CONFIG_GPIO_XGENE is not set ++# CONFIG_GPIO_XILINX is not set ++# CONFIG_GPIO_AMD_FCH is not set ++# end of Memory mapped GPIO drivers ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_GW_PLD is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCA9570 is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++# end of I2C GPIO expanders ++ ++# ++# MFD GPIO expanders ++# ++# end of MFD GPIO expanders ++ ++# ++# PCI GPIO expanders ++# ++# CONFIG_GPIO_BT8XX is not set ++# CONFIG_GPIO_PCI_IDIO_16 is not set ++# CONFIG_GPIO_PCIE_IDIO_24 is not set ++# CONFIG_GPIO_RDC321X is not set ++# end of PCI GPIO expanders ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX3191X is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++# CONFIG_GPIO_XRA1403 is not set ++# end of SPI GPIO expanders ++ ++# ++# USB GPIO expanders ++# ++# end of USB GPIO expanders ++ ++# CONFIG_GPIO_AGGREGATOR is not set ++# CONFIG_GPIO_MOCKUP is not set ++# CONFIG_W1 is not set ++CONFIG_POWER_RESET=y ++# CONFIG_POWER_RESET_BRCMSTB is not set ++# CONFIG_POWER_RESET_GPIO is not set ++# CONFIG_POWER_RESET_GPIO_RESTART is not set ++# CONFIG_POWER_RESET_LTC2952 is not set ++# CONFIG_POWER_RESET_RESTART is not set ++# CONFIG_POWER_RESET_XGENE is not set ++# CONFIG_POWER_RESET_SYSCON is not set ++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set ++# CONFIG_SYSCON_REBOOT_MODE is not set ++# CONFIG_NVMEM_REBOOT_MODE is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_GENERIC_ADC_BATTERY is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_CHARGER_ADP5061 is not set ++# CONFIG_BATTERY_CW2015 is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_CHARGER_SBS is not set ++# CONFIG_MANAGER_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_MANAGER is not set ++# CONFIG_CHARGER_LT3651 is not set ++# CONFIG_CHARGER_DETECTOR_MAX14656 is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ2515X is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_BQ25980 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_BATTERY_RT5033 is not set ++# CONFIG_CHARGER_RT9455 is not set ++# CONFIG_CHARGER_UCS1002 is not set ++# CONFIG_CHARGER_BD99954 is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_BD9571MWV is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_MADERA is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_GATEWORKS_GSC is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_MP2629 is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_LPC_ICH is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_INTEL_PMT is not set ++# CONFIG_MFD_IQS62X is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77650 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6360 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_CPCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++CONFIG_MFD_SYSCON=y ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_TI_LMU is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TI_LP87565 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TQMX86 is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_LOCHNAGAR is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_MFD_ROHM_BD718XX is not set ++# CONFIG_MFD_ROHM_BD70528 is not set ++# CONFIG_MFD_ROHM_BD71828 is not set ++# CONFIG_MFD_STPMIC1 is not set ++# CONFIG_MFD_STMFX is not set ++# CONFIG_MFD_INTEL_M10_BMC is not set ++# end of Multifunction device drivers ++ ++CONFIG_REGULATOR=y ++# CONFIG_REGULATOR_DEBUG is not set ++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set ++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set ++# CONFIG_REGULATOR_88PG86X is not set ++# CONFIG_REGULATOR_ACT8865 is not set ++# CONFIG_REGULATOR_AD5398 is not set ++# CONFIG_REGULATOR_DA9210 is not set ++# CONFIG_REGULATOR_DA9211 is not set ++# CONFIG_REGULATOR_FAN53555 is not set ++# CONFIG_REGULATOR_FAN53880 is not set ++# CONFIG_REGULATOR_GPIO is not set ++# CONFIG_REGULATOR_ISL9305 is not set ++# CONFIG_REGULATOR_ISL6271A is not set ++# CONFIG_REGULATOR_LP3971 is not set ++# CONFIG_REGULATOR_LP3972 is not set ++# CONFIG_REGULATOR_LP872X is not set ++# CONFIG_REGULATOR_LP8755 is not set ++# CONFIG_REGULATOR_LTC3589 is not set ++# CONFIG_REGULATOR_LTC3676 is not set ++# CONFIG_REGULATOR_MAX1586 is not set ++# CONFIG_REGULATOR_MAX8649 is not set ++# CONFIG_REGULATOR_MAX8660 is not set ++# CONFIG_REGULATOR_MAX8952 is not set ++# CONFIG_REGULATOR_MAX77826 is not set ++# CONFIG_REGULATOR_MCP16502 is not set ++# CONFIG_REGULATOR_MP5416 is not set ++# CONFIG_REGULATOR_MP8859 is not set ++# CONFIG_REGULATOR_MP886X is not set ++# CONFIG_REGULATOR_MPQ7920 is not set ++# CONFIG_REGULATOR_MT6311 is not set ++# CONFIG_REGULATOR_PCA9450 is not set ++# CONFIG_REGULATOR_PFUZE100 is not set ++# CONFIG_REGULATOR_PV88060 is not set ++# CONFIG_REGULATOR_PV88080 is not set ++# CONFIG_REGULATOR_PV88090 is not set ++# CONFIG_REGULATOR_PWM is not set ++# CONFIG_REGULATOR_RT4801 is not set ++# CONFIG_REGULATOR_RTMV20 is not set ++# CONFIG_REGULATOR_SLG51000 is not set ++# CONFIG_REGULATOR_SY8106A is not set ++# CONFIG_REGULATOR_SY8824X is not set ++# CONFIG_REGULATOR_SY8827N is not set ++# CONFIG_REGULATOR_TPS51632 is not set ++# CONFIG_REGULATOR_TPS62360 is not set ++# CONFIG_REGULATOR_TPS65023 is not set ++# CONFIG_REGULATOR_TPS6507X is not set ++# CONFIG_REGULATOR_TPS65132 is not set ++# CONFIG_REGULATOR_TPS6524X is not set ++# CONFIG_REGULATOR_VCTRL is not set ++# CONFIG_RC_CORE is not set ++# CONFIG_MEDIA_CEC_SUPPORT is not set ++CONFIG_MEDIA_SUPPORT=y ++# CONFIG_MEDIA_SUPPORT_FILTER is not set ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Media device types ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_SDR_SUPPORT=y ++CONFIG_MEDIA_PLATFORM_SUPPORT=y ++CONFIG_MEDIA_TEST_SUPPORT=y ++# end of Media device types ++ ++# ++# Media core support ++# ++CONFIG_VIDEO_DEV=y ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_DVB_CORE=y ++# end of Media core support ++ ++# ++# Video4Linux options ++# ++CONFIG_VIDEO_V4L2=y ++CONFIG_VIDEO_V4L2_I2C=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# end of Video4Linux options ++ ++# ++# Digital TV options ++# ++# CONFIG_DVB_MMAP is not set ++CONFIG_DVB_NET=y ++CONFIG_DVB_MAX_ADAPTERS=16 ++CONFIG_DVB_DYNAMIC_MINORS=y ++# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set ++# CONFIG_DVB_ULE_DEBUG is not set ++# end of Digital TV options ++ ++# ++# Media drivers ++# ++CONFIG_MEDIA_USB_SUPPORT=y ++ ++# ++# Webcam devices ++# ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=m ++# CONFIG_USB_M5602 is not set ++# CONFIG_USB_STV06XX is not set ++# CONFIG_USB_GL860 is not set ++# CONFIG_USB_GSPCA_BENQ is not set ++# CONFIG_USB_GSPCA_CONEX is not set ++# CONFIG_USB_GSPCA_CPIA1 is not set ++# CONFIG_USB_GSPCA_DTCS033 is not set ++# CONFIG_USB_GSPCA_ETOMS is not set ++# CONFIG_USB_GSPCA_FINEPIX is not set ++# CONFIG_USB_GSPCA_JEILINJ is not set ++# CONFIG_USB_GSPCA_JL2005BCD is not set ++# CONFIG_USB_GSPCA_KINECT is not set ++# CONFIG_USB_GSPCA_KONICA is not set ++# CONFIG_USB_GSPCA_MARS is not set ++# CONFIG_USB_GSPCA_MR97310A is not set ++# CONFIG_USB_GSPCA_NW80X is not set ++# CONFIG_USB_GSPCA_OV519 is not set ++# CONFIG_USB_GSPCA_OV534 is not set ++# CONFIG_USB_GSPCA_OV534_9 is not set ++# CONFIG_USB_GSPCA_PAC207 is not set ++# CONFIG_USB_GSPCA_PAC7302 is not set ++# CONFIG_USB_GSPCA_PAC7311 is not set ++# CONFIG_USB_GSPCA_SE401 is not set ++# CONFIG_USB_GSPCA_SN9C2028 is not set ++# CONFIG_USB_GSPCA_SN9C20X is not set ++# CONFIG_USB_GSPCA_SONIXB is not set ++# CONFIG_USB_GSPCA_SONIXJ is not set ++# CONFIG_USB_GSPCA_SPCA500 is not set ++# CONFIG_USB_GSPCA_SPCA501 is not set ++# CONFIG_USB_GSPCA_SPCA505 is not set ++# CONFIG_USB_GSPCA_SPCA506 is not set ++# CONFIG_USB_GSPCA_SPCA508 is not set ++# CONFIG_USB_GSPCA_SPCA561 is not set ++# CONFIG_USB_GSPCA_SPCA1528 is not set ++# CONFIG_USB_GSPCA_SQ905 is not set ++# CONFIG_USB_GSPCA_SQ905C is not set ++# CONFIG_USB_GSPCA_SQ930X is not set ++# CONFIG_USB_GSPCA_STK014 is not set ++# CONFIG_USB_GSPCA_STK1135 is not set ++# CONFIG_USB_GSPCA_STV0680 is not set ++# CONFIG_USB_GSPCA_SUNPLUS is not set ++# CONFIG_USB_GSPCA_T613 is not set ++# CONFIG_USB_GSPCA_TOPRO is not set ++# CONFIG_USB_GSPCA_TOUPTEK is not set ++# CONFIG_USB_GSPCA_TV8532 is not set ++# CONFIG_USB_GSPCA_VC032X is not set ++# CONFIG_USB_GSPCA_VICAM is not set ++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set ++# CONFIG_USB_GSPCA_ZC3XX is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++# CONFIG_VIDEO_USBTV is not set ++ ++# ++# Analog TV USB devices ++# ++# CONFIG_VIDEO_PVRUSB2 is not set ++# CONFIG_VIDEO_HDPVR is not set ++# CONFIG_VIDEO_STK1160_COMMON is not set ++# CONFIG_VIDEO_GO7007 is not set ++ ++# ++# Analog/digital TV USB devices ++# ++# CONFIG_VIDEO_AU0828 is not set ++# CONFIG_VIDEO_CX231XX is not set ++ ++# ++# Digital TV USB devices ++# ++# CONFIG_DVB_USB_V2 is not set ++# CONFIG_DVB_TTUSB_BUDGET is not set ++# CONFIG_DVB_TTUSB_DEC is not set ++# CONFIG_SMS_USB_DRV is not set ++# CONFIG_DVB_B2C2_FLEXCOP_USB is not set ++# CONFIG_DVB_AS102 is not set ++ ++# ++# Webcam, TV (analog/digital) USB devices ++# ++# CONFIG_VIDEO_EM28XX is not set ++ ++# ++# Software defined radio USB devices ++# ++# CONFIG_USB_AIRSPY is not set ++# CONFIG_USB_HACKRF is not set ++# CONFIG_USB_MSI2500 is not set ++# CONFIG_MEDIA_PCI_SUPPORT is not set ++CONFIG_RADIO_ADAPTERS=y ++# CONFIG_RADIO_SI470X is not set ++# CONFIG_RADIO_SI4713 is not set ++# CONFIG_USB_MR800 is not set ++# CONFIG_USB_DSBR is not set ++# CONFIG_RADIO_MAXIRADIO is not set ++# CONFIG_RADIO_SHARK is not set ++# CONFIG_RADIO_SHARK2 is not set ++# CONFIG_USB_KEENE is not set ++# CONFIG_USB_RAREMONO is not set ++# CONFIG_USB_MA901 is not set ++# CONFIG_RADIO_TEA5764 is not set ++# CONFIG_RADIO_SAA7706H is not set ++# CONFIG_RADIO_TEF6862 is not set ++# CONFIG_RADIO_WL1273 is not set ++CONFIG_VIDEOBUF2_CORE=y ++CONFIG_VIDEOBUF2_V4L2=y ++CONFIG_VIDEOBUF2_MEMOPS=y ++CONFIG_VIDEOBUF2_VMALLOC=y ++CONFIG_V4L_PLATFORM_DRIVERS=y ++# CONFIG_VIDEO_CAFE_CCIC is not set ++# CONFIG_VIDEO_CADENCE is not set ++# CONFIG_VIDEO_ASPEED is not set ++# CONFIG_VIDEO_MUX is not set ++# CONFIG_VIDEO_XILINX is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_DVB_PLATFORM_DRIVERS is not set ++# CONFIG_SDR_PLATFORM_DRIVERS is not set ++ ++# ++# MMC/SDIO DVB adapters ++# ++# CONFIG_SMS_SDIO_DRV is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++# CONFIG_DVB_TEST_DRIVERS is not set ++# end of Media drivers ++ ++# ++# Media ancillary drivers ++# ++CONFIG_MEDIA_ATTACH=y ++ ++# ++# Audio decoders, processors and mixers ++# ++# CONFIG_VIDEO_TVAUDIO is not set ++# CONFIG_VIDEO_TDA7432 is not set ++# CONFIG_VIDEO_TDA9840 is not set ++# CONFIG_VIDEO_TEA6415C is not set ++# CONFIG_VIDEO_TEA6420 is not set ++# CONFIG_VIDEO_MSP3400 is not set ++# CONFIG_VIDEO_CS3308 is not set ++# CONFIG_VIDEO_CS5345 is not set ++# CONFIG_VIDEO_CS53L32A is not set ++# CONFIG_VIDEO_TLV320AIC23B is not set ++# CONFIG_VIDEO_UDA1342 is not set ++# CONFIG_VIDEO_WM8775 is not set ++# CONFIG_VIDEO_WM8739 is not set ++# CONFIG_VIDEO_VP27SMPX is not set ++# CONFIG_VIDEO_SONY_BTF_MPX is not set ++# end of Audio decoders, processors and mixers ++ ++# ++# RDS decoders ++# ++# CONFIG_VIDEO_SAA6588 is not set ++# end of RDS decoders ++ ++# ++# Video decoders ++# ++# CONFIG_VIDEO_ADV7180 is not set ++# CONFIG_VIDEO_ADV7183 is not set ++# CONFIG_VIDEO_ADV748X is not set ++# CONFIG_VIDEO_ADV7604 is not set ++# CONFIG_VIDEO_ADV7842 is not set ++# CONFIG_VIDEO_BT819 is not set ++# CONFIG_VIDEO_BT856 is not set ++# CONFIG_VIDEO_BT866 is not set ++# CONFIG_VIDEO_KS0127 is not set ++# CONFIG_VIDEO_ML86V7667 is not set ++# CONFIG_VIDEO_SAA7110 is not set ++# CONFIG_VIDEO_SAA711X is not set ++# CONFIG_VIDEO_TC358743 is not set ++# CONFIG_VIDEO_TVP514X is not set ++# CONFIG_VIDEO_TVP5150 is not set ++# CONFIG_VIDEO_TVP7002 is not set ++# CONFIG_VIDEO_TW2804 is not set ++# CONFIG_VIDEO_TW9903 is not set ++# CONFIG_VIDEO_TW9906 is not set ++# CONFIG_VIDEO_TW9910 is not set ++# CONFIG_VIDEO_VPX3220 is not set ++# CONFIG_VIDEO_MAX9286 is not set ++ ++# ++# Video and audio decoders ++# ++# CONFIG_VIDEO_SAA717X is not set ++# CONFIG_VIDEO_CX25840 is not set ++# end of Video decoders ++ ++# ++# Video encoders ++# ++# CONFIG_VIDEO_SAA7127 is not set ++# CONFIG_VIDEO_SAA7185 is not set ++# CONFIG_VIDEO_ADV7170 is not set ++# CONFIG_VIDEO_ADV7175 is not set ++# CONFIG_VIDEO_ADV7343 is not set ++# CONFIG_VIDEO_ADV7393 is not set ++# CONFIG_VIDEO_ADV7511 is not set ++# CONFIG_VIDEO_AD9389B is not set ++# CONFIG_VIDEO_AK881X is not set ++# CONFIG_VIDEO_THS8200 is not set ++# end of Video encoders ++ ++# ++# Video improvement chips ++# ++# CONFIG_VIDEO_UPD64031A is not set ++# CONFIG_VIDEO_UPD64083 is not set ++# end of Video improvement chips ++ ++# ++# Audio/Video compression chips ++# ++# CONFIG_VIDEO_SAA6752HS is not set ++# end of Audio/Video compression chips ++ ++# ++# SDR tuner chips ++# ++# CONFIG_SDR_MAX2175 is not set ++# end of SDR tuner chips ++ ++# ++# Miscellaneous helper chips ++# ++# CONFIG_VIDEO_THS7303 is not set ++# CONFIG_VIDEO_M52790 is not set ++# CONFIG_VIDEO_I2C is not set ++# CONFIG_VIDEO_ST_MIPID02 is not set ++# end of Miscellaneous helper chips ++ ++# ++# Camera sensor devices ++# ++# CONFIG_VIDEO_HI556 is not set ++# CONFIG_VIDEO_IMX214 is not set ++# CONFIG_VIDEO_IMX219 is not set ++# CONFIG_VIDEO_IMX258 is not set ++# CONFIG_VIDEO_IMX274 is not set ++# CONFIG_VIDEO_IMX290 is not set ++# CONFIG_VIDEO_IMX319 is not set ++# CONFIG_VIDEO_IMX355 is not set ++# CONFIG_VIDEO_OV2640 is not set ++# CONFIG_VIDEO_OV2659 is not set ++# CONFIG_VIDEO_OV2680 is not set ++# CONFIG_VIDEO_OV2685 is not set ++# CONFIG_VIDEO_OV5640 is not set ++# CONFIG_VIDEO_OV5645 is not set ++# CONFIG_VIDEO_OV5647 is not set ++# CONFIG_VIDEO_OV6650 is not set ++# CONFIG_VIDEO_OV5670 is not set ++# CONFIG_VIDEO_OV5675 is not set ++# CONFIG_VIDEO_OV5695 is not set ++# CONFIG_VIDEO_OV7251 is not set ++# CONFIG_VIDEO_OV772X is not set ++# CONFIG_VIDEO_OV7640 is not set ++# CONFIG_VIDEO_OV7670 is not set ++# CONFIG_VIDEO_OV7740 is not set ++# CONFIG_VIDEO_OV8856 is not set ++# CONFIG_VIDEO_OV9640 is not set ++# CONFIG_VIDEO_OV9650 is not set ++# CONFIG_VIDEO_OV13858 is not set ++# CONFIG_VIDEO_VS6624 is not set ++# CONFIG_VIDEO_MT9M001 is not set ++# CONFIG_VIDEO_MT9M032 is not set ++# CONFIG_VIDEO_MT9M111 is not set ++# CONFIG_VIDEO_MT9P031 is not set ++# CONFIG_VIDEO_MT9T001 is not set ++# CONFIG_VIDEO_MT9T112 is not set ++# CONFIG_VIDEO_MT9V011 is not set ++# CONFIG_VIDEO_MT9V032 is not set ++# CONFIG_VIDEO_MT9V111 is not set ++# CONFIG_VIDEO_SR030PC30 is not set ++# CONFIG_VIDEO_NOON010PC30 is not set ++# CONFIG_VIDEO_M5MOLS is not set ++# CONFIG_VIDEO_RDACM20 is not set ++# CONFIG_VIDEO_RJ54N1 is not set ++# CONFIG_VIDEO_S5K6AA is not set ++# CONFIG_VIDEO_S5K6A3 is not set ++# CONFIG_VIDEO_S5K4ECGX is not set ++# CONFIG_VIDEO_S5K5BAF is not set ++# CONFIG_VIDEO_SMIAPP is not set ++# CONFIG_VIDEO_ET8EK8 is not set ++# CONFIG_VIDEO_S5C73M3 is not set ++# end of Camera sensor devices ++ ++# ++# Lens drivers ++# ++# CONFIG_VIDEO_AD5820 is not set ++# CONFIG_VIDEO_AK7375 is not set ++# CONFIG_VIDEO_DW9714 is not set ++# CONFIG_VIDEO_DW9768 is not set ++# CONFIG_VIDEO_DW9807_VCM is not set ++# end of Lens drivers ++ ++# ++# Flash devices ++# ++# CONFIG_VIDEO_ADP1653 is not set ++# CONFIG_VIDEO_LM3560 is not set ++# CONFIG_VIDEO_LM3646 is not set ++# end of Flash devices ++ ++# ++# SPI helper chips ++# ++# CONFIG_VIDEO_GS1662 is not set ++# end of SPI helper chips ++ ++# ++# Media SPI Adapters ++# ++# CONFIG_CXD2880_SPI_DRV is not set ++# end of Media SPI Adapters ++ ++CONFIG_MEDIA_TUNER=y ++ ++# ++# Customize TV tuners ++# ++CONFIG_MEDIA_TUNER_SIMPLE=y ++# CONFIG_MEDIA_TUNER_TDA18250 is not set ++CONFIG_MEDIA_TUNER_TDA8290=y ++CONFIG_MEDIA_TUNER_TDA827X=y ++CONFIG_MEDIA_TUNER_TDA18271=y ++CONFIG_MEDIA_TUNER_TDA9887=y ++CONFIG_MEDIA_TUNER_TEA5761=y ++CONFIG_MEDIA_TUNER_TEA5767=y ++# CONFIG_MEDIA_TUNER_MSI001 is not set ++CONFIG_MEDIA_TUNER_MT20XX=y ++# CONFIG_MEDIA_TUNER_MT2060 is not set ++# CONFIG_MEDIA_TUNER_MT2063 is not set ++# CONFIG_MEDIA_TUNER_MT2266 is not set ++# CONFIG_MEDIA_TUNER_MT2131 is not set ++# CONFIG_MEDIA_TUNER_QT1010 is not set ++CONFIG_MEDIA_TUNER_XC2028=y ++CONFIG_MEDIA_TUNER_XC5000=y ++CONFIG_MEDIA_TUNER_XC4000=y ++# CONFIG_MEDIA_TUNER_MXL5005S is not set ++# CONFIG_MEDIA_TUNER_MXL5007T is not set ++CONFIG_MEDIA_TUNER_MC44S803=y ++# CONFIG_MEDIA_TUNER_MAX2165 is not set ++# CONFIG_MEDIA_TUNER_TDA18218 is not set ++# CONFIG_MEDIA_TUNER_FC0011 is not set ++# CONFIG_MEDIA_TUNER_FC0012 is not set ++# CONFIG_MEDIA_TUNER_FC0013 is not set ++# CONFIG_MEDIA_TUNER_TDA18212 is not set ++# CONFIG_MEDIA_TUNER_E4000 is not set ++# CONFIG_MEDIA_TUNER_FC2580 is not set ++# CONFIG_MEDIA_TUNER_M88RS6000T is not set ++# CONFIG_MEDIA_TUNER_TUA9001 is not set ++# CONFIG_MEDIA_TUNER_SI2157 is not set ++# CONFIG_MEDIA_TUNER_IT913X is not set ++# CONFIG_MEDIA_TUNER_R820T is not set ++# CONFIG_MEDIA_TUNER_MXL301RF is not set ++# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set ++# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set ++# end of Customize TV tuners ++ ++# ++# Customise DVB Frontends ++# ++ ++# ++# Multistandard (satellite) frontends ++# ++# CONFIG_DVB_STB0899 is not set ++# CONFIG_DVB_STB6100 is not set ++# CONFIG_DVB_STV090x is not set ++# CONFIG_DVB_STV0910 is not set ++# CONFIG_DVB_STV6110x is not set ++# CONFIG_DVB_STV6111 is not set ++# CONFIG_DVB_MXL5XX is not set ++# CONFIG_DVB_M88DS3103 is not set ++ ++# ++# Multistandard (cable + terrestrial) frontends ++# ++# CONFIG_DVB_DRXK is not set ++# CONFIG_DVB_TDA18271C2DD is not set ++# CONFIG_DVB_SI2165 is not set ++# CONFIG_DVB_MN88472 is not set ++# CONFIG_DVB_MN88473 is not set ++ ++# ++# DVB-S (satellite) frontends ++# ++# CONFIG_DVB_CX24110 is not set ++# CONFIG_DVB_CX24123 is not set ++# CONFIG_DVB_MT312 is not set ++# CONFIG_DVB_ZL10036 is not set ++# CONFIG_DVB_ZL10039 is not set ++# CONFIG_DVB_S5H1420 is not set ++# CONFIG_DVB_STV0288 is not set ++# CONFIG_DVB_STB6000 is not set ++# CONFIG_DVB_STV0299 is not set ++# CONFIG_DVB_STV6110 is not set ++# CONFIG_DVB_STV0900 is not set ++# CONFIG_DVB_TDA8083 is not set ++# CONFIG_DVB_TDA10086 is not set ++# CONFIG_DVB_TDA8261 is not set ++# CONFIG_DVB_VES1X93 is not set ++# CONFIG_DVB_TUNER_ITD1000 is not set ++# CONFIG_DVB_TUNER_CX24113 is not set ++# CONFIG_DVB_TDA826X is not set ++# CONFIG_DVB_TUA6100 is not set ++# CONFIG_DVB_CX24116 is not set ++# CONFIG_DVB_CX24117 is not set ++# CONFIG_DVB_CX24120 is not set ++# CONFIG_DVB_SI21XX is not set ++# CONFIG_DVB_TS2020 is not set ++# CONFIG_DVB_DS3000 is not set ++# CONFIG_DVB_MB86A16 is not set ++# CONFIG_DVB_TDA10071 is not set ++ ++# ++# DVB-T (terrestrial) frontends ++# ++# CONFIG_DVB_SP8870 is not set ++# CONFIG_DVB_SP887X is not set ++# CONFIG_DVB_CX22700 is not set ++# CONFIG_DVB_CX22702 is not set ++# CONFIG_DVB_S5H1432 is not set ++# CONFIG_DVB_DRXD is not set ++# CONFIG_DVB_L64781 is not set ++# CONFIG_DVB_TDA1004X is not set ++# CONFIG_DVB_NXT6000 is not set ++# CONFIG_DVB_MT352 is not set ++# CONFIG_DVB_ZL10353 is not set ++# CONFIG_DVB_DIB3000MB is not set ++# CONFIG_DVB_DIB3000MC is not set ++# CONFIG_DVB_DIB7000M is not set ++# CONFIG_DVB_DIB7000P is not set ++# CONFIG_DVB_DIB9000 is not set ++# CONFIG_DVB_TDA10048 is not set ++# CONFIG_DVB_AF9013 is not set ++# CONFIG_DVB_EC100 is not set ++# CONFIG_DVB_STV0367 is not set ++# CONFIG_DVB_CXD2820R is not set ++# CONFIG_DVB_CXD2841ER is not set ++# CONFIG_DVB_RTL2830 is not set ++# CONFIG_DVB_RTL2832 is not set ++# CONFIG_DVB_RTL2832_SDR is not set ++# CONFIG_DVB_SI2168 is not set ++# CONFIG_DVB_ZD1301_DEMOD is not set ++# CONFIG_DVB_CXD2880 is not set ++ ++# ++# DVB-C (cable) frontends ++# ++# CONFIG_DVB_VES1820 is not set ++# CONFIG_DVB_TDA10021 is not set ++# CONFIG_DVB_TDA10023 is not set ++# CONFIG_DVB_STV0297 is not set ++ ++# ++# ATSC (North American/Korean Terrestrial/Cable DTV) frontends ++# ++# CONFIG_DVB_NXT200X is not set ++# CONFIG_DVB_OR51211 is not set ++# CONFIG_DVB_OR51132 is not set ++# CONFIG_DVB_BCM3510 is not set ++# CONFIG_DVB_LGDT330X is not set ++# CONFIG_DVB_LGDT3305 is not set ++# CONFIG_DVB_LGDT3306A is not set ++# CONFIG_DVB_LG2160 is not set ++# CONFIG_DVB_S5H1409 is not set ++# CONFIG_DVB_AU8522_DTV is not set ++# CONFIG_DVB_AU8522_V4L is not set ++# CONFIG_DVB_S5H1411 is not set ++ ++# ++# ISDB-T (terrestrial) frontends ++# ++# CONFIG_DVB_S921 is not set ++# CONFIG_DVB_DIB8000 is not set ++# CONFIG_DVB_MB86A20S is not set ++ ++# ++# ISDB-S (satellite) & ISDB-T (terrestrial) frontends ++# ++# CONFIG_DVB_TC90522 is not set ++# CONFIG_DVB_MN88443X is not set ++ ++# ++# Digital terrestrial only tuners/PLL ++# ++# CONFIG_DVB_PLL is not set ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# SEC control devices for DVB-S ++# ++# CONFIG_DVB_DRX39XYJ is not set ++# CONFIG_DVB_LNBH25 is not set ++# CONFIG_DVB_LNBH29 is not set ++# CONFIG_DVB_LNBP21 is not set ++# CONFIG_DVB_LNBP22 is not set ++# CONFIG_DVB_ISL6405 is not set ++# CONFIG_DVB_ISL6421 is not set ++# CONFIG_DVB_ISL6423 is not set ++# CONFIG_DVB_A8293 is not set ++# CONFIG_DVB_LGS8GL5 is not set ++# CONFIG_DVB_LGS8GXX is not set ++# CONFIG_DVB_ATBM8830 is not set ++# CONFIG_DVB_TDA665x is not set ++# CONFIG_DVB_IX2505V is not set ++# CONFIG_DVB_M88RS2000 is not set ++# CONFIG_DVB_AF9033 is not set ++# CONFIG_DVB_HORUS3A is not set ++# CONFIG_DVB_ASCOT2E is not set ++# CONFIG_DVB_HELENE is not set ++ ++# ++# Common Interface (EN50221) controller drivers ++# ++# CONFIG_DVB_CXD2099 is not set ++# CONFIG_DVB_SP2 is not set ++# end of Customise DVB Frontends ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++# end of Media ancillary drivers ++ ++# ++# Graphics support ++# ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 ++# CONFIG_DRM is not set ++ ++# ++# ARM devices ++# ++# end of ARM devices ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_ARMCLCD is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_I740 is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_FB_SM712 is not set ++# end of Frame buffer Devices ++ ++# ++# Backlight & LCD device support ++# ++# CONFIG_LCD_CLASS_DEVICE is not set ++# CONFIG_BACKLIGHT_CLASS_DEVICE is not set ++# end of Backlight & LCD device support ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_DUMMY_CONSOLE_COLUMNS=80 ++CONFIG_DUMMY_CONSOLE_ROWS=25 ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# end of Console display driver support ++ ++# CONFIG_LOGO is not set ++# end of Graphics support ++ ++CONFIG_SOUND=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_OSSEMUL is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ALS300 is not set ++# CONFIG_SND_ALI5451 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_AZT3328 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_CTXFI is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_EMU10K1 is not set ++# CONFIG_SND_EMU10K1X is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_ES1938 is not set ++# CONFIG_SND_ES1968 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_ICE1712 is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_LOLA is not set ++# CONFIG_SND_LX6464ES is not set ++# CONFIG_SND_MAESTRO3 is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SE6X is not set ++# CONFIG_SND_SONICVIBES is not set ++# CONFIG_SND_TRIDENT is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_HDA_INTEL is not set ++# end of HD-Audio ++ ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_A4TECH=y ++# CONFIG_HID_ACCUTOUCH is not set ++# CONFIG_HID_ACRUX is not set ++CONFIG_HID_APPLE=y ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++CONFIG_HID_BELKIN=y ++# CONFIG_HID_BETOP_FF is not set ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++# CONFIG_HID_COUGAR is not set ++# CONFIG_HID_MACALLY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CMEDIA is not set ++# CONFIG_HID_CREATIVE_SB0540 is not set ++CONFIG_HID_CYPRESS=y ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++CONFIG_HID_EZKEY=y ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_GLORIOUS is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_VIVALDI is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_VIEWSONIC is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_ITE is not set ++# CONFIG_HID_JABRA is not set ++# CONFIG_HID_TWINHAN is not set ++CONFIG_HID_KENSINGTON=y ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MALTRON is not set ++# CONFIG_HID_MAYFLASH is not set ++# CONFIG_HID_REDRAGON is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTI is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_RETRODE is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEAM is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_UDRAW_PS3 is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++# CONFIG_HID_MCP2221 is not set ++# end of Special HID drivers ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++# end of USB HID support ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++# end of I2C HID support ++# end of HID support ++ ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_COMMON=y ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_USB_CONN_GPIO is not set ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_PCI=y ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_FEW_INIT_RETRIES is not set ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_OTG=y ++CONFIG_USB_OTG_PRODUCTLIST=y ++# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++CONFIG_USB_AUTOSUSPEND_DELAY=2 ++# CONFIG_USB_MON is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_XHCI_HCD=y ++# CONFIG_USB_XHCI_DBGCAP is not set ++CONFIG_USB_XHCI_PCI=y ++# CONFIG_USB_XHCI_PCI_RENESAS is not set ++CONFIG_USB_XHCI_PLATFORM=y ++# CONFIG_USB_EHCI_HCD is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++CONFIG_USB_WDM=y ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++CONFIG_USB_UAS=y ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++CONFIG_USBIP_CORE=y ++CONFIG_USBIP_VHCI_HCD=y ++CONFIG_USBIP_VHCI_HC_PORTS=8 ++CONFIG_USBIP_VHCI_NR_HCS=1 ++CONFIG_USBIP_HOST=y ++CONFIG_USBIP_VUDC=y ++CONFIG_USBIP_DEBUG=y ++# CONFIG_USB_CDNS3 is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++ ++# ++# Platform Glue Driver Support ++# ++# CONFIG_USB_DWC3_HAPS is not set ++# CONFIG_USB_DWC3_OF_SIMPLE is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++CONFIG_USB_SERIAL_CONSOLE=y ++CONFIG_USB_SERIAL_GENERIC=y ++# CONFIG_USB_SERIAL_SIMPLE is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++CONFIG_USB_SERIAL_CH341=y ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++CONFIG_USB_SERIAL_CP210X=y ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_F81232 is not set ++# CONFIG_USB_SERIAL_F8153X is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_METRO is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MXUPORT is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_QCAUX is not set ++# CONFIG_USB_SERIAL_QUALCOMM is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_SYMBOL is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++CONFIG_USB_SERIAL_WWAN=y ++CONFIG_USB_SERIAL_OPTION=y ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_OPTICON is not set ++# CONFIG_USB_SERIAL_XSENS_MT is not set ++# CONFIG_USB_SERIAL_WISHBONE is not set ++# CONFIG_USB_SERIAL_SSU100 is not set ++# CONFIG_USB_SERIAL_QT2 is not set ++# CONFIG_USB_SERIAL_UPD78F0730 is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_APPLE_MFI_FASTCHARGE is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HUB_USB251XB is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# end of USB Physical Layer drivers ++ ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++# CONFIG_U_SERIAL_CONSOLE is not set ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_SNP_UDC_PLAT is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_AMD5536UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_NET2280 is not set ++# CONFIG_USB_GOKU is not set ++# CONFIG_USB_EG20T is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_MAX3420_UDC is not set ++# CONFIG_USB_DUMMY_HCD is not set ++# end of USB Peripheral Controller ++ ++CONFIG_USB_LIBCOMPOSITE=y ++CONFIG_USB_F_ACM=y ++CONFIG_USB_U_SERIAL=y ++CONFIG_USB_U_ETHER=y ++CONFIG_USB_U_AUDIO=y ++CONFIG_USB_F_NCM=y ++CONFIG_USB_F_ECM=y ++CONFIG_USB_F_EEM=y ++CONFIG_USB_F_SUBSET=y ++CONFIG_USB_F_RNDIS=y ++CONFIG_USB_F_MASS_STORAGE=y ++CONFIG_USB_F_FS=y ++CONFIG_USB_F_UAC1=y ++CONFIG_USB_F_UVC=y ++CONFIG_USB_F_HID=y ++CONFIG_USB_CONFIGFS=y ++# CONFIG_USB_CONFIGFS_SERIAL is not set ++CONFIG_USB_CONFIGFS_ACM=y ++# CONFIG_USB_CONFIGFS_OBEX is not set ++CONFIG_USB_CONFIGFS_NCM=y ++CONFIG_USB_CONFIGFS_ECM=y ++CONFIG_USB_CONFIGFS_ECM_SUBSET=y ++CONFIG_USB_CONFIGFS_RNDIS=y ++CONFIG_USB_CONFIGFS_EEM=y ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++# CONFIG_USB_CONFIGFS_F_LB_SS is not set ++# CONFIG_USB_CONFIGFS_F_FS is not set ++CONFIG_USB_CONFIGFS_F_UAC1=y ++# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set ++# CONFIG_USB_CONFIGFS_F_UAC2 is not set ++# CONFIG_USB_CONFIGFS_F_MIDI is not set ++# CONFIG_USB_CONFIGFS_F_HID is not set ++CONFIG_USB_CONFIGFS_F_UVC=y ++# CONFIG_USB_CONFIGFS_F_PRINTER is not set ++ ++# ++# USB Gadget precomposed configurations ++# ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_AUDIO is not set ++CONFIG_USB_ETH=y ++CONFIG_USB_ETH_RNDIS=y ++CONFIG_USB_ETH_EEM=y ++CONFIG_USB_G_NCM=y ++CONFIG_USB_GADGETFS=y ++CONFIG_USB_FUNCTIONFS=y ++CONFIG_USB_FUNCTIONFS_ETH=y ++CONFIG_USB_FUNCTIONFS_RNDIS=y ++# CONFIG_USB_FUNCTIONFS_GENERIC is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++CONFIG_USB_CDC_COMPOSITE=y ++CONFIG_USB_G_ACM_MS=y ++CONFIG_USB_G_MULTI=y ++CONFIG_USB_G_MULTI_RNDIS=y ++CONFIG_USB_G_MULTI_CDC=y ++CONFIG_USB_G_HID=y ++# CONFIG_USB_G_DBGP is not set ++# CONFIG_USB_G_WEBCAM is not set ++# CONFIG_USB_RAW_GADGET is not set ++# end of USB Gadget precomposed configurations ++ ++CONFIG_MPP_TO_GADGET_UVC=y ++# CONFIG_TYPEC is not set ++# CONFIG_USB_ROLE_SWITCH is not set ++CONFIG_MMC=y ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_ARMMMCI is not set ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_IO_ACCESSORS=y ++CONFIG_MMC_SDHCI_PCI=y ++CONFIG_MMC_RICOH_MMC=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_OF_ARASAN=y ++CONFIG_MMC_SDHCI_OF_ASPEED=y ++CONFIG_MMC_SDHCI_OF_AT91=y ++CONFIG_MMC_SDHCI_OF_DWCMSHC=y ++CONFIG_MMC_SDHCI_CADENCE=y ++CONFIG_MMC_SDHCI_F_SDH30=m ++CONFIG_MMC_SDHCI_MILBEAUT=m ++# CONFIG_MMC_TIFM_SD is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_CB710 is not set ++# CONFIG_MMC_VIA_SDMMC is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++CONFIG_MMC_CQHCI=y ++# CONFIG_MMC_HSQ is not set ++# CONFIG_MMC_TOSHIBA_PCI is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MMC_SDHCI_XENON is not set ++# CONFIG_MMC_SDHCI_OMAP is not set ++# CONFIG_MMC_SDHCI_AM654 is not set ++CONFIG_MMC_SDHCI_SS928V100=y ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_EDAC_SUPPORT=y ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++CONFIG_RTC_NVMEM=y ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABEOZ9 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12026 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF85363 is not set ++CONFIG_RTC_DRV_PCF8563=y ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV3028 is not set ++# CONFIG_RTC_DRV_RV3032 is not set ++CONFIG_RTC_DRV_RV8803=y ++# CONFIG_RTC_DRV_SD3078 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_PL030 is not set ++# CONFIG_RTC_DRV_PL031 is not set ++# CONFIG_RTC_DRV_CADENCE is not set ++# CONFIG_RTC_DRV_FTRTC010 is not set ++# CONFIG_RTC_DRV_R7301 is not set ++ ++# ++# HID Sensor RTC drivers ++# ++CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set ++ ++# ++# DMA Devices ++# ++CONFIG_DMA_ENGINE=y ++CONFIG_DMA_OF=y ++# CONFIG_ALTERA_MSGDMA is not set ++# CONFIG_AMBA_PL08X is not set ++# CONFIG_DW_AXI_DMAC is not set ++# CONFIG_FSL_EDMA is not set ++# CONFIG_FSL_QDMA is not set ++# CONFIG_HISI_DMA is not set ++# CONFIG_INTEL_IDMA64 is not set ++# CONFIG_MV_XOR_V2 is not set ++# CONFIG_PL330_DMA is not set ++# CONFIG_PLX_DMA is not set ++# CONFIG_XILINX_DMA is not set ++# CONFIG_XILINX_ZYNQMP_DMA is not set ++# CONFIG_XILINX_ZYNQMP_DPDMA is not set ++# CONFIG_QCOM_HIDMA_MGMT is not set ++# CONFIG_QCOM_HIDMA is not set ++# CONFIG_DW_DMAC is not set ++# CONFIG_DW_DMAC_PCI is not set ++# CONFIG_DW_EDMA is not set ++# CONFIG_DW_EDMA_PCIE is not set ++# CONFIG_SF_PDMA is not set ++ ++# ++# DMA Clients ++# ++# CONFIG_ASYNC_TX_DMA is not set ++# CONFIG_DMATEST is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_UDMABUF is not set ++# CONFIG_DMABUF_MOVE_NOTIFY is not set ++# CONFIG_DMABUF_SELFTESTS is not set ++# CONFIG_DMABUF_HEAPS is not set ++# end of DMABUF options ++ ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VFIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++# CONFIG_VIRTIO_MENU is not set ++# CONFIG_VDPA is not set ++CONFIG_VHOST_MENU=y ++# CONFIG_VHOST_NET is not set ++# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# end of Microsoft Hyper-V guest support ++ ++# CONFIG_GREYBUS is not set ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++# CONFIG_MELLANOX_PLATFORM is not set ++CONFIG_LOONGARCH_PLATFORM_DEVICES=y ++CONFIG_HAVE_CLK=y ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++# CONFIG_COMMON_CLK_MAX9485 is not set ++# CONFIG_COMMON_CLK_SI5341 is not set ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI544 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_XGENE is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_VC5 is not set ++# CONFIG_COMMON_CLK_FIXED_MMIO is not set ++CONFIG_RESET_BSP=y ++CONFIG_COMMON_CLK_SS928V100=y ++# CONFIG_HWSPINLOCK is not set ++ ++# ++# Clock Source drivers ++# ++CONFIG_TIMER_OF=y ++CONFIG_TIMER_PROBE=y ++CONFIG_CLKSRC_MMIO=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y ++# CONFIG_FSL_ERRATUM_A008585 is not set ++CONFIG_HISILICON_ERRATUM_161010101=y ++CONFIG_ARM64_ERRATUM_858921=y ++CONFIG_ARM_TIMER_SP804=y ++# CONFIG_MICROCHIP_PIT64B is not set ++# end of Clock Source drivers ++ ++# CONFIG_MAILBOX is not set ++CONFIG_IOMMU_IOVA=y ++CONFIG_IOASID=y ++CONFIG_IOMMU_API=y ++CONFIG_IOMMU_SUPPORT=y ++ ++# ++# Generic IOMMU Pagetable Support ++# ++CONFIG_IOMMU_IO_PGTABLE=y ++CONFIG_IOMMU_IO_PGTABLE_LPAE=y ++# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set ++# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set ++ ++# ++# Generic PASID table support ++# ++CONFIG_IOMMU_PASID_TABLE=y ++CONFIG_ARM_SMMU_V3_CONTEXT=y ++# end of Generic PASID table support ++# end of Generic IOMMU Pagetable Support ++ ++# CONFIG_IOMMU_DEBUGFS is not set ++# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set ++CONFIG_OF_IOMMU=y ++CONFIG_IOMMU_DMA=y ++CONFIG_IOMMU_SVA_LIB=y ++CONFIG_IOMMU_PAGE_FAULT=y ++# CONFIG_ARM_SMMU is not set ++CONFIG_ARM_SMMU_V3=y ++CONFIG_ARM_SMMU_V3_SVA=y ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_REMOTEPROC is not set ++# end of Remoteproc drivers ++ ++# ++# Rpmsg drivers ++# ++# CONFIG_RPMSG_VIRTIO is not set ++# end of Rpmsg drivers ++ ++# CONFIG_SOUNDWIRE is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Amlogic SoC drivers ++# ++# end of Amlogic SoC drivers ++ ++# ++# Aspeed SoC drivers ++# ++# end of Aspeed SoC drivers ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++# end of Broadcom SoC drivers ++ ++# ++# NXP/Freescale QorIQ SoC drivers ++# ++# CONFIG_QUICC_ENGINE is not set ++# CONFIG_FSL_RCPM is not set ++# end of NXP/Freescale QorIQ SoC drivers ++ ++# ++# i.MX SoC drivers ++# ++# end of i.MX SoC drivers ++ ++# ++# Qualcomm SoC drivers ++# ++# end of Qualcomm SoC drivers ++ ++# CONFIG_SOC_TI is not set ++ ++# ++# Xilinx SoC drivers ++# ++# CONFIG_XILINX_VCU is not set ++# end of Xilinx SoC drivers ++ ++# ++# Hisilicon SoC driver support ++# ++# end of Hisilicon SoC driver support ++# end of SOC (System On Chip) specific Drivers ++ ++CONFIG_PM_DEVFREQ=y ++ ++# ++# DEVFREQ Governors ++# ++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y ++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set ++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set ++# CONFIG_DEVFREQ_GOV_USERSPACE is not set ++# CONFIG_DEVFREQ_GOV_PASSIVE is not set ++ ++# ++# DEVFREQ Drivers ++# ++# CONFIG_PM_DEVFREQ_EVENT is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++CONFIG_IIO=y ++# CONFIG_IIO_BUFFER is not set ++# CONFIG_IIO_CONFIGFS is not set ++# CONFIG_IIO_TRIGGER is not set ++# CONFIG_IIO_SW_DEVICE is not set ++# CONFIG_IIO_SW_TRIGGER is not set ++# CONFIG_IIO_TRIGGERED_EVENT is not set ++ ++# ++# Accelerometers ++# ++# CONFIG_ADIS16201 is not set ++# CONFIG_ADIS16209 is not set ++# CONFIG_ADXL345_I2C is not set ++# CONFIG_ADXL345_SPI is not set ++# CONFIG_ADXL372_SPI is not set ++# CONFIG_ADXL372_I2C is not set ++# CONFIG_BMA180 is not set ++# CONFIG_BMA220 is not set ++# CONFIG_BMA400 is not set ++# CONFIG_BMC150_ACCEL is not set ++# CONFIG_DA280 is not set ++# CONFIG_DA311 is not set ++# CONFIG_DMARD06 is not set ++# CONFIG_DMARD09 is not set ++# CONFIG_DMARD10 is not set ++# CONFIG_IIO_ST_ACCEL_3AXIS is not set ++# CONFIG_KXSD9 is not set ++# CONFIG_KXCJK1013 is not set ++# CONFIG_MC3230 is not set ++# CONFIG_MMA7455_I2C is not set ++# CONFIG_MMA7455_SPI is not set ++# CONFIG_MMA7660 is not set ++# CONFIG_MMA8452 is not set ++# CONFIG_MMA9551 is not set ++# CONFIG_MMA9553 is not set ++# CONFIG_MXC4005 is not set ++# CONFIG_MXC6255 is not set ++# CONFIG_SCA3000 is not set ++# CONFIG_STK8312 is not set ++# CONFIG_STK8BA50 is not set ++# end of Accelerometers ++ ++# ++# Analog to digital converters ++# ++# CONFIG_AD7091R5 is not set ++# CONFIG_AD7124 is not set ++# CONFIG_AD7192 is not set ++# CONFIG_AD7266 is not set ++# CONFIG_AD7291 is not set ++# CONFIG_AD7292 is not set ++# CONFIG_AD7298 is not set ++# CONFIG_AD7476 is not set ++# CONFIG_AD7606_IFACE_PARALLEL is not set ++# CONFIG_AD7606_IFACE_SPI is not set ++# CONFIG_AD7766 is not set ++# CONFIG_AD7768_1 is not set ++# CONFIG_AD7780 is not set ++# CONFIG_AD7791 is not set ++# CONFIG_AD7793 is not set ++# CONFIG_AD7887 is not set ++# CONFIG_AD7923 is not set ++# CONFIG_AD7949 is not set ++# CONFIG_AD799X is not set ++# CONFIG_ADI_AXI_ADC is not set ++# CONFIG_CC10001_ADC is not set ++# CONFIG_ENVELOPE_DETECTOR is not set ++# CONFIG_HI8435 is not set ++CONFIG_VENDOR_LSADC=y ++# CONFIG_HX711 is not set ++# CONFIG_INA2XX_ADC is not set ++# CONFIG_LTC2471 is not set ++# CONFIG_LTC2485 is not set ++# CONFIG_LTC2496 is not set ++# CONFIG_LTC2497 is not set ++# CONFIG_MAX1027 is not set ++# CONFIG_MAX11100 is not set ++# CONFIG_MAX1118 is not set ++# CONFIG_MAX1241 is not set ++# CONFIG_MAX1363 is not set ++# CONFIG_MAX9611 is not set ++# CONFIG_MCP320X is not set ++# CONFIG_MCP3422 is not set ++# CONFIG_MCP3911 is not set ++# CONFIG_NAU7802 is not set ++# CONFIG_SD_ADC_MODULATOR is not set ++# CONFIG_TI_ADC081C is not set ++# CONFIG_TI_ADC0832 is not set ++# CONFIG_TI_ADC084S021 is not set ++# CONFIG_TI_ADC12138 is not set ++# CONFIG_TI_ADC108S102 is not set ++# CONFIG_TI_ADC128S052 is not set ++# CONFIG_TI_ADC161S626 is not set ++# CONFIG_TI_ADS1015 is not set ++# CONFIG_TI_ADS7950 is not set ++# CONFIG_TI_ADS8344 is not set ++# CONFIG_TI_ADS8688 is not set ++# CONFIG_TI_ADS124S08 is not set ++# CONFIG_TI_TLC4541 is not set ++# CONFIG_VF610_ADC is not set ++# CONFIG_XILINX_XADC is not set ++# end of Analog to digital converters ++ ++# ++# Analog Front Ends ++# ++# CONFIG_IIO_RESCALE is not set ++# end of Analog Front Ends ++ ++# ++# Amplifiers ++# ++# CONFIG_AD8366 is not set ++# CONFIG_HMC425 is not set ++# end of Amplifiers ++ ++# ++# Chemical Sensors ++# ++# CONFIG_ATLAS_PH_SENSOR is not set ++# CONFIG_ATLAS_EZO_SENSOR is not set ++# CONFIG_BME680 is not set ++# CONFIG_CCS811 is not set ++# CONFIG_IAQCORE is not set ++# CONFIG_SCD30_CORE is not set ++# CONFIG_SENSIRION_SGP30 is not set ++# CONFIG_SPS30 is not set ++# CONFIG_VZ89X is not set ++# end of Chemical Sensors ++ ++# ++# Hid Sensor IIO Common ++# ++# end of Hid Sensor IIO Common ++ ++# ++# SSP Sensor Common ++# ++# CONFIG_IIO_SSP_SENSORHUB is not set ++# end of SSP Sensor Common ++ ++# ++# Digital to analog converters ++# ++# CONFIG_AD5064 is not set ++# CONFIG_AD5360 is not set ++# CONFIG_AD5380 is not set ++# CONFIG_AD5421 is not set ++# CONFIG_AD5446 is not set ++# CONFIG_AD5449 is not set ++# CONFIG_AD5592R is not set ++# CONFIG_AD5593R is not set ++# CONFIG_AD5504 is not set ++# CONFIG_AD5624R_SPI is not set ++# CONFIG_AD5686_SPI is not set ++# CONFIG_AD5696_I2C is not set ++# CONFIG_AD5755 is not set ++# CONFIG_AD5758 is not set ++# CONFIG_AD5761 is not set ++# CONFIG_AD5764 is not set ++# CONFIG_AD5770R is not set ++# CONFIG_AD5791 is not set ++# CONFIG_AD7303 is not set ++# CONFIG_AD8801 is not set ++# CONFIG_DPOT_DAC is not set ++# CONFIG_DS4424 is not set ++# CONFIG_LTC1660 is not set ++# CONFIG_LTC2632 is not set ++# CONFIG_M62332 is not set ++# CONFIG_MAX517 is not set ++# CONFIG_MAX5821 is not set ++# CONFIG_MCP4725 is not set ++# CONFIG_MCP4922 is not set ++# CONFIG_TI_DAC082S085 is not set ++# CONFIG_TI_DAC5571 is not set ++# CONFIG_TI_DAC7311 is not set ++# CONFIG_TI_DAC7612 is not set ++# CONFIG_VF610_DAC is not set ++# end of Digital to analog converters ++ ++# ++# IIO dummy driver ++# ++# end of IIO dummy driver ++ ++# ++# Frequency Synthesizers DDS/PLL ++# ++ ++# ++# Clock Generator/Distribution ++# ++# CONFIG_AD9523 is not set ++# end of Clock Generator/Distribution ++ ++# ++# Phase-Locked Loop (PLL) frequency synthesizers ++# ++# CONFIG_ADF4350 is not set ++# CONFIG_ADF4371 is not set ++# end of Phase-Locked Loop (PLL) frequency synthesizers ++# end of Frequency Synthesizers DDS/PLL ++ ++# ++# Digital gyroscope sensors ++# ++# CONFIG_ADIS16080 is not set ++# CONFIG_ADIS16130 is not set ++# CONFIG_ADIS16136 is not set ++# CONFIG_ADIS16260 is not set ++# CONFIG_ADXRS290 is not set ++# CONFIG_ADXRS450 is not set ++# CONFIG_BMG160 is not set ++# CONFIG_FXAS21002C is not set ++# CONFIG_MPU3050_I2C is not set ++# CONFIG_IIO_ST_GYRO_3AXIS is not set ++# CONFIG_ITG3200 is not set ++# end of Digital gyroscope sensors ++ ++# ++# Health Sensors ++# ++ ++# ++# Heart Rate Monitors ++# ++# CONFIG_AFE4403 is not set ++# CONFIG_AFE4404 is not set ++# CONFIG_MAX30100 is not set ++# CONFIG_MAX30102 is not set ++# end of Heart Rate Monitors ++# end of Health Sensors ++ ++# ++# Humidity sensors ++# ++# CONFIG_AM2315 is not set ++# CONFIG_DHT11 is not set ++# CONFIG_HDC100X is not set ++# CONFIG_HDC2010 is not set ++# CONFIG_HTS221 is not set ++# CONFIG_HTU21 is not set ++# CONFIG_SI7005 is not set ++# CONFIG_SI7020 is not set ++# end of Humidity sensors ++ ++# ++# Inertial measurement units ++# ++# CONFIG_ADIS16400 is not set ++# CONFIG_ADIS16460 is not set ++# CONFIG_ADIS16475 is not set ++# CONFIG_ADIS16480 is not set ++# CONFIG_BMI160_I2C is not set ++# CONFIG_BMI160_SPI is not set ++# CONFIG_FXOS8700_I2C is not set ++# CONFIG_FXOS8700_SPI is not set ++# CONFIG_KMX61 is not set ++# CONFIG_INV_ICM42600_I2C is not set ++# CONFIG_INV_ICM42600_SPI is not set ++# CONFIG_INV_MPU6050_I2C is not set ++# CONFIG_INV_MPU6050_SPI is not set ++# CONFIG_IIO_ST_LSM6DSX is not set ++# end of Inertial measurement units ++ ++# ++# Light sensors ++# ++# CONFIG_ADJD_S311 is not set ++# CONFIG_ADUX1020 is not set ++# CONFIG_AL3010 is not set ++# CONFIG_AL3320A is not set ++# CONFIG_APDS9300 is not set ++# CONFIG_APDS9960 is not set ++# CONFIG_AS73211 is not set ++# CONFIG_BH1750 is not set ++# CONFIG_BH1780 is not set ++# CONFIG_CM32181 is not set ++# CONFIG_CM3232 is not set ++# CONFIG_CM3323 is not set ++# CONFIG_CM3605 is not set ++# CONFIG_CM36651 is not set ++# CONFIG_GP2AP002 is not set ++# CONFIG_GP2AP020A00F is not set ++# CONFIG_SENSORS_ISL29018 is not set ++# CONFIG_SENSORS_ISL29028 is not set ++# CONFIG_ISL29125 is not set ++# CONFIG_JSA1212 is not set ++# CONFIG_RPR0521 is not set ++# CONFIG_LTR501 is not set ++# CONFIG_LV0104CS is not set ++# CONFIG_MAX44000 is not set ++# CONFIG_MAX44009 is not set ++# CONFIG_NOA1305 is not set ++# CONFIG_OPT3001 is not set ++# CONFIG_PA12203001 is not set ++# CONFIG_SI1133 is not set ++# CONFIG_SI1145 is not set ++# CONFIG_STK3310 is not set ++# CONFIG_ST_UVIS25 is not set ++# CONFIG_TCS3414 is not set ++# CONFIG_TCS3472 is not set ++# CONFIG_SENSORS_TSL2563 is not set ++# CONFIG_TSL2583 is not set ++# CONFIG_TSL2772 is not set ++# CONFIG_TSL4531 is not set ++# CONFIG_US5182D is not set ++# CONFIG_VCNL4000 is not set ++# CONFIG_VCNL4035 is not set ++# CONFIG_VEML6030 is not set ++# CONFIG_VEML6070 is not set ++# CONFIG_VL6180 is not set ++# CONFIG_ZOPT2201 is not set ++# end of Light sensors ++ ++# ++# Magnetometer sensors ++# ++# CONFIG_AK8974 is not set ++# CONFIG_AK8975 is not set ++# CONFIG_AK09911 is not set ++# CONFIG_BMC150_MAGN_I2C is not set ++# CONFIG_BMC150_MAGN_SPI is not set ++# CONFIG_MAG3110 is not set ++# CONFIG_MMC35240 is not set ++# CONFIG_IIO_ST_MAGN_3AXIS is not set ++# CONFIG_SENSORS_HMC5843_I2C is not set ++# CONFIG_SENSORS_HMC5843_SPI is not set ++# CONFIG_SENSORS_RM3100_I2C is not set ++# CONFIG_SENSORS_RM3100_SPI is not set ++# end of Magnetometer sensors ++ ++# ++# Multiplexers ++# ++# CONFIG_IIO_MUX is not set ++# end of Multiplexers ++ ++# ++# Inclinometer sensors ++# ++# end of Inclinometer sensors ++ ++# ++# Linear and angular position sensors ++# ++# end of Linear and angular position sensors ++ ++# ++# Digital potentiometers ++# ++# CONFIG_AD5272 is not set ++# CONFIG_DS1803 is not set ++# CONFIG_MAX5432 is not set ++# CONFIG_MAX5481 is not set ++# CONFIG_MAX5487 is not set ++# CONFIG_MCP4018 is not set ++# CONFIG_MCP4131 is not set ++# CONFIG_MCP4531 is not set ++# CONFIG_MCP41010 is not set ++# CONFIG_TPL0102 is not set ++# end of Digital potentiometers ++ ++# ++# Digital potentiostats ++# ++# CONFIG_LMP91000 is not set ++# end of Digital potentiostats ++ ++# ++# Pressure sensors ++# ++# CONFIG_ABP060MG is not set ++# CONFIG_BMP280 is not set ++# CONFIG_DLHL60D is not set ++# CONFIG_DPS310 is not set ++# CONFIG_HP03 is not set ++# CONFIG_ICP10100 is not set ++# CONFIG_MPL115_I2C is not set ++# CONFIG_MPL115_SPI is not set ++# CONFIG_MPL3115 is not set ++# CONFIG_MS5611 is not set ++# CONFIG_MS5637 is not set ++# CONFIG_IIO_ST_PRESS is not set ++# CONFIG_T5403 is not set ++# CONFIG_HP206C is not set ++# CONFIG_ZPA2326 is not set ++# end of Pressure sensors ++ ++# ++# Lightning sensors ++# ++# CONFIG_AS3935 is not set ++# end of Lightning sensors ++ ++# ++# Proximity and distance sensors ++# ++# CONFIG_ISL29501 is not set ++# CONFIG_LIDAR_LITE_V2 is not set ++# CONFIG_MB1232 is not set ++# CONFIG_PING is not set ++# CONFIG_RFD77402 is not set ++# CONFIG_SRF04 is not set ++# CONFIG_SX9310 is not set ++# CONFIG_SX9500 is not set ++# CONFIG_SRF08 is not set ++# CONFIG_VCNL3020 is not set ++# CONFIG_VL53L0X_I2C is not set ++# end of Proximity and distance sensors ++ ++# ++# Resolver to digital converters ++# ++# CONFIG_AD2S90 is not set ++# CONFIG_AD2S1200 is not set ++# end of Resolver to digital converters ++ ++# ++# Temperature sensors ++# ++# CONFIG_LTC2983 is not set ++# CONFIG_MAXIM_THERMOCOUPLE is not set ++# CONFIG_MLX90614 is not set ++# CONFIG_MLX90632 is not set ++# CONFIG_TMP006 is not set ++# CONFIG_TMP007 is not set ++# CONFIG_TSYS01 is not set ++# CONFIG_TSYS02D is not set ++# CONFIG_MAX31856 is not set ++# end of Temperature sensors ++ ++# CONFIG_NTB is not set ++# CONFIG_VME_BUS is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_DEBUG is not set ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_PWM_BSP=y ++ ++# ++# IRQ chip support ++# ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++CONFIG_ARM_GIC_V2M=y ++CONFIG_ARM_GIC_V3=y ++CONFIG_ARM_GIC_V3_ITS=y ++CONFIG_ARM_GIC_V3_ITS_PCI=y ++# CONFIG_AL_FIC is not set ++CONFIG_HISILICON_IRQ_MBIGEN=y ++CONFIG_PARTITION_PERCPU=y ++# end of IRQ chip support ++ ++# CONFIG_IPACK_BUS is not set ++CONFIG_RESET_CONTROLLER=y ++# CONFIG_RESET_TI_SYSCON is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_XGENE is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_PHY_CADENCE_TORRENT is not set ++# CONFIG_PHY_CADENCE_DPHY is not set ++# CONFIG_PHY_CADENCE_SIERRA is not set ++# CONFIG_PHY_CADENCE_SALVO is not set ++# CONFIG_PHY_FSL_IMX8MQ_USB is not set ++# CONFIG_PHY_MIXEL_MIPI_DPHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_PHY_CPCAP_USB is not set ++# CONFIG_PHY_MAPPHONE_MDM6600 is not set ++# CONFIG_PHY_OCELOT_SERDES is not set ++CONFIG_VENDOR_USB_PHY=y ++CONFIG_PHY_BSP_USB3=y ++CONFIG_BSP_USB_PHY=y ++CONFIG_USB_MODE_OPTION=y ++CONFIG_USB_DRD0_IN_HOST=y ++# end of PHY Subsystem ++ ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Performance monitor support ++# ++# CONFIG_ARM_CCI_PMU is not set ++# CONFIG_ARM_CCN is not set ++# CONFIG_ARM_CMN is not set ++CONFIG_ARM_PMU=y ++# CONFIG_ARM_DSU_PMU is not set ++# CONFIG_ARM_SPE_PMU is not set ++# CONFIG_HISI_PCIE_PMU is not set ++# CONFIG_HNS3_PMU is not set ++# end of Performance monitor support ++ ++# CONFIG_RAS is not set ++# CONFIG_USB4 is not set ++ ++# ++# Android ++# ++# CONFIG_ANDROID is not set ++# end of Android ++ ++# ++# Vendor Hooks ++# ++# end of Vendor Hooks ++ ++# CONFIG_LIBNVDIMM is not set ++# CONFIG_DAX is not set ++CONFIG_NVMEM=y ++CONFIG_NVMEM_SYSFS=y ++ ++# ++# HW tracing support ++# ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++# CONFIG_HISI_PTT is not set ++# end of HW tracing support ++ ++# CONFIG_FPGA is not set ++# CONFIG_FSI is not set ++# CONFIG_TEE is not set ++CONFIG_PM_OPP=y ++# CONFIG_SIOX is not set ++# CONFIG_SLIMBUS is not set ++# CONFIG_INTERCONNECT is not set ++# CONFIG_COUNTER is not set ++# CONFIG_MOST is not set ++# CONFIG_ROH is not set ++ ++# ++# Vendor driver support ++# ++# CONFIG_CMA_MEM_SHARED is not set ++# CONFIG_CMA_ADVANCE_SHARE is not set ++CONFIG_VENDOR_NPU=y ++# end of Vendor driver support ++# end of Device Drivers ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_VALIDATE_FS_PARSER is not set ++CONFIG_FS_IOMAP=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT2=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++# CONFIG_EXT4_DEBUG is not set ++# CONFIG_EXT4_MITIGATION_FALSE_SHARING is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_XFS_FS=y ++CONFIG_XFS_SUPPORT_V4=y ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++# CONFIG_XFS_ONLINE_SCRUB is not set ++# CONFIG_XFS_WARN is not set ++# CONFIG_XFS_DEBUG is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++# CONFIG_FS_DAX is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_EXPORTFS=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++# CONFIG_FS_VERITY is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++CONFIG_QUOTA=y ++# CONFIG_QUOTA_NETLINK_INTERFACE is not set ++CONFIG_PRINT_QUOTA_WARNING=y ++# CONFIG_QUOTA_DEBUG is not set ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS4_FS=m ++CONFIG_AUTOFS_FS=m ++CONFIG_FUSE_FS=y ++# CONFIG_CUSE is not set ++# CONFIG_VIRTIO_FS is not set ++CONFIG_OVERLAY_FS=m ++CONFIG_OVERLAY_FS_REDIRECT_DIR=y ++CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y ++CONFIG_OVERLAY_FS_INDEX=y ++# CONFIG_OVERLAY_FS_XINO_AUTO is not set ++CONFIG_OVERLAY_FS_METACOPY=y ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++# end of Caches ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++# end of CD-ROM/DVD Filesystems ++ ++# ++# DOS/FAT/EXFAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++# CONFIG_EXFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++# CONFIG_NTFS3_FS is not set ++# end of DOS/FAT/EXFAT/NT Filesystems ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_TMPFS_INODE64 is not set ++# CONFIG_HUGETLBFS is not set ++CONFIG_ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y ++CONFIG_MEMFD_CREATE=y ++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y ++CONFIG_CONFIGFS_FS=y ++# end of Pseudo filesystems ++ ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++CONFIG_CRAMFS_BLOCKDEV=y ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++# CONFIG_SQUASHFS_ZSTD is not set ++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set ++# CONFIG_SQUASHFS_EMBEDDED is not set ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_EROFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V2=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++CONFIG_NFS_DISABLE_UDP_SUPPORT=y ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=y ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_SMB_SERVER is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=y ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++# CONFIG_UNICODE is not set ++CONFIG_IO_WQ=y ++# end of File systems ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_KEYS_REQUEST_CACHE is not set ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEY_DH_OPERATIONS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++# CONFIG_HARDENED_USERCOPY is not set ++# CONFIG_FORTIFY_SOURCE is not set ++# CONFIG_STATIC_USERMODEHELPER is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,bpf" ++ ++# ++# Kernel hardening options ++# ++ ++# ++# Memory initialization ++# ++CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y ++CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y ++CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y ++CONFIG_INIT_STACK_NONE=y ++# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set ++# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set ++# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set ++# CONFIG_INIT_STACK_ALL_PATTERN is not set ++# CONFIG_INIT_STACK_ALL_ZERO is not set ++# CONFIG_GCC_PLUGIN_STACKLEAK is not set ++# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set ++# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set ++# end of Memory initialization ++# end of Kernel hardening options ++ ++# CONFIG_SECURITY_BOOT_INIT is not set ++# end of Security options ++ ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_SKCIPHER=y ++CONFIG_CRYPTO_SKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=y ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_AKCIPHER=y ++CONFIG_CRYPTO_KPP2=y ++CONFIG_CRYPTO_KPP=y ++CONFIG_CRYPTO_ACOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++CONFIG_CRYPTO_GF128MUL=y ++CONFIG_CRYPTO_NULL=y ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Public-key cryptography ++# ++CONFIG_CRYPTO_RSA=y ++# CONFIG_CRYPTO_DH is not set ++CONFIG_CRYPTO_ECC=y ++CONFIG_CRYPTO_ECDH=y ++# CONFIG_CRYPTO_ECDSA is not set ++# CONFIG_CRYPTO_ECRDSA is not set ++# CONFIG_CRYPTO_SM2 is not set ++# CONFIG_CRYPTO_CURVE25519 is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_CCM=y ++CONFIG_CRYPTO_GCM=y ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++# CONFIG_CRYPTO_AEGIS128 is not set ++CONFIG_CRYPTO_SEQIV=m ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CFB is not set ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_OFB is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++# CONFIG_CRYPTO_ADIANTUM is not set ++# CONFIG_CRYPTO_ESSIV is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_XXHASH is not set ++# CONFIG_CRYPTO_BLAKE2B is not set ++# CONFIG_CRYPTO_BLAKE2S is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++CONFIG_CRYPTO_GHASH=y ++# CONFIG_CRYPTO_POLY1305 is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_SM3_GENERIC is not set ++# CONFIG_CRYPTO_STREEBOG is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_TI is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_SM4_GENERIC is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++# CONFIG_CRYPTO_ZSTD is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=y ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=y ++CONFIG_CRYPTO_JITTERENTROPY=y ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++CONFIG_CRYPTO_HASH_INFO=y ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set ++# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set ++# CONFIG_CRYPTO_DEV_CCP is not set ++# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set ++# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set ++# CONFIG_CRYPTO_DEV_SAFEXCEL is not set ++# CONFIG_CRYPTO_DEV_CCREE is not set ++# CONFIG_CRYPTO_DEV_HISI_SEC is not set ++# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set ++CONFIG_ASYMMETRIC_KEY_TYPE=y ++CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y ++CONFIG_X509_CERTIFICATE_PARSER=y ++# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set ++CONFIG_PKCS7_MESSAGE_PARSER=y ++# CONFIG_PKCS7_TEST_KEY is not set ++# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set ++# CONFIG_PGP_LIBRARY is not set ++# CONFIG_PGP_KEY_PARSER is not set ++# CONFIG_PGP_PRELOAD is not set ++ ++# ++# Certificates for signature checking ++# ++CONFIG_SYSTEM_TRUSTED_KEYRING=y ++CONFIG_SYSTEM_TRUSTED_KEYS="" ++# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set ++# CONFIG_SECONDARY_TRUSTED_KEYRING is not set ++# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set ++# CONFIG_PGP_PRELOAD_PUBLIC_KEYS is not set ++# end of Certificates for signature checking ++ ++# ++# Library routines ++# ++CONFIG_LINEAR_RANGES=y ++# CONFIG_PACKING is not set ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++# CONFIG_CORDIC is not set ++# CONFIG_PRIME_NUMBERS is not set ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++CONFIG_ARCH_HAS_FAST_MULTIPLIER=y ++CONFIG_ARCH_USE_SYM_ANNOTATIONS=y ++# CONFIG_INDIRECT_PIO is not set ++ ++# ++# Crypto library routines ++# ++CONFIG_CRYPTO_LIB_AES=y ++CONFIG_CRYPTO_LIB_ARC4=y ++CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y ++# CONFIG_CRYPTO_LIB_CHACHA is not set ++# CONFIG_CRYPTO_LIB_CURVE25519 is not set ++CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 ++# CONFIG_CRYPTO_LIB_POLY1305 is not set ++# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set ++CONFIG_CRYPTO_LIB_SHA256=y ++# end of Crypto library routines ++ ++CONFIG_LIB_MEMNEQ=y ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC64 is not set ++# CONFIG_CRC4 is not set ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++# CONFIG_CRC8 is not set ++CONFIG_XXHASH=y ++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_INTERVAL_TREE=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DMA_OPS=y ++CONFIG_NEED_SG_DMA_LENGTH=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_DMA_ADDR_T_64BIT=y ++CONFIG_DMA_DECLARE_COHERENT=y ++CONFIG_ARCH_HAS_SETUP_DMA_OPS=y ++CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y ++CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y ++CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y ++CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y ++CONFIG_SWIOTLB=y ++CONFIG_DMA_NONCOHERENT_MMAP=y ++CONFIG_DMA_COHERENT_POOL=y ++CONFIG_DMA_REMAP=y ++CONFIG_DMA_DIRECT_REMAP=y ++CONFIG_DMA_CMA=y ++# CONFIG_DMA_PERNUMA_CMA is not set ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=4 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_DMA_MAP_BENCHMARK is not set ++CONFIG_SGL_ALLOC=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_GLOB=y ++# CONFIG_GLOB_SELFTEST is not set ++CONFIG_NLATTR=y ++CONFIG_CLZ_TAB=y ++# CONFIG_IRQ_POLL is not set ++CONFIG_MPILIB=y ++CONFIG_LIBFDT=y ++CONFIG_OID_REGISTRY=y ++CONFIG_HAVE_GENERIC_VDSO=y ++CONFIG_GENERIC_GETTIMEOFDAY=y ++CONFIG_GENERIC_VDSO_TIME_NS=y ++CONFIG_SG_POOL=y ++CONFIG_ARCH_STACKWALK=y ++CONFIG_SBITMAP=y ++# CONFIG_STRING_SELFTEST is not set ++# end of Library routines ++ ++CONFIG_LIB_PRINT=y ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++# CONFIG_PRINTK_CALLER is not set ++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 ++CONFIG_CONSOLE_LOGLEVEL_QUIET=4 ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++# CONFIG_DYNAMIC_DEBUG_CORE is not set ++CONFIG_SYMBOLIC_ERRNAME=y ++CONFIG_DEBUG_BUGVERBOSE=y ++# end of printk and dmesg options ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=2048 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_HEADERS_INSTALL is not set ++# CONFIG_OPTIMIZE_INLINING is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set ++CONFIG_ARCH_WANT_FRAME_POINTERS=y ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_PGO_KERNEL is not set ++# end of Compile-time checks and compiler options ++ ++# ++# Generic Kernel Debugging Instruments ++# ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 ++CONFIG_MAGIC_SYSRQ_SERIAL=y ++CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" ++CONFIG_DEBUG_FS=y ++CONFIG_DEBUG_FS_ALLOW_ALL=y ++# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set ++# CONFIG_DEBUG_FS_ALLOW_NONE is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y ++# CONFIG_UBSAN is not set ++CONFIG_HAVE_KCSAN_COMPILER=y ++# end of Generic Kernel Debugging Instruments ++ ++CONFIG_DEBUG_KERNEL=y ++CONFIG_DEBUG_MISC=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_OWNER is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_RODATA_TEST is not set ++CONFIG_ARCH_HAS_DEBUG_WX=y ++# CONFIG_DEBUG_WX is not set ++CONFIG_GENERIC_PTDUMP=y ++# CONFIG_PTDUMP_DEBUGFS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_VM_PGTABLE is not set ++CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y ++# CONFIG_DEBUG_VIRTUAL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y ++CONFIG_HAVE_ARCH_KASAN_VMALLOC=y ++CONFIG_CC_HAS_KASAN_GENERIC=y ++CONFIG_CC_HAS_KASAN_SW_TAGS=y ++CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y ++# CONFIG_KASAN is not set ++CONFIG_HAVE_ARCH_KFENCE=y ++# CONFIG_KFENCE is not set ++# end of Memory Debugging ++ ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Oops, Lockups and Hangs ++# ++CONFIG_PANIC_ON_OOPS=y ++CONFIG_PANIC_ON_OOPS_VALUE=1 ++CONFIG_PANIC_TIMEOUT=1 ++# CONFIG_SOFTLOCKUP_DETECTOR is not set ++ ++# ++# ARM64 NMI watchdog configuration ++# ++# end of ARM64 NMI watchdog configuration ++ ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_WQ_WATCHDOG is not set ++# CONFIG_TEST_LOCKUP is not set ++# end of Debug Oops, Lockups and Hangs ++ ++# ++# Scheduler Debugging ++# ++CONFIG_SCHED_DEBUG=y ++CONFIG_SCHED_INFO=y ++CONFIG_SCHEDSTATS=y ++# end of Scheduler Debugging ++ ++# CONFIG_DEBUG_TIMEKEEPING is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_LOCK_DEBUGGING_SUPPORT=y ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_RWSEMS is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_WW_MUTEX_SELFTEST is not set ++# CONFIG_SCF_TORTURE_TEST is not set ++# CONFIG_CSD_LOCK_WAIT_DEBUG is not set ++# end of Lock Debugging (spinlocks, mutexes, etc...) ++ ++CONFIG_STACKTRACE=y ++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_HAVE_DEBUG_BUGVERBOSE=y ++ ++# ++# Debug kernel data structures ++# ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PLIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_BUG_ON_DATA_CORRUPTION is not set ++# end of Debug kernel data structures ++ ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_RCU_SCALE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_RCU_REF_SCALE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=60 ++CONFIG_RCU_TRACE=y ++# CONFIG_RCU_EQS_DEBUG is not set ++# end of RCU Debugging ++ ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACE_CLOCK=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++# CONFIG_SAMPLES is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++ ++# ++# arm64 Debugging ++# ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_ARM64_RELOC_TEST is not set ++# CONFIG_CORESIGHT is not set ++# end of arm64 Debugging ++ ++# ++# Kernel Testing and Coverage ++# ++# CONFIG_KUNIT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++CONFIG_ARCH_HAS_KCOV=y ++CONFIG_CC_HAS_SANCOV_TRACE_PC=y ++# CONFIG_KCOV is not set ++CONFIG_RUNTIME_TESTING_MENU=y ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_TEST_MIN_HEAP is not set ++# CONFIG_TEST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_REED_SOLOMON_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_STRSCPY is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_XARRAY is not set ++# CONFIG_TEST_OVERFLOW is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_TEST_IDA is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_BITOPS is not set ++# CONFIG_TEST_VMALLOC is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_BLACKHOLE_DEV is not set ++# CONFIG_FIND_BIT_BENCHMARK is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_SYSCTL is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_TEST_KMOD is not set ++# CONFIG_TEST_MEMCAT_P is not set ++# CONFIG_TEST_STACKINIT is not set ++# CONFIG_TEST_MEMINIT is not set ++# CONFIG_TEST_FREE_PAGES is not set ++# CONFIG_MEMTEST is not set ++# end of Kernel Testing and Coverage ++# end of Kernel hacking +diff --git a/arch/arm64/configs/ss928v100_defconfig b/arch/arm64/configs/ss928v100_defconfig +new file mode 100644 +index 000000000000..b1208fd69331 +--- /dev/null ++++ b/arch/arm64/configs/ss928v100_defconfig +@@ -0,0 +1,3665 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm64 4.19.90 Kernel Configuration ++# ++ ++# ++# Compiler: aarch64-mix210-linux-gcc (HC&C V1R3C00SPC200B042_20221123) 7.3.0 ++# ++CONFIG_CC_IS_GCC=y ++CONFIG_GCC_VERSION=70300 ++CONFIG_CLANG_VERSION=0 ++CONFIG_CC_HAS_ASM_GOTO=y ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++CONFIG_THREAD_INFO_IN_TASK=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_BUILD_SALT="" ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y ++CONFIG_GENERIC_IRQ_MIGRATION=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_GENERIC_MSI_IRQ=y ++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_IRQ_MULTI_HANDLER=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_HZ_PERIODIC=y ++# CONFIG_NO_HZ_IDLE is not set ++# CONFIG_NO_HZ_FULL is not set ++# CONFIG_NO_HZ is not set ++# CONFIG_HIGH_RES_TIMERS is not set ++CONFIG_PREEMPT_NONE=y ++# CONFIG_PREEMPT_VOLUNTARY is not set ++# CONFIG_PREEMPT is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++CONFIG_CPU_ISOLATION=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++CONFIG_TREE_SRCU=y ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_NEED_SEGCBLIST=y ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y ++CONFIG_ARCH_SUPPORTS_INT128=y ++# CONFIG_CGROUPS is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_CHECKPOINT_RESTORE is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++CONFIG_RELAY=y ++# CONFIG_BLK_DEV_INITRD is not set ++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_SYSCTL_EXCEPTION_TRACE=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++# CONFIG_FHANDLE is not set ++CONFIG_POSIX_TIMERS=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_FUTEX_PI=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_MEMBARRIER=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_USERFAULTFD=y ++CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y ++CONFIG_RSEQ=y ++# CONFIG_DEBUG_RSEQ is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++# CONFIG_PC104 is not set ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++CONFIG_SLAB_MERGE_DEFAULT=y ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SLAB_FREELIST_HARDENED is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_PROFILING is not set ++CONFIG_ARM64=y ++CONFIG_64BIT=y ++CONFIG_MMU=y ++CONFIG_ARM64_PAGE_SHIFT=12 ++CONFIG_ARM64_CONT_SHIFT=4 ++CONFIG_ARCH_MMAP_RND_BITS_MIN=18 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=24 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_BUG=y ++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CSUM=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA32=y ++CONFIG_HAVE_GENERIC_GUP=y ++CONFIG_SMP=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_PGTABLE_LEVELS=3 ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_ARCH_PROC_KCORE_TEXT=y ++ ++# ++# Platform selection ++# ++# CONFIG_ARCH_ACTIONS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_BCM2835 is not set ++# CONFIG_ARCH_BCM_IPROC is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_BRCMSTB is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_K3 is not set ++# CONFIG_ARCH_LAYERSCAPE is not set ++# CONFIG_ARCH_LG1K is not set ++# CONFIG_ARCH_HISI is not set ++CONFIG_ARCH_BSP=y ++# CONFIG_ARCH_SS528V100 is not set ++# CONFIG_ARCH_SS625V100 is not set ++# CONFIG_ARCH_SS919V100 is not set ++# CONFIG_ARCH_SS015V100 is not set ++CONFIG_ARCH_SS928V100=y ++# CONFIG_ARCH_SS927V100 is not set ++# CONFIG_ARCH_MEDIATEK is not set ++# CONFIG_ARCH_MESON is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALTEK is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SEATTLE is not set ++# CONFIG_ARCH_SYNQUACER is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_STRATIX10 is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_SPRD is not set ++# CONFIG_ARCH_THUNDER is not set ++# CONFIG_ARCH_THUNDER2 is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_XGENE is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQMP is not set ++ ++# ++# Bus support ++# ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++CONFIG_PCI_DOMAINS_GENERIC=y ++CONFIG_PCI_SYSCALL=y ++CONFIG_PCIEPORTBUS=y ++# CONFIG_PCIEAER is not set ++# CONFIG_PCIEASPM is not set ++CONFIG_PCIE_PME=y ++# CONFIG_PCIE_PTM is not set ++CONFIG_PCI_MSI=y ++CONFIG_PCI_MSI_IRQ_DOMAIN=y ++CONFIG_PCI_QUIRKS=y ++# CONFIG_PCI_DEBUG is not set ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++# CONFIG_PCI_PRI is not set ++# CONFIG_PCI_PASID is not set ++# CONFIG_HOTPLUG_PCI is not set ++ ++# ++# PCI controller drivers ++# ++ ++# ++# Cadence PCIe controllers support ++# ++# CONFIG_PCIE_CADENCE_HOST is not set ++# CONFIG_PCI_FTPCI100 is not set ++# CONFIG_PCI_HOST_GENERIC is not set ++# CONFIG_PCIE_XILINX is not set ++# CONFIG_PCI_XGENE is not set ++# CONFIG_PCI_HOST_THUNDER_PEM is not set ++# CONFIG_PCI_HOST_THUNDER_ECAM is not set ++ ++# ++# DesignWare PCI Core Support ++# ++# CONFIG_PCIE_DW_PLAT_HOST is not set ++# CONFIG_PCI_HISI is not set ++# CONFIG_PCIE_KIRIN is not set ++ ++# ++# PCI Endpoint ++# ++# CONFIG_PCI_ENDPOINT is not set ++ ++# ++# PCI switch controller drivers ++# ++# CONFIG_PCI_SW_SWITCHTEC is not set ++# CONFIG_BSP_PCIE is not set ++ ++# ++# Kernel Features ++# ++ ++# ++# ARM errata workarounds via the alternatives framework ++# ++CONFIG_ARM64_ERRATUM_826319=y ++CONFIG_ARM64_ERRATUM_827319=y ++CONFIG_ARM64_ERRATUM_824069=y ++CONFIG_ARM64_ERRATUM_819472=y ++CONFIG_ARM64_ERRATUM_832075=y ++CONFIG_ARM64_ERRATUM_845719=y ++CONFIG_ARM64_ERRATUM_843419=y ++CONFIG_ARM64_ERRATUM_1024718=y ++CONFIG_ARM64_ERRATUM_1463225=y ++CONFIG_CAVIUM_ERRATUM_22375=y ++CONFIG_CAVIUM_ERRATUM_23154=y ++CONFIG_CAVIUM_ERRATUM_27456=y ++CONFIG_CAVIUM_ERRATUM_30115=y ++CONFIG_QCOM_FALKOR_ERRATUM_1003=y ++CONFIG_QCOM_FALKOR_ERRATUM_1009=y ++CONFIG_QCOM_QDF2400_ERRATUM_0065=y ++CONFIG_SOCIONEXT_SYNQUACER_PREITS=y ++CONFIG_HISILICON_ERRATUM_161600802=y ++CONFIG_QCOM_FALKOR_ERRATUM_E1041=y ++CONFIG_ARM64_4K_PAGES=y ++# CONFIG_ARM64_16K_PAGES is not set ++# CONFIG_ARM64_64K_PAGES is not set ++CONFIG_ARM64_VA_BITS_39=y ++# CONFIG_ARM64_VA_BITS_48 is not set ++CONFIG_ARM64_VA_BITS=39 ++CONFIG_ARM64_PA_BITS_48=y ++CONFIG_ARM64_PA_BITS=48 ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_SCHED_MC=y ++# CONFIG_SCHED_SMT is not set ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_NUMA is not set ++CONFIG_HOLES_IN_ZONE=y ++CONFIG_HZ_100=y ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y ++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_ARCH_SPARSEMEM_DEFAULT=y ++CONFIG_ARCH_SELECT_MEMORY_MODEL=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_SYS_SUPPORTS_HUGETLBFS=y ++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y ++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y ++# CONFIG_SECCOMP is not set ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++# CONFIG_XEN is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_UNMAP_KERNEL_AT_EL0=y ++CONFIG_HARDEN_BRANCH_PREDICTOR=y ++CONFIG_HARDEN_EL2_VECTORS=y ++CONFIG_ARM64_SSBD=y ++# CONFIG_ARMV8_DEPRECATED is not set ++# CONFIG_ARM64_SW_TTBR0_PAN is not set ++ ++# ++# ARMv8.1 architectural features ++# ++CONFIG_ARM64_HW_AFDBM=y ++CONFIG_ARM64_PAN=y ++# CONFIG_ARM64_LSE_ATOMICS is not set ++CONFIG_ARM64_VHE=y ++ ++# ++# ARMv8.2 architectural features ++# ++CONFIG_ARM64_UAO=y ++# CONFIG_ARM64_PMEM is not set ++CONFIG_ARM64_RAS_EXTN=y ++CONFIG_ARM64_SVE=y ++CONFIG_ARM64_MODULE_PLTS=y ++# CONFIG_RANDOMIZE_BASE is not set ++ ++# ++# Boot options ++# ++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox" ++# CONFIG_CMDLINE_FORCE is not set ++# CONFIG_EFI is not set ++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y ++CONFIG_IMG_GZ_DTB=y ++# CONFIG_IMG_DTB is not set ++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb" ++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="vendor/ss928v100-demb-flash" ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++# CONFIG_PM_WAKELOCKS is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++CONFIG_CPUFREQ_DT=y ++CONFIG_CPUFREQ_DT_PLATDEV=y ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# Firmware Drivers ++# ++CONFIG_ARM_PSCI_FW=y ++# CONFIG_ARM_SDE_INTERFACE is not set ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++# CONFIG_GOOGLE_FIRMWARE is not set ++ ++# ++# Tegra firmware driver ++# ++# CONFIG_VIRTUALIZATION is not set ++# CONFIG_ARM64_CRYPTO is not set ++ ++# ++# General architecture-dependent options ++# ++# CONFIG_KPROBES is not set ++# CONFIG_JUMP_LABEL is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y ++CONFIG_ARCH_HAS_SET_MEMORY=y ++CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_RSEQ=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_HAVE_RCU_TABLE_FREE=y ++CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y ++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y ++CONFIG_HAVE_CMPXCHG_LOCAL=y ++CONFIG_HAVE_CMPXCHG_DOUBLE=y ++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_STACKPROTECTOR=y ++CONFIG_CC_HAS_STACKPROTECTOR_NONE=y ++CONFIG_STACKPROTECTOR=y ++CONFIG_STACKPROTECTOR_STRONG=y ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y ++CONFIG_HAVE_ARCH_HUGE_VMAP=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_ARCH_MMAP_RND_BITS=18 ++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_COMPAT_OLD_SIGACTION=y ++CONFIG_COMPAT_32BIT_TIME=y ++CONFIG_HAVE_ARCH_VMAP_STACK=y ++CONFIG_VMAP_STACK=y ++CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y ++CONFIG_STRICT_KERNEL_RWX=y ++CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y ++CONFIG_STRICT_MODULE_RWX=y ++CONFIG_REFCOUNT_FULL=y ++CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_PLUGIN_HOSTCC="" ++CONFIG_HAVE_GCC_PLUGINS=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++CONFIG_BLK_SCSI_REQUEST=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_DEV_ZONED is not set ++CONFIG_BLK_CMDLINE_PARSER=y ++# CONFIG_BLK_WBT is not set ++# CONFIG_BLK_SED_OPAL is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_AIX_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_CMDLINE_PARTITION=y ++CONFIG_BLOCK_COMPAT=y ++CONFIG_BLK_MQ_PCI=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_CFQ is not set ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_MQ_IOSCHED_DEADLINE=y ++CONFIG_MQ_IOSCHED_KYBER=y ++# CONFIG_IOSCHED_BFQ is not set ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_READ_LOCK=y ++CONFIG_ARCH_INLINE_READ_LOCK_BH=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_READ_UNLOCK=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_WRITE_LOCK=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_SPIN_TRYLOCK=y ++CONFIG_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK=y ++CONFIG_INLINE_SPIN_LOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_READ_LOCK=y ++CONFIG_INLINE_READ_LOCK_BH=y ++CONFIG_INLINE_READ_LOCK_IRQ=y ++CONFIG_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_INLINE_READ_UNLOCK=y ++CONFIG_INLINE_READ_UNLOCK_BH=y ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_WRITE_LOCK=y ++CONFIG_INLINE_WRITE_LOCK_BH=y ++CONFIG_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_INLINE_WRITE_UNLOCK=y ++CONFIG_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y ++CONFIG_QUEUED_SPINLOCKS=y ++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y ++CONFIG_QUEUED_RWLOCKS=y ++CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y ++CONFIG_FREEZER=y ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_COMPAT_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Memory Management options ++# ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_EXTREME=y ++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y ++CONFIG_SPARSEMEM_VMEMMAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_MMU_NOTIFIER=y ++CONFIG_KSM=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y ++# CONFIG_MEMORY_FAILURE is not set ++# CONFIG_TRANSPARENT_HUGEPAGE is not set ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++# CONFIG_PERCPU_STATS is not set ++# CONFIG_GUP_BENCHMARK is not set ++CONFIG_ARCH_HAS_PTE_SPECIAL=y ++CONFIG_NET=y ++CONFIG_NET_INGRESS=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_TLS is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_INTERFACE is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_XDP_SOCKETS is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++CONFIG_NET_IP_TUNNEL=m ++# CONFIG_IP_MROUTE is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_NET_FOU_IP_TUNNELS is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_INET_RAW_DIAG is not set ++# CONFIG_INET_DIAG_DESTROY is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=y ++CONFIG_IPV6_ROUTER_PREF=y ++# CONFIG_IPV6_ROUTE_INFO is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++# CONFIG_IPV6_ILA is not set ++CONFIG_INET6_XFRM_MODE_TRANSPORT=m ++CONFIG_INET6_XFRM_MODE_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_BEET=m ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++# CONFIG_IPV6_VTI is not set ++CONFIG_IPV6_SIT=m ++# CONFIG_IPV6_SIT_6RD is not set ++CONFIG_IPV6_NDISC_NODETYPE=y ++# CONFIG_IPV6_TUNNEL is not set ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_IPV6_SEG6_LWTUNNEL is not set ++# CONFIG_IPV6_SEG6_HMAC is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++CONFIG_NETFILTER=y ++CONFIG_NETFILTER_ADVANCED=y ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_INGRESS=y ++# CONFIG_NETFILTER_NETLINK_ACCT is not set ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NETFILTER_NETLINK_OSF is not set ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NF_LOG_NETDEV is not set ++# CONFIG_NF_TABLES is not set ++# CONFIG_NETFILTER_XTABLES is not set ++# CONFIG_IP_SET is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV4 is not set ++# CONFIG_NF_TPROXY_IPV4 is not set ++# CONFIG_NF_DUP_IPV4 is not set ++# CONFIG_NF_LOG_ARP is not set ++# CONFIG_NF_LOG_IPV4 is not set ++# CONFIG_NF_REJECT_IPV4 is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++ ++# ++# IPv6: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV6 is not set ++# CONFIG_NF_TPROXY_IPV6 is not set ++# CONFIG_NF_DUP_IPV6 is not set ++# CONFIG_NF_REJECT_IPV6 is not set ++# CONFIG_NF_LOG_IPV6 is not set ++# CONFIG_IP6_NF_IPTABLES is not set ++# CONFIG_BPFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_6LOWPAN is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_NET_NSH is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++# CONFIG_BPF_STREAM_PARSER is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_PSAMPLE is not set ++# CONFIG_NET_IFE is not set ++# CONFIG_LWTUNNEL is not set ++CONFIG_DST_CACHE=y ++CONFIG_GRO_CELLS=y ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++# CONFIG_FAILOVER is not set ++CONFIG_HAVE_EBPF_JIT=y ++ ++# ++# Device Drivers ++# ++CONFIG_ARM_AMBA=y ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++ ++# ++# Firmware loader ++# ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set ++CONFIG_GENERIC_CPU_AUTOPROBE=y ++CONFIG_GENERIC_CPU_VULNERABILITIES=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_REGMAP_MMIO=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_DMA_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=4 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++CONFIG_GENERIC_ARCH_TOPOLOGY=y ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_SIMPLE_PM_BUS is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_GNSS is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++CONFIG_MTD_OF_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# Partition parsers ++# ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_MCHP23K256 is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++CONFIG_MTD_BLOCK2MTD=y ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++# CONFIG_MTD_ONENAND is not set ++CONFIG_MTD_SPI_NAND_BSP=y ++# CONFIG_BSP_NAND_ECC_STATUS_REPORT is not set ++# CONFIG_BSP_NAND_FS_MAY_NO_YAFFS2 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_NAND_DENALI_PCI is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_RICOH is not set ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_CAFE is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++CONFIG_MTD_SPI_NAND_FMC100=y ++# CONFIG_MTD_SPI_NAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++CONFIG_MTD_SPI_NOR=y ++# CONFIG_MTD_MT81xx_NOR is not set ++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set ++# CONFIG_SPI_CADENCE_QUADSPI is not set ++CONFIG_SPI_BSP_SFC=y ++# CONFIG_MTD_SPI_IDS is not set ++# CONFIG_CLOSE_SPI_8PIN_4IO is not set ++CONFIG_BSP_SPI_BLOCK_PROTECT=y ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_KOBJ=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SKD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=65536 ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++# CONFIG_BLK_DEV_RSXX is not set ++ ++# ++# NVME Support ++# ++# CONFIG_BLK_DEV_NVME is not set ++# CONFIG_NVME_FC is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_PCI_ENDPOINT_TEST is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++# CONFIG_EEPROM_IDT_89HPESX is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC & related support ++# ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_GENWQE is not set ++# CONFIG_ECHO is not set ++# CONFIG_MISC_RTSX_PCI is not set ++# CONFIG_MISC_RTSX_USB is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_CXGB3_ISCSI is not set ++# CONFIG_SCSI_CXGB4_ISCSI is not set ++# CONFIG_SCSI_BNX2_ISCSI is not set ++# CONFIG_BE2ISCSI is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_HPSA is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_3W_SAS is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_MVUMI is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_SCSI_ESAS2R is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_MPT3SAS is not set ++# CONFIG_SCSI_MPT2SAS is not set ++# CONFIG_SCSI_SMARTPQI is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_SCSI_SNIC is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_AM53C974 is not set ++# CONFIG_SCSI_WD719X is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_PMCRAID is not set ++# CONFIG_SCSI_PM8001 is not set ++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_HAVE_PATA_PLATFORM=y ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_FIREWIRE_NOSY is not set ++CONFIG_NETDEVICES=y ++CONFIG_NET_CORE=y ++# CONFIG_BONDING is not set ++# CONFIG_DUMMY is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NET_TEAM is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_IPVLAN is not set ++# CONFIG_VXLAN is not set ++# CONFIG_GENEVE is not set ++# CONFIG_GTP is not set ++# CONFIG_MACSEC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_TUN is not set ++# CONFIG_TUN_VNET_CROSS_LE is not set ++# CONFIG_VETH is not set ++# CONFIG_NLMON is not set ++# CONFIG_ARCNET is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++CONFIG_ETHERNET=y ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++# CONFIG_NET_VENDOR_AGERE is not set ++# CONFIG_NET_VENDOR_ALACRITECH is not set ++# CONFIG_NET_VENDOR_ALTEON is not set ++# CONFIG_ALTERA_TSE is not set ++# CONFIG_NET_VENDOR_AMAZON is not set ++# CONFIG_NET_VENDOR_AMD is not set ++# CONFIG_NET_VENDOR_AQUANTIA is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_VENDOR_ATHEROS is not set ++# CONFIG_NET_VENDOR_AURORA is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_BROCADE is not set ++# CONFIG_NET_VENDOR_CADENCE is not set ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++# CONFIG_NET_VENDOR_CORTINA is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_VENDOR_DEC is not set ++# CONFIG_NET_VENDOR_DLINK is not set ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++# CONFIG_NET_VENDOR_HISILICON is not set ++# CONFIG_NET_VENDOR_HP is not set ++# CONFIG_NET_VENDOR_HUAWEI is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++CONFIG_NET_VENDOR_BSP=y ++# CONFIG_BSP_FEMAC is not set ++CONFIG_ETH_GMAC=y ++CONFIG_GMAC_DDR_64BIT=y ++CONFIG_GMAC_DESC_4WORD=y ++CONFIG_GMAC_RXCSUM=y ++CONFIG_RX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF ++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF ++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16 ++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32 ++# CONFIG_JME is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MELLANOX is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_MICROSEMI is not set ++# CONFIG_NET_VENDOR_MYRI is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_NETERION is not set ++# CONFIG_NET_VENDOR_NETRONOME is not set ++# CONFIG_NET_VENDOR_NI is not set ++# CONFIG_NET_VENDOR_NVIDIA is not set ++# CONFIG_NET_VENDOR_OKI is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_PACKET_ENGINES is not set ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++# CONFIG_NET_VENDOR_RDC is not set ++# CONFIG_NET_VENDOR_REALTEK is not set ++# CONFIG_NET_VENDOR_RENESAS is not set ++# CONFIG_NET_VENDOR_ROCKER is not set ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SOLARFLARE is not set ++# CONFIG_NET_VENDOR_SILAN is not set ++# CONFIG_NET_VENDOR_SIS is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_SOCIONEXT is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++# CONFIG_NET_VENDOR_SUN is not set ++# CONFIG_NET_VENDOR_SYNOPSYS is not set ++# CONFIG_NET_VENDOR_TEHUTI is not set ++# CONFIG_NET_VENDOR_TI is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_MDIO_DEVICE=y ++CONFIG_MDIO_BUS=y ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++# CONFIG_MDIO_BSP_FEMAC is not set ++CONFIG_MDIO_BSP_GEMAC=y ++# CONFIG_MDIO_MSCC_MIIM is not set ++# CONFIG_MDIO_OCTEON is not set ++# CONFIG_MDIO_THUNDER is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AX88796B_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_CORTINA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83822_PHY is not set ++# CONFIG_DP83TC811_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MARVELL_10G_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROCHIP_T1_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_RENESAS_PHY is not set ++# CONFIG_ROCKCHIP_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++CONFIG_USB_NET_DRIVERS=y ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_VMXNET3 is not set ++# CONFIG_NET_FAILOVER is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++CONFIG_INPUT_JOYDEV=y ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_DLINK_DIR685 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++CONFIG_MOUSE_PS2_SMBUS=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++CONFIG_INPUT_JOYSTICK=y ++# CONFIG_JOYSTICK_ANALOG is not set ++# CONFIG_JOYSTICK_A3D is not set ++# CONFIG_JOYSTICK_ADI is not set ++# CONFIG_JOYSTICK_COBRA is not set ++# CONFIG_JOYSTICK_GF2K is not set ++# CONFIG_JOYSTICK_GRIP is not set ++# CONFIG_JOYSTICK_GRIP_MP is not set ++# CONFIG_JOYSTICK_GUILLEMOT is not set ++# CONFIG_JOYSTICK_INTERACT is not set ++# CONFIG_JOYSTICK_SIDEWINDER is not set ++# CONFIG_JOYSTICK_TMDC is not set ++# CONFIG_JOYSTICK_IFORCE is not set ++# CONFIG_JOYSTICK_WARRIOR is not set ++# CONFIG_JOYSTICK_MAGELLAN is not set ++# CONFIG_JOYSTICK_SPACEORB is not set ++# CONFIG_JOYSTICK_SPACEBALL is not set ++# CONFIG_JOYSTICK_STINGER is not set ++# CONFIG_JOYSTICK_TWIDJOY is not set ++# CONFIG_JOYSTICK_ZHENHUA is not set ++# CONFIG_JOYSTICK_AS5011 is not set ++# CONFIG_JOYSTICK_JOYDUMP is not set ++# CONFIG_JOYSTICK_XPAD is not set ++# CONFIG_JOYSTICK_PSXPAD_SPI is not set ++# CONFIG_JOYSTICK_PXRC is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_AD714X is not set ++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set ++# CONFIG_INPUT_BMA150 is not set ++# CONFIG_INPUT_E3X0_BUTTON is not set ++# CONFIG_INPUT_MMA8450 is not set ++# CONFIG_INPUT_GP2A is not set ++# CONFIG_INPUT_GPIO_BEEPER is not set ++# CONFIG_INPUT_GPIO_DECODER is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_KXTJ9 is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++# CONFIG_INPUT_REGULATOR_HAPTIC is not set ++CONFIG_INPUT_UINPUT=y ++# CONFIG_INPUT_PCF8574 is not set ++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set ++# CONFIG_INPUT_ADXL34X is not set ++# CONFIG_INPUT_CMA3000 is not set ++# CONFIG_INPUT_DRV260X_HAPTICS is not set ++# CONFIG_INPUT_DRV2665_HAPTICS is not set ++# CONFIG_INPUT_DRV2667_HAPTICS is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_AMBAKMI is not set ++# CONFIG_SERIO_PCIPS2 is not set ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_SERIO_GPIO_PS2 is not set ++# CONFIG_USERIO is not set ++CONFIG_GAMEPORT=y ++# CONFIG_GAMEPORT_NS558 is not set ++# CONFIG_GAMEPORT_L4 is not set ++# CONFIG_GAMEPORT_EMU10K1 is not set ++# CONFIG_GAMEPORT_FM801 is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_VT_CONSOLE_SLEEP=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_LDISC_AUTOLOAD=y ++CONFIG_DEVMEM=y ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_EARLYCON=y ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_AMBA_PL010 is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_RP2 is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_DEV_BUS is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_APPLICOM is not set ++ ++# ++# PCMCIA character devices ++# ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_GPMUX is not set ++# CONFIG_I2C_MUX_LTC4306 is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_PINCTRL is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_DEMUX_PINCTRL is not set ++# CONFIG_I2C_MUX_MLXCPLD is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CADENCE is not set ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_DESIGNWARE_PCI is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++CONFIG_I2C_BSP=y ++# CONFIG_I2C_NOMADIK is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_THUNDERX is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++CONFIG_DMA_MSG_MIN_LEN=5 ++CONFIG_DMA_MSG_MAX_LEN=4090 ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++# CONFIG_SPI_MEM is not set ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++CONFIG_SPI_PL022=y ++# CONFIG_SPI_PXA2XX is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_THUNDERX is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPI_SLAVE is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++# CONFIG_PPS is not set ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_PINCTRL=y ++CONFIG_GENERIC_PINCTRL_GROUPS=y ++CONFIG_PINMUX=y ++CONFIG_GENERIC_PINMUX_FUNCTIONS=y ++CONFIG_PINCONF=y ++CONFIG_GENERIC_PINCONF=y ++# CONFIG_DEBUG_PINCTRL is not set ++# CONFIG_PINCTRL_AMD is not set ++# CONFIG_PINCTRL_MCP23S08 is not set ++CONFIG_PINCTRL_SINGLE=y ++# CONFIG_PINCTRL_SX150X is not set ++CONFIG_GPIOLIB=y ++CONFIG_GPIOLIB_FASTPATH_LIMIT=512 ++CONFIG_OF_GPIO=y ++CONFIG_GPIOLIB_IRQCHIP=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_GENERIC=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_FTGPIO010 is not set ++CONFIG_GPIO_GENERIC_PLATFORM=y ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_HLWD is not set ++# CONFIG_GPIO_MB86S7X is not set ++# CONFIG_GPIO_MOCKUP is not set ++CONFIG_GPIO_PL061=y ++# CONFIG_GPIO_SYSCON is not set ++# CONFIG_GPIO_XGENE is not set ++# CONFIG_GPIO_XILINX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++ ++# ++# MFD GPIO expanders ++# ++ ++# ++# PCI GPIO expanders ++# ++# CONFIG_GPIO_BT8XX is not set ++# CONFIG_GPIO_PCI_IDIO_16 is not set ++# CONFIG_GPIO_PCIE_IDIO_24 is not set ++# CONFIG_GPIO_RDC321X is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX3191X is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++# CONFIG_GPIO_XRA1403 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++CONFIG_POWER_RESET=y ++# CONFIG_POWER_RESET_BRCMSTB is not set ++# CONFIG_POWER_RESET_GPIO is not set ++# CONFIG_POWER_RESET_GPIO_RESTART is not set ++# CONFIG_POWER_RESET_BSP is not set ++# CONFIG_POWER_RESET_LTC2952 is not set ++# CONFIG_POWER_RESET_RESTART is not set ++# CONFIG_POWER_RESET_XGENE is not set ++# CONFIG_POWER_RESET_SYSCON is not set ++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set ++# CONFIG_SYSCON_REBOOT_MODE is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_CHARGER_ADP5061 is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_CHARGER_SBS is not set ++# CONFIG_MANAGER_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_MANAGER is not set ++# CONFIG_CHARGER_LTC3651 is not set ++# CONFIG_CHARGER_DETECTOR_MAX14656 is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_CHARGER_RT9455 is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++CONFIG_MFD_CORE=y ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_BD9571MWV is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_MADERA is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++CONFIG_MFD_BSP_FMC=y ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_LPC_ICH is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_CPCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++CONFIG_MFD_SYSCON=y ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_TI_LMU is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TI_LP87565 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_MFD_ROHM_BD718XX is not set ++CONFIG_REGULATOR=y ++# CONFIG_REGULATOR_DEBUG is not set ++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set ++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set ++# CONFIG_REGULATOR_88PG86X is not set ++# CONFIG_REGULATOR_ACT8865 is not set ++# CONFIG_REGULATOR_AD5398 is not set ++# CONFIG_REGULATOR_ANATOP is not set ++# CONFIG_REGULATOR_DA9210 is not set ++# CONFIG_REGULATOR_DA9211 is not set ++# CONFIG_REGULATOR_FAN53555 is not set ++# CONFIG_REGULATOR_GPIO is not set ++# CONFIG_REGULATOR_ISL9305 is not set ++# CONFIG_REGULATOR_ISL6271A is not set ++# CONFIG_REGULATOR_LP3971 is not set ++# CONFIG_REGULATOR_LP3972 is not set ++# CONFIG_REGULATOR_LP872X is not set ++# CONFIG_REGULATOR_LP8755 is not set ++# CONFIG_REGULATOR_LTC3589 is not set ++# CONFIG_REGULATOR_LTC3676 is not set ++# CONFIG_REGULATOR_MAX1586 is not set ++# CONFIG_REGULATOR_MAX8649 is not set ++# CONFIG_REGULATOR_MAX8660 is not set ++# CONFIG_REGULATOR_MAX8952 is not set ++# CONFIG_REGULATOR_MT6311 is not set ++# CONFIG_REGULATOR_PFUZE100 is not set ++# CONFIG_REGULATOR_PV88060 is not set ++# CONFIG_REGULATOR_PV88080 is not set ++# CONFIG_REGULATOR_PV88090 is not set ++# CONFIG_REGULATOR_SY8106A is not set ++# CONFIG_REGULATOR_TPS51632 is not set ++# CONFIG_REGULATOR_TPS62360 is not set ++# CONFIG_REGULATOR_TPS65023 is not set ++# CONFIG_REGULATOR_TPS6507X is not set ++# CONFIG_REGULATOR_TPS65132 is not set ++# CONFIG_REGULATOR_TPS6524X is not set ++# CONFIG_REGULATOR_VCTRL is not set ++# CONFIG_RC_CORE is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CEC_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++ ++# ++# Media drivers ++# ++CONFIG_MEDIA_USB_SUPPORT=y ++ ++# ++# Webcam devices ++# ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=m ++# CONFIG_USB_M5602 is not set ++# CONFIG_USB_STV06XX is not set ++# CONFIG_USB_GL860 is not set ++# CONFIG_USB_GSPCA_BENQ is not set ++# CONFIG_USB_GSPCA_CONEX is not set ++# CONFIG_USB_GSPCA_CPIA1 is not set ++# CONFIG_USB_GSPCA_DTCS033 is not set ++# CONFIG_USB_GSPCA_ETOMS is not set ++# CONFIG_USB_GSPCA_FINEPIX is not set ++# CONFIG_USB_GSPCA_JEILINJ is not set ++# CONFIG_USB_GSPCA_JL2005BCD is not set ++# CONFIG_USB_GSPCA_KINECT is not set ++# CONFIG_USB_GSPCA_KONICA is not set ++# CONFIG_USB_GSPCA_MARS is not set ++# CONFIG_USB_GSPCA_MR97310A is not set ++# CONFIG_USB_GSPCA_NW80X is not set ++# CONFIG_USB_GSPCA_OV519 is not set ++# CONFIG_USB_GSPCA_OV534 is not set ++# CONFIG_USB_GSPCA_OV534_9 is not set ++# CONFIG_USB_GSPCA_PAC207 is not set ++# CONFIG_USB_GSPCA_PAC7302 is not set ++# CONFIG_USB_GSPCA_PAC7311 is not set ++# CONFIG_USB_GSPCA_SE401 is not set ++# CONFIG_USB_GSPCA_SN9C2028 is not set ++# CONFIG_USB_GSPCA_SN9C20X is not set ++# CONFIG_USB_GSPCA_SONIXB is not set ++# CONFIG_USB_GSPCA_SONIXJ is not set ++# CONFIG_USB_GSPCA_SPCA500 is not set ++# CONFIG_USB_GSPCA_SPCA501 is not set ++# CONFIG_USB_GSPCA_SPCA505 is not set ++# CONFIG_USB_GSPCA_SPCA506 is not set ++# CONFIG_USB_GSPCA_SPCA508 is not set ++# CONFIG_USB_GSPCA_SPCA561 is not set ++# CONFIG_USB_GSPCA_SPCA1528 is not set ++# CONFIG_USB_GSPCA_SQ905 is not set ++# CONFIG_USB_GSPCA_SQ905C is not set ++# CONFIG_USB_GSPCA_SQ930X is not set ++# CONFIG_USB_GSPCA_STK014 is not set ++# CONFIG_USB_GSPCA_STK1135 is not set ++# CONFIG_USB_GSPCA_STV0680 is not set ++# CONFIG_USB_GSPCA_SUNPLUS is not set ++# CONFIG_USB_GSPCA_T613 is not set ++# CONFIG_USB_GSPCA_TOPRO is not set ++# CONFIG_USB_GSPCA_TOUPTEK is not set ++# CONFIG_USB_GSPCA_TV8532 is not set ++# CONFIG_USB_GSPCA_VC032X is not set ++# CONFIG_USB_GSPCA_VICAM is not set ++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set ++# CONFIG_USB_GSPCA_ZC3XX is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++# CONFIG_VIDEO_USBTV is not set ++ ++# ++# Webcam, TV (analog/digital) USB devices ++# ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_MEDIA_PCI_SUPPORT is not set ++CONFIG_V4L_PLATFORM_DRIVERS=y ++# CONFIG_VIDEO_CAFE_CCIC is not set ++# CONFIG_VIDEO_CADENCE is not set ++# CONFIG_SOC_CAMERA is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++CONFIG_VIDEOBUF2_CORE=y ++CONFIG_VIDEOBUF2_V4L2=y ++CONFIG_VIDEOBUF2_MEMOPS=y ++CONFIG_VIDEOBUF2_VMALLOC=y ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# SDR tuner chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Media SPI Adapters ++# ++ ++# ++# Tools to develop new frontends ++# ++ ++# ++# Graphics support ++# ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 ++# CONFIG_DRM is not set ++# CONFIG_DRM_DP_CEC is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# AMD Library routines ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_ARMCLCD is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_I740 is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_FB_SM712 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_DUMMY_CONSOLE_COLUMNS=80 ++CONFIG_DUMMY_CONSOLE_ROWS=25 ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_OSSEMUL is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_CTXFI is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_LOLA is not set ++# CONFIG_SND_LX6464ES is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SE6X is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_HDA_INTEL is not set ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_A4TECH=y ++# CONFIG_HID_ACCUTOUCH is not set ++# CONFIG_HID_ACRUX is not set ++CONFIG_HID_APPLE=y ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++CONFIG_HID_BELKIN=y ++# CONFIG_HID_BETOP_FF is not set ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++# CONFIG_HID_COUGAR is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CMEDIA is not set ++CONFIG_HID_CYPRESS=y ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++CONFIG_HID_EZKEY=y ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_ITE is not set ++# CONFIG_HID_JABRA is not set ++# CONFIG_HID_TWINHAN is not set ++CONFIG_HID_KENSINGTON=y ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++CONFIG_HID_LOGITECH=y ++# CONFIG_HID_LOGITECH_HIDPP is not set ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++# CONFIG_LOGIG940_FF is not set ++# CONFIG_LOGIWHEELS_FF is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MAYFLASH is not set ++# CONFIG_HID_REDRAGON is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTI is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_RETRODE is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEAM is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_UDRAW_PS3 is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_PCI=y ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_XHCI_HCD=y ++# CONFIG_USB_XHCI_DBGCAP is not set ++CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_XHCI_PLATFORM=y ++# CONFIG_USB_EHCI_HCD is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++ ++# ++# Platform Glue Driver Support ++# ++# CONFIG_USB_DWC3_HAPS is not set ++# CONFIG_USB_DWC3_OF_SIMPLE is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HUB_USB251XB is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++# CONFIG_U_SERIAL_CONSOLE is not set ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_SNP_UDC_PLAT is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_AMD5536UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_NET2280 is not set ++# CONFIG_USB_GOKU is not set ++# CONFIG_USB_EG20T is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=y ++CONFIG_USB_F_ACM=y ++CONFIG_USB_U_SERIAL=y ++CONFIG_USB_U_ETHER=y ++CONFIG_USB_U_AUDIO=y ++CONFIG_USB_F_RNDIS=y ++CONFIG_USB_F_MASS_STORAGE=y ++CONFIG_USB_F_UAC1=y ++CONFIG_USB_F_UVC=y ++CONFIG_USB_CONFIGFS=y ++# CONFIG_USB_CONFIGFS_SERIAL is not set ++CONFIG_USB_CONFIGFS_ACM=y ++# CONFIG_USB_CONFIGFS_OBEX is not set ++# CONFIG_USB_CONFIGFS_NCM is not set ++# CONFIG_USB_CONFIGFS_ECM is not set ++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set ++CONFIG_USB_CONFIGFS_RNDIS=y ++# CONFIG_USB_CONFIGFS_EEM is not set ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++# CONFIG_USB_CONFIGFS_F_LB_SS is not set ++# CONFIG_USB_CONFIGFS_F_FS is not set ++CONFIG_USB_CONFIGFS_F_UAC1=y ++# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set ++# CONFIG_USB_CONFIGFS_F_UAC2 is not set ++# CONFIG_USB_CONFIGFS_F_MIDI is not set ++# CONFIG_USB_CONFIGFS_F_HID is not set ++CONFIG_USB_CONFIGFS_F_UVC=y ++# CONFIG_USB_CONFIGFS_F_PRINTER is not set ++CONFIG_MPP_TO_GADGET_UVC=y ++# CONFIG_TYPEC is not set ++# CONFIG_USB_ROLE_SWITCH is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_ARMMMCI is not set ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_IO_ACCESSORS=y ++# CONFIG_MMC_SDHCI_PCI is not set ++CONFIG_MMC_SDHCI_PLTFM=y ++# CONFIG_MMC_SDHCI_OF_ARASAN is not set ++# CONFIG_MMC_SDHCI_OF_AT91 is not set ++# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set ++# CONFIG_MMC_SDHCI_CADENCE is not set ++CONFIG_MMC_SDHCI_BSP=y ++# CONFIG_MMC_SDHCI_F_SDH30 is not set ++# CONFIG_MMC_TIFM_SD is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_CB710 is not set ++# CONFIG_MMC_VIA_SDMMC is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_CQHCI is not set ++# CONFIG_MMC_TOSHIBA_PCI is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MMC_SDHCI_XENON is not set ++# CONFIG_MMC_SDHCI_OMAP is not set ++# CONFIG_MMC_CQ_HCI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_EDAC_SUPPORT=y ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++CONFIG_RTC_NVMEM=y ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12026 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF85363 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_BSP is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_PL030 is not set ++# CONFIG_RTC_DRV_PL031 is not set ++# CONFIG_RTC_DRV_FTRTC010 is not set ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_R7301 is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set ++ ++# ++# DMA Devices ++# ++CONFIG_DMA_ENGINE=y ++CONFIG_DMA_VIRTUAL_CHANNELS=y ++CONFIG_DMA_OF=y ++# CONFIG_ALTERA_MSGDMA is not set ++# CONFIG_AMBA_PL08X is not set ++# CONFIG_DW_AXI_DMAC is not set ++# CONFIG_FSL_EDMA is not set ++# CONFIG_INTEL_IDMA64 is not set ++CONFIG_EDMACV310=y ++# CONFIG_MV_XOR_V2 is not set ++# CONFIG_PL330_DMA is not set ++# CONFIG_XILINX_DMA is not set ++# CONFIG_XILINX_ZYNQMP_DMA is not set ++# CONFIG_QCOM_HIDMA_MGMT is not set ++# CONFIG_QCOM_HIDMA is not set ++# CONFIG_DW_DMAC is not set ++# CONFIG_DW_DMAC_PCI is not set ++ ++# ++# DMA Clients ++# ++# CONFIG_ASYNC_TX_DMA is not set ++# CONFIG_DMATEST is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VFIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++# CONFIG_VIRTIO_MENU is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_VERSATILE is not set ++# CONFIG_CLK_HSDK is not set ++# CONFIG_COMMON_CLK_MAX9485 is not set ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI544 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_XGENE is not set ++# CONFIG_COMMON_CLK_VC5 is not set ++CONFIG_COMMON_CLK_SS928V100=y ++CONFIG_RESET_BSP=y ++# CONFIG_HWSPINLOCK is not set ++ ++# ++# Clock Source drivers ++# ++CONFIG_TIMER_OF=y ++CONFIG_TIMER_PROBE=y ++CONFIG_CLKSRC_MMIO=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y ++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set ++# CONFIG_FSL_ERRATUM_A008585 is not set ++CONFIG_HISILICON_ERRATUM_161010101=y ++CONFIG_ARM64_ERRATUM_858921=y ++CONFIG_ARM_TIMER_SP804=y ++# CONFIG_TIMER_BSP_SP804 is not set ++# CONFIG_MAILBOX is not set ++CONFIG_IOMMU_API=y ++CONFIG_IOMMU_SUPPORT=y ++ ++# ++# Generic IOMMU Pagetable Support ++# ++CONFIG_IOMMU_IO_PGTABLE=y ++CONFIG_IOMMU_IO_PGTABLE_LPAE=y ++# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set ++# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set ++ ++# ++# Generic PASID table support ++# ++CONFIG_IOMMU_PASID_TABLE=y ++CONFIG_ARM_SMMU_V3_CONTEXT=y ++# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set ++CONFIG_IOMMU_IOVA=y ++CONFIG_OF_IOMMU=y ++CONFIG_IOMMU_DMA=y ++CONFIG_IOMMU_SVA=y ++CONFIG_IOMMU_PAGE_FAULT=y ++# CONFIG_ARM_SMMU is not set ++CONFIG_ARM_SMMU_V3=y ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_REMOTEPROC is not set ++ ++# ++# Rpmsg drivers ++# ++# CONFIG_RPMSG_VIRTIO is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Amlogic SoC drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++ ++# ++# NXP/Freescale QorIQ SoC drivers ++# ++ ++# ++# i.MX SoC drivers ++# ++ ++# ++# Qualcomm SoC drivers ++# ++# CONFIG_SOC_TI is not set ++ ++# ++# Xilinx SoC drivers ++# ++# CONFIG_XILINX_VCU is not set ++CONFIG_PM_DEVFREQ=y ++ ++# ++# DEVFREQ Governors ++# ++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y ++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set ++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set ++# CONFIG_DEVFREQ_GOV_USERSPACE is not set ++# CONFIG_DEVFREQ_GOV_PASSIVE is not set ++ ++# ++# DEVFREQ Drivers ++# ++# CONFIG_PM_DEVFREQ_EVENT is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_NTB is not set ++# CONFIG_VME_BUS is not set ++# CONFIG_PWM is not set ++ ++# ++# IRQ chip support ++# ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++CONFIG_ARM_GIC_V2M=y ++CONFIG_ARM_GIC_V3=y ++CONFIG_ARM_GIC_V3_ITS=y ++CONFIG_ARM_GIC_V3_ITS_PCI=y ++CONFIG_HISILICON_IRQ_MBIGEN=y ++CONFIG_PARTITION_PERCPU=y ++# CONFIG_IPACK_BUS is not set ++CONFIG_RESET_CONTROLLER=y ++# CONFIG_RESET_TI_SYSCON is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_XGENE is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_PHY_MAPPHONE_MDM6600 is not set ++CONFIG_VENDOR_USB_PHY=y ++CONFIG_PHY_BSP_USB3=y ++CONFIG_BSP_USB_PHY=y ++CONFIG_USB_MODE_OPTION=y ++# CONFIG_USB_DRD0_IN_HOST is not set ++CONFIG_USB_DRD0_IN_DEVICE=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++# CONFIG_RAS is not set ++# CONFIG_LIBNVDIMM is not set ++# CONFIG_DAX is not set ++CONFIG_NVMEM=y ++ ++# ++# HW tracing support ++# ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++# CONFIG_FPGA is not set ++# CONFIG_FSI is not set ++# CONFIG_TEE is not set ++CONFIG_PM_OPP=y ++# CONFIG_SIOX is not set ++# CONFIG_SLIMBUS is not set ++ ++# ++# Vendor driver support ++# ++# CONFIG_CMA_MEM_SHARED is not set ++# CONFIG_CMA_ADVANCE_SHARE is not set ++CONFIG_VENDOR_NPU=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++CONFIG_FS_IOMAP=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT2=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++# CONFIG_EXT4_ENCRYPTION is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_XFS_FS=y ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++# CONFIG_XFS_ONLINE_SCRUB is not set ++# CONFIG_XFS_WARN is not set ++# CONFIG_XFS_DEBUG is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++# CONFIG_FS_DAX is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_EXPORTFS=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++CONFIG_QUOTA=y ++# CONFIG_QUOTA_NETLINK_INTERFACE is not set ++CONFIG_PRINT_QUOTA_WARNING=y ++# CONFIG_QUOTA_DEBUG is not set ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS4_FS=m ++CONFIG_AUTOFS_FS=m ++CONFIG_FUSE_FS=y ++# CONFIG_CUSE is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLBFS is not set ++CONFIG_MEMFD_CREATE=y ++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++CONFIG_JFFS2_RTIME=y ++CONFIG_UBIFS_FS=y ++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++CONFIG_UBIFS_FS_XATTR=y ++# CONFIG_UBIFS_FS_ENCRYPTION is not set ++CONFIG_UBIFS_FS_SECURITY=y ++CONFIG_CRAMFS=y ++CONFIG_CRAMFS_BLOCKDEV=y ++# CONFIG_CRAMFS_MTD is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++# CONFIG_SQUASHFS_ZSTD is not set ++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set ++# CONFIG_SQUASHFS_EMBEDDED is not set ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V2=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=y ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=y ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++# CONFIG_HARDENED_USERCOPY is not set ++# CONFIG_FORTIFY_SOURCE is not set ++# CONFIG_STATIC_USERMODEHELPER is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=m ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=m ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++CONFIG_CRYPTO_ACOMP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=m ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_CCM=m ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++# CONFIG_CRYPTO_AEGIS128 is not set ++# CONFIG_CRYPTO_AEGIS128L is not set ++# CONFIG_CRYPTO_AEGIS256 is not set ++# CONFIG_CRYPTO_MORUS640 is not set ++# CONFIG_CRYPTO_MORUS1280 is not set ++CONFIG_CRYPTO_SEQIV=m ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CFB is not set ++CONFIG_CRYPTO_CTR=m ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=m ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_SM3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_TI is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_SM4 is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++# CONFIG_CRYPTO_ZSTD is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=m ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=m ++CONFIG_CRYPTO_JITTERENTROPY=m ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_CCP is not set ++# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set ++# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set ++# CONFIG_CRYPTO_DEV_CCREE is not set ++# CONFIG_CRYPTO_DEV_HISI_SEC is not set ++ ++# ++# Certificates for signature checking ++# ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++CONFIG_ARCH_HAS_FAST_MULTIPLIER=y ++# CONFIG_INDIRECT_PIO is not set ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC64 is not set ++# CONFIG_CRC4 is not set ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++# CONFIG_CRC8 is not set ++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_NEED_SG_DMA_LENGTH=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_DMA_ADDR_T_64BIT=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_DMA_DIRECT_OPS=y ++CONFIG_SWIOTLB=y ++CONFIG_SGL_ALLOC=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_STRING_SELFTEST is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 ++CONFIG_CONSOLE_LOGLEVEL_QUIET=4 ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=2048 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++CONFIG_ARCH_WANT_FRAME_POINTERS=y ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 ++CONFIG_MAGIC_SYSRQ_SERIAL=y ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_RODATA_TEST is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y ++# CONFIG_DEBUG_VIRTUAL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++CONFIG_ARCH_HAS_KCOV=y ++CONFIG_CC_HAS_SANCOV_TRACE_PC=y ++# CONFIG_KCOV is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_SOFTLOCKUP_DETECTOR is not set ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_WQ_WATCHDOG is not set ++CONFIG_PANIC_ON_OOPS=y ++CONFIG_PANIC_ON_OOPS_VALUE=1 ++CONFIG_PANIC_TIMEOUT=0 ++CONFIG_SCHED_DEBUG=y ++CONFIG_SCHED_INFO=y ++CONFIG_SCHEDSTATS=y ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_LOCK_DEBUGGING_SUPPORT=y ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_RWSEMS is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_WW_MUTEX_SELFTEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_HAVE_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=60 ++CONFIG_RCU_TRACE=y ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACE_CLOCK=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++# CONFIG_DMA_API_DEBUG is not set ++CONFIG_RUNTIME_TESTING_MENU=y ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_TEST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_BITFIELD is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_OVERFLOW is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_TEST_IDA is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_FIND_BIT_BENCHMARK is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_SYSCTL is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_TEST_KMOD is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_BUG_ON_DATA_CORRUPTION is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM64_PTDUMP_DEBUGFS is not set ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set ++# CONFIG_DEBUG_WX is not set ++# CONFIG_DEBUG_ALIGN_RODATA is not set ++# CONFIG_ARM64_RELOC_TEST is not set ++# CONFIG_CORESIGHT is not set +diff --git a/arch/arm64/configs/ss928v100_emmc_defconfig b/arch/arm64/configs/ss928v100_emmc_defconfig +new file mode 100644 +index 000000000000..0f7a1e6d102c +--- /dev/null ++++ b/arch/arm64/configs/ss928v100_emmc_defconfig +@@ -0,0 +1,4137 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm64 4.19.90 Kernel Configuration ++# ++ ++# ++# Compiler: aarch64-mix210-linux-gcc (20220321) 7.3.0 ++# ++CONFIG_CC_IS_GCC=y ++CONFIG_GCC_VERSION=70300 ++CONFIG_CLANG_VERSION=0 ++CONFIG_CC_HAS_ASM_GOTO=y ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++CONFIG_THREAD_INFO_IN_TASK=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_BUILD_SALT="" ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y ++CONFIG_GENERIC_IRQ_MIGRATION=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_GENERIC_MSI_IRQ=y ++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++# CONFIG_GENERIC_IRQ_DEBUGFS is not set ++CONFIG_GENERIC_IRQ_MULTI_HANDLER=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_HZ_PERIODIC=y ++# CONFIG_NO_HZ_IDLE is not set ++# CONFIG_NO_HZ_FULL is not set ++# CONFIG_NO_HZ is not set ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_PREEMPT_NONE=y ++# CONFIG_PREEMPT_VOLUNTARY is not set ++# CONFIG_PREEMPT is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++CONFIG_CPU_ISOLATION=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++CONFIG_TREE_SRCU=y ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_NEED_SEGCBLIST=y ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y ++CONFIG_ARCH_SUPPORTS_INT128=y ++CONFIG_CGROUPS=y ++# CONFIG_MEMCG is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_CGROUP_PIDS is not set ++# CONFIG_CGROUP_RDMA is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_CGROUP_BPF is not set ++# CONFIG_CGROUP_DEBUG is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_CHECKPOINT_RESTORE is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++CONFIG_RELAY=y ++# CONFIG_BLK_DEV_INITRD is not set ++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_SYSCTL_EXCEPTION_TRACE=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++# CONFIG_FHANDLE is not set ++CONFIG_POSIX_TIMERS=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_FUTEX_PI=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_MEMBARRIER=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_USERFAULTFD=y ++CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y ++CONFIG_RSEQ=y ++# CONFIG_DEBUG_RSEQ is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++# CONFIG_PC104 is not set ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++CONFIG_SLAB_MERGE_DEFAULT=y ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SLAB_FREELIST_HARDENED is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++CONFIG_SYSTEM_DATA_VERIFICATION=y ++# CONFIG_PROFILING is not set ++CONFIG_ARM64=y ++CONFIG_64BIT=y ++CONFIG_MMU=y ++CONFIG_ARM64_PAGE_SHIFT=12 ++CONFIG_ARM64_CONT_SHIFT=4 ++CONFIG_ARCH_MMAP_RND_BITS_MIN=18 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=24 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_BUG=y ++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CSUM=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA32=y ++CONFIG_HAVE_GENERIC_GUP=y ++CONFIG_SMP=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_PGTABLE_LEVELS=3 ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_ARCH_PROC_KCORE_TEXT=y ++ ++# ++# Platform selection ++# ++# CONFIG_ARCH_ACTIONS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_BCM2835 is not set ++# CONFIG_ARCH_BCM_IPROC is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_BRCMSTB is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_K3 is not set ++# CONFIG_ARCH_LAYERSCAPE is not set ++# CONFIG_ARCH_LG1K is not set ++# CONFIG_ARCH_HISI is not set ++CONFIG_ARCH_BSP=y ++# CONFIG_ARCH_SS528V100 is not set ++# CONFIG_ARCH_SS625V100 is not set ++# CONFIG_ARCH_SS919V100 is not set ++# CONFIG_ARCH_SS015V100 is not set ++CONFIG_ARCH_SS928V100=y ++# CONFIG_ARCH_SS927V100 is not set ++# CONFIG_ARCH_MEDIATEK is not set ++# CONFIG_ARCH_MESON is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALTEK is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SEATTLE is not set ++# CONFIG_ARCH_SYNQUACER is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_STRATIX10 is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_SPRD is not set ++# CONFIG_ARCH_THUNDER is not set ++# CONFIG_ARCH_THUNDER2 is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_XGENE is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQMP is not set ++ ++# ++# Bus support ++# ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++CONFIG_PCI_DOMAINS_GENERIC=y ++CONFIG_PCI_SYSCALL=y ++CONFIG_PCIEPORTBUS=y ++# CONFIG_PCIEAER is not set ++# CONFIG_PCIEASPM is not set ++CONFIG_PCIE_PME=y ++# CONFIG_PCIE_PTM is not set ++CONFIG_PCI_MSI=y ++CONFIG_PCI_MSI_IRQ_DOMAIN=y ++CONFIG_PCI_QUIRKS=y ++# CONFIG_PCI_DEBUG is not set ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++# CONFIG_PCI_PRI is not set ++# CONFIG_PCI_PASID is not set ++# CONFIG_HOTPLUG_PCI is not set ++ ++# ++# PCI controller drivers ++# ++ ++# ++# Cadence PCIe controllers support ++# ++# CONFIG_PCIE_CADENCE_HOST is not set ++# CONFIG_PCI_FTPCI100 is not set ++# CONFIG_PCI_HOST_GENERIC is not set ++# CONFIG_PCIE_XILINX is not set ++# CONFIG_PCI_XGENE is not set ++# CONFIG_PCI_HOST_THUNDER_PEM is not set ++# CONFIG_PCI_HOST_THUNDER_ECAM is not set ++ ++# ++# DesignWare PCI Core Support ++# ++# CONFIG_PCIE_DW_PLAT_HOST is not set ++# CONFIG_PCI_HISI is not set ++# CONFIG_PCIE_KIRIN is not set ++ ++# ++# PCI Endpoint ++# ++# CONFIG_PCI_ENDPOINT is not set ++ ++# ++# PCI switch controller drivers ++# ++# CONFIG_PCI_SW_SWITCHTEC is not set ++# CONFIG_BSP_PCIE is not set ++ ++# ++# Kernel Features ++# ++ ++# ++# ARM errata workarounds via the alternatives framework ++# ++CONFIG_ARM64_ERRATUM_826319=y ++CONFIG_ARM64_ERRATUM_827319=y ++CONFIG_ARM64_ERRATUM_824069=y ++CONFIG_ARM64_ERRATUM_819472=y ++CONFIG_ARM64_ERRATUM_832075=y ++CONFIG_ARM64_ERRATUM_845719=y ++CONFIG_ARM64_ERRATUM_843419=y ++CONFIG_ARM64_ERRATUM_1024718=y ++CONFIG_ARM64_ERRATUM_1463225=y ++CONFIG_CAVIUM_ERRATUM_22375=y ++CONFIG_CAVIUM_ERRATUM_23154=y ++CONFIG_CAVIUM_ERRATUM_27456=y ++CONFIG_CAVIUM_ERRATUM_30115=y ++CONFIG_QCOM_FALKOR_ERRATUM_1003=y ++CONFIG_QCOM_FALKOR_ERRATUM_1009=y ++CONFIG_QCOM_QDF2400_ERRATUM_0065=y ++CONFIG_SOCIONEXT_SYNQUACER_PREITS=y ++CONFIG_HISILICON_ERRATUM_161600802=y ++CONFIG_QCOM_FALKOR_ERRATUM_E1041=y ++CONFIG_ARM64_4K_PAGES=y ++# CONFIG_ARM64_16K_PAGES is not set ++# CONFIG_ARM64_64K_PAGES is not set ++CONFIG_ARM64_VA_BITS_39=y ++# CONFIG_ARM64_VA_BITS_48 is not set ++CONFIG_ARM64_VA_BITS=39 ++CONFIG_ARM64_PA_BITS_48=y ++CONFIG_ARM64_PA_BITS=48 ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_SCHED_MC=y ++# CONFIG_SCHED_SMT is not set ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_NUMA is not set ++CONFIG_HOLES_IN_ZONE=y ++CONFIG_HZ_100=y ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y ++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_ARCH_SPARSEMEM_DEFAULT=y ++CONFIG_ARCH_SELECT_MEMORY_MODEL=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_SYS_SUPPORTS_HUGETLBFS=y ++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y ++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y ++# CONFIG_SECCOMP is not set ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++# CONFIG_XEN is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_UNMAP_KERNEL_AT_EL0=y ++CONFIG_HARDEN_BRANCH_PREDICTOR=y ++CONFIG_HARDEN_EL2_VECTORS=y ++CONFIG_ARM64_SSBD=y ++# CONFIG_ARMV8_DEPRECATED is not set ++# CONFIG_ARM64_SW_TTBR0_PAN is not set ++ ++# ++# ARMv8.1 architectural features ++# ++CONFIG_ARM64_HW_AFDBM=y ++CONFIG_ARM64_PAN=y ++# CONFIG_ARM64_LSE_ATOMICS is not set ++CONFIG_ARM64_VHE=y ++ ++# ++# ARMv8.2 architectural features ++# ++CONFIG_ARM64_UAO=y ++# CONFIG_ARM64_PMEM is not set ++CONFIG_ARM64_RAS_EXTN=y ++CONFIG_ARM64_SVE=y ++CONFIG_ARM64_MODULE_PLTS=y ++# CONFIG_RANDOMIZE_BASE is not set ++ ++# ++# Boot options ++# ++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox" ++# CONFIG_CMDLINE_FORCE is not set ++# CONFIG_EFI is not set ++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y ++CONFIG_IMG_GZ_DTB=y ++# CONFIG_IMG_DTB is not set ++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb" ++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="vendor/ss928v100-demb-emmc" ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++# CONFIG_PM_WAKELOCKS is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++CONFIG_CPUFREQ_DT=y ++CONFIG_CPUFREQ_DT_PLATDEV=y ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# Firmware Drivers ++# ++CONFIG_ARM_PSCI_FW=y ++# CONFIG_ARM_SDE_INTERFACE is not set ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++# CONFIG_GOOGLE_FIRMWARE is not set ++ ++# ++# Tegra firmware driver ++# ++# CONFIG_VIRTUALIZATION is not set ++# CONFIG_ARM64_CRYPTO is not set ++ ++# ++# General architecture-dependent options ++# ++# CONFIG_KPROBES is not set ++# CONFIG_JUMP_LABEL is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y ++CONFIG_ARCH_HAS_SET_MEMORY=y ++CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_RSEQ=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_HAVE_RCU_TABLE_FREE=y ++CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y ++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y ++CONFIG_HAVE_CMPXCHG_LOCAL=y ++CONFIG_HAVE_CMPXCHG_DOUBLE=y ++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_STACKPROTECTOR=y ++CONFIG_CC_HAS_STACKPROTECTOR_NONE=y ++CONFIG_STACKPROTECTOR=y ++CONFIG_STACKPROTECTOR_STRONG=y ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y ++CONFIG_HAVE_ARCH_HUGE_VMAP=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_ARCH_MMAP_RND_BITS=18 ++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_COMPAT_OLD_SIGACTION=y ++CONFIG_COMPAT_32BIT_TIME=y ++CONFIG_HAVE_ARCH_VMAP_STACK=y ++CONFIG_VMAP_STACK=y ++CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y ++CONFIG_STRICT_KERNEL_RWX=y ++CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y ++CONFIG_STRICT_MODULE_RWX=y ++CONFIG_REFCOUNT_FULL=y ++CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_PLUGIN_HOSTCC="" ++CONFIG_HAVE_GCC_PLUGINS=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++CONFIG_BLK_SCSI_REQUEST=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_DEV_ZONED is not set ++CONFIG_BLK_CMDLINE_PARSER=y ++# CONFIG_BLK_WBT is not set ++CONFIG_BLK_DEBUG_FS=y ++# CONFIG_BLK_SED_OPAL is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_AIX_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_CMDLINE_PARTITION=y ++CONFIG_BLOCK_COMPAT=y ++CONFIG_BLK_MQ_PCI=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_CFQ is not set ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_MQ_IOSCHED_DEADLINE=y ++CONFIG_MQ_IOSCHED_KYBER=y ++# CONFIG_IOSCHED_BFQ is not set ++CONFIG_ASN1=y ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_READ_LOCK=y ++CONFIG_ARCH_INLINE_READ_LOCK_BH=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_READ_UNLOCK=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_WRITE_LOCK=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_SPIN_TRYLOCK=y ++CONFIG_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK=y ++CONFIG_INLINE_SPIN_LOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_READ_LOCK=y ++CONFIG_INLINE_READ_LOCK_BH=y ++CONFIG_INLINE_READ_LOCK_IRQ=y ++CONFIG_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_INLINE_READ_UNLOCK=y ++CONFIG_INLINE_READ_UNLOCK_BH=y ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_WRITE_LOCK=y ++CONFIG_INLINE_WRITE_LOCK_BH=y ++CONFIG_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_INLINE_WRITE_UNLOCK=y ++CONFIG_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y ++CONFIG_QUEUED_SPINLOCKS=y ++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y ++CONFIG_QUEUED_RWLOCKS=y ++CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y ++CONFIG_FREEZER=y ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_COMPAT_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Memory Management options ++# ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_EXTREME=y ++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y ++CONFIG_SPARSEMEM_VMEMMAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_MMU_NOTIFIER=y ++CONFIG_KSM=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y ++# CONFIG_MEMORY_FAILURE is not set ++# CONFIG_TRANSPARENT_HUGEPAGE is not set ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++# CONFIG_CMA_DEBUGFS is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++# CONFIG_PERCPU_STATS is not set ++# CONFIG_GUP_BENCHMARK is not set ++CONFIG_ARCH_HAS_PTE_SPECIAL=y ++CONFIG_NET=y ++CONFIG_COMPAT_NETLINK_MESSAGES=y ++CONFIG_NET_INGRESS=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_TLS is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_INTERFACE is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_XDP_SOCKETS is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++# CONFIG_IP_PNP_BOOTP is not set ++# CONFIG_IP_PNP_RARP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++CONFIG_NET_IP_TUNNEL=m ++# CONFIG_IP_MROUTE is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_NET_FOU_IP_TUNNELS is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_INET_RAW_DIAG is not set ++# CONFIG_INET_DIAG_DESTROY is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=y ++CONFIG_IPV6_ROUTER_PREF=y ++# CONFIG_IPV6_ROUTE_INFO is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++# CONFIG_IPV6_ILA is not set ++CONFIG_INET6_XFRM_MODE_TRANSPORT=m ++CONFIG_INET6_XFRM_MODE_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_BEET=m ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++# CONFIG_IPV6_VTI is not set ++CONFIG_IPV6_SIT=m ++# CONFIG_IPV6_SIT_6RD is not set ++CONFIG_IPV6_NDISC_NODETYPE=y ++# CONFIG_IPV6_TUNNEL is not set ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_IPV6_SEG6_LWTUNNEL is not set ++# CONFIG_IPV6_SEG6_HMAC is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++CONFIG_NETFILTER=y ++CONFIG_NETFILTER_ADVANCED=y ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_INGRESS=y ++# CONFIG_NETFILTER_NETLINK_ACCT is not set ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NETFILTER_NETLINK_OSF is not set ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NF_LOG_NETDEV is not set ++# CONFIG_NF_TABLES is not set ++# CONFIG_NETFILTER_XTABLES is not set ++# CONFIG_IP_SET is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV4 is not set ++# CONFIG_NF_TPROXY_IPV4 is not set ++# CONFIG_NF_DUP_IPV4 is not set ++# CONFIG_NF_LOG_ARP is not set ++# CONFIG_NF_LOG_IPV4 is not set ++# CONFIG_NF_REJECT_IPV4 is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++ ++# ++# IPv6: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV6 is not set ++# CONFIG_NF_TPROXY_IPV6 is not set ++# CONFIG_NF_DUP_IPV6 is not set ++# CONFIG_NF_REJECT_IPV6 is not set ++# CONFIG_NF_LOG_IPV6 is not set ++# CONFIG_IP6_NF_IPTABLES is not set ++# CONFIG_BPFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_6LOWPAN is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_NET_NSH is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++# CONFIG_BPF_STREAM_PARSER is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_SPY=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=y ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y ++CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y ++# CONFIG_CFG80211_DEFAULT_PS is not set ++CONFIG_CFG80211_DEBUGFS=y ++# CONFIG_CFG80211_CRDA_SUPPORT is not set ++CONFIG_CFG80211_WEXT=y ++# CONFIG_MAC80211 is not set ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_PSAMPLE is not set ++# CONFIG_NET_IFE is not set ++# CONFIG_LWTUNNEL is not set ++CONFIG_DST_CACHE=y ++CONFIG_GRO_CELLS=y ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++# CONFIG_FAILOVER is not set ++CONFIG_HAVE_EBPF_JIT=y ++ ++# ++# Device Drivers ++# ++CONFIG_ARM_AMBA=y ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++ ++# ++# Firmware loader ++# ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set ++CONFIG_GENERIC_CPU_AUTOPROBE=y ++CONFIG_GENERIC_CPU_VULNERABILITIES=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_REGMAP_MMIO=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_DMA_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=4 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++CONFIG_GENERIC_ARCH_TOPOLOGY=y ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_SIMPLE_PM_BUS is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_GNSS is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_KOBJ=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SKD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=65536 ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++# CONFIG_BLK_DEV_RSXX is not set ++ ++# ++# NVME Support ++# ++# CONFIG_BLK_DEV_NVME is not set ++# CONFIG_NVME_FC is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_PCI_ENDPOINT_TEST is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++# CONFIG_EEPROM_IDT_89HPESX is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC & related support ++# ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_GENWQE is not set ++# CONFIG_ECHO is not set ++# CONFIG_MISC_RTSX_PCI is not set ++# CONFIG_MISC_RTSX_USB is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_CXGB3_ISCSI is not set ++# CONFIG_SCSI_CXGB4_ISCSI is not set ++# CONFIG_SCSI_BNX2_ISCSI is not set ++# CONFIG_BE2ISCSI is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_HPSA is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_3W_SAS is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_MVUMI is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_SCSI_ESAS2R is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_MPT3SAS is not set ++# CONFIG_SCSI_MPT2SAS is not set ++# CONFIG_SCSI_SMARTPQI is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_SCSI_SNIC is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_AM53C974 is not set ++# CONFIG_SCSI_WD719X is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_PMCRAID is not set ++# CONFIG_SCSI_PM8001 is not set ++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_HAVE_PATA_PLATFORM=y ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_FIREWIRE_NOSY is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++CONFIG_NET_CORE=y ++# CONFIG_BONDING is not set ++# CONFIG_DUMMY is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NET_TEAM is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_IPVLAN is not set ++# CONFIG_VXLAN is not set ++# CONFIG_GENEVE is not set ++# CONFIG_GTP is not set ++# CONFIG_MACSEC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_TUN is not set ++# CONFIG_TUN_VNET_CROSS_LE is not set ++# CONFIG_VETH is not set ++# CONFIG_NLMON is not set ++# CONFIG_ARCNET is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++CONFIG_ETHERNET=y ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++# CONFIG_NET_VENDOR_AGERE is not set ++# CONFIG_NET_VENDOR_ALACRITECH is not set ++# CONFIG_NET_VENDOR_ALTEON is not set ++# CONFIG_ALTERA_TSE is not set ++# CONFIG_NET_VENDOR_AMAZON is not set ++# CONFIG_NET_VENDOR_AMD is not set ++# CONFIG_NET_VENDOR_AQUANTIA is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_VENDOR_ATHEROS is not set ++# CONFIG_NET_VENDOR_AURORA is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_BROCADE is not set ++# CONFIG_NET_VENDOR_CADENCE is not set ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++# CONFIG_NET_VENDOR_CORTINA is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_VENDOR_DEC is not set ++# CONFIG_NET_VENDOR_DLINK is not set ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++# CONFIG_NET_VENDOR_HISILICON is not set ++# CONFIG_NET_VENDOR_HP is not set ++# CONFIG_NET_VENDOR_HUAWEI is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++CONFIG_NET_VENDOR_BSP=y ++# CONFIG_BSP_FEMAC is not set ++CONFIG_ETH_GMAC=y ++CONFIG_GMAC_DDR_64BIT=y ++CONFIG_GMAC_DESC_4WORD=y ++CONFIG_GMAC_RXCSUM=y ++CONFIG_RX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF ++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF ++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16 ++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32 ++# CONFIG_JME is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MELLANOX is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_MICROSEMI is not set ++# CONFIG_NET_VENDOR_MYRI is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_NETERION is not set ++# CONFIG_NET_VENDOR_NETRONOME is not set ++# CONFIG_NET_VENDOR_NI is not set ++# CONFIG_NET_VENDOR_NVIDIA is not set ++# CONFIG_NET_VENDOR_OKI is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_PACKET_ENGINES is not set ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++# CONFIG_NET_VENDOR_RDC is not set ++# CONFIG_NET_VENDOR_REALTEK is not set ++# CONFIG_NET_VENDOR_RENESAS is not set ++# CONFIG_NET_VENDOR_ROCKER is not set ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SOLARFLARE is not set ++# CONFIG_NET_VENDOR_SILAN is not set ++# CONFIG_NET_VENDOR_SIS is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_SOCIONEXT is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++# CONFIG_NET_VENDOR_SUN is not set ++# CONFIG_NET_VENDOR_SYNOPSYS is not set ++# CONFIG_NET_VENDOR_TEHUTI is not set ++# CONFIG_NET_VENDOR_TI is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_MDIO_DEVICE=y ++CONFIG_MDIO_BUS=y ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++# CONFIG_MDIO_BSP_FEMAC is not set ++CONFIG_MDIO_BSP_GEMAC=y ++# CONFIG_MDIO_MSCC_MIIM is not set ++# CONFIG_MDIO_OCTEON is not set ++# CONFIG_MDIO_THUNDER is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AX88796B_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_CORTINA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83822_PHY is not set ++# CONFIG_DP83TC811_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MARVELL_10G_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROCHIP_T1_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_RENESAS_PHY is not set ++# CONFIG_ROCKCHIP_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++CONFIG_USB_NET_DRIVERS=y ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=y ++CONFIG_USB_NET_AX88179_178A=y ++CONFIG_USB_NET_CDCETHER=y ++# CONFIG_USB_NET_CDC_EEM is not set ++CONFIG_USB_NET_CDC_NCM=y ++# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set ++# CONFIG_USB_NET_CDC_MBIM is not set ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SR9700 is not set ++# CONFIG_USB_NET_SR9800 is not set ++# CONFIG_USB_NET_SMSC75XX is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++# CONFIG_USB_NET_GL620A is not set ++CONFIG_USB_NET_NET1080=y ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++# CONFIG_USB_NET_RNDIS_HOST is not set ++CONFIG_USB_NET_CDC_SUBSET_ENABLE=y ++CONFIG_USB_NET_CDC_SUBSET=y ++# CONFIG_USB_ALI_M5632 is not set ++# CONFIG_USB_AN2720 is not set ++CONFIG_USB_BELKIN=y ++CONFIG_USB_ARMLINUX=y ++# CONFIG_USB_EPSON2888 is not set ++# CONFIG_USB_KC2190 is not set ++CONFIG_USB_NET_ZAURUS=y ++# CONFIG_USB_NET_CX82310_ETH is not set ++# CONFIG_USB_NET_KALMIA is not set ++CONFIG_USB_NET_QMI_WWAN=y ++# CONFIG_USB_NET_INT51X1 is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_USB_SIERRA_NET is not set ++# CONFIG_USB_VL600 is not set ++# CONFIG_USB_NET_CH9200 is not set ++CONFIG_USB_NET_EC20_GOBINET=y ++CONFIG_WLAN=y ++# CONFIG_WIRELESS_WDS is not set ++# CONFIG_WLAN_VENDOR_ADMTEK is not set ++# CONFIG_WLAN_VENDOR_ATH is not set ++# CONFIG_WLAN_VENDOR_ATMEL is not set ++# CONFIG_WLAN_VENDOR_BROADCOM is not set ++# CONFIG_WLAN_VENDOR_CISCO is not set ++# CONFIG_WLAN_VENDOR_INTEL is not set ++# CONFIG_WLAN_VENDOR_INTERSIL is not set ++# CONFIG_WLAN_VENDOR_MARVELL is not set ++# CONFIG_WLAN_VENDOR_MEDIATEK is not set ++# CONFIG_WLAN_VENDOR_RALINK is not set ++# CONFIG_WLAN_VENDOR_REALTEK is not set ++# CONFIG_WLAN_VENDOR_RSI is not set ++# CONFIG_WLAN_VENDOR_ST is not set ++# CONFIG_WLAN_VENDOR_TI is not set ++# CONFIG_WLAN_VENDOR_ZYDAS is not set ++# CONFIG_WLAN_VENDOR_QUANTENNA is not set ++CONFIG_HI1102A=y ++CONFIG_HI110X_SDIO_FPGA=y ++CONFIG_HI110X_SDIO_NON_STD_CARD_SUPPORT=y ++CONFIG_HI110X_SDIO_DETECT_FUNCTION=y ++CONFIG_HI1102_WIFI=y ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_VMXNET3 is not set ++# CONFIG_NETDEVSIM is not set ++# CONFIG_NET_FAILOVER is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++CONFIG_INPUT_JOYDEV=y ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADC is not set ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_DLINK_DIR685 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++CONFIG_MOUSE_PS2_SMBUS=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++CONFIG_INPUT_JOYSTICK=y ++# CONFIG_JOYSTICK_ANALOG is not set ++# CONFIG_JOYSTICK_A3D is not set ++# CONFIG_JOYSTICK_ADI is not set ++# CONFIG_JOYSTICK_COBRA is not set ++# CONFIG_JOYSTICK_GF2K is not set ++# CONFIG_JOYSTICK_GRIP is not set ++# CONFIG_JOYSTICK_GRIP_MP is not set ++# CONFIG_JOYSTICK_GUILLEMOT is not set ++# CONFIG_JOYSTICK_INTERACT is not set ++# CONFIG_JOYSTICK_SIDEWINDER is not set ++# CONFIG_JOYSTICK_TMDC is not set ++# CONFIG_JOYSTICK_IFORCE is not set ++# CONFIG_JOYSTICK_WARRIOR is not set ++# CONFIG_JOYSTICK_MAGELLAN is not set ++# CONFIG_JOYSTICK_SPACEORB is not set ++# CONFIG_JOYSTICK_SPACEBALL is not set ++# CONFIG_JOYSTICK_STINGER is not set ++# CONFIG_JOYSTICK_TWIDJOY is not set ++# CONFIG_JOYSTICK_ZHENHUA is not set ++# CONFIG_JOYSTICK_AS5011 is not set ++# CONFIG_JOYSTICK_JOYDUMP is not set ++# CONFIG_JOYSTICK_XPAD is not set ++# CONFIG_JOYSTICK_PSXPAD_SPI is not set ++# CONFIG_JOYSTICK_PXRC is not set ++# CONFIG_INPUT_TABLET is not set ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_PROPERTIES=y ++# CONFIG_TOUCHSCREEN_ADS7846 is not set ++# CONFIG_TOUCHSCREEN_AD7877 is not set ++# CONFIG_TOUCHSCREEN_AD7879 is not set ++# CONFIG_TOUCHSCREEN_ADC is not set ++# CONFIG_TOUCHSCREEN_AR1021_I2C is not set ++# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set ++# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_BU21013 is not set ++# CONFIG_TOUCHSCREEN_BU21029 is not set ++# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set ++# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set ++# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set ++# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set ++# CONFIG_TOUCHSCREEN_DYNAPRO is not set ++# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set ++# CONFIG_TOUCHSCREEN_EETI is not set ++# CONFIG_TOUCHSCREEN_EGALAX is not set ++# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set ++# CONFIG_TOUCHSCREEN_EXC3000 is not set ++# CONFIG_TOUCHSCREEN_FUJITSU is not set ++CONFIG_TOUCHSCREEN_GOODIX=y ++# CONFIG_TOUCHSCREEN_HIDEEP is not set ++# CONFIG_TOUCHSCREEN_ILI210X is not set ++# CONFIG_TOUCHSCREEN_S6SY761 is not set ++# CONFIG_TOUCHSCREEN_GUNZE is not set ++# CONFIG_TOUCHSCREEN_EKTF2127 is not set ++# CONFIG_TOUCHSCREEN_ELAN is not set ++# CONFIG_TOUCHSCREEN_ELO is not set ++# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set ++# CONFIG_TOUCHSCREEN_WACOM_I2C is not set ++# CONFIG_TOUCHSCREEN_MAX11801 is not set ++# CONFIG_TOUCHSCREEN_MCS5000 is not set ++# CONFIG_TOUCHSCREEN_MMS114 is not set ++# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set ++# CONFIG_TOUCHSCREEN_MTOUCH is not set ++# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set ++# CONFIG_TOUCHSCREEN_INEXIO is not set ++# CONFIG_TOUCHSCREEN_MK712 is not set ++# CONFIG_TOUCHSCREEN_PENMOUNT is not set ++# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set ++# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set ++# CONFIG_TOUCHSCREEN_TOUCHWIN is not set ++# CONFIG_TOUCHSCREEN_PIXCIR is not set ++# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set ++# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set ++# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set ++# CONFIG_TOUCHSCREEN_TSC_SERIO is not set ++# CONFIG_TOUCHSCREEN_TSC2004 is not set ++# CONFIG_TOUCHSCREEN_TSC2005 is not set ++# CONFIG_TOUCHSCREEN_TSC2007 is not set ++# CONFIG_TOUCHSCREEN_RM_TS is not set ++# CONFIG_TOUCHSCREEN_SILEAD is not set ++# CONFIG_TOUCHSCREEN_SIS_I2C is not set ++# CONFIG_TOUCHSCREEN_ST1232 is not set ++# CONFIG_TOUCHSCREEN_SUR40 is not set ++# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set ++# CONFIG_TOUCHSCREEN_SX8654 is not set ++# CONFIG_TOUCHSCREEN_TPS6507X is not set ++# CONFIG_TOUCHSCREEN_ZET6223 is not set ++# CONFIG_TOUCHSCREEN_ZFORCE is not set ++# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_AD714X is not set ++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set ++# CONFIG_INPUT_BMA150 is not set ++# CONFIG_INPUT_E3X0_BUTTON is not set ++# CONFIG_INPUT_MMA8450 is not set ++# CONFIG_INPUT_GP2A is not set ++# CONFIG_INPUT_GPIO_BEEPER is not set ++# CONFIG_INPUT_GPIO_DECODER is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_KXTJ9 is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++# CONFIG_INPUT_REGULATOR_HAPTIC is not set ++CONFIG_INPUT_UINPUT=y ++# CONFIG_INPUT_PCF8574 is not set ++# CONFIG_INPUT_PWM_BEEPER is not set ++# CONFIG_INPUT_PWM_VIBRA is not set ++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set ++# CONFIG_INPUT_ADXL34X is not set ++# CONFIG_INPUT_CMA3000 is not set ++# CONFIG_INPUT_DRV260X_HAPTICS is not set ++# CONFIG_INPUT_DRV2665_HAPTICS is not set ++# CONFIG_INPUT_DRV2667_HAPTICS is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_AMBAKMI is not set ++# CONFIG_SERIO_PCIPS2 is not set ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_SERIO_GPIO_PS2 is not set ++# CONFIG_USERIO is not set ++CONFIG_GAMEPORT=y ++# CONFIG_GAMEPORT_NS558 is not set ++# CONFIG_GAMEPORT_L4 is not set ++# CONFIG_GAMEPORT_EMU10K1 is not set ++# CONFIG_GAMEPORT_FM801 is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_VT_CONSOLE_SLEEP=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_LDISC_AUTOLOAD=y ++CONFIG_DEVMEM=y ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_EARLYCON=y ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_AMBA_PL010 is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_RP2 is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_DEV_BUS is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_APPLICOM is not set ++ ++# ++# PCMCIA character devices ++# ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_GPMUX is not set ++# CONFIG_I2C_MUX_LTC4306 is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_PINCTRL is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_DEMUX_PINCTRL is not set ++# CONFIG_I2C_MUX_MLXCPLD is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CADENCE is not set ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_DESIGNWARE_PCI is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++CONFIG_I2C_BSP=y ++# CONFIG_I2C_NOMADIK is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_THUNDERX is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++CONFIG_DMA_MSG_MIN_LEN=5 ++CONFIG_DMA_MSG_MAX_LEN=4090 ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++# CONFIG_SPI_MEM is not set ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++CONFIG_SPI_PL022=y ++# CONFIG_SPI_PXA2XX is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_THUNDERX is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPI_SLAVE is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++# CONFIG_PPS is not set ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_PINCTRL=y ++CONFIG_GENERIC_PINCTRL_GROUPS=y ++CONFIG_PINMUX=y ++CONFIG_GENERIC_PINMUX_FUNCTIONS=y ++CONFIG_PINCONF=y ++CONFIG_GENERIC_PINCONF=y ++# CONFIG_DEBUG_PINCTRL is not set ++# CONFIG_PINCTRL_AMD is not set ++# CONFIG_PINCTRL_MCP23S08 is not set ++CONFIG_PINCTRL_SINGLE=y ++# CONFIG_PINCTRL_SX150X is not set ++CONFIG_GPIOLIB=y ++CONFIG_GPIOLIB_FASTPATH_LIMIT=512 ++CONFIG_OF_GPIO=y ++CONFIG_GPIOLIB_IRQCHIP=y ++CONFIG_DEBUG_GPIO=y ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_GENERIC=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_FTGPIO010 is not set ++CONFIG_GPIO_GENERIC_PLATFORM=y ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_HLWD is not set ++# CONFIG_GPIO_MB86S7X is not set ++# CONFIG_GPIO_MOCKUP is not set ++CONFIG_GPIO_PL061=y ++# CONFIG_GPIO_SYSCON is not set ++# CONFIG_GPIO_XGENE is not set ++# CONFIG_GPIO_XILINX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++ ++# ++# MFD GPIO expanders ++# ++ ++# ++# PCI GPIO expanders ++# ++# CONFIG_GPIO_BT8XX is not set ++# CONFIG_GPIO_PCI_IDIO_16 is not set ++# CONFIG_GPIO_PCIE_IDIO_24 is not set ++# CONFIG_GPIO_RDC321X is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX3191X is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++# CONFIG_GPIO_XRA1403 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++CONFIG_POWER_RESET=y ++# CONFIG_POWER_RESET_BRCMSTB is not set ++# CONFIG_POWER_RESET_GPIO is not set ++# CONFIG_POWER_RESET_GPIO_RESTART is not set ++# CONFIG_POWER_RESET_BSP is not set ++# CONFIG_POWER_RESET_LTC2952 is not set ++# CONFIG_POWER_RESET_RESTART is not set ++# CONFIG_POWER_RESET_XGENE is not set ++# CONFIG_POWER_RESET_SYSCON is not set ++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set ++# CONFIG_SYSCON_REBOOT_MODE is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_GENERIC_ADC_BATTERY is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_CHARGER_ADP5061 is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_LEGO_EV3 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_CHARGER_SBS is not set ++# CONFIG_MANAGER_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_MANAGER is not set ++# CONFIG_CHARGER_LTC3651 is not set ++# CONFIG_CHARGER_DETECTOR_MAX14656 is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_CHARGER_RT9455 is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++CONFIG_MFD_CORE=y ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_BD9571MWV is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_MADERA is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++CONFIG_MFD_BSP_FMC=y ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_LPC_ICH is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_CPCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++CONFIG_MFD_SYSCON=y ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_TI_LMU is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TI_LP87565 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_MFD_ROHM_BD718XX is not set ++CONFIG_REGULATOR=y ++# CONFIG_REGULATOR_DEBUG is not set ++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set ++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set ++# CONFIG_REGULATOR_88PG86X is not set ++# CONFIG_REGULATOR_ACT8865 is not set ++# CONFIG_REGULATOR_AD5398 is not set ++# CONFIG_REGULATOR_ANATOP is not set ++# CONFIG_REGULATOR_DA9210 is not set ++# CONFIG_REGULATOR_DA9211 is not set ++# CONFIG_REGULATOR_FAN53555 is not set ++# CONFIG_REGULATOR_GPIO is not set ++# CONFIG_REGULATOR_ISL9305 is not set ++# CONFIG_REGULATOR_ISL6271A is not set ++# CONFIG_REGULATOR_LP3971 is not set ++# CONFIG_REGULATOR_LP3972 is not set ++# CONFIG_REGULATOR_LP872X is not set ++# CONFIG_REGULATOR_LP8755 is not set ++# CONFIG_REGULATOR_LTC3589 is not set ++# CONFIG_REGULATOR_LTC3676 is not set ++# CONFIG_REGULATOR_MAX1586 is not set ++# CONFIG_REGULATOR_MAX8649 is not set ++# CONFIG_REGULATOR_MAX8660 is not set ++# CONFIG_REGULATOR_MAX8952 is not set ++# CONFIG_REGULATOR_MT6311 is not set ++# CONFIG_REGULATOR_PFUZE100 is not set ++# CONFIG_REGULATOR_PV88060 is not set ++# CONFIG_REGULATOR_PV88080 is not set ++# CONFIG_REGULATOR_PV88090 is not set ++# CONFIG_REGULATOR_PWM is not set ++# CONFIG_REGULATOR_SY8106A is not set ++# CONFIG_REGULATOR_TPS51632 is not set ++# CONFIG_REGULATOR_TPS62360 is not set ++# CONFIG_REGULATOR_TPS65023 is not set ++# CONFIG_REGULATOR_TPS6507X is not set ++# CONFIG_REGULATOR_TPS65132 is not set ++# CONFIG_REGULATOR_TPS6524X is not set ++# CONFIG_REGULATOR_VCTRL is not set ++# CONFIG_RC_CORE is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CEC_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++ ++# ++# Media drivers ++# ++CONFIG_MEDIA_USB_SUPPORT=y ++ ++# ++# Webcam devices ++# ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=m ++# CONFIG_USB_M5602 is not set ++# CONFIG_USB_STV06XX is not set ++# CONFIG_USB_GL860 is not set ++# CONFIG_USB_GSPCA_BENQ is not set ++# CONFIG_USB_GSPCA_CONEX is not set ++# CONFIG_USB_GSPCA_CPIA1 is not set ++# CONFIG_USB_GSPCA_DTCS033 is not set ++# CONFIG_USB_GSPCA_ETOMS is not set ++# CONFIG_USB_GSPCA_FINEPIX is not set ++# CONFIG_USB_GSPCA_JEILINJ is not set ++# CONFIG_USB_GSPCA_JL2005BCD is not set ++# CONFIG_USB_GSPCA_KINECT is not set ++# CONFIG_USB_GSPCA_KONICA is not set ++# CONFIG_USB_GSPCA_MARS is not set ++# CONFIG_USB_GSPCA_MR97310A is not set ++# CONFIG_USB_GSPCA_NW80X is not set ++# CONFIG_USB_GSPCA_OV519 is not set ++# CONFIG_USB_GSPCA_OV534 is not set ++# CONFIG_USB_GSPCA_OV534_9 is not set ++# CONFIG_USB_GSPCA_PAC207 is not set ++# CONFIG_USB_GSPCA_PAC7302 is not set ++# CONFIG_USB_GSPCA_PAC7311 is not set ++# CONFIG_USB_GSPCA_SE401 is not set ++# CONFIG_USB_GSPCA_SN9C2028 is not set ++# CONFIG_USB_GSPCA_SN9C20X is not set ++# CONFIG_USB_GSPCA_SONIXB is not set ++# CONFIG_USB_GSPCA_SONIXJ is not set ++# CONFIG_USB_GSPCA_SPCA500 is not set ++# CONFIG_USB_GSPCA_SPCA501 is not set ++# CONFIG_USB_GSPCA_SPCA505 is not set ++# CONFIG_USB_GSPCA_SPCA506 is not set ++# CONFIG_USB_GSPCA_SPCA508 is not set ++# CONFIG_USB_GSPCA_SPCA561 is not set ++# CONFIG_USB_GSPCA_SPCA1528 is not set ++# CONFIG_USB_GSPCA_SQ905 is not set ++# CONFIG_USB_GSPCA_SQ905C is not set ++# CONFIG_USB_GSPCA_SQ930X is not set ++# CONFIG_USB_GSPCA_STK014 is not set ++# CONFIG_USB_GSPCA_STK1135 is not set ++# CONFIG_USB_GSPCA_STV0680 is not set ++# CONFIG_USB_GSPCA_SUNPLUS is not set ++# CONFIG_USB_GSPCA_T613 is not set ++# CONFIG_USB_GSPCA_TOPRO is not set ++# CONFIG_USB_GSPCA_TOUPTEK is not set ++# CONFIG_USB_GSPCA_TV8532 is not set ++# CONFIG_USB_GSPCA_VC032X is not set ++# CONFIG_USB_GSPCA_VICAM is not set ++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set ++# CONFIG_USB_GSPCA_ZC3XX is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++# CONFIG_VIDEO_USBTV is not set ++ ++# ++# Webcam, TV (analog/digital) USB devices ++# ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_MEDIA_PCI_SUPPORT is not set ++CONFIG_V4L_PLATFORM_DRIVERS=y ++# CONFIG_VIDEO_CAFE_CCIC is not set ++# CONFIG_VIDEO_CADENCE is not set ++# CONFIG_SOC_CAMERA is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++CONFIG_VIDEOBUF2_CORE=y ++CONFIG_VIDEOBUF2_V4L2=y ++CONFIG_VIDEOBUF2_MEMOPS=y ++CONFIG_VIDEOBUF2_VMALLOC=y ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# SDR tuner chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Media SPI Adapters ++# ++ ++# ++# Tools to develop new frontends ++# ++ ++# ++# Graphics support ++# ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 ++# CONFIG_DRM is not set ++# CONFIG_DRM_DP_CEC is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# AMD Library routines ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_ARMCLCD is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_I740 is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_FB_SM712 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_DUMMY_CONSOLE_COLUMNS=80 ++CONFIG_DUMMY_CONSOLE_ROWS=25 ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_OSSEMUL is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_CTXFI is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_LOLA is not set ++# CONFIG_SND_LX6464ES is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SE6X is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_HDA_INTEL is not set ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_A4TECH=y ++# CONFIG_HID_ACCUTOUCH is not set ++# CONFIG_HID_ACRUX is not set ++CONFIG_HID_APPLE=y ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++CONFIG_HID_BELKIN=y ++# CONFIG_HID_BETOP_FF is not set ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++# CONFIG_HID_COUGAR is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CMEDIA is not set ++CONFIG_HID_CYPRESS=y ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++CONFIG_HID_EZKEY=y ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_ITE is not set ++# CONFIG_HID_JABRA is not set ++# CONFIG_HID_TWINHAN is not set ++CONFIG_HID_KENSINGTON=y ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++CONFIG_HID_LOGITECH=y ++# CONFIG_HID_LOGITECH_HIDPP is not set ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++# CONFIG_LOGIG940_FF is not set ++# CONFIG_LOGIWHEELS_FF is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MAYFLASH is not set ++# CONFIG_HID_REDRAGON is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTI is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_RETRODE is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEAM is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_UDRAW_PS3 is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_PCI=y ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_XHCI_HCD=y ++# CONFIG_USB_XHCI_DBGCAP is not set ++CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_XHCI_PLATFORM=y ++# CONFIG_USB_EHCI_HCD is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++CONFIG_USB_WDM=y ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++CONFIG_USB_UAS=y ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++ ++# ++# Platform Glue Driver Support ++# ++# CONFIG_USB_DWC3_HAPS is not set ++# CONFIG_USB_DWC3_OF_SIMPLE is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++CONFIG_USB_SERIAL=y ++# CONFIG_USB_SERIAL_CONSOLE is not set ++# CONFIG_USB_SERIAL_GENERIC is not set ++# CONFIG_USB_SERIAL_SIMPLE is not set ++# CONFIG_USB_SERIAL_AIRCABLE is not set ++# CONFIG_USB_SERIAL_ARK3116 is not set ++# CONFIG_USB_SERIAL_BELKIN is not set ++# CONFIG_USB_SERIAL_CH341 is not set ++# CONFIG_USB_SERIAL_WHITEHEAT is not set ++# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set ++CONFIG_USB_SERIAL_CP210X=y ++# CONFIG_USB_SERIAL_CYPRESS_M8 is not set ++# CONFIG_USB_SERIAL_EMPEG is not set ++# CONFIG_USB_SERIAL_FTDI_SIO is not set ++# CONFIG_USB_SERIAL_VISOR is not set ++# CONFIG_USB_SERIAL_IPAQ is not set ++# CONFIG_USB_SERIAL_IR is not set ++# CONFIG_USB_SERIAL_EDGEPORT is not set ++# CONFIG_USB_SERIAL_EDGEPORT_TI is not set ++# CONFIG_USB_SERIAL_F81232 is not set ++# CONFIG_USB_SERIAL_F8153X is not set ++# CONFIG_USB_SERIAL_GARMIN is not set ++# CONFIG_USB_SERIAL_IPW is not set ++# CONFIG_USB_SERIAL_IUU is not set ++# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set ++# CONFIG_USB_SERIAL_KEYSPAN is not set ++# CONFIG_USB_SERIAL_KLSI is not set ++# CONFIG_USB_SERIAL_KOBIL_SCT is not set ++# CONFIG_USB_SERIAL_MCT_U232 is not set ++# CONFIG_USB_SERIAL_METRO is not set ++# CONFIG_USB_SERIAL_MOS7720 is not set ++# CONFIG_USB_SERIAL_MOS7840 is not set ++# CONFIG_USB_SERIAL_MXUPORT is not set ++# CONFIG_USB_SERIAL_NAVMAN is not set ++# CONFIG_USB_SERIAL_PL2303 is not set ++# CONFIG_USB_SERIAL_OTI6858 is not set ++# CONFIG_USB_SERIAL_QCAUX is not set ++# CONFIG_USB_SERIAL_QUALCOMM is not set ++# CONFIG_USB_SERIAL_SPCP8X5 is not set ++# CONFIG_USB_SERIAL_SAFE is not set ++# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set ++# CONFIG_USB_SERIAL_SYMBOL is not set ++# CONFIG_USB_SERIAL_TI is not set ++# CONFIG_USB_SERIAL_CYBERJACK is not set ++# CONFIG_USB_SERIAL_XIRCOM is not set ++CONFIG_USB_SERIAL_WWAN=y ++CONFIG_USB_SERIAL_OPTION=y ++# CONFIG_USB_SERIAL_OMNINET is not set ++# CONFIG_USB_SERIAL_OPTICON is not set ++# CONFIG_USB_SERIAL_XSENS_MT is not set ++# CONFIG_USB_SERIAL_WISHBONE is not set ++# CONFIG_USB_SERIAL_SSU100 is not set ++# CONFIG_USB_SERIAL_QT2 is not set ++# CONFIG_USB_SERIAL_UPD78F0730 is not set ++# CONFIG_USB_SERIAL_DEBUG is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HUB_USB251XB is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++# CONFIG_U_SERIAL_CONSOLE is not set ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_SNP_UDC_PLAT is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_AMD5536UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_NET2280 is not set ++# CONFIG_USB_GOKU is not set ++# CONFIG_USB_EG20T is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=y ++CONFIG_USB_F_ACM=y ++CONFIG_USB_U_SERIAL=y ++CONFIG_USB_U_ETHER=y ++CONFIG_USB_U_AUDIO=y ++CONFIG_USB_F_RNDIS=y ++CONFIG_USB_F_MASS_STORAGE=y ++CONFIG_USB_F_UAC1=y ++CONFIG_USB_F_UVC=y ++CONFIG_USB_CONFIGFS=y ++# CONFIG_USB_CONFIGFS_SERIAL is not set ++CONFIG_USB_CONFIGFS_ACM=y ++# CONFIG_USB_CONFIGFS_OBEX is not set ++# CONFIG_USB_CONFIGFS_NCM is not set ++# CONFIG_USB_CONFIGFS_ECM is not set ++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set ++CONFIG_USB_CONFIGFS_RNDIS=y ++# CONFIG_USB_CONFIGFS_EEM is not set ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++# CONFIG_USB_CONFIGFS_F_LB_SS is not set ++# CONFIG_USB_CONFIGFS_F_FS is not set ++CONFIG_USB_CONFIGFS_F_UAC1=y ++# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set ++# CONFIG_USB_CONFIGFS_F_UAC2 is not set ++# CONFIG_USB_CONFIGFS_F_MIDI is not set ++# CONFIG_USB_CONFIGFS_F_HID is not set ++CONFIG_USB_CONFIGFS_F_UVC=y ++# CONFIG_USB_CONFIGFS_F_PRINTER is not set ++CONFIG_MPP_TO_GADGET_UVC=y ++# CONFIG_TYPEC is not set ++# CONFIG_USB_ROLE_SWITCH is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_ARMMMCI is not set ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_IO_ACCESSORS=y ++# CONFIG_MMC_SDHCI_PCI is not set ++CONFIG_MMC_SDHCI_PLTFM=y ++# CONFIG_MMC_SDHCI_OF_ARASAN is not set ++# CONFIG_MMC_SDHCI_OF_AT91 is not set ++# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set ++# CONFIG_MMC_SDHCI_CADENCE is not set ++CONFIG_MMC_SDHCI_BSP=y ++# CONFIG_MMC_SDHCI_F_SDH30 is not set ++# CONFIG_MMC_TIFM_SD is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_CB710 is not set ++# CONFIG_MMC_VIA_SDMMC is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++CONFIG_MMC_CQHCI=y ++# CONFIG_MMC_TOSHIBA_PCI is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MMC_SDHCI_XENON is not set ++# CONFIG_MMC_SDHCI_OMAP is not set ++# CONFIG_MMC_CQ_HCI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_EDAC_SUPPORT=y ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++CONFIG_RTC_NVMEM=y ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12026 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF85363 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++CONFIG_RTC_DRV_RV8803=y ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_BSP is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_PL030 is not set ++# CONFIG_RTC_DRV_PL031 is not set ++# CONFIG_RTC_DRV_FTRTC010 is not set ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_R7301 is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set ++ ++# ++# DMA Devices ++# ++CONFIG_DMA_ENGINE=y ++CONFIG_DMA_VIRTUAL_CHANNELS=y ++CONFIG_DMA_OF=y ++# CONFIG_ALTERA_MSGDMA is not set ++# CONFIG_AMBA_PL08X is not set ++# CONFIG_DW_AXI_DMAC is not set ++# CONFIG_FSL_EDMA is not set ++# CONFIG_INTEL_IDMA64 is not set ++CONFIG_EDMACV310=y ++# CONFIG_MV_XOR_V2 is not set ++# CONFIG_PL330_DMA is not set ++# CONFIG_XILINX_DMA is not set ++# CONFIG_XILINX_ZYNQMP_DMA is not set ++# CONFIG_QCOM_HIDMA_MGMT is not set ++# CONFIG_QCOM_HIDMA is not set ++# CONFIG_DW_DMAC is not set ++# CONFIG_DW_DMAC_PCI is not set ++ ++# ++# DMA Clients ++# ++# CONFIG_ASYNC_TX_DMA is not set ++# CONFIG_DMATEST is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VFIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++# CONFIG_VIRTIO_MENU is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_VERSATILE is not set ++# CONFIG_CLK_HSDK is not set ++# CONFIG_COMMON_CLK_MAX9485 is not set ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI544 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_XGENE is not set ++# CONFIG_COMMON_CLK_PWM is not set ++# CONFIG_COMMON_CLK_VC5 is not set ++CONFIG_COMMON_CLK_SS928V100=y ++CONFIG_RESET_BSP=y ++# CONFIG_HWSPINLOCK is not set ++ ++# ++# Clock Source drivers ++# ++CONFIG_TIMER_OF=y ++CONFIG_TIMER_PROBE=y ++CONFIG_CLKSRC_MMIO=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y ++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set ++# CONFIG_FSL_ERRATUM_A008585 is not set ++CONFIG_HISILICON_ERRATUM_161010101=y ++CONFIG_ARM64_ERRATUM_858921=y ++CONFIG_ARM_TIMER_SP804=y ++# CONFIG_TIMER_BSP_SP804 is not set ++# CONFIG_MAILBOX is not set ++CONFIG_IOMMU_API=y ++CONFIG_IOMMU_SUPPORT=y ++ ++# ++# Generic IOMMU Pagetable Support ++# ++CONFIG_IOMMU_IO_PGTABLE=y ++CONFIG_IOMMU_IO_PGTABLE_LPAE=y ++# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set ++# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set ++ ++# ++# Generic PASID table support ++# ++CONFIG_IOMMU_PASID_TABLE=y ++CONFIG_ARM_SMMU_V3_CONTEXT=y ++# CONFIG_IOMMU_DEBUGFS is not set ++# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set ++CONFIG_IOMMU_IOVA=y ++CONFIG_OF_IOMMU=y ++CONFIG_IOMMU_DMA=y ++CONFIG_IOMMU_SVA=y ++CONFIG_IOMMU_PAGE_FAULT=y ++# CONFIG_ARM_SMMU is not set ++CONFIG_ARM_SMMU_V3=y ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_REMOTEPROC is not set ++ ++# ++# Rpmsg drivers ++# ++# CONFIG_RPMSG_VIRTIO is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Amlogic SoC drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++ ++# ++# NXP/Freescale QorIQ SoC drivers ++# ++ ++# ++# i.MX SoC drivers ++# ++ ++# ++# Qualcomm SoC drivers ++# ++# CONFIG_SOC_TI is not set ++ ++# ++# Xilinx SoC drivers ++# ++# CONFIG_XILINX_VCU is not set ++CONFIG_PM_DEVFREQ=y ++ ++# ++# DEVFREQ Governors ++# ++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y ++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set ++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set ++# CONFIG_DEVFREQ_GOV_USERSPACE is not set ++# CONFIG_DEVFREQ_GOV_PASSIVE is not set ++ ++# ++# DEVFREQ Drivers ++# ++# CONFIG_PM_DEVFREQ_EVENT is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++CONFIG_IIO=y ++# CONFIG_IIO_BUFFER is not set ++# CONFIG_IIO_CONFIGFS is not set ++# CONFIG_IIO_TRIGGER is not set ++# CONFIG_IIO_SW_DEVICE is not set ++# CONFIG_IIO_SW_TRIGGER is not set ++ ++# ++# Accelerometers ++# ++# CONFIG_ADIS16201 is not set ++# CONFIG_ADIS16209 is not set ++# CONFIG_ADXL345_I2C is not set ++# CONFIG_ADXL345_SPI is not set ++# CONFIG_BMA180 is not set ++# CONFIG_BMA220 is not set ++# CONFIG_BMC150_ACCEL is not set ++# CONFIG_DA280 is not set ++# CONFIG_DA311 is not set ++# CONFIG_DMARD06 is not set ++# CONFIG_DMARD09 is not set ++# CONFIG_DMARD10 is not set ++# CONFIG_IIO_CROS_EC_ACCEL_LEGACY is not set ++# CONFIG_IIO_ST_ACCEL_3AXIS is not set ++# CONFIG_KXSD9 is not set ++# CONFIG_KXCJK1013 is not set ++# CONFIG_MC3230 is not set ++# CONFIG_MMA7455_I2C is not set ++# CONFIG_MMA7455_SPI is not set ++# CONFIG_MMA7660 is not set ++# CONFIG_MMA8452 is not set ++# CONFIG_MMA9551 is not set ++# CONFIG_MMA9553 is not set ++# CONFIG_MXC4005 is not set ++# CONFIG_MXC6255 is not set ++# CONFIG_SCA3000 is not set ++# CONFIG_STK8312 is not set ++# CONFIG_STK8BA50 is not set ++ ++# ++# Analog to digital converters ++# ++# CONFIG_AD7266 is not set ++# CONFIG_AD7291 is not set ++# CONFIG_AD7298 is not set ++# CONFIG_AD7476 is not set ++# CONFIG_AD7766 is not set ++# CONFIG_AD7791 is not set ++# CONFIG_AD7793 is not set ++# CONFIG_AD7887 is not set ++# CONFIG_AD7923 is not set ++# CONFIG_AD799X is not set ++# CONFIG_CC10001_ADC is not set ++# CONFIG_ENVELOPE_DETECTOR is not set ++# CONFIG_HI8435 is not set ++CONFIG_VENDOR_LSADC=y ++# CONFIG_HX711 is not set ++# CONFIG_INA2XX_ADC is not set ++# CONFIG_LTC2471 is not set ++# CONFIG_LTC2485 is not set ++# CONFIG_LTC2497 is not set ++# CONFIG_MAX1027 is not set ++# CONFIG_MAX11100 is not set ++# CONFIG_MAX1118 is not set ++# CONFIG_MAX1363 is not set ++# CONFIG_MAX9611 is not set ++# CONFIG_MCP320X is not set ++# CONFIG_MCP3422 is not set ++# CONFIG_NAU7802 is not set ++# CONFIG_SD_ADC_MODULATOR is not set ++# CONFIG_TI_ADC081C is not set ++# CONFIG_TI_ADC0832 is not set ++# CONFIG_TI_ADC084S021 is not set ++# CONFIG_TI_ADC12138 is not set ++# CONFIG_TI_ADC108S102 is not set ++# CONFIG_TI_ADC128S052 is not set ++# CONFIG_TI_ADC161S626 is not set ++# CONFIG_TI_ADS1015 is not set ++# CONFIG_TI_ADS7950 is not set ++# CONFIG_TI_ADS8688 is not set ++# CONFIG_TI_TLC4541 is not set ++# CONFIG_VF610_ADC is not set ++ ++# ++# Analog Front Ends ++# ++# CONFIG_IIO_RESCALE is not set ++ ++# ++# Amplifiers ++# ++# CONFIG_AD8366 is not set ++ ++# ++# Chemical Sensors ++# ++# CONFIG_ATLAS_PH_SENSOR is not set ++# CONFIG_BME680 is not set ++# CONFIG_CCS811 is not set ++# CONFIG_IAQCORE is not set ++# CONFIG_VZ89X is not set ++ ++# ++# Hid Sensor IIO Common ++# ++ ++# ++# SSP Sensor Common ++# ++# CONFIG_IIO_SSP_SENSORHUB is not set ++ ++# ++# Counters ++# ++ ++# ++# Digital to analog converters ++# ++# CONFIG_AD5064 is not set ++# CONFIG_AD5360 is not set ++# CONFIG_AD5380 is not set ++# CONFIG_AD5421 is not set ++# CONFIG_AD5446 is not set ++# CONFIG_AD5449 is not set ++# CONFIG_AD5592R is not set ++# CONFIG_AD5593R is not set ++# CONFIG_AD5504 is not set ++# CONFIG_AD5624R_SPI is not set ++# CONFIG_LTC2632 is not set ++# CONFIG_AD5686_SPI is not set ++# CONFIG_AD5696_I2C is not set ++# CONFIG_AD5755 is not set ++# CONFIG_AD5758 is not set ++# CONFIG_AD5761 is not set ++# CONFIG_AD5764 is not set ++# CONFIG_AD5791 is not set ++# CONFIG_AD7303 is not set ++# CONFIG_AD8801 is not set ++# CONFIG_DPOT_DAC is not set ++# CONFIG_DS4424 is not set ++# CONFIG_M62332 is not set ++# CONFIG_MAX517 is not set ++# CONFIG_MAX5821 is not set ++# CONFIG_MCP4725 is not set ++# CONFIG_MCP4922 is not set ++# CONFIG_TI_DAC082S085 is not set ++# CONFIG_TI_DAC5571 is not set ++# CONFIG_VF610_DAC is not set ++ ++# ++# IIO dummy driver ++# ++ ++# ++# Frequency Synthesizers DDS/PLL ++# ++ ++# ++# Clock Generator/Distribution ++# ++# CONFIG_AD9523 is not set ++ ++# ++# Phase-Locked Loop (PLL) frequency synthesizers ++# ++# CONFIG_ADF4350 is not set ++ ++# ++# Digital gyroscope sensors ++# ++# CONFIG_ADIS16080 is not set ++# CONFIG_ADIS16130 is not set ++# CONFIG_ADIS16136 is not set ++# CONFIG_ADIS16260 is not set ++# CONFIG_ADXRS450 is not set ++# CONFIG_BMG160 is not set ++# CONFIG_MPU3050_I2C is not set ++# CONFIG_IIO_ST_GYRO_3AXIS is not set ++# CONFIG_ITG3200 is not set ++ ++# ++# Health Sensors ++# ++ ++# ++# Heart Rate Monitors ++# ++# CONFIG_AFE4403 is not set ++# CONFIG_AFE4404 is not set ++# CONFIG_MAX30100 is not set ++# CONFIG_MAX30102 is not set ++ ++# ++# Humidity sensors ++# ++# CONFIG_AM2315 is not set ++# CONFIG_DHT11 is not set ++# CONFIG_HDC100X is not set ++# CONFIG_HTS221 is not set ++# CONFIG_HTU21 is not set ++# CONFIG_SI7005 is not set ++# CONFIG_SI7020 is not set ++ ++# ++# Inertial measurement units ++# ++# CONFIG_ADIS16400 is not set ++# CONFIG_ADIS16480 is not set ++# CONFIG_BMI160_I2C is not set ++# CONFIG_BMI160_SPI is not set ++# CONFIG_KMX61 is not set ++# CONFIG_INV_MPU6050_I2C is not set ++# CONFIG_INV_MPU6050_SPI is not set ++# CONFIG_IIO_ST_LSM6DSX is not set ++ ++# ++# Light sensors ++# ++# CONFIG_ADJD_S311 is not set ++# CONFIG_AL3320A is not set ++# CONFIG_APDS9300 is not set ++# CONFIG_APDS9960 is not set ++# CONFIG_BH1750 is not set ++# CONFIG_BH1780 is not set ++# CONFIG_CM32181 is not set ++# CONFIG_CM3232 is not set ++# CONFIG_CM3323 is not set ++# CONFIG_CM3605 is not set ++# CONFIG_CM36651 is not set ++# CONFIG_GP2AP020A00F is not set ++# CONFIG_SENSORS_ISL29018 is not set ++# CONFIG_SENSORS_ISL29028 is not set ++# CONFIG_ISL29125 is not set ++# CONFIG_JSA1212 is not set ++# CONFIG_RPR0521 is not set ++# CONFIG_LTR501 is not set ++# CONFIG_LV0104CS is not set ++# CONFIG_MAX44000 is not set ++# CONFIG_OPT3001 is not set ++# CONFIG_PA12203001 is not set ++# CONFIG_SI1133 is not set ++# CONFIG_SI1145 is not set ++# CONFIG_STK3310 is not set ++# CONFIG_ST_UVIS25 is not set ++# CONFIG_TCS3414 is not set ++# CONFIG_TCS3472 is not set ++# CONFIG_SENSORS_TSL2563 is not set ++# CONFIG_TSL2583 is not set ++# CONFIG_TSL2772 is not set ++# CONFIG_TSL4531 is not set ++# CONFIG_US5182D is not set ++# CONFIG_VCNL4000 is not set ++# CONFIG_VEML6070 is not set ++# CONFIG_VL6180 is not set ++# CONFIG_ZOPT2201 is not set ++ ++# ++# Magnetometer sensors ++# ++# CONFIG_AK8974 is not set ++# CONFIG_AK8975 is not set ++# CONFIG_AK09911 is not set ++# CONFIG_BMC150_MAGN_I2C is not set ++# CONFIG_BMC150_MAGN_SPI is not set ++# CONFIG_MAG3110 is not set ++# CONFIG_MMC35240 is not set ++# CONFIG_IIO_ST_MAGN_3AXIS is not set ++# CONFIG_SENSORS_HMC5843_I2C is not set ++# CONFIG_SENSORS_HMC5843_SPI is not set ++ ++# ++# Multiplexers ++# ++# CONFIG_IIO_MUX is not set ++ ++# ++# Inclinometer sensors ++# ++ ++# ++# Digital potentiometers ++# ++# CONFIG_AD5272 is not set ++# CONFIG_DS1803 is not set ++# CONFIG_MAX5481 is not set ++# CONFIG_MAX5487 is not set ++# CONFIG_MCP4018 is not set ++# CONFIG_MCP4131 is not set ++# CONFIG_MCP4531 is not set ++# CONFIG_TPL0102 is not set ++ ++# ++# Digital potentiostats ++# ++# CONFIG_LMP91000 is not set ++ ++# ++# Pressure sensors ++# ++# CONFIG_ABP060MG is not set ++# CONFIG_BMP280 is not set ++# CONFIG_HP03 is not set ++# CONFIG_MPL115_I2C is not set ++# CONFIG_MPL115_SPI is not set ++# CONFIG_MPL3115 is not set ++# CONFIG_MS5611 is not set ++# CONFIG_MS5637 is not set ++# CONFIG_IIO_ST_PRESS is not set ++# CONFIG_T5403 is not set ++# CONFIG_HP206C is not set ++# CONFIG_ZPA2326 is not set ++ ++# ++# Lightning sensors ++# ++# CONFIG_AS3935 is not set ++ ++# ++# Proximity and distance sensors ++# ++# CONFIG_ISL29501 is not set ++# CONFIG_LIDAR_LITE_V2 is not set ++# CONFIG_RFD77402 is not set ++# CONFIG_SRF04 is not set ++# CONFIG_SX9500 is not set ++# CONFIG_SRF08 is not set ++ ++# ++# Resolver to digital converters ++# ++# CONFIG_AD2S1200 is not set ++ ++# ++# Temperature sensors ++# ++# CONFIG_MAXIM_THERMOCOUPLE is not set ++# CONFIG_MLX90614 is not set ++# CONFIG_MLX90632 is not set ++# CONFIG_TMP006 is not set ++# CONFIG_TMP007 is not set ++# CONFIG_TSYS01 is not set ++# CONFIG_TSYS02D is not set ++# CONFIG_NTB is not set ++# CONFIG_VME_BUS is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_PWM_BSP=y ++ ++# ++# IRQ chip support ++# ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++CONFIG_ARM_GIC_V2M=y ++CONFIG_ARM_GIC_V3=y ++CONFIG_ARM_GIC_V3_ITS=y ++CONFIG_ARM_GIC_V3_ITS_PCI=y ++CONFIG_HISILICON_IRQ_MBIGEN=y ++CONFIG_PARTITION_PERCPU=y ++# CONFIG_IPACK_BUS is not set ++CONFIG_RESET_CONTROLLER=y ++# CONFIG_RESET_TI_SYSCON is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_XGENE is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_PHY_CPCAP_USB is not set ++# CONFIG_PHY_MAPPHONE_MDM6600 is not set ++CONFIG_VENDOR_USB_PHY=y ++CONFIG_PHY_BSP_USB3=y ++CONFIG_BSP_USB_PHY=y ++CONFIG_USB_MODE_OPTION=y ++CONFIG_USB_DRD0_IN_HOST=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++# CONFIG_RAS is not set ++# CONFIG_LIBNVDIMM is not set ++# CONFIG_DAX is not set ++CONFIG_NVMEM=y ++ ++# ++# HW tracing support ++# ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++# CONFIG_FPGA is not set ++# CONFIG_FSI is not set ++# CONFIG_TEE is not set ++CONFIG_PM_OPP=y ++# CONFIG_SIOX is not set ++# CONFIG_SLIMBUS is not set ++ ++# ++# Vendor driver support ++# ++# CONFIG_CMA_MEM_SHARED is not set ++# CONFIG_CMA_ADVANCE_SHARE is not set ++CONFIG_VENDOR_NPU=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++CONFIG_FS_IOMAP=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT2=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++# CONFIG_EXT4_ENCRYPTION is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_XFS_FS=y ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++# CONFIG_XFS_ONLINE_SCRUB is not set ++# CONFIG_XFS_WARN is not set ++# CONFIG_XFS_DEBUG is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++# CONFIG_FS_DAX is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_EXPORTFS=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++CONFIG_QUOTA=y ++# CONFIG_QUOTA_NETLINK_INTERFACE is not set ++CONFIG_PRINT_QUOTA_WARNING=y ++# CONFIG_QUOTA_DEBUG is not set ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS4_FS=m ++CONFIG_AUTOFS_FS=m ++CONFIG_FUSE_FS=y ++# CONFIG_CUSE is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLBFS is not set ++CONFIG_MEMFD_CREATE=y ++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_CRAMFS=y ++CONFIG_CRAMFS_BLOCKDEV=y ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++# CONFIG_SQUASHFS_ZSTD is not set ++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set ++# CONFIG_SQUASHFS_EMBEDDED is not set ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V2=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_ROOT_NFS is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=y ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=y ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++CONFIG_KEYS_COMPAT=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEY_DH_OPERATIONS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++# CONFIG_HARDENED_USERCOPY is not set ++# CONFIG_FORTIFY_SOURCE is not set ++# CONFIG_STATIC_USERMODEHELPER is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=m ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=m ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_AKCIPHER=y ++CONFIG_CRYPTO_KPP2=y ++CONFIG_CRYPTO_ACOMP2=y ++CONFIG_CRYPTO_RSA=y ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=m ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_CCM=m ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++# CONFIG_CRYPTO_AEGIS128 is not set ++# CONFIG_CRYPTO_AEGIS128L is not set ++# CONFIG_CRYPTO_AEGIS256 is not set ++# CONFIG_CRYPTO_MORUS640 is not set ++# CONFIG_CRYPTO_MORUS1280 is not set ++CONFIG_CRYPTO_SEQIV=m ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CFB is not set ++CONFIG_CRYPTO_CTR=m ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=m ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_SM3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_TI is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_SM4 is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++# CONFIG_CRYPTO_ZSTD is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=m ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=m ++CONFIG_CRYPTO_JITTERENTROPY=m ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++CONFIG_CRYPTO_HASH_INFO=y ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_CCP is not set ++# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set ++# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set ++# CONFIG_CRYPTO_DEV_CCREE is not set ++# CONFIG_CRYPTO_DEV_HISI_SEC is not set ++CONFIG_ASYMMETRIC_KEY_TYPE=y ++CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y ++CONFIG_X509_CERTIFICATE_PARSER=y ++CONFIG_PKCS7_MESSAGE_PARSER=y ++# CONFIG_PKCS7_TEST_KEY is not set ++# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set ++ ++# ++# Certificates for signature checking ++# ++CONFIG_SYSTEM_TRUSTED_KEYRING=y ++CONFIG_SYSTEM_TRUSTED_KEYS="" ++# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set ++# CONFIG_SECONDARY_TRUSTED_KEYRING is not set ++# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++CONFIG_ARCH_HAS_FAST_MULTIPLIER=y ++# CONFIG_INDIRECT_PIO is not set ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC64 is not set ++# CONFIG_CRC4 is not set ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++# CONFIG_CRC8 is not set ++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_NEED_SG_DMA_LENGTH=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_DMA_ADDR_T_64BIT=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_DMA_DIRECT_OPS=y ++CONFIG_SWIOTLB=y ++CONFIG_SGL_ALLOC=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_CLZ_TAB=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_MPILIB=y ++CONFIG_LIBFDT=y ++CONFIG_OID_REGISTRY=y ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_STRING_SELFTEST is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 ++CONFIG_CONSOLE_LOGLEVEL_QUIET=4 ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=2048 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++CONFIG_ARCH_WANT_FRAME_POINTERS=y ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 ++CONFIG_MAGIC_SYSRQ_SERIAL=y ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_RODATA_TEST is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y ++# CONFIG_DEBUG_VIRTUAL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++CONFIG_ARCH_HAS_KCOV=y ++CONFIG_CC_HAS_SANCOV_TRACE_PC=y ++# CONFIG_KCOV is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_SOFTLOCKUP_DETECTOR is not set ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_WQ_WATCHDOG is not set ++CONFIG_PANIC_ON_OOPS=y ++CONFIG_PANIC_ON_OOPS_VALUE=1 ++CONFIG_PANIC_TIMEOUT=1 ++CONFIG_SCHED_DEBUG=y ++CONFIG_SCHED_INFO=y ++CONFIG_SCHEDSTATS=y ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_LOCK_DEBUGGING_SUPPORT=y ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_RWSEMS is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_WW_MUTEX_SELFTEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_HAVE_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=60 ++CONFIG_RCU_TRACE=y ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACE_CLOCK=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++# CONFIG_DMA_API_DEBUG is not set ++CONFIG_RUNTIME_TESTING_MENU=y ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_TEST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_BITFIELD is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_OVERFLOW is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_TEST_IDA is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_FIND_BIT_BENCHMARK is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_SYSCTL is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_TEST_KMOD is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_BUG_ON_DATA_CORRUPTION is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM64_PTDUMP_DEBUGFS is not set ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set ++# CONFIG_DEBUG_WX is not set ++# CONFIG_DEBUG_ALIGN_RODATA is not set ++# CONFIG_ARM64_RELOC_TEST is not set ++# CONFIG_CORESIGHT is not set +diff --git a/arch/arm64/configs/ss928v100_nand_defconfig b/arch/arm64/configs/ss928v100_nand_defconfig +new file mode 100644 +index 000000000000..30d5aa8374d1 +--- /dev/null ++++ b/arch/arm64/configs/ss928v100_nand_defconfig +@@ -0,0 +1,3669 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm64 4.19.90 Kernel Configuration ++# ++ ++# ++# Compiler: aarch64-mix210-linux-gcc (HC&C V1R3C00SPC200B042_20221123) 7.3.0 ++# ++CONFIG_CC_IS_GCC=y ++CONFIG_GCC_VERSION=70300 ++CONFIG_CLANG_VERSION=0 ++CONFIG_CC_HAS_ASM_GOTO=y ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++CONFIG_THREAD_INFO_IN_TASK=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_BUILD_SALT="" ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_GENERIC_IRQ_SHOW_LEVEL=y ++CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y ++CONFIG_GENERIC_IRQ_MIGRATION=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_IRQ_DOMAIN_HIERARCHY=y ++CONFIG_GENERIC_MSI_IRQ=y ++CONFIG_GENERIC_MSI_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_IRQ_MULTI_HANDLER=y ++CONFIG_ARCH_CLOCKSOURCE_DATA=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_HZ_PERIODIC=y ++# CONFIG_NO_HZ_IDLE is not set ++# CONFIG_NO_HZ_FULL is not set ++# CONFIG_NO_HZ is not set ++# CONFIG_HIGH_RES_TIMERS is not set ++CONFIG_PREEMPT_NONE=y ++# CONFIG_PREEMPT_VOLUNTARY is not set ++# CONFIG_PREEMPT is not set ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++CONFIG_CPU_ISOLATION=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_RCU=y ++# CONFIG_RCU_EXPERT is not set ++CONFIG_SRCU=y ++CONFIG_TREE_SRCU=y ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_NEED_SEGCBLIST=y ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y ++CONFIG_ARCH_SUPPORTS_INT128=y ++# CONFIG_CGROUPS is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_CHECKPOINT_RESTORE is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++CONFIG_RELAY=y ++# CONFIG_BLK_DEV_INITRD is not set ++CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_SYSCTL_EXCEPTION_TRACE=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++CONFIG_MULTIUSER=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++# CONFIG_FHANDLE is not set ++CONFIG_POSIX_TIMERS=y ++CONFIG_PRINTK=y ++CONFIG_PRINTK_NMI=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_FUTEX_PI=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_MEMBARRIER=y ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_KALLSYMS_BASE_RELATIVE=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_USERFAULTFD=y ++CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y ++CONFIG_RSEQ=y ++# CONFIG_DEBUG_RSEQ is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++# CONFIG_PC104 is not set ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++CONFIG_SLAB_MERGE_DEFAULT=y ++# CONFIG_SLAB_FREELIST_RANDOM is not set ++# CONFIG_SLAB_FREELIST_HARDENED is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_PROFILING is not set ++CONFIG_ARM64=y ++CONFIG_64BIT=y ++CONFIG_MMU=y ++CONFIG_ARM64_PAGE_SHIFT=12 ++CONFIG_ARM64_CONT_SHIFT=4 ++CONFIG_ARCH_MMAP_RND_BITS_MIN=18 ++CONFIG_ARCH_MMAP_RND_BITS_MAX=24 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_BUG=y ++CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CSUM=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA32=y ++CONFIG_HAVE_GENERIC_GUP=y ++CONFIG_SMP=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_PGTABLE_LEVELS=3 ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_ARCH_PROC_KCORE_TEXT=y ++ ++# ++# Platform selection ++# ++# CONFIG_ARCH_ACTIONS is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_ALPINE is not set ++# CONFIG_ARCH_BCM2835 is not set ++# CONFIG_ARCH_BCM_IPROC is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_BRCMSTB is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_K3 is not set ++# CONFIG_ARCH_LAYERSCAPE is not set ++# CONFIG_ARCH_LG1K is not set ++# CONFIG_ARCH_HISI is not set ++CONFIG_ARCH_BSP=y ++# CONFIG_ARCH_SS528V100 is not set ++# CONFIG_ARCH_SS625V100 is not set ++# CONFIG_ARCH_SS919V100 is not set ++# CONFIG_ARCH_SS015V100 is not set ++CONFIG_ARCH_SS928V100=y ++# CONFIG_ARCH_SS927V100 is not set ++# CONFIG_ARCH_MEDIATEK is not set ++# CONFIG_ARCH_MESON is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_REALTEK is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SEATTLE is not set ++# CONFIG_ARCH_SYNQUACER is not set ++# CONFIG_ARCH_RENESAS is not set ++# CONFIG_ARCH_STRATIX10 is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_SPRD is not set ++# CONFIG_ARCH_THUNDER is not set ++# CONFIG_ARCH_THUNDER2 is not set ++# CONFIG_ARCH_UNIPHIER is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_XGENE is not set ++# CONFIG_ARCH_ZX is not set ++# CONFIG_ARCH_ZYNQMP is not set ++ ++# ++# Bus support ++# ++CONFIG_PCI=y ++CONFIG_PCI_DOMAINS=y ++CONFIG_PCI_DOMAINS_GENERIC=y ++CONFIG_PCI_SYSCALL=y ++CONFIG_PCIEPORTBUS=y ++# CONFIG_PCIEAER is not set ++# CONFIG_PCIEASPM is not set ++CONFIG_PCIE_PME=y ++# CONFIG_PCIE_PTM is not set ++CONFIG_PCI_MSI=y ++CONFIG_PCI_MSI_IRQ_DOMAIN=y ++CONFIG_PCI_QUIRKS=y ++# CONFIG_PCI_DEBUG is not set ++# CONFIG_PCI_STUB is not set ++# CONFIG_PCI_IOV is not set ++# CONFIG_PCI_PRI is not set ++# CONFIG_PCI_PASID is not set ++# CONFIG_HOTPLUG_PCI is not set ++ ++# ++# PCI controller drivers ++# ++ ++# ++# Cadence PCIe controllers support ++# ++# CONFIG_PCIE_CADENCE_HOST is not set ++# CONFIG_PCI_FTPCI100 is not set ++# CONFIG_PCI_HOST_GENERIC is not set ++# CONFIG_PCIE_XILINX is not set ++# CONFIG_PCI_XGENE is not set ++# CONFIG_PCI_HOST_THUNDER_PEM is not set ++# CONFIG_PCI_HOST_THUNDER_ECAM is not set ++ ++# ++# DesignWare PCI Core Support ++# ++# CONFIG_PCIE_DW_PLAT_HOST is not set ++# CONFIG_PCI_HISI is not set ++# CONFIG_PCIE_KIRIN is not set ++ ++# ++# PCI Endpoint ++# ++# CONFIG_PCI_ENDPOINT is not set ++ ++# ++# PCI switch controller drivers ++# ++# CONFIG_PCI_SW_SWITCHTEC is not set ++# CONFIG_BSP_PCIE is not set ++ ++# ++# Kernel Features ++# ++ ++# ++# ARM errata workarounds via the alternatives framework ++# ++CONFIG_ARM64_ERRATUM_826319=y ++CONFIG_ARM64_ERRATUM_827319=y ++CONFIG_ARM64_ERRATUM_824069=y ++CONFIG_ARM64_ERRATUM_819472=y ++CONFIG_ARM64_ERRATUM_832075=y ++CONFIG_ARM64_ERRATUM_845719=y ++CONFIG_ARM64_ERRATUM_843419=y ++CONFIG_ARM64_ERRATUM_1024718=y ++CONFIG_ARM64_ERRATUM_1463225=y ++CONFIG_CAVIUM_ERRATUM_22375=y ++CONFIG_CAVIUM_ERRATUM_23154=y ++CONFIG_CAVIUM_ERRATUM_27456=y ++CONFIG_CAVIUM_ERRATUM_30115=y ++CONFIG_QCOM_FALKOR_ERRATUM_1003=y ++CONFIG_QCOM_FALKOR_ERRATUM_1009=y ++CONFIG_QCOM_QDF2400_ERRATUM_0065=y ++CONFIG_SOCIONEXT_SYNQUACER_PREITS=y ++CONFIG_HISILICON_ERRATUM_161600802=y ++CONFIG_QCOM_FALKOR_ERRATUM_E1041=y ++CONFIG_ARM64_4K_PAGES=y ++# CONFIG_ARM64_16K_PAGES is not set ++# CONFIG_ARM64_64K_PAGES is not set ++CONFIG_ARM64_VA_BITS_39=y ++# CONFIG_ARM64_VA_BITS_48 is not set ++CONFIG_ARM64_VA_BITS=39 ++CONFIG_ARM64_PA_BITS_48=y ++CONFIG_ARM64_PA_BITS=48 ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_SCHED_MC=y ++# CONFIG_SCHED_SMT is not set ++CONFIG_NR_CPUS=4 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_NUMA is not set ++CONFIG_HOLES_IN_ZONE=y ++CONFIG_HZ_100=y ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y ++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_ARCH_SPARSEMEM_DEFAULT=y ++CONFIG_ARCH_SELECT_MEMORY_MODEL=y ++CONFIG_ARCH_FLATMEM_ENABLE=y ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_SYS_SUPPORTS_HUGETLBFS=y ++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y ++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y ++# CONFIG_SECCOMP is not set ++# CONFIG_PARAVIRT is not set ++# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++# CONFIG_XEN is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_UNMAP_KERNEL_AT_EL0=y ++CONFIG_HARDEN_BRANCH_PREDICTOR=y ++CONFIG_HARDEN_EL2_VECTORS=y ++CONFIG_ARM64_SSBD=y ++# CONFIG_ARMV8_DEPRECATED is not set ++# CONFIG_ARM64_SW_TTBR0_PAN is not set ++ ++# ++# ARMv8.1 architectural features ++# ++CONFIG_ARM64_HW_AFDBM=y ++CONFIG_ARM64_PAN=y ++# CONFIG_ARM64_LSE_ATOMICS is not set ++CONFIG_ARM64_VHE=y ++ ++# ++# ARMv8.2 architectural features ++# ++CONFIG_ARM64_UAO=y ++# CONFIG_ARM64_PMEM is not set ++CONFIG_ARM64_RAS_EXTN=y ++CONFIG_ARM64_SVE=y ++CONFIG_ARM64_MODULE_PLTS=y ++# CONFIG_RANDOMIZE_BASE is not set ++ ++# ++# Boot options ++# ++CONFIG_CMDLINE="mem=128M console=ttyAMA0,115200 console=ttyMTD,blackbox" ++# CONFIG_CMDLINE_FORCE is not set ++# CONFIG_EFI is not set ++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y ++CONFIG_IMG_GZ_DTB=y ++# CONFIG_IMG_DTB is not set ++CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb" ++CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="vendor/ss928v100-demb-flash" ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++# CONFIG_SUSPEND_SKIP_SYNC is not set ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++# CONFIG_PM_WAKELOCKS is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_ATTR_SET=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set ++ ++# ++# CPU frequency scaling drivers ++# ++CONFIG_CPUFREQ_DT=y ++CONFIG_CPUFREQ_DT_PLATDEV=y ++# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set ++# CONFIG_QORIQ_CPUFREQ is not set ++ ++# ++# Firmware Drivers ++# ++CONFIG_ARM_PSCI_FW=y ++# CONFIG_ARM_SDE_INTERFACE is not set ++# CONFIG_FIRMWARE_MEMMAP is not set ++# CONFIG_FW_CFG_SYSFS is not set ++CONFIG_HAVE_ARM_SMCCC=y ++# CONFIG_GOOGLE_FIRMWARE is not set ++ ++# ++# Tegra firmware driver ++# ++# CONFIG_VIRTUALIZATION is not set ++# CONFIG_ARM64_CRYPTO is not set ++ ++# ++# General architecture-dependent options ++# ++# CONFIG_KPROBES is not set ++# CONFIG_JUMP_LABEL is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_NMI=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_ARCH_HAS_FORTIFY_SOURCE=y ++CONFIG_ARCH_HAS_SET_MEMORY=y ++CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_RSEQ=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_HAVE_RCU_TABLE_FREE=y ++CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y ++CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y ++CONFIG_HAVE_CMPXCHG_LOCAL=y ++CONFIG_HAVE_CMPXCHG_DOUBLE=y ++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_STACKPROTECTOR=y ++CONFIG_CC_HAS_STACKPROTECTOR_NONE=y ++CONFIG_STACKPROTECTOR=y ++CONFIG_STACKPROTECTOR_STRONG=y ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y ++CONFIG_HAVE_ARCH_HUGE_VMAP=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_ARCH_HAS_ELF_RANDOMIZE=y ++CONFIG_HAVE_ARCH_MMAP_RND_BITS=y ++CONFIG_ARCH_MMAP_RND_BITS=18 ++CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_COMPAT_OLD_SIGACTION=y ++CONFIG_COMPAT_32BIT_TIME=y ++CONFIG_HAVE_ARCH_VMAP_STACK=y ++CONFIG_VMAP_STACK=y ++CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y ++CONFIG_STRICT_KERNEL_RWX=y ++CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y ++CONFIG_STRICT_MODULE_RWX=y ++CONFIG_REFCOUNT_FULL=y ++CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y ++CONFIG_PLUGIN_HOSTCC="" ++CONFIG_HAVE_GCC_PLUGINS=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++# CONFIG_TRIM_UNUSED_KSYMS is not set ++CONFIG_BLOCK=y ++CONFIG_BLK_SCSI_REQUEST=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_DEV_ZONED is not set ++CONFIG_BLK_CMDLINE_PARSER=y ++# CONFIG_BLK_WBT is not set ++# CONFIG_BLK_SED_OPAL is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_AIX_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++# CONFIG_MAC_PARTITION is not set ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_CMDLINE_PARTITION=y ++CONFIG_BLOCK_COMPAT=y ++CONFIG_BLK_MQ_PCI=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_CFQ is not set ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_MQ_IOSCHED_DEADLINE=y ++CONFIG_MQ_IOSCHED_KYBER=y ++# CONFIG_IOSCHED_BFQ is not set ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK=y ++CONFIG_ARCH_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_READ_LOCK=y ++CONFIG_ARCH_INLINE_READ_LOCK_BH=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_READ_UNLOCK=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_INLINE_WRITE_LOCK=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_SPIN_TRYLOCK=y ++CONFIG_INLINE_SPIN_TRYLOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK=y ++CONFIG_INLINE_SPIN_LOCK_BH=y ++CONFIG_INLINE_SPIN_LOCK_IRQ=y ++CONFIG_INLINE_SPIN_LOCK_IRQSAVE=y ++CONFIG_INLINE_SPIN_UNLOCK_BH=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_READ_LOCK=y ++CONFIG_INLINE_READ_LOCK_BH=y ++CONFIG_INLINE_READ_LOCK_IRQ=y ++CONFIG_INLINE_READ_LOCK_IRQSAVE=y ++CONFIG_INLINE_READ_UNLOCK=y ++CONFIG_INLINE_READ_UNLOCK_BH=y ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++CONFIG_INLINE_READ_UNLOCK_IRQRESTORE=y ++CONFIG_INLINE_WRITE_LOCK=y ++CONFIG_INLINE_WRITE_LOCK_BH=y ++CONFIG_INLINE_WRITE_LOCK_IRQ=y ++CONFIG_INLINE_WRITE_LOCK_IRQSAVE=y ++CONFIG_INLINE_WRITE_UNLOCK=y ++CONFIG_INLINE_WRITE_UNLOCK_BH=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_LOCK_SPIN_ON_OWNER=y ++CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y ++CONFIG_QUEUED_SPINLOCKS=y ++CONFIG_ARCH_USE_QUEUED_RWLOCKS=y ++CONFIG_QUEUED_RWLOCKS=y ++CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y ++CONFIG_FREEZER=y ++ ++# ++# Executable file formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_COMPAT_BINFMT_ELF=y ++CONFIG_ELFCORE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Memory Management options ++# ++CONFIG_SELECT_MEMORY_MODEL=y ++# CONFIG_FLATMEM_MANUAL is not set ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_EXTREME=y ++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y ++CONFIG_SPARSEMEM_VMEMMAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_MMU_NOTIFIER=y ++CONFIG_KSM=y ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y ++# CONFIG_MEMORY_FAILURE is not set ++# CONFIG_TRANSPARENT_HUGEPAGE is not set ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set ++# CONFIG_IDLE_PAGE_TRACKING is not set ++CONFIG_FRAME_VECTOR=y ++# CONFIG_PERCPU_STATS is not set ++# CONFIG_GUP_BENCHMARK is not set ++CONFIG_ARCH_HAS_PTE_SPECIAL=y ++CONFIG_NET=y ++CONFIG_NET_INGRESS=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_TLS is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_INTERFACE is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_XDP_SOCKETS is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++CONFIG_NET_IP_TUNNEL=m ++# CONFIG_IP_MROUTE is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_NET_FOU_IP_TUNNELS is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++CONFIG_INET_TUNNEL=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_INET_RAW_DIAG is not set ++# CONFIG_INET_DIAG_DESTROY is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++CONFIG_IPV6=y ++CONFIG_IPV6_ROUTER_PREF=y ++# CONFIG_IPV6_ROUTE_INFO is not set ++# CONFIG_IPV6_OPTIMISTIC_DAD is not set ++# CONFIG_INET6_AH is not set ++# CONFIG_INET6_ESP is not set ++# CONFIG_INET6_IPCOMP is not set ++# CONFIG_IPV6_MIP6 is not set ++# CONFIG_IPV6_ILA is not set ++CONFIG_INET6_XFRM_MODE_TRANSPORT=m ++CONFIG_INET6_XFRM_MODE_TUNNEL=m ++CONFIG_INET6_XFRM_MODE_BEET=m ++# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set ++# CONFIG_IPV6_VTI is not set ++CONFIG_IPV6_SIT=m ++# CONFIG_IPV6_SIT_6RD is not set ++CONFIG_IPV6_NDISC_NODETYPE=y ++# CONFIG_IPV6_TUNNEL is not set ++# CONFIG_IPV6_MULTIPLE_TABLES is not set ++# CONFIG_IPV6_MROUTE is not set ++# CONFIG_IPV6_SEG6_LWTUNNEL is not set ++# CONFIG_IPV6_SEG6_HMAC is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++CONFIG_NETFILTER=y ++CONFIG_NETFILTER_ADVANCED=y ++ ++# ++# Core Netfilter Configuration ++# ++CONFIG_NETFILTER_INGRESS=y ++# CONFIG_NETFILTER_NETLINK_ACCT is not set ++# CONFIG_NETFILTER_NETLINK_QUEUE is not set ++# CONFIG_NETFILTER_NETLINK_LOG is not set ++# CONFIG_NETFILTER_NETLINK_OSF is not set ++# CONFIG_NF_CONNTRACK is not set ++# CONFIG_NF_LOG_NETDEV is not set ++# CONFIG_NF_TABLES is not set ++# CONFIG_NETFILTER_XTABLES is not set ++# CONFIG_IP_SET is not set ++# CONFIG_IP_VS is not set ++ ++# ++# IP: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV4 is not set ++# CONFIG_NF_TPROXY_IPV4 is not set ++# CONFIG_NF_DUP_IPV4 is not set ++# CONFIG_NF_LOG_ARP is not set ++# CONFIG_NF_LOG_IPV4 is not set ++# CONFIG_NF_REJECT_IPV4 is not set ++# CONFIG_IP_NF_IPTABLES is not set ++# CONFIG_IP_NF_ARPTABLES is not set ++ ++# ++# IPv6: Netfilter Configuration ++# ++# CONFIG_NF_SOCKET_IPV6 is not set ++# CONFIG_NF_TPROXY_IPV6 is not set ++# CONFIG_NF_DUP_IPV6 is not set ++# CONFIG_NF_REJECT_IPV6 is not set ++# CONFIG_NF_LOG_IPV6 is not set ++# CONFIG_IP6_NF_IPTABLES is not set ++# CONFIG_BPFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_6LOWPAN is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_MPLS is not set ++# CONFIG_NET_NSH is not set ++# CONFIG_HSR is not set ++# CONFIG_NET_SWITCHDEV is not set ++# CONFIG_NET_L3_MASTER_DEV is not set ++# CONFIG_NET_NCSI is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++# CONFIG_BPF_STREAM_PARSER is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_AF_KCM is not set ++CONFIG_WIRELESS=y ++# CONFIG_CFG80211 is not set ++ ++# ++# CFG80211 needs to be enabled for MAC80211 ++# ++CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++# CONFIG_PSAMPLE is not set ++# CONFIG_NET_IFE is not set ++# CONFIG_LWTUNNEL is not set ++CONFIG_DST_CACHE=y ++CONFIG_GRO_CELLS=y ++# CONFIG_NET_DEVLINK is not set ++CONFIG_MAY_USE_DEVLINK=y ++# CONFIG_FAILOVER is not set ++CONFIG_HAVE_EBPF_JIT=y ++ ++# ++# Device Drivers ++# ++CONFIG_ARM_AMBA=y ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++ ++# ++# Firmware loader ++# ++CONFIG_FW_LOADER=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set ++# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set ++CONFIG_GENERIC_CPU_AUTOPROBE=y ++CONFIG_GENERIC_CPU_VULNERABILITIES=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++CONFIG_REGMAP_MMIO=y ++CONFIG_DMA_SHARED_BUFFER=y ++# CONFIG_DMA_FENCE_TRACE is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=4 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++CONFIG_GENERIC_ARCH_TOPOLOGY=y ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_SIMPLE_PM_BUS is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_GNSS is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++CONFIG_MTD_OF_PARTS=y ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# Partition parsers ++# ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_PARTITIONED_MASTER is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_INTEL_VR_NOR is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_PMC551 is not set ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_M25P80 is not set ++# CONFIG_MTD_MCHP23K256 is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++CONFIG_MTD_BLOCK2MTD=y ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++# CONFIG_MTD_ONENAND is not set ++# CONFIG_MTD_SPI_NAND_BSP is not set ++# CONFIG_BSP_NAND_ECC_STATUS_REPORT is not set ++# CONFIG_BSP_NAND_FS_MAY_NO_YAFFS2 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_NAND_DENALI_PCI is not set ++# CONFIG_MTD_NAND_DENALI_DT is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_RICOH is not set ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_CAFE is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_BRCMNAND is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++CONFIG_MTD_NAND_FMC100=y ++# CONFIG_FMC100_NAND_EDO_MODE is not set ++CONFIG_RW_H_WIDTH=10 ++CONFIG_R_L_WIDTH=10 ++CONFIG_W_L_WIDTH=10 ++# CONFIG_MTD_SPI_NAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++CONFIG_MTD_SPI_NOR=y ++# CONFIG_MTD_MT81xx_NOR is not set ++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set ++# CONFIG_SPI_CADENCE_QUADSPI is not set ++CONFIG_SPI_BSP_SFC=y ++# CONFIG_MTD_SPI_IDS is not set ++# CONFIG_CLOSE_SPI_8PIN_4IO is not set ++CONFIG_BSP_SPI_BLOCK_PROTECT=y ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++# CONFIG_OF_UNITTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_KOBJ=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_OF_OVERLAY is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set ++# CONFIG_BLK_DEV_DAC960 is not set ++# CONFIG_BLK_DEV_UMEM is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_SKD is not set ++# CONFIG_BLK_DEV_SX8 is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=65536 ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++# CONFIG_BLK_DEV_RSXX is not set ++ ++# ++# NVME Support ++# ++# CONFIG_BLK_DEV_NVME is not set ++# CONFIG_NVME_FC is not set ++# CONFIG_NVME_TARGET is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_PHANTOM is not set ++# CONFIG_SGI_IOC4 is not set ++# CONFIG_TIFM_CORE is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_HP_ILO is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_PCI_ENDPOINT_TEST is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++# CONFIG_EEPROM_IDT_89HPESX is not set ++# CONFIG_CB710_CORE is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC & related support ++# ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# SCIF Bus Driver ++# ++ ++# ++# VOP Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++ ++# ++# SCIF Driver ++# ++ ++# ++# Intel MIC Coprocessor State Management (COSM) Drivers ++# ++ ++# ++# VOP Driver ++# ++# CONFIG_GENWQE is not set ++# CONFIG_ECHO is not set ++# CONFIG_MISC_RTSX_PCI is not set ++# CONFIG_MISC_RTSX_USB is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_CXGB3_ISCSI is not set ++# CONFIG_SCSI_CXGB4_ISCSI is not set ++# CONFIG_SCSI_BNX2_ISCSI is not set ++# CONFIG_BE2ISCSI is not set ++# CONFIG_BLK_DEV_3W_XXXX_RAID is not set ++# CONFIG_SCSI_HPSA is not set ++# CONFIG_SCSI_3W_9XXX is not set ++# CONFIG_SCSI_3W_SAS is not set ++# CONFIG_SCSI_ACARD is not set ++# CONFIG_SCSI_AACRAID is not set ++# CONFIG_SCSI_AIC7XXX is not set ++# CONFIG_SCSI_AIC79XX is not set ++# CONFIG_SCSI_AIC94XX is not set ++# CONFIG_SCSI_MVSAS is not set ++# CONFIG_SCSI_MVUMI is not set ++# CONFIG_SCSI_ADVANSYS is not set ++# CONFIG_SCSI_ARCMSR is not set ++# CONFIG_SCSI_ESAS2R is not set ++# CONFIG_MEGARAID_NEWGEN is not set ++# CONFIG_MEGARAID_LEGACY is not set ++# CONFIG_MEGARAID_SAS is not set ++# CONFIG_SCSI_MPT3SAS is not set ++# CONFIG_SCSI_MPT2SAS is not set ++# CONFIG_SCSI_SMARTPQI is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_HPTIOP is not set ++# CONFIG_SCSI_SNIC is not set ++# CONFIG_SCSI_DMX3191D is not set ++# CONFIG_SCSI_IPS is not set ++# CONFIG_SCSI_INITIO is not set ++# CONFIG_SCSI_INIA100 is not set ++# CONFIG_SCSI_STEX is not set ++# CONFIG_SCSI_SYM53C8XX_2 is not set ++# CONFIG_SCSI_QLOGIC_1280 is not set ++# CONFIG_SCSI_QLA_ISCSI is not set ++# CONFIG_SCSI_DC395x is not set ++# CONFIG_SCSI_AM53C974 is not set ++# CONFIG_SCSI_WD719X is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_PMCRAID is not set ++# CONFIG_SCSI_PM8001 is not set ++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_HAVE_PATA_PLATFORM=y ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_FUSION is not set ++ ++# ++# IEEE 1394 (FireWire) support ++# ++# CONFIG_FIREWIRE is not set ++# CONFIG_FIREWIRE_NOSY is not set ++CONFIG_NETDEVICES=y ++CONFIG_NET_CORE=y ++# CONFIG_BONDING is not set ++# CONFIG_DUMMY is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_FC is not set ++# CONFIG_NET_TEAM is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_IPVLAN is not set ++# CONFIG_VXLAN is not set ++# CONFIG_GENEVE is not set ++# CONFIG_GTP is not set ++# CONFIG_MACSEC is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_TUN is not set ++# CONFIG_TUN_VNET_CROSS_LE is not set ++# CONFIG_VETH is not set ++# CONFIG_NLMON is not set ++# CONFIG_ARCNET is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++CONFIG_ETHERNET=y ++# CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_ADAPTEC is not set ++# CONFIG_NET_VENDOR_AGERE is not set ++# CONFIG_NET_VENDOR_ALACRITECH is not set ++# CONFIG_NET_VENDOR_ALTEON is not set ++# CONFIG_ALTERA_TSE is not set ++# CONFIG_NET_VENDOR_AMAZON is not set ++# CONFIG_NET_VENDOR_AMD is not set ++# CONFIG_NET_VENDOR_AQUANTIA is not set ++# CONFIG_NET_VENDOR_ARC is not set ++# CONFIG_NET_VENDOR_ATHEROS is not set ++# CONFIG_NET_VENDOR_AURORA is not set ++# CONFIG_NET_VENDOR_BROADCOM is not set ++# CONFIG_NET_VENDOR_BROCADE is not set ++# CONFIG_NET_VENDOR_CADENCE is not set ++# CONFIG_NET_VENDOR_CAVIUM is not set ++# CONFIG_NET_VENDOR_CHELSIO is not set ++# CONFIG_NET_VENDOR_CISCO is not set ++# CONFIG_NET_VENDOR_CORTINA is not set ++# CONFIG_DNET is not set ++# CONFIG_NET_VENDOR_DEC is not set ++# CONFIG_NET_VENDOR_DLINK is not set ++# CONFIG_NET_VENDOR_EMULEX is not set ++# CONFIG_NET_VENDOR_EZCHIP is not set ++# CONFIG_NET_VENDOR_HISILICON is not set ++# CONFIG_NET_VENDOR_HP is not set ++# CONFIG_NET_VENDOR_HUAWEI is not set ++# CONFIG_NET_VENDOR_INTEL is not set ++CONFIG_NET_VENDOR_BSP=y ++# CONFIG_BSP_FEMAC is not set ++CONFIG_ETH_GMAC=y ++CONFIG_GMAC_DDR_64BIT=y ++CONFIG_GMAC_DESC_4WORD=y ++CONFIG_GMAC_RXCSUM=y ++CONFIG_RX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_SUPPORT=y ++CONFIG_TX_FLOW_CTRL_PAUSE_TIME=0xFFFF ++CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL=0xFFFF ++CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD=16 ++CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD=32 ++# CONFIG_JME is not set ++# CONFIG_NET_VENDOR_MARVELL is not set ++# CONFIG_NET_VENDOR_MELLANOX is not set ++# CONFIG_NET_VENDOR_MICREL is not set ++# CONFIG_NET_VENDOR_MICROCHIP is not set ++# CONFIG_NET_VENDOR_MICROSEMI is not set ++# CONFIG_NET_VENDOR_MYRI is not set ++# CONFIG_FEALNX is not set ++# CONFIG_NET_VENDOR_NATSEMI is not set ++# CONFIG_NET_VENDOR_NETERION is not set ++# CONFIG_NET_VENDOR_NETRONOME is not set ++# CONFIG_NET_VENDOR_NI is not set ++# CONFIG_NET_VENDOR_NVIDIA is not set ++# CONFIG_NET_VENDOR_OKI is not set ++# CONFIG_ETHOC is not set ++# CONFIG_NET_VENDOR_PACKET_ENGINES is not set ++# CONFIG_NET_VENDOR_QLOGIC is not set ++# CONFIG_NET_VENDOR_QUALCOMM is not set ++# CONFIG_NET_VENDOR_RDC is not set ++# CONFIG_NET_VENDOR_REALTEK is not set ++# CONFIG_NET_VENDOR_RENESAS is not set ++# CONFIG_NET_VENDOR_ROCKER is not set ++# CONFIG_NET_VENDOR_SAMSUNG is not set ++# CONFIG_NET_VENDOR_SEEQ is not set ++# CONFIG_NET_VENDOR_SOLARFLARE is not set ++# CONFIG_NET_VENDOR_SILAN is not set ++# CONFIG_NET_VENDOR_SIS is not set ++# CONFIG_NET_VENDOR_SMSC is not set ++# CONFIG_NET_VENDOR_SOCIONEXT is not set ++# CONFIG_NET_VENDOR_STMICRO is not set ++# CONFIG_NET_VENDOR_SUN is not set ++# CONFIG_NET_VENDOR_SYNOPSYS is not set ++# CONFIG_NET_VENDOR_TEHUTI is not set ++# CONFIG_NET_VENDOR_TI is not set ++# CONFIG_NET_VENDOR_VIA is not set ++# CONFIG_NET_VENDOR_WIZNET is not set ++# CONFIG_FDDI is not set ++# CONFIG_HIPPI is not set ++CONFIG_MDIO_DEVICE=y ++CONFIG_MDIO_BUS=y ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_HISI_FEMAC is not set ++# CONFIG_MDIO_BSP_FEMAC is not set ++CONFIG_MDIO_BSP_GEMAC=y ++# CONFIG_MDIO_MSCC_MIIM is not set ++# CONFIG_MDIO_OCTEON is not set ++# CONFIG_MDIO_THUNDER is not set ++CONFIG_PHYLIB=y ++CONFIG_SWPHY=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AMD_PHY is not set ++# CONFIG_AQUANTIA_PHY is not set ++# CONFIG_AX88796B_PHY is not set ++# CONFIG_AT803X_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_CORTINA_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_DP83822_PHY is not set ++# CONFIG_DP83TC811_PHY is not set ++# CONFIG_DP83848_PHY is not set ++# CONFIG_DP83867_PHY is not set ++CONFIG_FIXED_PHY=y ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_INTEL_XWAY_PHY is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_MARVELL_10G_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_MICROCHIP_PHY is not set ++# CONFIG_MICROCHIP_T1_PHY is not set ++# CONFIG_MICROSEMI_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_RENESAS_PHY is not set ++# CONFIG_ROCKCHIP_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_TERANETICS_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_XILINX_GMII2RGMII is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++CONFIG_USB_NET_DRIVERS=y ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++# CONFIG_USB_LAN78XX is not set ++# CONFIG_USB_USBNET is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_VMXNET3 is not set ++# CONFIG_NET_FAILOVER is not set ++# CONFIG_ISDN is not set ++# CONFIG_NVM is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++CONFIG_INPUT_FF_MEMLESS=y ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_MOUSEDEV_PSAUX=y ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++CONFIG_INPUT_JOYDEV=y ++CONFIG_INPUT_EVDEV=y ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++CONFIG_INPUT_KEYBOARD=y ++# CONFIG_KEYBOARD_ADP5588 is not set ++# CONFIG_KEYBOARD_ADP5589 is not set ++CONFIG_KEYBOARD_ATKBD=y ++# CONFIG_KEYBOARD_QT1070 is not set ++# CONFIG_KEYBOARD_QT2160 is not set ++# CONFIG_KEYBOARD_DLINK_DIR685 is not set ++# CONFIG_KEYBOARD_LKKBD is not set ++# CONFIG_KEYBOARD_GPIO is not set ++# CONFIG_KEYBOARD_GPIO_POLLED is not set ++# CONFIG_KEYBOARD_TCA6416 is not set ++# CONFIG_KEYBOARD_TCA8418 is not set ++# CONFIG_KEYBOARD_MATRIX is not set ++# CONFIG_KEYBOARD_LM8333 is not set ++# CONFIG_KEYBOARD_MAX7359 is not set ++# CONFIG_KEYBOARD_MCS is not set ++# CONFIG_KEYBOARD_MPR121 is not set ++# CONFIG_KEYBOARD_NEWTON is not set ++# CONFIG_KEYBOARD_OPENCORES is not set ++# CONFIG_KEYBOARD_SAMSUNG is not set ++# CONFIG_KEYBOARD_STOWAWAY is not set ++# CONFIG_KEYBOARD_SUNKBD is not set ++# CONFIG_KEYBOARD_OMAP4 is not set ++# CONFIG_KEYBOARD_XTKBD is not set ++# CONFIG_KEYBOARD_CAP11XX is not set ++# CONFIG_KEYBOARD_BCM is not set ++CONFIG_INPUT_MOUSE=y ++CONFIG_MOUSE_PS2=y ++CONFIG_MOUSE_PS2_ALPS=y ++CONFIG_MOUSE_PS2_BYD=y ++CONFIG_MOUSE_PS2_LOGIPS2PP=y ++CONFIG_MOUSE_PS2_SYNAPTICS=y ++CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y ++CONFIG_MOUSE_PS2_CYPRESS=y ++CONFIG_MOUSE_PS2_TRACKPOINT=y ++# CONFIG_MOUSE_PS2_ELANTECH is not set ++# CONFIG_MOUSE_PS2_SENTELIC is not set ++# CONFIG_MOUSE_PS2_TOUCHKIT is not set ++CONFIG_MOUSE_PS2_FOCALTECH=y ++CONFIG_MOUSE_PS2_SMBUS=y ++# CONFIG_MOUSE_SERIAL is not set ++# CONFIG_MOUSE_APPLETOUCH is not set ++# CONFIG_MOUSE_BCM5974 is not set ++# CONFIG_MOUSE_CYAPA is not set ++# CONFIG_MOUSE_ELAN_I2C is not set ++# CONFIG_MOUSE_VSXXXAA is not set ++# CONFIG_MOUSE_GPIO is not set ++# CONFIG_MOUSE_SYNAPTICS_I2C is not set ++# CONFIG_MOUSE_SYNAPTICS_USB is not set ++CONFIG_INPUT_JOYSTICK=y ++# CONFIG_JOYSTICK_ANALOG is not set ++# CONFIG_JOYSTICK_A3D is not set ++# CONFIG_JOYSTICK_ADI is not set ++# CONFIG_JOYSTICK_COBRA is not set ++# CONFIG_JOYSTICK_GF2K is not set ++# CONFIG_JOYSTICK_GRIP is not set ++# CONFIG_JOYSTICK_GRIP_MP is not set ++# CONFIG_JOYSTICK_GUILLEMOT is not set ++# CONFIG_JOYSTICK_INTERACT is not set ++# CONFIG_JOYSTICK_SIDEWINDER is not set ++# CONFIG_JOYSTICK_TMDC is not set ++# CONFIG_JOYSTICK_IFORCE is not set ++# CONFIG_JOYSTICK_WARRIOR is not set ++# CONFIG_JOYSTICK_MAGELLAN is not set ++# CONFIG_JOYSTICK_SPACEORB is not set ++# CONFIG_JOYSTICK_SPACEBALL is not set ++# CONFIG_JOYSTICK_STINGER is not set ++# CONFIG_JOYSTICK_TWIDJOY is not set ++# CONFIG_JOYSTICK_ZHENHUA is not set ++# CONFIG_JOYSTICK_AS5011 is not set ++# CONFIG_JOYSTICK_JOYDUMP is not set ++# CONFIG_JOYSTICK_XPAD is not set ++# CONFIG_JOYSTICK_PSXPAD_SPI is not set ++# CONFIG_JOYSTICK_PXRC is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_AD714X is not set ++# CONFIG_INPUT_ATMEL_CAPTOUCH is not set ++# CONFIG_INPUT_BMA150 is not set ++# CONFIG_INPUT_E3X0_BUTTON is not set ++# CONFIG_INPUT_MMA8450 is not set ++# CONFIG_INPUT_GP2A is not set ++# CONFIG_INPUT_GPIO_BEEPER is not set ++# CONFIG_INPUT_GPIO_DECODER is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_KXTJ9 is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++# CONFIG_INPUT_REGULATOR_HAPTIC is not set ++CONFIG_INPUT_UINPUT=y ++# CONFIG_INPUT_PCF8574 is not set ++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set ++# CONFIG_INPUT_ADXL34X is not set ++# CONFIG_INPUT_CMA3000 is not set ++# CONFIG_INPUT_DRV260X_HAPTICS is not set ++# CONFIG_INPUT_DRV2665_HAPTICS is not set ++# CONFIG_INPUT_DRV2667_HAPTICS is not set ++# CONFIG_RMI4_CORE is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++CONFIG_SERIO_SERPORT=y ++# CONFIG_SERIO_AMBAKMI is not set ++# CONFIG_SERIO_PCIPS2 is not set ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_SERIO_GPIO_PS2 is not set ++# CONFIG_USERIO is not set ++CONFIG_GAMEPORT=y ++# CONFIG_GAMEPORT_NS558 is not set ++# CONFIG_GAMEPORT_L4 is not set ++# CONFIG_GAMEPORT_EMU10K1 is not set ++# CONFIG_GAMEPORT_FM801 is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_VT_CONSOLE_SLEEP=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_NOZOMI is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_LDISC_AUTOLOAD=y ++CONFIG_DEVMEM=y ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_EARLYCON=y ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_AMBA_PL010 is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++# CONFIG_SERIAL_UARTLITE is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_JSM is not set ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_RP2 is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set ++# CONFIG_SERIAL_DEV_BUS is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_APPLICOM is not set ++ ++# ++# PCMCIA character devices ++# ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++CONFIG_DEVPORT=y ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_MUX=y ++ ++# ++# Multiplexer I2C Chip support ++# ++# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set ++# CONFIG_I2C_MUX_GPIO is not set ++# CONFIG_I2C_MUX_GPMUX is not set ++# CONFIG_I2C_MUX_LTC4306 is not set ++# CONFIG_I2C_MUX_PCA9541 is not set ++# CONFIG_I2C_MUX_PCA954x is not set ++# CONFIG_I2C_MUX_PINCTRL is not set ++# CONFIG_I2C_MUX_REG is not set ++# CONFIG_I2C_DEMUX_PINCTRL is not set ++# CONFIG_I2C_MUX_MLXCPLD is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# PC SMBus host controller drivers ++# ++# CONFIG_I2C_ALI1535 is not set ++# CONFIG_I2C_ALI1563 is not set ++# CONFIG_I2C_ALI15X3 is not set ++# CONFIG_I2C_AMD756 is not set ++# CONFIG_I2C_AMD8111 is not set ++# CONFIG_I2C_I801 is not set ++# CONFIG_I2C_ISCH is not set ++# CONFIG_I2C_PIIX4 is not set ++# CONFIG_I2C_NFORCE2 is not set ++# CONFIG_I2C_SIS5595 is not set ++# CONFIG_I2C_SIS630 is not set ++# CONFIG_I2C_SIS96X is not set ++# CONFIG_I2C_VIA is not set ++# CONFIG_I2C_VIAPRO is not set ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CADENCE is not set ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_DESIGNWARE_PCI is not set ++# CONFIG_I2C_EMEV2 is not set ++# CONFIG_I2C_GPIO is not set ++CONFIG_I2C_BSP=y ++# CONFIG_I2C_NOMADIK is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_THUNDERX is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++CONFIG_DMA_MSG_MIN_LEN=5 ++CONFIG_DMA_MSG_MAX_LEN=4090 ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_SLAVE is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++# CONFIG_SPI_MEM is not set ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_AXI_SPI_ENGINE is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_DESIGNWARE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++CONFIG_SPI_PL022=y ++# CONFIG_SPI_PXA2XX is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_THUNDERX is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_ZYNQMP_GQSPI is not set ++ ++# ++# SPI Protocol Masters ++# ++CONFIG_SPI_SPIDEV=y ++# CONFIG_SPI_LOOPBACK_TEST is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPI_SLAVE is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++# CONFIG_PPS is not set ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_PINCTRL=y ++CONFIG_GENERIC_PINCTRL_GROUPS=y ++CONFIG_PINMUX=y ++CONFIG_GENERIC_PINMUX_FUNCTIONS=y ++CONFIG_PINCONF=y ++CONFIG_GENERIC_PINCONF=y ++# CONFIG_DEBUG_PINCTRL is not set ++# CONFIG_PINCTRL_AMD is not set ++# CONFIG_PINCTRL_MCP23S08 is not set ++CONFIG_PINCTRL_SINGLE=y ++# CONFIG_PINCTRL_SX150X is not set ++CONFIG_GPIOLIB=y ++CONFIG_GPIOLIB_FASTPATH_LIMIT=512 ++CONFIG_OF_GPIO=y ++CONFIG_GPIOLIB_IRQCHIP=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_GENERIC=y ++ ++# ++# Memory mapped GPIO drivers ++# ++# CONFIG_GPIO_74XX_MMIO is not set ++# CONFIG_GPIO_ALTERA is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_FTGPIO010 is not set ++CONFIG_GPIO_GENERIC_PLATFORM=y ++# CONFIG_GPIO_GRGPIO is not set ++# CONFIG_GPIO_HLWD is not set ++# CONFIG_GPIO_MB86S7X is not set ++# CONFIG_GPIO_MOCKUP is not set ++CONFIG_GPIO_PL061=y ++# CONFIG_GPIO_SYSCON is not set ++# CONFIG_GPIO_XGENE is not set ++# CONFIG_GPIO_XILINX is not set ++ ++# ++# I2C GPIO expanders ++# ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_TPIC2810 is not set ++ ++# ++# MFD GPIO expanders ++# ++ ++# ++# PCI GPIO expanders ++# ++# CONFIG_GPIO_BT8XX is not set ++# CONFIG_GPIO_PCI_IDIO_16 is not set ++# CONFIG_GPIO_PCIE_IDIO_24 is not set ++# CONFIG_GPIO_RDC321X is not set ++ ++# ++# SPI GPIO expanders ++# ++# CONFIG_GPIO_74X164 is not set ++# CONFIG_GPIO_MAX3191X is not set ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_PISOSR is not set ++# CONFIG_GPIO_XRA1403 is not set ++ ++# ++# USB GPIO expanders ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_AVS is not set ++CONFIG_POWER_RESET=y ++# CONFIG_POWER_RESET_BRCMSTB is not set ++# CONFIG_POWER_RESET_GPIO is not set ++# CONFIG_POWER_RESET_GPIO_RESTART is not set ++# CONFIG_POWER_RESET_BSP is not set ++# CONFIG_POWER_RESET_LTC2952 is not set ++# CONFIG_POWER_RESET_RESTART is not set ++# CONFIG_POWER_RESET_XGENE is not set ++# CONFIG_POWER_RESET_SYSCON is not set ++# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set ++# CONFIG_SYSCON_REBOOT_MODE is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_CHARGER_ADP5061 is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++# CONFIG_BATTERY_DS2782 is not set ++# CONFIG_BATTERY_SBS is not set ++# CONFIG_CHARGER_SBS is not set ++# CONFIG_MANAGER_SBS is not set ++# CONFIG_BATTERY_BQ27XXX is not set ++# CONFIG_BATTERY_MAX17040 is not set ++# CONFIG_BATTERY_MAX17042 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_LP8727 is not set ++# CONFIG_CHARGER_GPIO is not set ++# CONFIG_CHARGER_MANAGER is not set ++# CONFIG_CHARGER_LTC3651 is not set ++# CONFIG_CHARGER_DETECTOR_MAX14656 is not set ++# CONFIG_CHARGER_BQ2415X is not set ++# CONFIG_CHARGER_BQ24257 is not set ++# CONFIG_CHARGER_BQ24735 is not set ++# CONFIG_CHARGER_BQ25890 is not set ++# CONFIG_CHARGER_SMB347 is not set ++# CONFIG_BATTERY_GAUGE_LTC2941 is not set ++# CONFIG_CHARGER_RT9455 is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++CONFIG_MFD_CORE=y ++# CONFIG_MFD_ACT8945A is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_ATMEL_FLEXCOM is not set ++# CONFIG_MFD_ATMEL_HLCDC is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_BD9571MWV is not set ++# CONFIG_MFD_AXP20X_I2C is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_MADERA is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9062 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_DA9150 is not set ++# CONFIG_MFD_DLN2 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++CONFIG_MFD_BSP_FMC=y ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_LPC_ICH is not set ++# CONFIG_LPC_SCH is not set ++# CONFIG_MFD_JANZ_CMODIO is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77620 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX77843 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MT6397 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_CPCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_RDC321X is not set ++# CONFIG_MFD_RT5033 is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SKY81452 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++CONFIG_MFD_SYSCON=y ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_TI_LMU is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65086 is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TI_LP873X is not set ++# CONFIG_MFD_TI_LP87565 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_VX855 is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_MFD_ROHM_BD718XX is not set ++CONFIG_REGULATOR=y ++# CONFIG_REGULATOR_DEBUG is not set ++# CONFIG_REGULATOR_FIXED_VOLTAGE is not set ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set ++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set ++# CONFIG_REGULATOR_88PG86X is not set ++# CONFIG_REGULATOR_ACT8865 is not set ++# CONFIG_REGULATOR_AD5398 is not set ++# CONFIG_REGULATOR_ANATOP is not set ++# CONFIG_REGULATOR_DA9210 is not set ++# CONFIG_REGULATOR_DA9211 is not set ++# CONFIG_REGULATOR_FAN53555 is not set ++# CONFIG_REGULATOR_GPIO is not set ++# CONFIG_REGULATOR_ISL9305 is not set ++# CONFIG_REGULATOR_ISL6271A is not set ++# CONFIG_REGULATOR_LP3971 is not set ++# CONFIG_REGULATOR_LP3972 is not set ++# CONFIG_REGULATOR_LP872X is not set ++# CONFIG_REGULATOR_LP8755 is not set ++# CONFIG_REGULATOR_LTC3589 is not set ++# CONFIG_REGULATOR_LTC3676 is not set ++# CONFIG_REGULATOR_MAX1586 is not set ++# CONFIG_REGULATOR_MAX8649 is not set ++# CONFIG_REGULATOR_MAX8660 is not set ++# CONFIG_REGULATOR_MAX8952 is not set ++# CONFIG_REGULATOR_MT6311 is not set ++# CONFIG_REGULATOR_PFUZE100 is not set ++# CONFIG_REGULATOR_PV88060 is not set ++# CONFIG_REGULATOR_PV88080 is not set ++# CONFIG_REGULATOR_PV88090 is not set ++# CONFIG_REGULATOR_SY8106A is not set ++# CONFIG_REGULATOR_TPS51632 is not set ++# CONFIG_REGULATOR_TPS62360 is not set ++# CONFIG_REGULATOR_TPS65023 is not set ++# CONFIG_REGULATOR_TPS6507X is not set ++# CONFIG_REGULATOR_TPS65132 is not set ++# CONFIG_REGULATOR_TPS6524X is not set ++# CONFIG_REGULATOR_VCTRL is not set ++# CONFIG_RC_CORE is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++# CONFIG_MEDIA_CEC_SUPPORT is not set ++# CONFIG_MEDIA_CONTROLLER is not set ++CONFIG_VIDEO_DEV=y ++CONFIG_VIDEO_V4L2=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++ ++# ++# Media drivers ++# ++CONFIG_MEDIA_USB_SUPPORT=y ++ ++# ++# Webcam devices ++# ++CONFIG_USB_VIDEO_CLASS=y ++CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y ++CONFIG_USB_GSPCA=m ++# CONFIG_USB_M5602 is not set ++# CONFIG_USB_STV06XX is not set ++# CONFIG_USB_GL860 is not set ++# CONFIG_USB_GSPCA_BENQ is not set ++# CONFIG_USB_GSPCA_CONEX is not set ++# CONFIG_USB_GSPCA_CPIA1 is not set ++# CONFIG_USB_GSPCA_DTCS033 is not set ++# CONFIG_USB_GSPCA_ETOMS is not set ++# CONFIG_USB_GSPCA_FINEPIX is not set ++# CONFIG_USB_GSPCA_JEILINJ is not set ++# CONFIG_USB_GSPCA_JL2005BCD is not set ++# CONFIG_USB_GSPCA_KINECT is not set ++# CONFIG_USB_GSPCA_KONICA is not set ++# CONFIG_USB_GSPCA_MARS is not set ++# CONFIG_USB_GSPCA_MR97310A is not set ++# CONFIG_USB_GSPCA_NW80X is not set ++# CONFIG_USB_GSPCA_OV519 is not set ++# CONFIG_USB_GSPCA_OV534 is not set ++# CONFIG_USB_GSPCA_OV534_9 is not set ++# CONFIG_USB_GSPCA_PAC207 is not set ++# CONFIG_USB_GSPCA_PAC7302 is not set ++# CONFIG_USB_GSPCA_PAC7311 is not set ++# CONFIG_USB_GSPCA_SE401 is not set ++# CONFIG_USB_GSPCA_SN9C2028 is not set ++# CONFIG_USB_GSPCA_SN9C20X is not set ++# CONFIG_USB_GSPCA_SONIXB is not set ++# CONFIG_USB_GSPCA_SONIXJ is not set ++# CONFIG_USB_GSPCA_SPCA500 is not set ++# CONFIG_USB_GSPCA_SPCA501 is not set ++# CONFIG_USB_GSPCA_SPCA505 is not set ++# CONFIG_USB_GSPCA_SPCA506 is not set ++# CONFIG_USB_GSPCA_SPCA508 is not set ++# CONFIG_USB_GSPCA_SPCA561 is not set ++# CONFIG_USB_GSPCA_SPCA1528 is not set ++# CONFIG_USB_GSPCA_SQ905 is not set ++# CONFIG_USB_GSPCA_SQ905C is not set ++# CONFIG_USB_GSPCA_SQ930X is not set ++# CONFIG_USB_GSPCA_STK014 is not set ++# CONFIG_USB_GSPCA_STK1135 is not set ++# CONFIG_USB_GSPCA_STV0680 is not set ++# CONFIG_USB_GSPCA_SUNPLUS is not set ++# CONFIG_USB_GSPCA_T613 is not set ++# CONFIG_USB_GSPCA_TOPRO is not set ++# CONFIG_USB_GSPCA_TOUPTEK is not set ++# CONFIG_USB_GSPCA_TV8532 is not set ++# CONFIG_USB_GSPCA_VC032X is not set ++# CONFIG_USB_GSPCA_VICAM is not set ++# CONFIG_USB_GSPCA_XIRLINK_CIT is not set ++# CONFIG_USB_GSPCA_ZC3XX is not set ++# CONFIG_USB_PWC is not set ++# CONFIG_VIDEO_CPIA2 is not set ++# CONFIG_USB_ZR364XX is not set ++# CONFIG_USB_STKWEBCAM is not set ++# CONFIG_USB_S2255 is not set ++# CONFIG_VIDEO_USBTV is not set ++ ++# ++# Webcam, TV (analog/digital) USB devices ++# ++# CONFIG_VIDEO_EM28XX is not set ++# CONFIG_MEDIA_PCI_SUPPORT is not set ++CONFIG_V4L_PLATFORM_DRIVERS=y ++# CONFIG_VIDEO_CAFE_CCIC is not set ++# CONFIG_VIDEO_CADENCE is not set ++# CONFIG_SOC_CAMERA is not set ++# CONFIG_V4L_MEM2MEM_DRIVERS is not set ++# CONFIG_V4L_TEST_DRIVERS is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++CONFIG_VIDEOBUF2_CORE=y ++CONFIG_VIDEOBUF2_V4L2=y ++CONFIG_VIDEOBUF2_MEMOPS=y ++CONFIG_VIDEOBUF2_VMALLOC=y ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) ++# ++CONFIG_MEDIA_SUBDRV_AUTOSELECT=y ++ ++# ++# Audio decoders, processors and mixers ++# ++ ++# ++# RDS decoders ++# ++ ++# ++# Video decoders ++# ++ ++# ++# Video and audio decoders ++# ++ ++# ++# Video encoders ++# ++ ++# ++# Camera sensor devices ++# ++ ++# ++# Flash devices ++# ++ ++# ++# Video improvement chips ++# ++ ++# ++# Audio/Video compression chips ++# ++ ++# ++# SDR tuner chips ++# ++ ++# ++# Miscellaneous helper chips ++# ++ ++# ++# Sensors used on soc_camera driver ++# ++ ++# ++# Media SPI Adapters ++# ++ ++# ++# Tools to develop new frontends ++# ++ ++# ++# Graphics support ++# ++CONFIG_VGA_ARB=y ++CONFIG_VGA_ARB_MAX_GPUS=16 ++# CONFIG_DRM is not set ++# CONFIG_DRM_DP_CEC is not set ++ ++# ++# ACP (Audio CoProcessor) Configuration ++# ++ ++# ++# AMD Library routines ++# ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB_CMDLINE=y ++CONFIG_FB_NOTIFY=y ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_CIRRUS is not set ++# CONFIG_FB_PM2 is not set ++# CONFIG_FB_ARMCLCD is not set ++# CONFIG_FB_CYBER2000 is not set ++# CONFIG_FB_ASILIANT is not set ++# CONFIG_FB_IMSTT is not set ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_NVIDIA is not set ++# CONFIG_FB_RIVA is not set ++# CONFIG_FB_I740 is not set ++# CONFIG_FB_MATROX is not set ++# CONFIG_FB_RADEON is not set ++# CONFIG_FB_ATY128 is not set ++# CONFIG_FB_ATY is not set ++# CONFIG_FB_S3 is not set ++# CONFIG_FB_SAVAGE is not set ++# CONFIG_FB_SIS is not set ++# CONFIG_FB_NEOMAGIC is not set ++# CONFIG_FB_KYRO is not set ++# CONFIG_FB_3DFX is not set ++# CONFIG_FB_VOODOO1 is not set ++# CONFIG_FB_VT8623 is not set ++# CONFIG_FB_TRIDENT is not set ++# CONFIG_FB_ARK is not set ++# CONFIG_FB_PM3 is not set ++# CONFIG_FB_CARMINE is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_IBM_GXT4500 is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_MB862XX is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_FB_SM712 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_DUMMY_CONSOLE_COLUMNS=80 ++CONFIG_DUMMY_CONSOLE_ROWS=25 ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++# CONFIG_SND_OSSEMUL is not set ++CONFIG_SND_PCM_TIMER=y ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_PROC_FS=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_SEQUENCER is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++CONFIG_SND_PCI=y ++# CONFIG_SND_AD1889 is not set ++# CONFIG_SND_ATIIXP is not set ++# CONFIG_SND_ATIIXP_MODEM is not set ++# CONFIG_SND_AU8810 is not set ++# CONFIG_SND_AU8820 is not set ++# CONFIG_SND_AU8830 is not set ++# CONFIG_SND_AW2 is not set ++# CONFIG_SND_BT87X is not set ++# CONFIG_SND_CA0106 is not set ++# CONFIG_SND_CMIPCI is not set ++# CONFIG_SND_OXYGEN is not set ++# CONFIG_SND_CS4281 is not set ++# CONFIG_SND_CS46XX is not set ++# CONFIG_SND_CTXFI is not set ++# CONFIG_SND_DARLA20 is not set ++# CONFIG_SND_GINA20 is not set ++# CONFIG_SND_LAYLA20 is not set ++# CONFIG_SND_DARLA24 is not set ++# CONFIG_SND_GINA24 is not set ++# CONFIG_SND_LAYLA24 is not set ++# CONFIG_SND_MONA is not set ++# CONFIG_SND_MIA is not set ++# CONFIG_SND_ECHO3G is not set ++# CONFIG_SND_INDIGO is not set ++# CONFIG_SND_INDIGOIO is not set ++# CONFIG_SND_INDIGODJ is not set ++# CONFIG_SND_INDIGOIOX is not set ++# CONFIG_SND_INDIGODJX is not set ++# CONFIG_SND_ENS1370 is not set ++# CONFIG_SND_ENS1371 is not set ++# CONFIG_SND_FM801 is not set ++# CONFIG_SND_HDSP is not set ++# CONFIG_SND_HDSPM is not set ++# CONFIG_SND_ICE1724 is not set ++# CONFIG_SND_INTEL8X0 is not set ++# CONFIG_SND_INTEL8X0M is not set ++# CONFIG_SND_KORG1212 is not set ++# CONFIG_SND_LOLA is not set ++# CONFIG_SND_LX6464ES is not set ++# CONFIG_SND_MIXART is not set ++# CONFIG_SND_NM256 is not set ++# CONFIG_SND_PCXHR is not set ++# CONFIG_SND_RIPTIDE is not set ++# CONFIG_SND_RME32 is not set ++# CONFIG_SND_RME96 is not set ++# CONFIG_SND_RME9652 is not set ++# CONFIG_SND_SE6X is not set ++# CONFIG_SND_VIA82XX is not set ++# CONFIG_SND_VIA82XX_MODEM is not set ++# CONFIG_SND_VIRTUOSO is not set ++# CONFIG_SND_VX222 is not set ++# CONFIG_SND_YMFPCI is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_HDA_INTEL is not set ++CONFIG_SND_HDA_PREALLOC_SIZE=64 ++CONFIG_SND_SPI=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++# CONFIG_SND_USB_POD is not set ++# CONFIG_SND_USB_PODHD is not set ++# CONFIG_SND_USB_TONEPORT is not set ++# CONFIG_SND_USB_VARIAX is not set ++# CONFIG_SND_SOC is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HID_BATTERY_STRENGTH is not set ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_A4TECH=y ++# CONFIG_HID_ACCUTOUCH is not set ++# CONFIG_HID_ACRUX is not set ++CONFIG_HID_APPLE=y ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++CONFIG_HID_BELKIN=y ++# CONFIG_HID_BETOP_FF is not set ++CONFIG_HID_CHERRY=y ++CONFIG_HID_CHICONY=y ++# CONFIG_HID_COUGAR is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CMEDIA is not set ++CONFIG_HID_CYPRESS=y ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++CONFIG_HID_EZKEY=y ++# CONFIG_HID_GEMBIRD is not set ++# CONFIG_HID_GFRM is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_ITE is not set ++# CONFIG_HID_JABRA is not set ++# CONFIG_HID_TWINHAN is not set ++CONFIG_HID_KENSINGTON=y ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++CONFIG_HID_LOGITECH=y ++# CONFIG_HID_LOGITECH_HIDPP is not set ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++# CONFIG_LOGIG940_FF is not set ++# CONFIG_LOGIWHEELS_FF is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MAYFLASH is not set ++# CONFIG_HID_REDRAGON is not set ++CONFIG_HID_MICROSOFT=y ++CONFIG_HID_MONTEREY=y ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTI is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PLANTRONICS is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_RETRODE is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEAM is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_UDRAW_PS3 is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++# CONFIG_HID_ALPS is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_PCI=y ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++CONFIG_USB_XHCI_HCD=y ++# CONFIG_USB_XHCI_DBGCAP is not set ++CONFIG_USB_XHCI_PCI=y ++CONFIG_USB_XHCI_PLATFORM=y ++# CONFIG_USB_EHCI_HCD is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_UHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++CONFIG_USB_DWC3=y ++# CONFIG_USB_DWC3_HOST is not set ++CONFIG_USB_DWC3_GADGET=y ++ ++# ++# Platform Glue Driver Support ++# ++# CONFIG_USB_DWC3_HAPS is not set ++# CONFIG_USB_DWC3_OF_SIMPLE is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++# CONFIG_USB_ISP1760 is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HUB_USB251XB is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_HSIC_USB4604 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=y ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++# CONFIG_U_SERIAL_CONSOLE is not set ++ ++# ++# USB Peripheral Controller ++# ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_SNP_UDC_PLAT is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_BDC_UDC is not set ++# CONFIG_USB_AMD5536UDC is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_NET2280 is not set ++# CONFIG_USB_GOKU is not set ++# CONFIG_USB_EG20T is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=y ++CONFIG_USB_F_ACM=y ++CONFIG_USB_U_SERIAL=y ++CONFIG_USB_U_ETHER=y ++CONFIG_USB_U_AUDIO=y ++CONFIG_USB_F_RNDIS=y ++CONFIG_USB_F_MASS_STORAGE=y ++CONFIG_USB_F_UAC1=y ++CONFIG_USB_F_UVC=y ++CONFIG_USB_CONFIGFS=y ++# CONFIG_USB_CONFIGFS_SERIAL is not set ++CONFIG_USB_CONFIGFS_ACM=y ++# CONFIG_USB_CONFIGFS_OBEX is not set ++# CONFIG_USB_CONFIGFS_NCM is not set ++# CONFIG_USB_CONFIGFS_ECM is not set ++# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set ++CONFIG_USB_CONFIGFS_RNDIS=y ++# CONFIG_USB_CONFIGFS_EEM is not set ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++# CONFIG_USB_CONFIGFS_F_LB_SS is not set ++# CONFIG_USB_CONFIGFS_F_FS is not set ++CONFIG_USB_CONFIGFS_F_UAC1=y ++# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set ++# CONFIG_USB_CONFIGFS_F_UAC2 is not set ++# CONFIG_USB_CONFIGFS_F_MIDI is not set ++# CONFIG_USB_CONFIGFS_F_HID is not set ++CONFIG_USB_CONFIGFS_F_UVC=y ++# CONFIG_USB_CONFIGFS_F_PRINTER is not set ++CONFIG_MPP_TO_GADGET_UVC=y ++# CONFIG_TYPEC is not set ++# CONFIG_USB_ROLE_SWITCH is not set ++# CONFIG_USB_ULPI_BUS is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++CONFIG_PWRSEQ_EMMC=y ++CONFIG_PWRSEQ_SIMPLE=y ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_ARMMMCI is not set ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_IO_ACCESSORS=y ++# CONFIG_MMC_SDHCI_PCI is not set ++CONFIG_MMC_SDHCI_PLTFM=y ++# CONFIG_MMC_SDHCI_OF_ARASAN is not set ++# CONFIG_MMC_SDHCI_OF_AT91 is not set ++# CONFIG_MMC_SDHCI_OF_DWCMSHC is not set ++# CONFIG_MMC_SDHCI_CADENCE is not set ++CONFIG_MMC_SDHCI_BSP=y ++# CONFIG_MMC_SDHCI_F_SDH30 is not set ++# CONFIG_MMC_TIFM_SD is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_CB710 is not set ++# CONFIG_MMC_VIA_SDMMC is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MMC_CQHCI is not set ++# CONFIG_MMC_TOSHIBA_PCI is not set ++# CONFIG_MMC_MTK is not set ++# CONFIG_MMC_SDHCI_XENON is not set ++# CONFIG_MMC_SDHCI_OMAP is not set ++# CONFIG_MMC_CQ_HCI is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_INFINIBAND is not set ++CONFIG_EDAC_SUPPORT=y ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_SYSTOHC_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++CONFIG_RTC_NVMEM=y ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_ABB5ZES3 is not set ++# CONFIG_RTC_DRV_ABX80X is not set ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12026 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF85363 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8010 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV8803 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1302 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6916 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_RX6110 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++CONFIG_RTC_I2C_AND_SPI=y ++ ++# ++# SPI and I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_BSP is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1685_FAMILY is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++# CONFIG_RTC_DRV_ZYNQMP is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_PL030 is not set ++# CONFIG_RTC_DRV_PL031 is not set ++# CONFIG_RTC_DRV_FTRTC010 is not set ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_R7301 is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++CONFIG_DMADEVICES=y ++# CONFIG_DMADEVICES_DEBUG is not set ++ ++# ++# DMA Devices ++# ++CONFIG_DMA_ENGINE=y ++CONFIG_DMA_VIRTUAL_CHANNELS=y ++CONFIG_DMA_OF=y ++# CONFIG_ALTERA_MSGDMA is not set ++# CONFIG_AMBA_PL08X is not set ++# CONFIG_DW_AXI_DMAC is not set ++# CONFIG_FSL_EDMA is not set ++# CONFIG_INTEL_IDMA64 is not set ++CONFIG_EDMACV310=y ++# CONFIG_MV_XOR_V2 is not set ++# CONFIG_PL330_DMA is not set ++# CONFIG_XILINX_DMA is not set ++# CONFIG_XILINX_ZYNQMP_DMA is not set ++# CONFIG_QCOM_HIDMA_MGMT is not set ++# CONFIG_QCOM_HIDMA is not set ++# CONFIG_DW_DMAC is not set ++# CONFIG_DW_DMAC_PCI is not set ++ ++# ++# DMA Clients ++# ++# CONFIG_ASYNC_TX_DMA is not set ++# CONFIG_DMATEST is not set ++ ++# ++# DMABUF options ++# ++# CONFIG_SYNC_FILE is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VFIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++# CONFIG_VIRTIO_MENU is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++# CONFIG_GOLDFISH is not set ++# CONFIG_CHROME_PLATFORMS is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_VERSATILE is not set ++# CONFIG_CLK_HSDK is not set ++# CONFIG_COMMON_CLK_MAX9485 is not set ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI514 is not set ++# CONFIG_COMMON_CLK_SI544 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_CDCE706 is not set ++# CONFIG_COMMON_CLK_CDCE925 is not set ++# CONFIG_COMMON_CLK_CS2000_CP is not set ++# CONFIG_CLK_QORIQ is not set ++# CONFIG_COMMON_CLK_XGENE is not set ++# CONFIG_COMMON_CLK_VC5 is not set ++CONFIG_COMMON_CLK_SS928V100=y ++CONFIG_RESET_BSP=y ++# CONFIG_HWSPINLOCK is not set ++ ++# ++# Clock Source drivers ++# ++CONFIG_TIMER_OF=y ++CONFIG_TIMER_PROBE=y ++CONFIG_CLKSRC_MMIO=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y ++# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set ++# CONFIG_FSL_ERRATUM_A008585 is not set ++CONFIG_HISILICON_ERRATUM_161010101=y ++CONFIG_ARM64_ERRATUM_858921=y ++CONFIG_ARM_TIMER_SP804=y ++# CONFIG_TIMER_BSP_SP804 is not set ++# CONFIG_MAILBOX is not set ++CONFIG_IOMMU_API=y ++CONFIG_IOMMU_SUPPORT=y ++ ++# ++# Generic IOMMU Pagetable Support ++# ++CONFIG_IOMMU_IO_PGTABLE=y ++CONFIG_IOMMU_IO_PGTABLE_LPAE=y ++# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set ++# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set ++ ++# ++# Generic PASID table support ++# ++CONFIG_IOMMU_PASID_TABLE=y ++CONFIG_ARM_SMMU_V3_CONTEXT=y ++# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set ++CONFIG_IOMMU_IOVA=y ++CONFIG_OF_IOMMU=y ++CONFIG_IOMMU_DMA=y ++CONFIG_IOMMU_SVA=y ++CONFIG_IOMMU_PAGE_FAULT=y ++# CONFIG_ARM_SMMU is not set ++CONFIG_ARM_SMMU_V3=y ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_REMOTEPROC is not set ++ ++# ++# Rpmsg drivers ++# ++# CONFIG_RPMSG_VIRTIO is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++ ++# ++# Amlogic SoC drivers ++# ++ ++# ++# Broadcom SoC drivers ++# ++# CONFIG_SOC_BRCMSTB is not set ++ ++# ++# NXP/Freescale QorIQ SoC drivers ++# ++ ++# ++# i.MX SoC drivers ++# ++ ++# ++# Qualcomm SoC drivers ++# ++# CONFIG_SOC_TI is not set ++ ++# ++# Xilinx SoC drivers ++# ++# CONFIG_XILINX_VCU is not set ++CONFIG_PM_DEVFREQ=y ++ ++# ++# DEVFREQ Governors ++# ++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y ++# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set ++# CONFIG_DEVFREQ_GOV_POWERSAVE is not set ++# CONFIG_DEVFREQ_GOV_USERSPACE is not set ++# CONFIG_DEVFREQ_GOV_PASSIVE is not set ++ ++# ++# DEVFREQ Drivers ++# ++# CONFIG_PM_DEVFREQ_EVENT is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_NTB is not set ++# CONFIG_VME_BUS is not set ++# CONFIG_PWM is not set ++ ++# ++# IRQ chip support ++# ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_MAX_NR=1 ++CONFIG_ARM_GIC_V2M=y ++CONFIG_ARM_GIC_V3=y ++CONFIG_ARM_GIC_V3_ITS=y ++CONFIG_ARM_GIC_V3_ITS_PCI=y ++CONFIG_HISILICON_IRQ_MBIGEN=y ++CONFIG_PARTITION_PERCPU=y ++# CONFIG_IPACK_BUS is not set ++CONFIG_RESET_CONTROLLER=y ++# CONFIG_RESET_TI_SYSCON is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++CONFIG_GENERIC_PHY=y ++# CONFIG_PHY_XGENE is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_PHY_PXA_28NM_HSIC is not set ++# CONFIG_PHY_PXA_28NM_USB2 is not set ++# CONFIG_PHY_MAPPHONE_MDM6600 is not set ++CONFIG_VENDOR_USB_PHY=y ++CONFIG_PHY_BSP_USB3=y ++CONFIG_BSP_USB_PHY=y ++CONFIG_USB_MODE_OPTION=y ++# CONFIG_USB_DRD0_IN_HOST is not set ++CONFIG_USB_DRD0_IN_DEVICE=y ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++# CONFIG_RAS is not set ++# CONFIG_LIBNVDIMM is not set ++# CONFIG_DAX is not set ++CONFIG_NVMEM=y ++ ++# ++# HW tracing support ++# ++# CONFIG_STM is not set ++# CONFIG_INTEL_TH is not set ++# CONFIG_FPGA is not set ++# CONFIG_FSI is not set ++# CONFIG_TEE is not set ++CONFIG_PM_OPP=y ++# CONFIG_SIOX is not set ++# CONFIG_SLIMBUS is not set ++ ++# ++# Vendor driver support ++# ++# CONFIG_CMA_MEM_SHARED is not set ++# CONFIG_CMA_ADVANCE_SHARE is not set ++CONFIG_VENDOR_NPU=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++CONFIG_FS_IOMAP=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT2=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++# CONFIG_EXT4_ENCRYPTION is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++CONFIG_XFS_FS=y ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++# CONFIG_XFS_ONLINE_SCRUB is not set ++# CONFIG_XFS_WARN is not set ++# CONFIG_XFS_DEBUG is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_F2FS_FS is not set ++# CONFIG_FS_DAX is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_EXPORTFS=y ++# CONFIG_EXPORTFS_BLOCK_OPS is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_MANDATORY_FILE_LOCKING=y ++# CONFIG_FS_ENCRYPTION is not set ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++CONFIG_QUOTA=y ++# CONFIG_QUOTA_NETLINK_INTERFACE is not set ++CONFIG_PRINT_QUOTA_WARNING=y ++# CONFIG_QUOTA_DEBUG is not set ++CONFIG_QUOTA_TREE=m ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_QUOTACTL=y ++CONFIG_AUTOFS4_FS=m ++CONFIG_AUTOFS_FS=m ++CONFIG_FUSE_FS=y ++# CONFIG_CUSE is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=y ++# CONFIG_JOLIET is not set ++# CONFIG_ZISOFS is not set ++CONFIG_UDF_FS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_FAT_DEFAULT_UTF8 is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++# CONFIG_PROC_CHILDREN is not set ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLBFS is not set ++CONFIG_MEMFD_CREATE=y ++CONFIG_ARCH_HAS_GIGANTIC_PAGE=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ORANGEFS_FS is not set ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++CONFIG_JFFS2_RTIME=y ++CONFIG_UBIFS_FS=y ++# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set ++CONFIG_UBIFS_FS_LZO=y ++CONFIG_UBIFS_FS_ZLIB=y ++# CONFIG_UBIFS_ATIME_SUPPORT is not set ++CONFIG_UBIFS_FS_XATTR=y ++# CONFIG_UBIFS_FS_ENCRYPTION is not set ++CONFIG_UBIFS_FS_SECURITY=y ++CONFIG_CRAMFS=y ++CONFIG_CRAMFS_BLOCKDEV=y ++# CONFIG_CRAMFS_MTD is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++# CONFIG_SQUASHFS_LZ4 is not set ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++# CONFIG_SQUASHFS_ZSTD is not set ++# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set ++# CONFIG_SQUASHFS_EMBEDDED is not set ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V2=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=y ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=y ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y ++# CONFIG_HARDENED_USERCOPY is not set ++# CONFIG_FORTIFY_SOURCE is not set ++# CONFIG_STATIC_USERMODEHELPER is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=m ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_RNG_DEFAULT=m ++CONFIG_CRYPTO_AKCIPHER2=y ++CONFIG_CRYPTO_KPP2=y ++CONFIG_CRYPTO_ACOMP2=y ++# CONFIG_CRYPTO_RSA is not set ++# CONFIG_CRYPTO_DH is not set ++# CONFIG_CRYPTO_ECDH is not set ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++CONFIG_CRYPTO_NULL=m ++CONFIG_CRYPTO_NULL2=y ++# CONFIG_CRYPTO_PCRYPT is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++CONFIG_CRYPTO_CCM=m ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_CHACHA20POLY1305 is not set ++# CONFIG_CRYPTO_AEGIS128 is not set ++# CONFIG_CRYPTO_AEGIS128L is not set ++# CONFIG_CRYPTO_AEGIS256 is not set ++# CONFIG_CRYPTO_MORUS640 is not set ++# CONFIG_CRYPTO_MORUS1280 is not set ++CONFIG_CRYPTO_SEQIV=m ++CONFIG_CRYPTO_ECHAINIV=m ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CFB is not set ++CONFIG_CRYPTO_CTR=m ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++# CONFIG_CRYPTO_KEYWRAP is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=m ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_POLY1305 is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA3 is not set ++# CONFIG_CRYPTO_SM3 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_TI is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_CHACHA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_SM4 is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_842 is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++# CONFIG_CRYPTO_ZSTD is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_DRBG_MENU=m ++CONFIG_CRYPTO_DRBG_HMAC=y ++# CONFIG_CRYPTO_DRBG_HASH is not set ++# CONFIG_CRYPTO_DRBG_CTR is not set ++CONFIG_CRYPTO_DRBG=m ++CONFIG_CRYPTO_JITTERENTROPY=m ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_USER_API_RNG is not set ++# CONFIG_CRYPTO_USER_API_AEAD is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_CCP is not set ++# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set ++# CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set ++# CONFIG_CRYPTO_DEV_CCREE is not set ++# CONFIG_CRYPTO_DEV_HISI_SEC is not set ++ ++# ++# Certificates for signature checking ++# ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_HAVE_ARCH_BITREVERSE=y ++CONFIG_RATIONAL=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++CONFIG_ARCH_HAS_FAST_MULTIPLIER=y ++# CONFIG_INDIRECT_PIO is not set ++CONFIG_CRC_CCITT=y ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC64 is not set ++# CONFIG_CRC4 is not set ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++# CONFIG_CRC8 is not set ++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_NEED_SG_DMA_LENGTH=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_DMA_ADDR_T_64BIT=y ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_DMA_DIRECT_OPS=y ++CONFIG_SWIOTLB=y ++CONFIG_SGL_ALLOC=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++# CONFIG_IRQ_POLL is not set ++CONFIG_LIBFDT=y ++CONFIG_SG_POOL=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++CONFIG_SBITMAP=y ++# CONFIG_STRING_SELFTEST is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 ++CONFIG_CONSOLE_LOGLEVEL_QUIET=4 ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=2048 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_PAGE_OWNER is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_SECTION_MISMATCH_WARN_ONLY=y ++CONFIG_ARCH_WANT_FRAME_POINTERS=y ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 ++CONFIG_MAGIC_SYSRQ_SERIAL=y ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_PAGE_EXTENSION is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_PAGE_POISONING is not set ++# CONFIG_DEBUG_RODATA_TEST is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y ++# CONFIG_DEBUG_VIRTUAL is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++CONFIG_HAVE_ARCH_KASAN=y ++# CONFIG_KASAN is not set ++CONFIG_ARCH_HAS_KCOV=y ++CONFIG_CC_HAS_SANCOV_TRACE_PC=y ++# CONFIG_KCOV is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_SOFTLOCKUP_DETECTOR is not set ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_WQ_WATCHDOG is not set ++CONFIG_PANIC_ON_OOPS=y ++CONFIG_PANIC_ON_OOPS_VALUE=1 ++CONFIG_PANIC_TIMEOUT=0 ++CONFIG_SCHED_DEBUG=y ++CONFIG_SCHED_INFO=y ++CONFIG_SCHEDSTATS=y ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_DEBUG_TIMEKEEPING is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_LOCK_DEBUGGING_SUPPORT=y ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_RWSEMS is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_WW_MUTEX_SELFTEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_HAVE_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_RCU_PERF_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=60 ++CONFIG_RCU_TRACE=y ++# CONFIG_RCU_EQS_DEBUG is not set ++# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACE_CLOCK=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++# CONFIG_DMA_API_DEBUG is not set ++CONFIG_RUNTIME_TESTING_MENU=y ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_TEST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_HEXDUMP is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_PRINTF is not set ++# CONFIG_TEST_BITMAP is not set ++# CONFIG_TEST_BITFIELD is not set ++# CONFIG_TEST_UUID is not set ++# CONFIG_TEST_OVERFLOW is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_TEST_HASH is not set ++# CONFIG_TEST_IDA is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_FIND_BIT_BENCHMARK is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_SYSCTL is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_TEST_STATIC_KEYS is not set ++# CONFIG_TEST_KMOD is not set ++# CONFIG_MEMTEST is not set ++# CONFIG_BUG_ON_DATA_CORRUPTION is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y ++# CONFIG_UBSAN is not set ++CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM64_PTDUMP_DEBUGFS is not set ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set ++# CONFIG_DEBUG_WX is not set ++# CONFIG_DEBUG_ALIGN_RODATA is not set ++# CONFIG_ARM64_RELOC_TEST is not set ++# CONFIG_CORESIGHT is not set +diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c +index 1006ed2d7c60..cdbd2606e4b8 100644 +--- a/arch/arm64/kernel/pci.c ++++ b/arch/arm64/kernel/pci.c +@@ -29,6 +29,18 @@ int pcibios_alloc_irq(struct pci_dev *dev) + + return 0; + } ++#else ++#ifdef CONFIG_ARCH_BSP ++/* ++ * Try to assign the IRQ number when probing a new device ++ */ ++int pcibios_alloc_irq(struct pci_dev *dev) ++{ ++ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); ++ ++ return 0; ++} ++#endif + #endif + + /* +diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c +index be67a9c42628..ab6cdc8a503c 100644 +--- a/arch/arm64/mm/init.c ++++ b/arch/arm64/mm/init.c +@@ -188,6 +188,10 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max) + unsigned int __maybe_unused acpi_zone_dma_bits; + unsigned int __maybe_unused dt_zone_dma_bits; + phys_addr_t __maybe_unused dma32_phys_limit = max_zone_phys(32); ++//#ifdef CONFIG_ARCH_BSP ++// extern phys_addr_t get_zones_start(void); ++// dma32_phys_limit = min(dma32_phys_limit, get_zones_start()); ++//#endif + + #ifdef CONFIG_ZONE_DMA + acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address()); +diff --git a/drivers/Kconfig b/drivers/Kconfig +index b1b3d958f065..0f5c83ae9bd8 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -240,4 +240,6 @@ source "drivers/most/Kconfig" + + source "drivers/roh/Kconfig" + ++source "drivers/vendor/Kconfig" ++ + endmenu +diff --git a/drivers/Makefile b/drivers/Makefile +index bfbf65533169..10342bad3b90 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -192,3 +192,4 @@ obj-$(CONFIG_INTERCONNECT) += interconnect/ + obj-$(CONFIG_COUNTER) += counter/ + obj-$(CONFIG_MOST) += most/ + obj-$(CONFIG_ROH) += roh/ ++obj-$(CONFIG_ARCH_BSP) += vendor/ +diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig +index c715d4681a0b..39c659f7a68d 100644 +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -384,5 +384,6 @@ source "drivers/clk/ti/Kconfig" + source "drivers/clk/uniphier/Kconfig" + source "drivers/clk/x86/Kconfig" + source "drivers/clk/zynqmp/Kconfig" ++source "drivers/clk/vendor/Kconfig" + + endif +diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile +index da8fcf147eb1..833b7600d36f 100644 +--- a/drivers/clk/Makefile ++++ b/drivers/clk/Makefile +@@ -124,3 +124,4 @@ endif + obj-$(CONFIG_ARCH_ZX) += zte/ + obj-$(CONFIG_ARCH_ZYNQ) += zynq/ + obj-$(CONFIG_COMMON_CLK_ZYNQMP) += zynqmp/ ++obj-$(CONFIG_ARCH_BSP) += vendor/ +diff --git a/drivers/clk/vendor/Kconfig b/drivers/clk/vendor/Kconfig +new file mode 100644 +index 000000000000..4f446ec69e8e +--- /dev/null ++++ b/drivers/clk/vendor/Kconfig +@@ -0,0 +1,12 @@ ++ ++ ++config RESET_BSP ++ bool "Vendor Reset Controller Driver" ++ default y ++ help ++ Build reset controller driver for Vendor device chipsets. ++config COMMON_CLK_SS928V100 ++ tristate "SS928V100 Clock Driver" ++ default y ++ help ++ build the clock driver for SS928V100 +diff --git a/drivers/clk/vendor/Makefile b/drivers/clk/vendor/Makefile +new file mode 100644 +index 000000000000..a2a3626a9954 +--- /dev/null ++++ b/drivers/clk/vendor/Makefile +@@ -0,0 +1,8 @@ ++# SPDX-License-Identifier: GPL-2.0 ++# ++ ++obj-y += clk.o clkgate_separated.o ++ ++obj-$(CONFIG_ARCH_HI3519DV500_FAMILY) += clk_hi3519dv500.o ++obj-$(CONFIG_RESET_BSP) += reset.o ++obj-$(CONFIG_COMMON_CLK_SS928V100) += clk_ss928v100.o +diff --git a/drivers/clk/vendor/clk.c b/drivers/clk/vendor/clk.c +new file mode 100644 +index 000000000000..ceef293f073f +--- /dev/null ++++ b/drivers/clk/vendor/clk.c +@@ -0,0 +1,288 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk.h" ++ ++static DEFINE_SPINLOCK(bsp_clk_lock); ++ ++struct bsp_clock_data *bsp_clk_alloc(struct platform_device *pdev, ++ int nr_clks) ++{ ++ struct bsp_clock_data *clk_data; ++ struct resource *res; ++ struct clk **clk_table; ++ ++ clk_data = devm_kmalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); ++ if (!clk_data) ++ return NULL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ return NULL; ++ clk_data->base = devm_ioremap(&pdev->dev, ++ res->start, resource_size(res)); ++ if (!clk_data->base) ++ return NULL; ++ ++ clk_table = devm_kmalloc_array(&pdev->dev, nr_clks, ++ sizeof(*clk_table), ++ GFP_KERNEL); ++ if (!clk_table) ++ return NULL; ++ ++ clk_data->clk_data.clks = clk_table; ++ clk_data->clk_data.clk_num = nr_clks; ++ ++ return clk_data; ++} ++EXPORT_SYMBOL_GPL(bsp_clk_alloc); ++ ++struct bsp_clock_data *bsp_clk_init(struct device_node *np, ++ int nr_clks) ++{ ++ struct bsp_clock_data *clk_data; ++ struct clk **clk_table; ++ void __iomem *base; ++ ++ base = of_iomap(np, 0); ++ if (!base) { ++ pr_err("%s: failed to map clock registers\n", __func__); ++ goto err; ++ } ++ ++ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); ++ if (!clk_data) ++ goto err; ++ ++ clk_data->base = base; ++ clk_table = kcalloc(nr_clks, sizeof(*clk_table), GFP_KERNEL); ++ if (!clk_table) ++ goto err_data; ++ ++ clk_data->clk_data.clks = clk_table; ++ clk_data->clk_data.clk_num = nr_clks; ++ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); ++ return clk_data; ++err_data: ++ if (base) { ++ iounmap(base); ++ base = NULL; ++ } ++ kfree(clk_data); ++err: ++ return NULL; ++} ++EXPORT_SYMBOL_GPL(bsp_clk_init); ++ ++int bsp_clk_register_fixed_rate(const struct bsp_fixed_rate_clock *clks, ++ int nums, struct bsp_clock_data *data) ++{ ++ struct clk *clk; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ clk = clk_register_fixed_rate(NULL, clks[i].name, ++ clks[i].parent_name, ++ clks[i].flags, ++ clks[i].fixed_rate); ++ if (IS_ERR(clk)) { ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ goto err; ++ } ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++ ++ return 0; ++ ++err: ++ while (i--) ++ clk_unregister_fixed_rate(data->clk_data.clks[clks[i].id]); ++ ++ return PTR_ERR(clk); ++} ++EXPORT_SYMBOL_GPL(bsp_clk_register_fixed_rate); ++ ++int bsp_clk_register_fixed_factor(const struct bsp_fixed_factor_clock *clks, ++ int nums, ++ struct bsp_clock_data *data) ++{ ++ struct clk *clk; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ clk = clk_register_fixed_factor(NULL, clks[i].name, ++ clks[i].parent_name, ++ clks[i].flags, clks[i].mult, ++ clks[i].div); ++ if (IS_ERR(clk)) { ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ goto err; ++ } ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++ ++ return 0; ++ ++err: ++ while (i--) ++ clk_unregister_fixed_factor(data->clk_data.clks[clks[i].id]); ++ ++ return PTR_ERR(clk); ++} ++EXPORT_SYMBOL_GPL(bsp_clk_register_fixed_factor); ++ ++int bsp_clk_register_mux(const struct bsp_mux_clock *clks, ++ int nums, struct bsp_clock_data *data) ++{ ++ struct clk *clk; ++ void __iomem *base = data->base; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ u32 mask = BIT(clks[i].width) - 1; ++ ++ clk = clk_register_mux_table(NULL, clks[i].name, ++ clks[i].parent_names, ++ clks[i].num_parents, clks[i].flags, ++ base + clks[i].offset, clks[i].shift, ++ mask, clks[i].mux_flags, ++ clks[i].table, &bsp_clk_lock); ++ if (IS_ERR(clk)) { ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ goto err; ++ } ++ ++ if (clks[i].alias) ++ clk_register_clkdev(clk, clks[i].alias, NULL); ++ ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++ ++ return 0; ++ ++err: ++ while (i--) ++ clk_unregister_mux(data->clk_data.clks[clks[i].id]); ++ ++ return PTR_ERR(clk); ++} ++EXPORT_SYMBOL_GPL(bsp_clk_register_mux); ++ ++int bsp_clk_register_divider(const struct bsp_divider_clock *clks, ++ int nums, struct bsp_clock_data *data) ++{ ++ struct clk *clk; ++ void __iomem *base = data->base; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ clk = clk_register_divider_table(NULL, clks[i].name, ++ clks[i].parent_name, ++ clks[i].flags, ++ base + clks[i].offset, ++ clks[i].shift, clks[i].width, ++ clks[i].div_flags, ++ clks[i].table, ++ &bsp_clk_lock); ++ if (IS_ERR(clk)) { ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ goto err; ++ } ++ ++ if (clks[i].alias) ++ clk_register_clkdev(clk, clks[i].alias, NULL); ++ ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++ ++ return 0; ++ ++err: ++ while (i--) ++ clk_unregister_divider(data->clk_data.clks[clks[i].id]); ++ ++ return PTR_ERR(clk); ++} ++EXPORT_SYMBOL_GPL(bsp_clk_register_divider); ++ ++int bsp_clk_register_gate(const struct bsp_gate_clock *clks, ++ int nums, struct bsp_clock_data *data) ++{ ++ struct clk *clk; ++ void __iomem *base = data->base; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ clk = clk_register_gate(NULL, clks[i].name, ++ clks[i].parent_name, ++ clks[i].flags, ++ base + clks[i].offset, ++ clks[i].bit_idx, ++ clks[i].gate_flags, ++ &bsp_clk_lock); ++ if (IS_ERR(clk)) { ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ goto err; ++ } ++ ++ if (clks[i].alias) ++ clk_register_clkdev(clk, clks[i].alias, NULL); ++ ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++ ++ return 0; ++ ++err: ++ while (i--) ++ clk_unregister_gate(data->clk_data.clks[clks[i].id]); ++ ++ return PTR_ERR(clk); ++} ++EXPORT_SYMBOL_GPL(bsp_clk_register_gate); ++ ++void bsp_clk_register_gate_sep(const struct bsp_gate_clock *clks, ++ int nums, struct bsp_clock_data *data) ++{ ++ struct clk *clk; ++ void __iomem *base = data->base; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ clk = bsp_register_clkgate_sep(NULL, clks[i].name, ++ clks[i].parent_name, ++ clks[i].flags, ++ base + clks[i].offset, ++ clks[i].bit_idx, ++ clks[i].gate_flags, ++ &bsp_clk_lock); ++ if (IS_ERR(clk)) { ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ continue; ++ } ++ ++ if (clks[i].alias) ++ clk_register_clkdev(clk, clks[i].alias, NULL); ++ ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++} ++EXPORT_SYMBOL_GPL(bsp_clk_register_gate_sep); ++ +diff --git a/drivers/clk/vendor/clk.h b/drivers/clk/vendor/clk.h +new file mode 100644 +index 000000000000..f197a9bc06fd +--- /dev/null ++++ b/drivers/clk/vendor/clk.h +@@ -0,0 +1,127 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef __BSP_CLK_H ++#define __BSP_CLK_H ++ ++#include ++#include ++#include ++ ++struct platform_device; ++ ++struct bsp_clock_data { ++ struct clk_onecell_data clk_data; ++ void __iomem *base; ++}; ++ ++struct bsp_fixed_rate_clock { ++ unsigned int id; ++ char *name; ++ const char *parent_name; ++ unsigned long flags; ++ unsigned long fixed_rate; ++}; ++ ++struct bsp_fixed_factor_clock { ++ unsigned int id; ++ char *name; ++ const char *parent_name; ++ unsigned long mult; ++ unsigned long div; ++ unsigned long flags; ++}; ++ ++struct bsp_mux_clock { ++ unsigned int id; ++ const char *name; ++ const char *const *parent_names; ++ u8 num_parents; ++ unsigned long flags; ++ unsigned long offset; ++ u8 shift; ++ u8 width; ++ u8 mux_flags; ++ u32 *table; ++ const char *alias; ++}; ++ ++struct bsp_phase_clock { ++ unsigned int id; ++ const char *name; ++ const char *parent_names; ++ unsigned long flags; ++ unsigned long offset; ++ u8 shift; ++ u8 width; ++ u32 *phase_degrees; ++ u32 *phase_regvals; ++ u8 phase_num; ++}; ++ ++struct bsp_divider_clock { ++ unsigned int id; ++ const char *name; ++ const char *parent_name; ++ unsigned long flags; ++ unsigned long offset; ++ u8 shift; ++ u8 width; ++ u8 div_flags; ++ struct clk_div_table *table; ++ const char *alias; ++}; ++ ++struct bsp_gate_clock { ++ unsigned int id; ++ const char *name; ++ const char *parent_name; ++ unsigned long flags; ++ unsigned long offset; ++ u8 bit_idx; ++ u8 gate_flags; ++ const char *alias; ++}; ++ ++struct clk *bsp_register_clkgate_sep(struct device *, const char *, ++ const char *, unsigned long, ++ void __iomem *, u8, ++ u8, spinlock_t *); ++ ++struct bsp_clock_data *bsp_clk_alloc(struct platform_device *, int); ++struct bsp_clock_data *bsp_clk_init(struct device_node *, int); ++int bsp_clk_register_fixed_rate(const struct bsp_fixed_rate_clock *, ++ int, struct bsp_clock_data *); ++int bsp_clk_register_fixed_factor(const struct bsp_fixed_factor_clock *, ++ int, struct bsp_clock_data *); ++int bsp_clk_register_mux(const struct bsp_mux_clock *, int, ++ struct bsp_clock_data *); ++int bsp_clk_register_divider(const struct bsp_divider_clock *, ++ int, struct bsp_clock_data *); ++int bsp_clk_register_gate(const struct bsp_gate_clock *, ++ int, struct bsp_clock_data *); ++void bsp_clk_register_gate_sep(const struct bsp_gate_clock *, ++ int, struct bsp_clock_data *); ++ ++#define bsp_clk_unregister(type) \ ++static inline \ ++void bsp_clk_unregister_##type(const struct bsp_##type##_clock *clks, \ ++ int nums, struct bsp_clock_data *data) \ ++{ \ ++ struct clk **clocks = data->clk_data.clks; \ ++ int i; \ ++ for (i = 0; i < nums; i++) { \ ++ int id = clks[i].id; \ ++ if (clocks[id]) \ ++ clk_unregister_##type(clocks[id]); \ ++ } \ ++} ++ ++bsp_clk_unregister(fixed_rate) ++bsp_clk_unregister(fixed_factor) ++bsp_clk_unregister(mux) ++bsp_clk_unregister(divider) ++bsp_clk_unregister(gate) ++ ++#endif /* __BSP_CLK_H */ +diff --git a/drivers/clk/vendor/clk_hi3519dv500.c b/drivers/clk/vendor/clk_hi3519dv500.c +new file mode 100644 +index 000000000000..e2c106fa3249 +--- /dev/null ++++ b/drivers/clk/vendor/clk_hi3519dv500.c +@@ -0,0 +1,507 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk.h" ++#include "crg.h" ++#include "reset.h" ++ ++/* soc clk config */ ++static const struct bsp_fixed_rate_clock hi3519dv500_fixed_rate_clks_crg[] = { ++ { HI3519DV500_FIXED_2400M, "2400m", NULL, 0, 2400000000, }, ++ { HI3519DV500_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, ++ { HI3519DV500_FIXED_1188M, "1188m", NULL, 0, 1188000000, }, ++ { HI3519DV500_FIXED_896M, "896m", NULL, 0, 896000000, }, ++ { HI3519DV500_FIXED_800M, "800m", NULL, 0, 800000000, }, ++ { HI3519DV500_FIXED_792M, "792m", NULL, 0, 792000000, }, ++ { HI3519DV500_FIXED_786M, "786m", NULL, 0, 786000000, }, ++ { HI3519DV500_FIXED_750M, "750m", NULL, 0, 750000000, }, ++ { HI3519DV500_FIXED_700M, "700m", NULL, 0, 700000000, }, ++ { HI3519DV500_FIXED_672M, "672m", NULL, 0, 672000000, }, ++ { HI3519DV500_FIXED_600M, "600m", NULL, 0, 600000000, }, ++ { HI3519DV500_FIXED_594M, "594m", NULL, 0, 594000000, }, ++ { HI3519DV500_FIXED_560M, "560m", NULL, 0, 560000000, }, ++ { HI3519DV500_FIXED_500M, "500m", NULL, 0, 500000000, }, ++ { HI3519DV500_FIXED_475M, "475m", NULL, 0, 475000000, }, ++ { HI3519DV500_FIXED_396M, "396m", NULL, 0, 396000000, }, ++ { HI3519DV500_FIXED_300M, "300m", NULL, 0, 300000000, }, ++ { HI3519DV500_FIXED_297M, "297m", NULL, 0, 297000000, }, ++ { HI3519DV500_FIXED_257M, "257m", NULL, 0, 257000000, }, ++ { HI3519DV500_FIXED_250M, "250m", NULL, 0, 250000000, }, ++ { HI3519DV500_FIXED_200M, "200m", NULL, 0, 200000000, }, ++ { HI3519DV500_FIXED_198M, "198m", NULL, 0, 198000000, }, ++ { HI3519DV500_FIXED_187P_5M, "187p5m", NULL, 0, 187500000, }, ++ { HI3519DV500_FIXED_150M, "150m", NULL, 0, 150000000, }, ++ { HI3519DV500_FIXED_148P_5M, "148p5m", NULL, 0, 148500000, }, ++ { HI3519DV500_FIXED_134M, "134m", NULL, 0, 134000000, }, ++ { HI3519DV500_FIXED_108M, "108m", NULL, 0, 108000000, }, ++ { HI3519DV500_FIXED_100M, "100m", NULL, 0, 100000000, }, ++ { HI3519DV500_FIXED_99M, "99m", NULL, 0, 99000000, }, ++ { HI3519DV500_FIXED_74P_25M, "74p25m", NULL, 0, 74250000, }, ++ { HI3519DV500_FIXED_72M, "72m", NULL, 0, 72000000, }, ++ { HI3519DV500_FIXED_64M, "64m", NULL, 0, 64000000, }, ++ { HI3519DV500_FIXED_60M, "60m", NULL, 0, 60000000, }, ++ { HI3519DV500_FIXED_54M, "54m", NULL, 0, 54000000, }, ++ { HI3519DV500_FIXED_50M, "50m", NULL, 0, 50000000, }, ++ { HI3519DV500_FIXED_49P_5M, "49p5m", NULL, 0, 49500000, }, ++ { HI3519DV500_FIXED_37P_125M, "37p125m", NULL, 0, 37125000, }, ++ { HI3519DV500_FIXED_36M, "36m", NULL, 0, 36000000, }, ++ { HI3519DV500_FIXED_27M, "27m", NULL, 0, 27000000, }, ++ { HI3519DV500_FIXED_25M, "25m", NULL, 0, 25000000, }, ++ { HI3519DV500_FIXED_24M, "24m", NULL, 0, 24000000, }, ++ { HI3519DV500_FIXED_12M, "12m", NULL, 0, 12000000, }, ++ { HI3519DV500_FIXED_12P_288M, "12p288m", NULL, 0, 12288000, }, ++ { HI3519DV500_FIXED_6M, "6m", NULL, 0, 6000000, }, ++ { HI3519DV500_FIXED_3M, "3m", NULL, 0, 3000000, }, ++ { HI3519DV500_FIXED_1P_6M, "1p6m", NULL, 0, 1600000, }, ++ { HI3519DV500_FIXED_400K, "400k", NULL, 0, 400000, }, ++ { HI3519DV500_FIXED_100K, "100k", NULL, 0, 100000, }, ++}; ++ ++ ++static const char *fmc_mux_p[] __initdata = { ++ "24m", "100m", "150m", "198m", "237m", "300m", "396m" ++}; ++static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6}; ++ ++static const char *mmc_mux_p[] __initdata = { ++ "400k", "25m", "50m", "100m", "150m", "187p5m", "200m" ++}; ++static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; ++ ++static const char *sdio0_mux_p[] __initdata = { ++ "400k", "25m", "50m", "100m", "150m", "187p5m", "200m" ++}; ++static u32 sdio0_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; ++ ++static const char *sdio1_mux_p[] __initdata = { ++ "400k", "25m", "50m", "100m", "150m", "187p5m", "200m" ++}; ++static u32 sdio1_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7}; ++ ++static const char *uart_mux_p[] __initdata = {"100m", "50m", "24m", "3m"}; ++static u32 uart_mux_table[] = {0, 1, 2, 3}; ++ ++static const char *i2c_mux_p[] __initdata = { ++ "50m", "100m" ++}; ++static u32 i2c_mux_table[] = {0, 1}; ++ ++static const char * pwm0_mux_p[] __initdata = {"198m"}; ++static u32 pwm0_mux_table[] = {0}; ++ ++static const char * pwm1_mux_p[] __initdata = {"198m"}; ++static u32 pwm1_mux_table[] = {0}; ++ ++static const char * pwm2_mux_p[] __initdata = {"198m"}; ++static u32 pwm2_mux_table[] = {0}; ++ ++static struct bsp_mux_clock hi3519dv500_mux_clks_crg[] __initdata = { ++ { ++ HI3519DV500_FMC_MUX, "fmc_mux", ++ fmc_mux_p, ARRAY_SIZE(fmc_mux_p), ++ CLK_SET_RATE_PARENT, 0x3f40, 12, 3, 0, fmc_mux_table, ++ }, ++ { ++ HI3519DV500_MMC0_MUX, "mmc0_mux", ++ mmc_mux_p, ARRAY_SIZE(mmc_mux_p), ++ CLK_SET_RATE_PARENT, 0x34c0, 24, 3, 0, mmc_mux_table, ++ }, ++ { ++ HI3519DV500_MMC1_MUX, "mmc1_mux", ++ sdio0_mux_p, ARRAY_SIZE(sdio0_mux_p), ++ CLK_SET_RATE_PARENT, 0x35c0, 24, 3, 0, sdio0_mux_table, ++ }, ++ { ++ HI3519DV500_MMC2_MUX, "mmc2_mux", ++ sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p), ++ CLK_SET_RATE_PARENT, 0x36c0, 24, 3, 0, sdio1_mux_table, ++ }, ++ { ++ HI3519DV500_UART0_MUX, "uart0_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4180, 12, 2, 0, uart_mux_table ++ }, ++ { ++ HI3519DV500_UART1_MUX, "uart1_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4188, 12, 2, 0, uart_mux_table ++ }, ++ { ++ HI3519DV500_UART2_MUX, "uart2_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4190, 12, 2, 0, uart_mux_table ++ }, ++ { ++ HI3519DV500_UART3_MUX, "uart3_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4198, 12, 2, 0, uart_mux_table ++ }, ++ { ++ HI3519DV500_UART4_MUX, "uart4_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x41a0, 12, 2, 0, uart_mux_table ++ }, ++ { ++ HI3519DV500_UART5_MUX, "uart5_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x41a8, 12, 2, 0, uart_mux_table ++ }, ++ { ++ HI3519DV500_I2C0_MUX, "i2c0_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4280, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C1_MUX, "i2c1_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4288, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C2_MUX, "i2c2_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4290, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C3_MUX, "i2c3_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4298, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C4_MUX, "i2c4_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x42a0, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C5_MUX, "i2c5_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x42a8, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C6_MUX, "i2c6_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x42b0, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_I2C7_MUX, "i2c7_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x42b8, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ HI3519DV500_PWM0_MUX, "pwm0_mux", ++ pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), ++ CLK_SET_RATE_PARENT, 0x4588, 12, 2, 0, pwm0_mux_table ++ }, ++ { ++ HI3519DV500_PWM1_MUX, "pwm1_mux", ++ pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), ++ CLK_SET_RATE_PARENT, 0x4590, 12, 2, 0, pwm1_mux_table ++ }, ++ { ++ HI3519DV500_PWM2_MUX, "pwm2_mux", ++ pwm2_mux_p, ARRAY_SIZE(pwm2_mux_p), ++ CLK_SET_RATE_PARENT, 0x4598, 12, 2, 0, pwm2_mux_table ++ }, ++}; ++ ++static struct bsp_fixed_factor_clock ++ hi3519dv500_fixed_factor_clks[] __initdata = { ++}; ++ ++static struct bsp_gate_clock hi3519dv500_gate_clks[] __initdata = { ++ { ++ HI3519DV500_FMC_CLK, "clk_fmc", "fmc_mux", ++ CLK_SET_RATE_PARENT, 0x3f40, 4, 0, ++ }, ++ { ++ HI3519DV500_MMC0_CLK, "clk_mmc0", "mmc0_mux", ++ CLK_SET_RATE_PARENT, 0x34c0, 0, 0, ++ }, ++ { ++ HI3519DV500_MMC0_HCLK, "hclk_mmc0", NULL, ++ CLK_SET_RATE_PARENT, 0x34c0, 1, 0, ++ }, ++ { ++ HI3519DV500_MMC1_CLK, "clk_mmc1", "mmc1_mux", ++ CLK_SET_RATE_PARENT, 0x35c0, 0, 0, ++ }, ++ { ++ HI3519DV500_MMC1_HCLK, "hclk_mmc1", NULL, ++ CLK_SET_RATE_PARENT, 0x35c0, 1, 0, ++ }, ++ { ++ HI3519DV500_MMC2_CLK, "clk_mmc2", "mmc2_mux", ++ CLK_SET_RATE_PARENT, 0x36c0, 0, 0, ++ }, ++ { ++ HI3519DV500_MMC2_HCLK, "hclk_mmc2", NULL, ++ CLK_SET_RATE_PARENT, 0x36c0, 1, 0, ++ }, ++ { ++ HI3519DV500_UART0_CLK, "clk_uart0", "uart0_mux", ++ CLK_SET_RATE_PARENT, 0x4180, 4, 0, ++ }, ++ { ++ HI3519DV500_UART1_CLK, "clk_uart1", "uart1_mux", ++ CLK_SET_RATE_PARENT, 0x4188, 4, 0, ++ }, ++ { ++ HI3519DV500_UART2_CLK, "clk_uart2", "uart2_mux", ++ CLK_SET_RATE_PARENT, 0x4190, 4, 0, ++ }, ++ { ++ HI3519DV500_UART3_CLK, "clk_uart3", "uart3_mux", ++ CLK_SET_RATE_PARENT, 0x4198, 4, 0, ++ }, ++ { ++ HI3519DV500_UART4_CLK, "clk_uart4", "uart4_mux", ++ CLK_SET_RATE_PARENT, 0x41A0, 4, 0, ++ }, ++ { ++ HI3519DV500_UART5_CLK, "clk_uart5", "uart5_mux", ++ CLK_SET_RATE_PARENT, 0x41a8, 4, 0, ++ }, ++ /* ethernet mac */ ++ { ++ HI3519DV500_ETH_CLK, "clk_eth", NULL, ++ CLK_SET_RATE_PARENT, 0x37c4, 4, 0, ++ }, ++ { ++ HI3519DV500_ETH_MACIF_CLK, "clk_eth_macif", NULL, ++ CLK_SET_RATE_PARENT, 0x37c0, 4, 0, ++ }, ++ { ++ HI3519DV500_ETH1_CLK, "clk_eth1", NULL, ++ CLK_SET_RATE_PARENT, 0x3804, 4, 0, ++ }, ++ { ++ HI3519DV500_ETH1_MACIF_CLK, "clk_eth1_macif", NULL, ++ CLK_SET_RATE_PARENT, 0x3800, 4, 0, ++ }, ++ { ++ HI3519DV500_I2C0_CLK, "clk_i2c0", "i2c0_mux", ++ CLK_SET_RATE_PARENT, 0x4280, 4, 0, ++ }, ++ { ++ HI3519DV500_I2C1_CLK, "clk_i2c1", "i2c1_mux", ++ CLK_SET_RATE_PARENT, 0x4288, 4, 0, ++ }, ++ { ++ HI3519DV500_I2C2_CLK, "clk_i2c2", "i2c2_mux", ++ CLK_SET_RATE_PARENT, 0x4290, 4, 0, ++ }, ++ { ++ HI3519DV500_I2C3_CLK, "clk_i2c3", "i2c3_mux", ++ CLK_SET_RATE_PARENT, 0x4298, 4, 0, ++ }, ++ { ++ HI3519DV500_I2C4_CLK, "clk_i2c4", "i2c4_mux", ++ CLK_SET_RATE_PARENT, 0x42a0, 4, 0, ++ }, ++ { HI3519DV500_I2C5_CLK, "clk_i2c5", "i2c5_mux", ++ CLK_SET_RATE_PARENT, 0x42a8, 4, 0, ++ }, ++ { HI3519DV500_I2C6_CLK, "clk_i2c6", "i2c6_mux", ++ CLK_SET_RATE_PARENT, 0x42b0, 4, 0, ++ }, ++ { HI3519DV500_I2C7_CLK, "clk_i2c7", "i2c7_mux", ++ CLK_SET_RATE_PARENT, 0x42b8, 4, 0, ++ }, ++ /* spi */ ++ { ++ HI3519DV500_SPI0_CLK, "clk_spi0", "100m", ++ CLK_SET_RATE_PARENT, 0x4480, 4, 0, ++ }, ++ { ++ HI3519DV500_SPI1_CLK, "clk_spi1", "100m", ++ CLK_SET_RATE_PARENT, 0x4488, 4, 0, ++ }, ++ { ++ HI3519DV500_SPI2_CLK, "clk_spi2", "100m", ++ CLK_SET_RATE_PARENT, 0x4490, 4, 0, ++ }, ++ { ++ HI3519DV500_SPI3_CLK, "clk_spi3", "100m", ++ CLK_SET_RATE_PARENT, 0x4498, 4, 0, ++ }, ++ { ++ HI3519DV500_EDMAC_AXICLK, "axi_clk_edmac", NULL, ++ CLK_SET_RATE_PARENT, 0x2a80, 5, 0, ++ }, ++ { ++ HI3519DV500_EDMAC_CLK, "clk_edmac", NULL, ++ CLK_SET_RATE_PARENT, 0x2a80, 4, 0, ++ }, ++ /* lsadc */ ++ { ++ HI3519DV500_LSADC_CLK, "clk_lsadc", NULL, ++ CLK_SET_RATE_PARENT, 0x46c0, 4, 0, ++ }, ++ /* pwm0 */ ++ { ++ HI3519DV500_PWM0_CLK, "clk_pwm0", "pwm0_mux", ++ CLK_SET_RATE_PARENT, 0x4588, 4, 0, ++ }, ++ /* pwm1 */ ++ { ++ HI3519DV500_PWM1_CLK, "clk_pwm1", "pwm1_mux", ++ CLK_SET_RATE_PARENT, 0x4590, 4, 0, ++ }, ++ /* pwm2 */ ++ { ++ HI3519DV500_PWM2_CLK, "clk_pwm2", "pwm2_mux", ++ CLK_SET_RATE_PARENT, 0x4598, 4, 0, ++ }, ++}; ++ ++static __init struct bsp_clock_data *hi3519dv500_clk_register( ++ struct platform_device *pdev) ++{ ++ struct bsp_clock_data *clk_data = NULL; ++ int ret; ++ ++ clk_data = bsp_clk_alloc(pdev, HI3519DV500_CRG_NR_CLKS); ++ if (clk_data == NULL) ++ return ERR_PTR(-ENOMEM); ++ ++ ret = bsp_clk_register_fixed_rate(hi3519dv500_fixed_rate_clks_crg, ++ ARRAY_SIZE(hi3519dv500_fixed_rate_clks_crg), clk_data); ++ if (ret) ++ return ERR_PTR(ret); ++ ++ ret = bsp_clk_register_mux(hi3519dv500_mux_clks_crg, ++ ARRAY_SIZE(hi3519dv500_mux_clks_crg), ++ clk_data); ++ if (ret) ++ goto unregister_fixed_rate; ++ ++ ret = bsp_clk_register_fixed_factor(hi3519dv500_fixed_factor_clks, ++ ARRAY_SIZE(hi3519dv500_fixed_factor_clks), clk_data); ++ if (ret) ++ goto unregister_mux; ++ ++ ret = bsp_clk_register_gate(hi3519dv500_gate_clks, ++ ARRAY_SIZE(hi3519dv500_gate_clks), ++ clk_data); ++ if (ret) ++ goto unregister_factor; ++ ++ ret = of_clk_add_provider(pdev->dev.of_node, ++ of_clk_src_onecell_get, &clk_data->clk_data); ++ if (ret) ++ goto unregister_gate; ++ ++ return clk_data; ++ ++unregister_gate: ++ bsp_clk_unregister_gate(hi3519dv500_gate_clks, ++ ARRAY_SIZE(hi3519dv500_gate_clks), clk_data); ++unregister_factor: ++ bsp_clk_unregister_fixed_factor(hi3519dv500_fixed_factor_clks, ++ ARRAY_SIZE(hi3519dv500_fixed_factor_clks), clk_data); ++unregister_mux: ++ bsp_clk_unregister_mux(hi3519dv500_mux_clks_crg, ++ ARRAY_SIZE(hi3519dv500_mux_clks_crg), ++ clk_data); ++unregister_fixed_rate: ++ bsp_clk_unregister_fixed_rate(hi3519dv500_fixed_rate_clks_crg, ++ ARRAY_SIZE(hi3519dv500_fixed_rate_clks_crg), clk_data); ++ return ERR_PTR(ret); ++} ++ ++static __init void hi3519dv500_clk_unregister(const struct platform_device *pdev) ++{ ++ struct bsp_crg_dev *crg = platform_get_drvdata(pdev); ++ ++ of_clk_del_provider(pdev->dev.of_node); ++ ++ bsp_clk_unregister_gate(hi3519dv500_gate_clks, ++ ARRAY_SIZE(hi3519dv500_gate_clks), crg->clk_data); ++ bsp_clk_unregister_mux(hi3519dv500_mux_clks_crg, ++ ARRAY_SIZE(hi3519dv500_mux_clks_crg), crg->clk_data); ++ bsp_clk_unregister_fixed_factor(hi3519dv500_fixed_factor_clks, ++ ARRAY_SIZE(hi3519dv500_fixed_factor_clks), crg->clk_data); ++ bsp_clk_unregister_fixed_rate(hi3519dv500_fixed_rate_clks_crg, ++ ARRAY_SIZE(hi3519dv500_fixed_rate_clks_crg), crg->clk_data); ++} ++ ++static const struct bsp_crg_funcs hi3519dv500_crg_funcs = { ++ .register_clks = hi3519dv500_clk_register, ++ .unregister_clks = hi3519dv500_clk_unregister, ++}; ++ ++ ++static const struct of_device_id hi3519dv500_crg_match_table[] = { ++ { ++ .compatible = "vendor,hi3519dv500_clock", ++ .data = &hi3519dv500_crg_funcs ++ }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, hi3519dv500_crg_match_table); ++ ++static int hi3519dv500_crg_probe(struct platform_device *pdev) ++{ ++ struct bsp_crg_dev *crg = NULL; ++ ++ crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); ++ if (crg == NULL) ++ return -ENOMEM; ++ ++ crg->funcs = of_device_get_match_data(&pdev->dev); ++ if (crg->funcs == NULL) ++ return -ENOENT; ++ ++ crg->rstc = vendor_reset_init(pdev); ++ if (crg->rstc == NULL) ++ return -ENOMEM; ++ ++ crg->clk_data = crg->funcs->register_clks(pdev); ++ if (IS_ERR(crg->clk_data)) { ++ bsp_reset_exit(crg->rstc); ++ return PTR_ERR(crg->clk_data); ++ } ++ ++ platform_set_drvdata(pdev, crg); ++ return 0; ++} ++ ++static int hi3519dv500_crg_remove(struct platform_device *pdev) ++{ ++ struct bsp_crg_dev *crg = platform_get_drvdata(pdev); ++ ++ bsp_reset_exit(crg->rstc); ++ crg->funcs->unregister_clks(pdev); ++ return 0; ++} ++ ++static struct platform_driver hi3519dv500_crg_driver = { ++ .probe = hi3519dv500_crg_probe, ++ .remove = hi3519dv500_crg_remove, ++ .driver = { ++ .name = "hi3519dv500_clock", ++ .of_match_table = hi3519dv500_crg_match_table, ++ }, ++}; ++ ++static int __init hi3519dv500_crg_init(void) ++{ ++ return platform_driver_register(&hi3519dv500_crg_driver); ++} ++core_initcall(hi3519dv500_crg_init); ++ ++static void __exit hi3519dv500_crg_exit(void) ++{ ++ platform_driver_unregister(&hi3519dv500_crg_driver); ++} ++module_exit(hi3519dv500_crg_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("HiSilicon HI3519DV500 CRG Driver"); +diff --git a/drivers/clk/vendor/clk_ss928v100.c b/drivers/clk/vendor/clk_ss928v100.c +new file mode 100644 +index 000000000000..952741837aaa +--- /dev/null ++++ b/drivers/clk/vendor/clk_ss928v100.c +@@ -0,0 +1,693 @@ ++/* ++ * SS928V100 Clock Driver ++ * ++ * Copyright (c) 2016-2017 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "clk.h" ++#include "crg.h" ++#include "reset.h" ++ ++struct ss928v100_pll_clock { ++ u32 id; ++ const char *name; ++ const char *parent_name; ++ u32 ctrl_reg1; ++ u8 frac_shift; ++ u8 frac_width; ++ u8 postdiv1_shift; ++ u8 postdiv1_width; ++ u8 postdiv2_shift; ++ u8 postdiv2_width; ++ u32 ctrl_reg2; ++ u8 fbdiv_shift; ++ u8 fbdiv_width; ++ u8 refdiv_shift; ++ u8 refdiv_width; ++}; ++ ++struct ss928v100_clk_pll { ++ struct clk_hw hw; ++ u32 id; ++ void __iomem *ctrl_reg1; ++ u8 frac_shift; ++ u8 frac_width; ++ u8 postdiv1_shift; ++ u8 postdiv1_width; ++ u8 postdiv2_shift; ++ u8 postdiv2_width; ++ void __iomem *ctrl_reg2; ++ u8 fbdiv_shift; ++ u8 fbdiv_width; ++ u8 refdiv_shift; ++ u8 refdiv_width; ++}; ++ ++/* soc clk config */ ++static const struct bsp_fixed_rate_clock ss928v100_fixed_rate_clks_crg[] = { ++ { SS928V100_FIXED_2400M, "2400m", NULL, 0, 2400000000, }, ++ { SS928V100_FIXED_1200M, "1200m", NULL, 0, 1200000000, }, ++ { SS928V100_FIXED_1188M, "1188m", NULL, 0, 1188000000, }, ++ { SS928V100_FIXED_896M, "896m", NULL, 0, 896000000, }, ++ { SS928V100_FIXED_800M, "800m", NULL, 0, 800000000, }, ++ { SS928V100_FIXED_792M, "792m", NULL, 0, 792000000, }, ++ { SS928V100_FIXED_786M, "786m", NULL, 0, 786000000, }, ++ { SS928V100_FIXED_750M, "750m", NULL, 0, 750000000, }, ++ { SS928V100_FIXED_700M, "700m", NULL, 0, 700000000, }, ++ { SS928V100_FIXED_672M, "672m", NULL, 0, 672000000, }, ++ { SS928V100_FIXED_600M, "600m", NULL, 0, 600000000, }, ++ { SS928V100_FIXED_594M, "594m", NULL, 0, 594000000, }, ++ { SS928V100_FIXED_560M, "560m", NULL, 0, 560000000, }, ++ { SS928V100_FIXED_500M, "500m", NULL, 0, 500000000, }, ++ { SS928V100_FIXED_475M, "475m", NULL, 0, 475000000, }, ++ { SS928V100_FIXED_396M, "396m", NULL, 0, 396000000, }, ++ { SS928V100_FIXED_300M, "300m", NULL, 0, 300000000, }, ++ { SS928V100_FIXED_297M, "297m", NULL, 0, 297000000, }, ++ { SS928V100_FIXED_257M, "257m", NULL, 0, 257000000, }, ++ { SS928V100_FIXED_250M, "250m", NULL, 0, 250000000, }, ++ { SS928V100_FIXED_200M, "200m", NULL, 0, 200000000, }, ++ { SS928V100_FIXED_198M, "198m", NULL, 0, 198000000, }, ++ { SS928V100_FIXED_187P_5M, "187p5m", NULL, 0, 187500000, }, ++ { SS928V100_FIXED_150M, "150m", NULL, 0, 150000000, }, ++ { SS928V100_FIXED_148P_5M, "148p5m", NULL, 0, 148500000, }, ++ { SS928V100_FIXED_134M, "134m", NULL, 0, 134000000, }, ++ { SS928V100_FIXED_108M, "108m", NULL, 0, 108000000, }, ++ { SS928V100_FIXED_100M, "100m", NULL, 0, 100000000, }, ++ { SS928V100_FIXED_99M, "99m", NULL, 0, 99000000, }, ++ { SS928V100_FIXED_74P_25M, "74p25m", NULL, 0, 74250000, }, ++ { SS928V100_FIXED_72M, "72m", NULL, 0, 72000000, }, ++ { SS928V100_FIXED_64M, "64m", NULL, 0, 64000000, }, ++ { SS928V100_FIXED_60M, "60m", NULL, 0, 60000000, }, ++ { SS928V100_FIXED_54M, "54m", NULL, 0, 54000000, }, ++ { SS928V100_FIXED_50M, "50m", NULL, 0, 50000000, }, ++ { SS928V100_FIXED_49P_5M, "49p5m", NULL, 0, 49500000, }, ++ { SS928V100_FIXED_37P_125M, "37p125m", NULL, 0, 37125000, }, ++ { SS928V100_FIXED_36M, "36m", NULL, 0, 36000000, }, ++ { SS928V100_FIXED_27M, "27m", NULL, 0, 27000000, }, ++ { SS928V100_FIXED_25M, "25m", NULL, 0, 25000000, }, ++ { SS928V100_FIXED_24M, "24m", NULL, 0, 24000000, }, ++ { SS928V100_FIXED_12M, "12m", NULL, 0, 12000000, }, ++ { SS928V100_FIXED_12P_288M, "12p288m", NULL, 0, 12288000, }, ++ { SS928V100_FIXED_6M, "6m", NULL, 0, 6000000, }, ++ { SS928V100_FIXED_3M, "3m", NULL, 0, 3000000, }, ++ { SS928V100_FIXED_1P_6M, "1p6m", NULL, 0, 1600000, }, ++ { SS928V100_FIXED_400K, "400k", NULL, 0, 400000, }, ++ { SS928V100_FIXED_100K, "100k", NULL, 0, 100000, }, ++}; ++ ++ ++static const char *fmc_mux_p[] __initdata = { ++ "24m", "99m", "148p5m", "198m", "250m", "297m", "396m" ++}; ++static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6}; ++ ++static const char *mmc_mux_p[] __initdata = { ++ "400k", "25m", "50m", "100m", "150m", "187p5m", "200m" ++}; ++static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6}; ++ ++static const char *sdio0_mux_p[] __initdata = { ++ "400k", "25m", "50m", "100m", "150m", "187p5m", "200m" ++}; ++static u32 sdio0_mux_table[] = {0, 1, 2, 3, 4, 5, 6}; ++ ++static const char *sdio1_mux_p[] __initdata = { ++ "400k", "25m", "50m", "100m", "150m", "187p5m", "200m" ++}; ++static u32 sdio1_mux_table[] = {0, 1, 2, 3, 4, 5, 6}; ++ ++static const char *hpaxi_mux_p[] __initdata = { ++ "24m", "396m", "475m" ++}; ++static u32 hpaxi_mux_table[] = {0, 1, 2}; ++ ++static const char *ddraxi_mux_p[] __initdata = { ++ "24m", "500m", "672m", "750m" ++}; ++static u32 ddraxi_mux_table[] = {0, 1, 2, 3}; ++ ++static const char *uart_mux_p[] __initdata = {"50m", "24m", "3m", "100m"}; ++static u32 uart_mux_table[] = {0, 1, 2, 3}; ++ ++static const char *i2c_mux_p[] __initdata = { ++ "50m", "100m" ++}; ++static u32 i2c_mux_table[] = {0, 1}; ++ ++static const char * pwm0_mux_p[] __initdata = {"200m"}; ++static u32 pwm0_mux_table[] = {0}; ++ ++static const char * pwm1_mux_p[] __initdata = {"200m"}; ++static u32 pwm1_mux_table[] = {0}; ++ ++static struct bsp_mux_clock ss928v100_mux_clks_crg[] __initdata = { ++ { ++ SS928V100_FMC_MUX, "fmc_mux", ++ fmc_mux_p, ARRAY_SIZE(fmc_mux_p), ++ CLK_SET_RATE_PARENT, 0x3f40, 12, 3, 0, fmc_mux_table, ++ }, ++ { ++ SS928V100_MMC0_MUX, "mmc0_mux", ++ mmc_mux_p, ARRAY_SIZE(mmc_mux_p), ++ CLK_SET_RATE_PARENT, 0x34c0, 24, 3, 0, mmc_mux_table, ++ }, ++ { ++ SS928V100_MMC1_MUX, "mmc1_mux", ++ sdio0_mux_p, ARRAY_SIZE(sdio0_mux_p), ++ CLK_SET_RATE_PARENT, 0x35c0, 24, 3, 0, sdio0_mux_table, ++ }, ++ { ++ SS928V100_MMC2_MUX, "mmc2_mux", ++ sdio1_mux_p, ARRAY_SIZE(sdio1_mux_p), ++ CLK_SET_RATE_PARENT, 0x36c0, 24, 3, 0, sdio1_mux_table, ++ }, ++ { ++ SS928V100_HPAXI_MUX, "hpaxi_mux", ++ hpaxi_mux_p, ARRAY_SIZE(hpaxi_mux_p), ++ CLK_SET_RATE_PARENT, 0x2000, 16, 2, 0, hpaxi_mux_table ++ }, ++ { ++ SS928V100_DDRAXI_MUX, "ddraxi_mux", ++ ddraxi_mux_p, ARRAY_SIZE(ddraxi_mux_p), ++ CLK_SET_RATE_PARENT, 0x2000, 12, 2, 0, ddraxi_mux_table ++ }, ++ { ++ SS928V100_UART0_MUX, "uart0_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4180, 12, 2, 0, uart_mux_table ++ }, ++ { ++ SS928V100_UART1_MUX, "uart1_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4188, 12, 2, 0, uart_mux_table ++ }, ++ { ++ SS928V100_UART2_MUX, "uart2_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4190, 12, 2, 0, uart_mux_table ++ }, ++ { ++ SS928V100_UART3_MUX, "uart3_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x4198, 12, 2, 0, uart_mux_table ++ }, ++ { ++ SS928V100_UART4_MUX, "uart4_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x41a0, 12, 2, 0, uart_mux_table ++ }, ++ { ++ SS928V100_UART5_MUX, "uart5_mux", ++ uart_mux_p, ARRAY_SIZE(uart_mux_p), ++ CLK_SET_RATE_PARENT, 0x41a8, 12, 2, 0, uart_mux_table ++ }, ++ { ++ SS928V100_I2C0_MUX, "i2c0_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4280, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ SS928V100_I2C1_MUX, "i2c1_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4288, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ SS928V100_I2C2_MUX, "i2c2_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4290, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ SS928V100_I2C3_MUX, "i2c3_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x4298, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ SS928V100_I2C4_MUX, "i2c4_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x42a0, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ SS928V100_I2C5_MUX, "i2c5_mux", ++ i2c_mux_p, ARRAY_SIZE(i2c_mux_p), ++ CLK_SET_RATE_PARENT, 0x42a8, 12, 1, 0, i2c_mux_table ++ }, ++ { ++ SS928V100_PWM0_MUX, "pwm0_mux", ++ pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), ++ CLK_SET_RATE_PARENT, 0x4588, 12, 2, 0, pwm0_mux_table ++ }, ++ { ++ SS928V100_PWM1_MUX, "pwm1_mux", ++ pwm1_mux_p, ARRAY_SIZE(pwm1_mux_p), ++ CLK_SET_RATE_PARENT, 0x4590, 12, 2, 0, pwm1_mux_table ++ }, ++}; ++ ++static struct bsp_fixed_factor_clock ++ ss928v100_fixed_factor_clks[] __initdata = { ++}; ++ ++static struct bsp_gate_clock ss928v100_gate_clks[] __initdata = { ++ { ++ SS928V100_FMC_CLK, "clk_fmc", "fmc_mux", ++ CLK_SET_RATE_PARENT, 0x3f40, 4, 0, ++ }, ++ { ++ SS928V100_MMC0_CLK, "clk_mmc0", "mmc0_mux", ++ CLK_SET_RATE_PARENT, 0x34c0, 0, 0, ++ }, ++ { ++ SS928V100_MMC1_CLK, "clk_mmc1", "mmc1_mux", ++ CLK_SET_RATE_PARENT, 0x35c0, 0, 0, ++ }, ++ { ++ SS928V100_MMC2_CLK, "clk_mmc2", "mmc2_mux", ++ CLK_SET_RATE_PARENT, 0x36c0, 0, 0, ++ }, ++ { ++ SS928V100_UART0_CLK, "clk_uart0", "uart0_mux", ++ CLK_SET_RATE_PARENT, 0x4180, 4, 0, ++ }, ++ { ++ SS928V100_UART1_CLK, "clk_uart1", "uart1_mux", ++ CLK_SET_RATE_PARENT, 0x4188, 4, 0, ++ }, ++ { ++ SS928V100_UART2_CLK, "clk_uart2", "uart2_mux", ++ CLK_SET_RATE_PARENT, 0x4190, 4, 0, ++ }, ++ { ++ SS928V100_UART3_CLK, "clk_uart3", "uart3_mux", ++ CLK_SET_RATE_PARENT, 0x4198, 4, 0, ++ }, ++ { ++ SS928V100_UART4_CLK, "clk_uart4", "uart4_mux", ++ CLK_SET_RATE_PARENT, 0x41A0, 4, 0, ++ }, ++ { ++ SS928V100_UART5_CLK, "clk_uart5", "uart5_mux", ++ CLK_SET_RATE_PARENT, 0x41a8, 4, 0, ++ }, ++ /* ethernet mac */ ++ { ++ SS928V100_ETH_CLK, "clk_eth", NULL, ++ CLK_SET_RATE_PARENT, 0x37c4, 4, 0, ++ }, ++ { ++ SS928V100_ETH_MACIF_CLK, "clk_eth_macif", NULL, ++ CLK_SET_RATE_PARENT, 0x37c0, 4, 0, ++ }, ++ { ++ SS928V100_ETH1_CLK, "clk_eth1", NULL, ++ CLK_SET_RATE_PARENT, 0x3804, 4, 0, ++ }, ++ { ++ SS928V100_ETH1_MACIF_CLK, "clk_eth1_macif", NULL, ++ CLK_SET_RATE_PARENT, 0x3800, 4, 0, ++ }, ++ { ++ SS928V100_I2C0_CLK, "clk_i2c0", "i2c0_mux", ++ CLK_SET_RATE_PARENT, 0x4280, 4, 0, ++ }, ++ { ++ SS928V100_I2C1_CLK, "clk_i2c1", "i2c1_mux", ++ CLK_SET_RATE_PARENT, 0x4288, 4, 0, ++ }, ++ { ++ SS928V100_I2C2_CLK, "clk_i2c2", "i2c2_mux", ++ CLK_SET_RATE_PARENT, 0x4290, 4, 0, ++ }, ++ { ++ SS928V100_I2C3_CLK, "clk_i2c3", "i2c3_mux", ++ CLK_SET_RATE_PARENT, 0x4298, 4, 0, ++ }, ++ { ++ SS928V100_I2C4_CLK, "clk_i2c4", "i2c4_mux", ++ CLK_SET_RATE_PARENT, 0x42a0, 4, 0, ++ }, ++ { SS928V100_I2C5_CLK, "clk_i2c5", "i2c5_mux", ++ CLK_SET_RATE_PARENT, 0x42a8, 4, 0, ++ }, ++ /* spi */ ++ { ++ SS928V100_SPI0_CLK, "clk_spi0", "100m", ++ CLK_SET_RATE_PARENT, 0x4480, 4, 0, ++ }, ++ { ++ SS928V100_SPI1_CLK, "clk_spi1", "100m", ++ CLK_SET_RATE_PARENT, 0x4488, 4, 0, ++ }, ++ { ++ SS928V100_SPI2_CLK, "clk_spi2", "100m", ++ CLK_SET_RATE_PARENT, 0x4490, 4, 0, ++ }, ++ { ++ SS928V100_SPI3_CLK, "clk_spi3", "100m", ++ CLK_SET_RATE_PARENT, 0x4498, 4, 0, ++ }, ++ { ++ SS928V100_EDMAC_AXICLK, "axi_clk_edmac", NULL, ++ CLK_SET_RATE_PARENT, 0x2a80, 5, 0, ++ }, ++ { ++ SS928V100_EDMAC_CLK, "clk_edmac", NULL, ++ CLK_SET_RATE_PARENT, 0x2a80, 4, 0, ++ }, ++ /* lsadc */ ++ { ++ SS928V100_LSADC_CLK, "clk_lsadc", NULL, ++ CLK_SET_RATE_PARENT, 0x46c0, 4, 0, ++ }, ++ /* pwm0 */ ++ { ++ SS928V100_PWM0_CLK, "clk_pwm0", "pwm0_mux", ++ CLK_SET_RATE_PARENT, 0x4588, 4, 0, ++ }, ++ /* pwm1 */ ++ { ++ SS928V100_PWM1_CLK, "clk_pwm1", "pwm1_mux", ++ CLK_SET_RATE_PARENT, 0x4590, 4, 0, ++ }, ++}; ++ ++static struct ss928v100_pll_clock ss928v100_pll_clks[] __initdata = { ++ { ++ SS928V100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3, ++ 0x4, 0, 12, 12, 6 ++ }, ++}; ++ ++#define to_pll_clk(_hw) container_of(_hw, struct ss928v100_clk_pll, hw) ++static void ss928v100_calc_pll(u32 *frac_val, u32 *fbdiv_val, ++ u32 *refdiv_val, u64 rate) ++{ ++ u64 rem; ++ *frac_val = 0; ++ /* Frequency divided by 1000000 can be converted from Hz to MHz. */ ++ rem = do_div(rate, 1000000); ++ /* rate/24 is the integral part of the frequency multiplication coefficient. */ ++ *fbdiv_val = rate / 24; ++ *refdiv_val = 1; ++ /* 2 to the 24th power */ ++ rem = rem * (1 << 24); ++ /* Frequency divided by 1000000 can be converted from Hz to MHz. */ ++ do_div(rem, 1000000); ++ *frac_val = rem; ++} ++ ++static int clk_pll_set_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct ss928v100_clk_pll *clk = to_pll_clk(hw); ++ u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val; ++ u32 val; ++ ++ /*Fixme ignore postdives now because apll don't use them*/ ++ postdiv1_val = postdiv2_val = 0; ++ ++ ss928v100_calc_pll(&frac_val, &fbdiv_val, &refdiv_val, (u64)rate); ++ ++ val = readl_relaxed(clk->ctrl_reg1); ++ val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift); ++ val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift); ++ val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift); ++ ++ val |= frac_val << clk->frac_shift; ++ val |= postdiv1_val << clk->postdiv1_shift; ++ val |= postdiv2_val << clk->postdiv2_shift; ++ writel_relaxed(val, clk->ctrl_reg1); ++ ++ val = readl_relaxed(clk->ctrl_reg2); ++ val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift); ++ val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift); ++ ++ val |= fbdiv_val << clk->fbdiv_shift; ++ val |= refdiv_val << clk->refdiv_shift; ++ writel_relaxed(val, clk->ctrl_reg2); ++ ++ return 0; ++} ++ ++static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct ss928v100_clk_pll *clk = to_pll_clk(hw); ++ u64 frac_val, fbdiv_val, refdiv_val; ++ u32 val; ++ u64 tmp, rate; ++ ++ val = readl_relaxed(clk->ctrl_reg1); ++ val = val >> clk->frac_shift; ++ val &= ((1 << clk->frac_width) - 1); ++ frac_val = val; ++ ++ val = readl_relaxed(clk->ctrl_reg2); ++ val = val >> clk->fbdiv_shift; ++ val &= ((1 << clk->fbdiv_width) - 1); ++ fbdiv_val = val; ++ ++ val = readl_relaxed(clk->ctrl_reg2); ++ val = val >> clk->refdiv_shift; ++ val &= ((1 << clk->refdiv_width) - 1); ++ refdiv_val = val; ++ ++ rate = 0; ++ /* rate = 24000000 * (fbdiv + frac / (1<<24) ) / refdiv */ ++ tmp = 24000000 * fbdiv_val; ++ rate += tmp; ++ do_div(rate, refdiv_val); ++ ++ return rate; ++} ++ ++static int clk_pll_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ return req->rate; ++} ++ ++static struct clk_ops clk_pll_ops = { ++ .set_rate = clk_pll_set_rate, ++ .determine_rate = clk_pll_determine_rate, ++ .recalc_rate = clk_pll_recalc_rate, ++}; ++ ++void clk_register_pll(const struct ss928v100_pll_clock *clks, ++ int nums, const struct bsp_clock_data *data) ++{ ++ void __iomem *base = data->base; ++ int i; ++ ++ for (i = 0; i < nums; i++) { ++ struct ss928v100_clk_pll *p_clk = NULL; ++ struct clk *clk = NULL; ++ struct clk_init_data init; ++ ++ p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL); ++ if (p_clk == NULL) ++ return; ++ ++ init.name = clks[i].name; ++ init.flags = CLK_IS_BASIC; ++ init.parent_names = ++ (clks[i].parent_name ? &clks[i].parent_name : NULL); ++ init.num_parents = (clks[i].parent_name ? 1 : 0); ++ init.ops = &clk_pll_ops; ++ ++ p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1; ++ p_clk->frac_shift = clks[i].frac_shift; ++ p_clk->frac_width = clks[i].frac_width; ++ p_clk->postdiv1_shift = clks[i].postdiv1_shift; ++ p_clk->postdiv1_width = clks[i].postdiv1_width; ++ p_clk->postdiv2_shift = clks[i].postdiv2_shift; ++ p_clk->postdiv2_width = clks[i].postdiv2_width; ++ ++ p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2; ++ p_clk->fbdiv_shift = clks[i].fbdiv_shift; ++ p_clk->fbdiv_width = clks[i].fbdiv_width; ++ p_clk->refdiv_shift = clks[i].refdiv_shift; ++ p_clk->refdiv_width = clks[i].refdiv_width; ++ p_clk->hw.init = &init; ++ ++ clk = clk_register(NULL, &p_clk->hw); ++ if (IS_ERR(clk)) { ++ kfree(p_clk); ++ pr_err("%s: failed to register clock %s\n", ++ __func__, clks[i].name); ++ continue; ++ } ++ ++ data->clk_data.clks[clks[i].id] = clk; ++ } ++} ++ ++static __init struct bsp_clock_data *ss928v100_clk_register( ++ struct platform_device *pdev) ++{ ++ struct bsp_clock_data *clk_data = NULL; ++ int ret; ++ ++ clk_data = bsp_clk_alloc(pdev, SS928V100_CRG_NR_CLKS); ++ if (clk_data == NULL) ++ return ERR_PTR(-ENOMEM); ++ ++ ret = bsp_clk_register_fixed_rate(ss928v100_fixed_rate_clks_crg, ++ ARRAY_SIZE(ss928v100_fixed_rate_clks_crg), clk_data); ++ if (ret) ++ return ERR_PTR(ret); ++ ++ clk_register_pll(ss928v100_pll_clks, ++ ARRAY_SIZE(ss928v100_pll_clks), clk_data); ++ ++ ret = bsp_clk_register_mux(ss928v100_mux_clks_crg, ++ ARRAY_SIZE(ss928v100_mux_clks_crg), ++ clk_data); ++ if (ret) ++ goto unregister_fixed_rate; ++ ++ ret = bsp_clk_register_fixed_factor(ss928v100_fixed_factor_clks, ++ ARRAY_SIZE(ss928v100_fixed_factor_clks), clk_data); ++ if (ret) ++ goto unregister_mux; ++ ++ ret = bsp_clk_register_gate(ss928v100_gate_clks, ++ ARRAY_SIZE(ss928v100_gate_clks), ++ clk_data); ++ if (ret) ++ goto unregister_factor; ++ ++ ret = of_clk_add_provider(pdev->dev.of_node, ++ of_clk_src_onecell_get, &clk_data->clk_data); ++ if (ret) ++ goto unregister_gate; ++ ++ return clk_data; ++ ++unregister_gate: ++ bsp_clk_unregister_gate(ss928v100_gate_clks, ++ ARRAY_SIZE(ss928v100_gate_clks), clk_data); ++unregister_factor: ++ bsp_clk_unregister_fixed_factor(ss928v100_fixed_factor_clks, ++ ARRAY_SIZE(ss928v100_fixed_factor_clks), clk_data); ++unregister_mux: ++ bsp_clk_unregister_mux(ss928v100_mux_clks_crg, ++ ARRAY_SIZE(ss928v100_mux_clks_crg), ++ clk_data); ++unregister_fixed_rate: ++ bsp_clk_unregister_fixed_rate(ss928v100_fixed_rate_clks_crg, ++ ARRAY_SIZE(ss928v100_fixed_rate_clks_crg), clk_data); ++ return ERR_PTR(ret); ++} ++ ++static __init void ss928v100_clk_unregister(const struct platform_device *pdev) ++{ ++ struct bsp_crg_dev *crg = platform_get_drvdata(pdev); ++ ++ of_clk_del_provider(pdev->dev.of_node); ++ ++ bsp_clk_unregister_gate(ss928v100_gate_clks, ++ ARRAY_SIZE(ss928v100_gate_clks), crg->clk_data); ++ bsp_clk_unregister_mux(ss928v100_mux_clks_crg, ++ ARRAY_SIZE(ss928v100_mux_clks_crg), crg->clk_data); ++ bsp_clk_unregister_fixed_factor(ss928v100_fixed_factor_clks, ++ ARRAY_SIZE(ss928v100_fixed_factor_clks), crg->clk_data); ++ bsp_clk_unregister_fixed_rate(ss928v100_fixed_rate_clks_crg, ++ ARRAY_SIZE(ss928v100_fixed_rate_clks_crg), crg->clk_data); ++} ++ ++static const struct bsp_crg_funcs ss928v100_crg_funcs = { ++ .register_clks = ss928v100_clk_register, ++ .unregister_clks = ss928v100_clk_unregister, ++}; ++ ++ ++static const struct of_device_id ss928v100_crg_match_table[] = { ++ { ++ .compatible = "vendor,ss928v100_clock", ++ .data = &ss928v100_crg_funcs ++ }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ss928v100_crg_match_table); ++ ++static int ss928v100_crg_probe(struct platform_device *pdev) ++{ ++ printk("ss928v100 clock driver probe\n"); ++ struct bsp_crg_dev *crg = NULL; ++ ++ crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL); ++ if (crg == NULL) ++ return -ENOMEM; ++ ++ crg->funcs = of_device_get_match_data(&pdev->dev); ++ if (crg->funcs == NULL) ++ return -ENOENT; ++ ++ crg->rstc = vendor_reset_init(pdev); ++ if (crg->rstc == NULL) ++ return -ENOMEM; ++ ++ crg->clk_data = crg->funcs->register_clks(pdev); ++ if (IS_ERR(crg->clk_data)) { ++ bsp_reset_exit(crg->rstc); ++ return PTR_ERR(crg->clk_data); ++ } ++ ++ platform_set_drvdata(pdev, crg); ++ return 0; ++} ++ ++static int ss928v100_crg_remove(struct platform_device *pdev) ++{ ++ struct bsp_crg_dev *crg = platform_get_drvdata(pdev); ++ ++ bsp_reset_exit(crg->rstc); ++ crg->funcs->unregister_clks(pdev); ++ return 0; ++} ++ ++static struct platform_driver ss928v100_crg_driver = { ++ .probe = ss928v100_crg_probe, ++ .remove = ss928v100_crg_remove, ++ .driver = { ++ .name = "ss928v100_clock", ++ .of_match_table = ss928v100_crg_match_table, ++ }, ++}; ++ ++static int __init ss928v100_crg_init(void) ++{ ++ return platform_driver_register(&ss928v100_crg_driver); ++} ++core_initcall(ss928v100_crg_init); ++ ++static void __exit ss928v100_crg_exit(void) ++{ ++ platform_driver_unregister(&ss928v100_crg_driver); ++} ++module_exit(ss928v100_crg_exit); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("SS928V100 CRG Driver"); +diff --git a/drivers/clk/vendor/clkgate_separated.c b/drivers/clk/vendor/clkgate_separated.c +new file mode 100644 +index 000000000000..d53783fb317e +--- /dev/null ++++ b/drivers/clk/vendor/clkgate_separated.c +@@ -0,0 +1,108 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "clk.h" ++ ++/* clock separated gate register offset */ ++#define CLKGATE_SEPERATED_ENABLE 0x0 ++#define CLKGATE_SEPERATED_DISABLE 0x4 ++#define CLKGATE_SEPERATED_STATUS 0x8 ++ ++struct clkgate_separated { ++ struct clk_hw hw; ++ void __iomem *enable; /* enable register */ ++ u8 bit_idx; /* bits in enable/disable register */ ++ u8 flags; ++ spinlock_t *lock; ++}; ++ ++static int clkgate_separated_enable(struct clk_hw *hw) ++{ ++ struct clkgate_separated *sclk; ++ unsigned long flags = 0; ++ u32 reg; ++ ++ sclk = container_of(hw, struct clkgate_separated, hw); ++ if (sclk->lock) ++ spin_lock_irqsave(sclk->lock, flags); ++ reg = BIT(sclk->bit_idx); ++ writel_relaxed(reg, sclk->enable); ++ readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); ++ if (sclk->lock) ++ spin_unlock_irqrestore(sclk->lock, flags); ++ return 0; ++} ++ ++static void clkgate_separated_disable(struct clk_hw *hw) ++{ ++ struct clkgate_separated *sclk; ++ unsigned long flags = 0; ++ u32 reg; ++ ++ sclk = container_of(hw, struct clkgate_separated, hw); ++ if (sclk->lock) ++ spin_lock_irqsave(sclk->lock, flags); ++ reg = BIT(sclk->bit_idx); ++ writel_relaxed(reg, sclk->enable + CLKGATE_SEPERATED_DISABLE); ++ readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); ++ if (sclk->lock) ++ spin_unlock_irqrestore(sclk->lock, flags); ++} ++ ++static int clkgate_separated_is_enabled(struct clk_hw *hw) ++{ ++ struct clkgate_separated *sclk; ++ u32 reg; ++ ++ sclk = container_of(hw, struct clkgate_separated, hw); ++ reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); ++ reg &= BIT(sclk->bit_idx); ++ if (reg) ++ return 1; ++ else ++ return 0; ++} ++ ++static const struct clk_ops clkgate_separated_ops = { ++ .enable = clkgate_separated_enable, ++ .disable = clkgate_separated_disable, ++ .is_enabled = clkgate_separated_is_enabled, ++}; ++ ++struct clk *bsp_register_clkgate_sep(struct device *dev, const char *name, ++ const char *parent_name, ++ unsigned long flags, ++ void __iomem *reg, u8 bit_idx, ++ u8 clk_gate_flags, spinlock_t *lock) ++{ ++ struct clkgate_separated *sclk; ++ struct clk *clk; ++ struct clk_init_data init; ++ ++ sclk = kzalloc(sizeof(*sclk), GFP_KERNEL); ++ if (!sclk) ++ return ERR_PTR(-ENOMEM); ++ ++ init.name = name; ++ init.ops = &clkgate_separated_ops; ++ init.flags = flags; ++ init.parent_names = (parent_name ? &parent_name : NULL); ++ init.num_parents = (parent_name ? 1 : 0); ++ ++ sclk->enable = reg + CLKGATE_SEPERATED_ENABLE; ++ sclk->bit_idx = bit_idx; ++ sclk->flags = clk_gate_flags; ++ sclk->hw.init = &init; ++ sclk->lock = lock; ++ ++ clk = clk_register(dev, &sclk->hw); ++ if (IS_ERR(clk)) ++ kfree(sclk); ++ return clk; ++} +diff --git a/drivers/clk/vendor/crg.h b/drivers/clk/vendor/crg.h +new file mode 100644 +index 000000000000..de73c36ad2b6 +--- /dev/null ++++ b/drivers/clk/vendor/crg.h +@@ -0,0 +1,24 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef __BSP_CRG_H ++#define __BSP_CRG_H ++ ++#include ++ ++struct bsp_clock_data; ++struct bsp_reset_controller; ++ ++struct bsp_crg_funcs { ++ struct bsp_clock_data* (*register_clks)(struct platform_device *pdev); ++ void (*unregister_clks)(const struct platform_device *pdev); ++}; ++ ++struct bsp_crg_dev { ++ struct bsp_clock_data *clk_data; ++ struct bsp_reset_controller *rstc; ++ const struct bsp_crg_funcs *funcs; ++}; ++ ++#endif /* __BSP_CRG_H */ +diff --git a/drivers/clk/vendor/reset.c b/drivers/clk/vendor/reset.c +new file mode 100644 +index 000000000000..b8c610bb7f4f +--- /dev/null ++++ b/drivers/clk/vendor/reset.c +@@ -0,0 +1,145 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "reset.h" ++ ++#define BSP_RESET_BIT_MASK 0x1f ++#define BSP_RESET_OFFSET_SHIFT 8 ++#define BSP_RESET_OFFSET_MASK 0xffff00 ++ ++struct bsp_reset_controller { ++ spinlock_t lock; ++ void __iomem *membase; ++ struct reset_controller_dev rcdev; ++}; ++ ++static int bsp_reset_of_xlate(struct reset_controller_dev *rcdev, ++ const struct of_phandle_args *reset_spec) ++{ ++ u32 offset; ++ u8 bit; ++ ++ offset = (reset_spec->args[0] << BSP_RESET_OFFSET_SHIFT) ++ & BSP_RESET_OFFSET_MASK; ++ bit = reset_spec->args[1] & BSP_RESET_BIT_MASK; ++ ++ return (offset | bit); ++} ++ ++static int bsp_reset_assert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct bsp_reset_controller *rstc = container_of(rcdev, ++ struct bsp_reset_controller, rcdev); ++ unsigned long flags; ++ u32 offset, reg; ++ u8 bit; ++ ++ offset = (id & BSP_RESET_OFFSET_MASK) >> BSP_RESET_OFFSET_SHIFT; ++ bit = id & BSP_RESET_BIT_MASK; ++ ++ spin_lock_irqsave(&rstc->lock, flags); ++ ++ reg = readl(rstc->membase + offset); ++ writel(reg | BIT(bit), rstc->membase + offset); ++ ++ spin_unlock_irqrestore(&rstc->lock, flags); ++ ++ return 0; ++} ++ ++static int bsp_reset_deassert(struct reset_controller_dev *rcdev, ++ unsigned long id) ++{ ++ struct bsp_reset_controller *rstc = container_of(rcdev, ++ struct bsp_reset_controller, rcdev); ++ unsigned long flags; ++ u32 offset, reg; ++ u8 bit; ++ ++ offset = (id & BSP_RESET_OFFSET_MASK) >> BSP_RESET_OFFSET_SHIFT; ++ bit = id & BSP_RESET_BIT_MASK; ++ ++ spin_lock_irqsave(&rstc->lock, flags); ++ ++ reg = readl(rstc->membase + offset); ++ writel(reg & ~BIT(bit), rstc->membase + offset); ++ ++ spin_unlock_irqrestore(&rstc->lock, flags); ++ ++ return 0; ++} ++ ++static const struct reset_control_ops bsp_reset_ops = { ++ .assert = bsp_reset_assert, ++ .deassert = bsp_reset_deassert, ++}; ++ ++#ifdef CONFIG_ARCH_BSP ++int __init bsp_reset_init(struct device_node *np, ++ int nr_rsts) ++{ ++ struct bsp_reset_controller *rstc; ++ ++ rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); ++ if (!rstc) ++ return -ENOMEM; ++ ++ rstc->membase = of_iomap(np, 0); ++ if (!rstc->membase){ ++ kfree(rstc); ++ return -EINVAL; ++ } ++ ++ spin_lock_init(&rstc->lock); ++ ++ rstc->rcdev.owner = THIS_MODULE; ++ rstc->rcdev.nr_resets = nr_rsts; ++ rstc->rcdev.ops = &bsp_reset_ops; ++ rstc->rcdev.of_node = np; ++ rstc->rcdev.of_reset_n_cells = 2; ++ rstc->rcdev.of_xlate = bsp_reset_of_xlate; ++ ++ return reset_controller_register(&rstc->rcdev); ++} ++EXPORT_SYMBOL_GPL(bsp_reset_init); ++#endif ++ ++struct bsp_reset_controller *vendor_reset_init(struct platform_device *pdev) ++{ ++ struct bsp_reset_controller *rstc; ++ struct resource *res; ++ ++ rstc = devm_kmalloc(&pdev->dev, sizeof(*rstc), GFP_KERNEL); ++ if (!rstc) ++ return NULL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ rstc->membase = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(rstc->membase)) ++ return NULL; ++ ++ spin_lock_init(&rstc->lock); ++ rstc->rcdev.owner = THIS_MODULE; ++ rstc->rcdev.ops = &bsp_reset_ops; ++ rstc->rcdev.of_node = pdev->dev.of_node; ++ rstc->rcdev.of_reset_n_cells = 2; /* 2:used to parse the resets node. */ ++ rstc->rcdev.of_xlate = bsp_reset_of_xlate; ++ reset_controller_register(&rstc->rcdev); ++ ++ return rstc; ++} ++EXPORT_SYMBOL_GPL(vendor_reset_init); ++ ++void bsp_reset_exit(struct bsp_reset_controller *rstc) ++{ ++ reset_controller_unregister(&rstc->rcdev); ++} ++EXPORT_SYMBOL_GPL(bsp_reset_exit); +diff --git a/drivers/clk/vendor/reset.h b/drivers/clk/vendor/reset.h +new file mode 100644 +index 000000000000..a9535170cedf +--- /dev/null ++++ b/drivers/clk/vendor/reset.h +@@ -0,0 +1,29 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef __BSP_RESET_H ++#define __BSP_RESET_H ++ ++#include ++ ++struct device_node; ++struct bsp_reset_controller; ++ ++#ifdef CONFIG_RESET_CONTROLLER ++struct bsp_reset_controller *vendor_reset_init(struct platform_device *pdev); ++#ifdef CONFIG_ARCH_BSP ++int __init bsp_reset_init(struct device_node *np, int nr_rsts); ++#endif ++void bsp_reset_exit(struct bsp_reset_controller *rstc); ++#else ++static inline ++struct bsp_reset_controller *vendor_reset_init(struct platform_device *pdev) ++{ ++ return 0; ++} ++static inline void bsp_reset_exit(struct bsp_reset_controller *rstc) ++{} ++#endif ++ ++#endif /* __BSP_RESET_H */ +diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile +index 8928816a4f30..69c7a9e57230 100644 +--- a/drivers/dma/Makefile ++++ b/drivers/dma/Makefile +@@ -82,6 +82,7 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o + obj-$(CONFIG_ZX_DMA) += zx_dma.o + obj-$(CONFIG_ST_FDMA) += st_fdma.o + obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ ++obj-$(CONFIG_EDMACV310) += edmacv310.o + + obj-y += mediatek/ + obj-y += qcom/ +diff --git a/drivers/dma/edmacv310.c b/drivers/dma/edmacv310.c +new file mode 100644 +index 000000000000..d3d475e6092d +--- /dev/null ++++ b/drivers/dma/edmacv310.c +@@ -0,0 +1,1450 @@ ++/* ++ * ++ * Copyright (c) 2015-2021 Shenshu Technologies Co., Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "edmacv310.h" ++#include "dmaengine.h" ++#include "virt-dma.h" ++#include ++ ++#define DRIVER_NAME "edmacv310" ++ ++#define MAX_TSFR_LLIS 512 ++#define EDMACV300_LLI_WORDS 64 ++#define EDMACV300_POOL_ALIGN 64 ++#define BITS_PER_HALF_WORD 32 ++#define ERR_STATUS_REG_NUM 3 ++ ++typedef struct edmac_lli { ++ u64 next_lli; ++ u32 reserved[5]; ++ u32 count; ++ u64 src_addr; ++ u64 dest_addr; ++ u32 config; ++ u32 pad[3]; ++} edmac_lli; ++ ++struct edmac_sg { ++ dma_addr_t src_addr; ++ dma_addr_t dst_addr; ++ size_t len; ++ struct list_head node; ++}; ++ ++struct transfer_desc { ++ struct virt_dma_desc virt_desc; ++ dma_addr_t llis_busaddr; ++ u64 *llis_vaddr; ++ u32 ccfg; ++ size_t size; ++ bool done; ++ bool cyclic; ++}; ++ ++enum edmac_dma_chan_state { ++ EDMAC_CHAN_IDLE, ++ EDMAC_CHAN_RUNNING, ++ EDMAC_CHAN_PAUSED, ++ EDMAC_CHAN_WAITING, ++}; ++ ++struct edmacv310_dma_chan { ++ bool slave; ++ int signal; ++ int id; ++ struct virt_dma_chan virt_chan; ++ struct edmacv310_phy_chan *phychan; ++ struct dma_slave_config cfg; ++ struct transfer_desc *at; ++ struct edmacv310_driver_data *host; ++ enum edmac_dma_chan_state state; ++}; ++ ++struct edmacv310_phy_chan { ++ unsigned int id; ++ void __iomem *base; ++ spinlock_t lock; ++ struct edmacv310_dma_chan *serving; ++}; ++ ++struct edmacv310_driver_data { ++ struct platform_device *dev; ++ struct dma_device slave; ++ struct dma_device memcpy; ++ void __iomem *base; ++ struct regmap *misc_regmap; ++ void __iomem *crg_ctrl; ++ struct edmacv310_phy_chan *phy_chans; ++ struct dma_pool *pool; ++ unsigned int misc_ctrl_base; ++ int irq; ++ unsigned int id; ++ struct clk *clk; ++ struct clk *axi_clk; ++ struct reset_control *rstc; ++ unsigned int channels; ++ unsigned int slave_requests; ++ unsigned int max_transfer_size; ++}; ++ ++#ifdef DEBUG_EDMAC ++void dump_lli(const u64 *llis_vaddr, unsigned int num) ++{ ++ edmac_lli *plli = (edmac_lli *)llis_vaddr; ++ unsigned int i; ++ ++ edmacv310_trace(EDMACV310_CONFIG_TRACE_LEVEL, "lli num = 0%d\n", num); ++ for (i = 0; i < num; i++) { ++ printk("lli%d:lli_L: 0x%llx\n", i, plli[i].next_lli & 0xffffffff); ++ printk("lli%d:lli_H: 0x%llx\n", i, (plli[i].next_lli >> BITS_PER_HALF_WORD) & 0xffffffff); ++ printk("lli%d:count: 0x%x\n", i, plli[i].count); ++ printk("lli%d:src_addr_L: 0x%llx\n", i, plli[i].src_addr & 0xffffffff); ++ printk("lli%d:src_addr_H: 0x%llx\n", i, (plli[i].src_addr >> BITS_PER_HALF_WORD) & 0xffffffff); ++ printk("lli%d:dst_addr_L: 0x%llx\n", i, plli[i].dest_addr & 0xffffffff); ++ printk("lli%d:dst_addr_H: 0x%llx\n", i, (plli[i].dest_addr >> BITS_PER_HALF_WORD) & 0xffffffff); ++ printk("lli%d:CONFIG: 0x%x\n", i, plli[i].config); ++ } ++} ++ ++#else ++void dump_lli(const u64 *llis_vaddr, unsigned int num) ++{ ++} ++#endif ++ ++static inline struct edmacv310_dma_chan *to_edamc_chan(const struct dma_chan *chan) ++{ ++ return container_of(chan, struct edmacv310_dma_chan, virt_chan.chan); ++} ++ ++static inline struct transfer_desc *to_edmac_transfer_desc( ++ const struct dma_async_tx_descriptor *tx) ++{ ++ return container_of(tx, struct transfer_desc, virt_desc.tx); ++} ++ ++static struct dma_chan *edmac_find_chan_id( ++ const struct edmacv310_driver_data *edmac, ++ int request_num) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = NULL; ++ ++ list_for_each_entry(edmac_dma_chan, &edmac->slave.channels, ++ virt_chan.chan.device_node) { ++ if (edmac_dma_chan->id == request_num) ++ return &edmac_dma_chan->virt_chan.chan; ++ } ++ return NULL; ++} ++ ++static struct dma_chan *edma_of_xlate(struct of_phandle_args *dma_spec, ++ struct of_dma *ofdma) ++{ ++ struct edmacv310_driver_data *edmac = ofdma->of_dma_data; ++ struct edmacv310_dma_chan *edmac_dma_chan = NULL; ++ struct dma_chan *dma_chan = NULL; ++ struct regmap *misc = NULL; ++ unsigned int signal, request_num; ++ unsigned int reg = 0; ++ unsigned int offset = 0; ++ ++ if (!edmac) ++ return NULL; ++ ++ misc = edmac->misc_regmap; ++ ++ if (dma_spec->args_count != 2) { /* check num of dts node args */ ++ edmacv310_error("args count not true!\n"); ++ return NULL; ++ } ++ ++ request_num = dma_spec->args[0]; ++ signal = dma_spec->args[1]; ++ ++ edmacv310_trace(EDMACV310_CONFIG_TRACE_LEVEL, "host->id = %d,signal = %d, request_num = %d\n", ++ edmac->id, signal, request_num); ++ ++ if (misc != NULL) { ++ offset = edmac->misc_ctrl_base + (request_num & (~0x3)); ++ regmap_read(misc, offset, ®); ++ /* set misc for signal line */ ++ reg &= ~(0x3f << ((request_num & 0x3) << 3)); ++ reg |= signal << ((request_num & 0x3) << 3); ++ regmap_write(misc, offset, reg); ++ } ++ ++ edmacv310_trace(EDMACV310_CONFIG_TRACE_LEVEL, "offset = 0x%x, reg = 0x%x\n", offset, reg); ++ ++ dma_chan = edmac_find_chan_id(edmac, request_num); ++ if (!dma_chan) { ++ edmacv310_error("DMA slave channel is not found!\n"); ++ return NULL; ++ } ++ ++ edmac_dma_chan = to_edamc_chan(dma_chan); ++ edmac_dma_chan->signal = request_num; ++ return dma_get_slave_channel(dma_chan); ++} ++ ++static int edmacv310_devm_get(struct edmacv310_driver_data *edmac) ++{ ++ struct platform_device *platdev = edmac->dev; ++ struct resource *res = NULL; ++ ++ edmac->clk = devm_clk_get(&(platdev->dev), "apb_pclk"); ++ if (IS_ERR(edmac->clk)) ++ return PTR_ERR(edmac->clk); ++ ++ edmac->axi_clk = devm_clk_get(&(platdev->dev), "axi_aclk"); ++ if (IS_ERR(edmac->axi_clk)) ++ return PTR_ERR(edmac->axi_clk); ++ ++ edmac->irq = platform_get_irq(platdev, 0); ++ if (unlikely(edmac->irq < 0)) ++ return -ENODEV; ++ ++ edmac->rstc = devm_reset_control_get(&(platdev->dev), "dma-reset"); ++ if (IS_ERR(edmac->rstc)) ++ return PTR_ERR(edmac->rstc); ++ ++ res = platform_get_resource(platdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ edmacv310_error("no reg resource\n"); ++ return -ENODEV; ++ } ++ ++ edmac->base = devm_ioremap_resource(&(platdev->dev), res); ++ if (IS_ERR(edmac->base)) ++ return PTR_ERR(edmac->base); ++ ++ res = platform_get_resource_byname(platdev, IORESOURCE_MEM, "dma_peri_channel_req_sel"); ++ if (res) { ++ void *dma_peri_channel_req_sel = ioremap(res->start, res->end - res->start); ++ if (IS_ERR(dma_peri_channel_req_sel)) ++ return PTR_ERR(dma_peri_channel_req_sel); ++ writel(0xffffffff, dma_peri_channel_req_sel); ++ iounmap(dma_peri_channel_req_sel); ++ } ++ return 0; ++} ++ ++static int edmacv310_of_property_read(struct edmacv310_driver_data *edmac) ++{ ++ struct platform_device *platdev = edmac->dev; ++ struct device_node *np = platdev->dev.of_node; ++ int ret; ++ ++ if (!of_find_property(np, "misc_regmap", NULL) || ++ !of_find_property(np, "misc_ctrl_base", NULL)) { ++ edmac->misc_regmap = 0; ++ } else { ++ edmac->misc_regmap = syscon_regmap_lookup_by_phandle(np, "misc_regmap"); ++ if (IS_ERR(edmac->misc_regmap)) ++ return PTR_ERR(edmac->misc_regmap); ++ ++ ret = of_property_read_u32(np, "misc_ctrl_base", &(edmac->misc_ctrl_base)); ++ if (ret) { ++ edmacv310_error("get dma-misc_ctrl_base fail\n"); ++ return -ENODEV; ++ } ++ } ++ ret = of_property_read_u32(np, "devid", &(edmac->id)); ++ if (ret) { ++ edmacv310_error("get edmac id fail\n"); ++ return -ENODEV; ++ } ++ ret = of_property_read_u32(np, "dma-channels", &(edmac->channels)); ++ if (ret) { ++ edmacv310_error("get dma-channels fail\n"); ++ return -ENODEV; ++ } ++ ret = of_property_read_u32(np, "dma-requests", &(edmac->slave_requests)); ++ if (ret) { ++ edmacv310_error("get dma-requests fail\n"); ++ return -ENODEV; ++ } ++ edmacv310_trace(EDMACV310_REG_TRACE_LEVEL, "dma-channels = %d, dma-requests = %d\n", ++ edmac->channels, edmac->slave_requests); ++ return 0; ++} ++ ++static int get_of_probe(struct edmacv310_driver_data *edmac) ++{ ++ struct platform_device *platdev = edmac->dev; ++ int ret; ++ ++ ret = edmacv310_devm_get(edmac); ++ if (ret) ++ return ret; ++ ++ ret = edmacv310_of_property_read(edmac); ++ if (ret) ++ return ret; ++ ++ return of_dma_controller_register(platdev->dev.of_node, ++ edma_of_xlate, edmac); ++} ++ ++static void edmac_free_chan_resources(struct dma_chan *chan) ++{ ++ vchan_free_chan_resources(to_virt_chan(chan)); ++} ++ ++static size_t read_residue_from_phychan( ++ const struct edmacv310_dma_chan *edmac_dma_chan, ++ const struct transfer_desc *tsf_desc) ++{ ++ size_t bytes; ++ u64 next_lli; ++ struct edmacv310_phy_chan *phychan = edmac_dma_chan->phychan; ++ unsigned int i, index; ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ edmac_lli *plli = NULL; ++ ++ next_lli = (edmacv310_readl(edmac->base + edmac_cx_lli_l(phychan->id)) & ++ (~(EDMAC_LLI_ALIGN - 1))); ++ next_lli |= ((u64)(edmacv310_readl(edmac->base + edmac_cx_lli_h( ++ phychan->id)) & 0xffffffff) << BITS_PER_HALF_WORD); ++ bytes = edmacv310_readl(edmac->base + edmac_cx_curr_cnt0( ++ phychan->id)); ++ if (next_lli != 0) { ++ /* It means lli mode */ ++ bytes += tsf_desc->size; ++ index = (next_lli - tsf_desc->llis_busaddr) / sizeof(*plli); ++ plli = (edmac_lli *)(tsf_desc->llis_vaddr); ++ ++ if (index > MAX_TSFR_LLIS) ++ return 0; ++ ++ for (i = 0; i < index; i++) ++ bytes -= plli[i].count; ++ } ++ return bytes; ++} ++ ++static enum dma_status edmac_tx_status(struct dma_chan *chan, ++ dma_cookie_t cookie, ++ struct dma_tx_state *txstate) ++{ ++ enum dma_status ret; ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ struct virt_dma_desc *vd = NULL; ++ struct transfer_desc *tsf_desc = NULL; ++ unsigned long flags; ++ size_t bytes; ++ ++ ret = dma_cookie_status(chan, cookie, txstate); ++ if (ret == DMA_COMPLETE) ++ return ret; ++ ++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags); ++ vd = vchan_find_desc(&edmac_dma_chan->virt_chan, cookie); ++ if (vd) { ++ /* no been trasfer */ ++ tsf_desc = to_edmac_transfer_desc(&vd->tx); ++ bytes = tsf_desc->size; ++ } else { ++ /* trasfering */ ++ tsf_desc = edmac_dma_chan->at; ++ ++ if (!(edmac_dma_chan->phychan) || !tsf_desc) { ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ return ret; ++ } ++ bytes = read_residue_from_phychan(edmac_dma_chan, tsf_desc); ++ } ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ dma_set_residue(txstate, bytes); ++ ++ if (edmac_dma_chan->state == EDMAC_CHAN_PAUSED && ret == DMA_IN_PROGRESS) ++ return DMA_PAUSED; ++ ++ return ret; ++} ++ ++static struct edmacv310_phy_chan *edmac_get_phy_channel( ++ const struct edmacv310_driver_data *edmac, ++ struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ struct edmacv310_phy_chan *ch = NULL; ++ unsigned long flags; ++ int i; ++ ++ for (i = 0; i < edmac->channels; i++) { ++ ch = &edmac->phy_chans[i]; ++ ++ spin_lock_irqsave(&ch->lock, flags); ++ ++ if (!ch->serving) { ++ ch->serving = edmac_dma_chan; ++ spin_unlock_irqrestore(&ch->lock, flags); ++ break; ++ } ++ spin_unlock_irqrestore(&ch->lock, flags); ++ } ++ ++ if (i == edmac->channels) ++ return NULL; ++ ++ return ch; ++} ++ ++static void edmac_write_lli(const struct edmacv310_driver_data *edmac, ++ const struct edmacv310_phy_chan *phychan, ++ const struct transfer_desc *tsf_desc) ++{ ++ edmac_lli *plli = (edmac_lli *)tsf_desc->llis_vaddr; ++ ++ if (plli->next_lli != 0x0) ++ edmacv310_writel((plli->next_lli & 0xffffffff) | EDMAC_LLI_ENABLE, ++ edmac->base + edmac_cx_lli_l(phychan->id)); ++ else ++ edmacv310_writel((plli->next_lli & 0xffffffff), ++ edmac->base + edmac_cx_lli_l(phychan->id)); ++ ++ edmacv310_writel(((plli->next_lli >> 32) & 0xffffffff), ++ edmac->base + edmac_cx_lli_h(phychan->id)); ++ edmacv310_writel(plli->count, edmac->base + edmac_cx_cnt0(phychan->id)); ++ edmacv310_writel(plli->src_addr & 0xffffffff, ++ edmac->base + edmac_cx_src_addr_l(phychan->id)); ++ edmacv310_writel((plli->src_addr >> 32) & 0xffffffff, ++ edmac->base + edmac_cx_src_addr_h(phychan->id)); ++ edmacv310_writel(plli->dest_addr & 0xffffffff, ++ edmac->base + edmac_cx_dest_addr_l(phychan->id)); ++ edmacv310_writel((plli->dest_addr >> 32) & 0xffffffff, ++ edmac->base + edmac_cx_dest_addr_h(phychan->id)); ++ edmacv310_writel(plli->config, ++ edmac->base + edmac_cx_config(phychan->id)); ++} ++ ++static void edmac_start_next_txd(struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct edmacv310_phy_chan *phychan = edmac_dma_chan->phychan; ++ struct virt_dma_desc *vd = vchan_next_desc(&edmac_dma_chan->virt_chan); ++ struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx); ++ unsigned int val; ++ list_del(&tsf_desc->virt_desc.node); ++ edmac_dma_chan->at = tsf_desc; ++ edmac_write_lli(edmac, phychan, tsf_desc); ++ val = edmacv310_readl(edmac->base + edmac_cx_config(phychan->id)); ++ edmacv310_trace(EDMACV310_REG_TRACE_LEVEL, " EDMAC_Cx_CONFIG = 0x%x\n", val); ++ edmacv310_writel(val | EDMAC_CXCONFIG_LLI_START, ++ edmac->base + edmac_cx_config(phychan->id)); ++} ++ ++static void edmac_start(struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct edmacv310_phy_chan *ch; ++ ch = edmac_get_phy_channel(edmac, edmac_dma_chan); ++ if (!ch) { ++ edmacv310_error("no phy channel available !\n"); ++ edmac_dma_chan->state = EDMAC_CHAN_WAITING; ++ return; ++ } ++ edmac_dma_chan->phychan = ch; ++ edmac_dma_chan->state = EDMAC_CHAN_RUNNING; ++ edmac_start_next_txd(edmac_dma_chan); ++} ++ ++static void edmac_issue_pending(struct dma_chan *chan) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ unsigned long flags; ++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags); ++ if (vchan_issue_pending(&edmac_dma_chan->virt_chan)) { ++ if (!edmac_dma_chan->phychan && edmac_dma_chan->state != EDMAC_CHAN_WAITING) ++ edmac_start(edmac_dma_chan); ++ } ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++} ++ ++static void edmac_free_txd_list(struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ LIST_HEAD(head); ++ vchan_get_all_descriptors(&edmac_dma_chan->virt_chan, &head); ++ vchan_dma_desc_free_list(&edmac_dma_chan->virt_chan, &head); ++} ++ ++static int edmac_config(struct dma_chan *chan, ++ struct dma_slave_config *config) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ if (!edmac_dma_chan->slave) { ++ edmacv310_error("slave is null!"); ++ return -EINVAL; ++ } ++ edmac_dma_chan->cfg = *config; ++ return 0; ++} ++ ++static void edmac_pause_phy_chan(const struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct edmacv310_phy_chan *phychan = edmac_dma_chan->phychan; ++ unsigned int val; ++ int timeout; ++ ++ val = edmacv310_readl(edmac->base + edmac_cx_config(phychan->id)); ++ val &= ~CCFG_EN; ++ edmacv310_writel(val, edmac->base + edmac_cx_config(phychan->id)); ++ /* Wait for channel inactive */ ++ for (timeout = 2000; timeout > 0; timeout--) { ++ if (!((0x1 << phychan->id) & edmacv310_readl(edmac->base + EDMAC_CH_STAT))) ++ break; ++ edmacv310_writel(val, edmac->base + edmac_cx_config(phychan->id)); ++ udelay(1); ++ } ++ if (timeout == 0) ++ edmacv310_error(":channel%u timeout waiting for pause, timeout:%d\n", ++ phychan->id, timeout); ++} ++ ++static int edmac_pause(struct dma_chan *chan) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags); ++ if (!edmac_dma_chan->phychan) { ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ return 0; ++ } ++ edmac_pause_phy_chan(edmac_dma_chan); ++ edmac_dma_chan->state = EDMAC_CHAN_PAUSED; ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ return 0; ++} ++ ++static void edmac_resume_phy_chan(const struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct edmacv310_phy_chan *phychan = edmac_dma_chan->phychan; ++ unsigned int val; ++ val = edmacv310_readl(edmac->base + edmac_cx_config(phychan->id)); ++ val |= CCFG_EN; ++ edmacv310_writel(val, edmac->base + edmac_cx_config(phychan->id)); ++} ++ ++static int edmac_resume(struct dma_chan *chan) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags); ++ ++ if (!edmac_dma_chan->phychan) { ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ return 0; ++ } ++ ++ edmac_resume_phy_chan(edmac_dma_chan); ++ edmac_dma_chan->state = EDMAC_CHAN_RUNNING; ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ ++ return 0; ++} ++ ++void edmac_phy_free(struct edmacv310_dma_chan *chan); ++static void edmac_desc_free(struct virt_dma_desc *vd); ++static int edmac_terminate_all(struct dma_chan *chan) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&edmac_dma_chan->virt_chan.lock, flags); ++ if (!edmac_dma_chan->phychan && !edmac_dma_chan->at) { ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ return 0; ++ } ++ ++ edmac_dma_chan->state = EDMAC_CHAN_IDLE; ++ ++ if (edmac_dma_chan->phychan) ++ edmac_phy_free(edmac_dma_chan); ++ if (edmac_dma_chan->at) { ++ edmac_desc_free(&edmac_dma_chan->at->virt_desc); ++ edmac_dma_chan->at = NULL; ++ } ++ edmac_free_txd_list(edmac_dma_chan); ++ spin_unlock_irqrestore(&edmac_dma_chan->virt_chan.lock, flags); ++ ++ return 0; ++} ++ ++static u32 get_width(enum dma_slave_buswidth width) ++{ ++ switch (width) { ++ case DMA_SLAVE_BUSWIDTH_1_BYTE: ++ return EDMAC_WIDTH_8BIT; ++ case DMA_SLAVE_BUSWIDTH_2_BYTES: ++ return EDMAC_WIDTH_16BIT; ++ case DMA_SLAVE_BUSWIDTH_4_BYTES: ++ return EDMAC_WIDTH_32BIT; ++ case DMA_SLAVE_BUSWIDTH_8_BYTES: ++ return EDMAC_WIDTH_64BIT; ++ default: ++ edmacv310_error("check here, width warning!\n"); ++ return ~0; ++ } ++} ++ ++static unsigned int edmac_set_config_value(enum dma_transfer_direction direction, ++ unsigned int addr_width, ++ unsigned int burst, ++ unsigned int signal) ++{ ++ unsigned int config, width; ++ ++ if (direction == DMA_MEM_TO_DEV) ++ config = EDMAC_CONFIG_SRC_INC; ++ else ++ config = EDMAC_CONFIG_DST_INC; ++ ++ edmacv310_trace(EDMACV310_CONFIG_TRACE_LEVEL, "addr_width = 0x%x\n", addr_width); ++ width = get_width(addr_width); ++ edmacv310_trace(EDMACV310_CONFIG_TRACE_LEVEL, "width = 0x%x\n", width); ++ config |= width << EDMAC_CONFIG_SRC_WIDTH_SHIFT; ++ config |= width << EDMAC_CONFIG_DST_WIDTH_SHIFT; ++ edmacv310_trace(EDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", config); ++ edmacv310_trace(EDMACV310_CONFIG_TRACE_LEVEL, "burst = 0x%x\n", burst); ++ config |= burst << EDMAC_CONFIG_SRC_BURST_SHIFT; ++ config |= burst << EDMAC_CONFIG_DST_BURST_SHIFT; ++ if (signal >= 0) { ++ edmacv310_trace(EDMACV310_REG_TRACE_LEVEL, "edmac_dma_chan->signal = %d\n", signal); ++ config |= (unsigned int)signal << EDMAC_CXCONFIG_SIGNAL_SHIFT; ++ } ++ config |= EDMAC_CXCONFIG_DEV_MEM_TYPE << EDMAC_CXCONFIG_TSF_TYPE_SHIFT; ++ return config; ++} ++ ++struct transfer_desc *edmac_init_tsf_desc(const struct dma_chan *chan, ++ enum dma_transfer_direction direction, ++ dma_addr_t *slave_addr) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ struct transfer_desc *tsf_desc; ++ unsigned int burst = 0; ++ unsigned int addr_width = 0; ++ unsigned int maxburst = 0; ++ tsf_desc = kzalloc(sizeof(*tsf_desc), GFP_NOWAIT); ++ if (!tsf_desc) ++ return NULL; ++ if (direction == DMA_MEM_TO_DEV) { ++ *slave_addr = edmac_dma_chan->cfg.dst_addr; ++ addr_width = edmac_dma_chan->cfg.dst_addr_width; ++ maxburst = edmac_dma_chan->cfg.dst_maxburst; ++ } else if (direction == DMA_DEV_TO_MEM) { ++ *slave_addr = edmac_dma_chan->cfg.src_addr; ++ addr_width = edmac_dma_chan->cfg.src_addr_width; ++ maxburst = edmac_dma_chan->cfg.src_maxburst; ++ } else { ++ kfree(tsf_desc); ++ edmacv310_error("direction unsupported!\n"); ++ return NULL; ++ } ++ ++ if (maxburst > (EDMAC_MAX_BURST_WIDTH)) ++ burst |= (EDMAC_MAX_BURST_WIDTH - 1); ++ else if (maxburst == 0) ++ burst |= EDMAC_MIN_BURST_WIDTH; ++ else ++ burst |= (maxburst - 1); ++ ++ tsf_desc->ccfg = edmac_set_config_value(direction, addr_width, ++ burst, edmac_dma_chan->signal); ++ edmacv310_trace(EDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", tsf_desc->ccfg); ++ return tsf_desc; ++} ++ ++static int edmac_fill_desc(const struct edmac_sg *dsg, ++ struct transfer_desc *tsf_desc, ++ unsigned int length, unsigned int num) ++{ ++ edmac_lli *plli = NULL; ++ ++ if (num >= MAX_TSFR_LLIS) { ++ edmacv310_error("lli out of range. \n"); ++ return -ENOMEM; ++ } ++ ++ plli = (edmac_lli *)(tsf_desc->llis_vaddr); ++ (void)memset_s(&plli[num], sizeof(edmac_lli), 0x0, sizeof(*plli)); ++ ++ plli[num].src_addr = dsg->src_addr; ++ plli[num].dest_addr = dsg->dst_addr; ++ plli[num].config = tsf_desc->ccfg; ++ plli[num].count = length; ++ tsf_desc->size += length; ++ ++ if (num > 0) { ++ plli[num - 1].next_lli = (tsf_desc->llis_busaddr + (num) * sizeof( ++ *plli)) & (~(EDMAC_LLI_ALIGN - 1)); ++ plli[num - 1].next_lli |= EDMAC_LLI_ENABLE; ++ } ++ return 0; ++} ++ ++static void free_dsg(struct list_head *dsg_head) ++{ ++ struct edmac_sg *dsg = NULL; ++ struct edmac_sg *_dsg = NULL; ++ ++ list_for_each_entry_safe(dsg, _dsg, dsg_head, node) { ++ list_del(&dsg->node); ++ kfree(dsg); ++ } ++} ++ ++static int edmac_add_sg(struct list_head *sg_head, ++ dma_addr_t dst, dma_addr_t src, ++ size_t len) ++{ ++ struct edmac_sg *dsg = NULL; ++ ++ if (len == 0) { ++ free_dsg(sg_head); ++ edmacv310_error("Transfer length is 0. \n"); ++ return -ENOMEM; ++ } ++ ++ dsg = (struct edmac_sg *)kzalloc(sizeof(*dsg), GFP_NOWAIT); ++ if (!dsg) { ++ free_dsg(sg_head); ++ edmacv310_error("alloc memory for dsg fail.\n"); ++ return -ENOMEM; ++ } ++ ++ list_add_tail(&dsg->node, sg_head); ++ dsg->src_addr = src; ++ dsg->dst_addr = dst; ++ dsg->len = len; ++ return 0; ++} ++ ++static int edmac_add_sg_slave(struct list_head *sg_head, ++ dma_addr_t slave_addr, dma_addr_t addr, ++ size_t length, ++ enum dma_transfer_direction direction) ++{ ++ dma_addr_t src = 0; ++ dma_addr_t dst = 0; ++ if (direction == DMA_MEM_TO_DEV) { ++ src = addr; ++ dst = slave_addr; ++ } else if (direction == DMA_DEV_TO_MEM) { ++ src = slave_addr; ++ dst = addr; ++ } else { ++ edmacv310_error("invali dma_transfer_direction.\n"); ++ return -ENOMEM; ++ } ++ return edmac_add_sg(sg_head, dst, src, length); ++} ++ ++static int edmac_fill_sg_for_slave(struct list_head *sg_head, ++ dma_addr_t slave_addr, ++ struct scatterlist *sgl, ++ unsigned int sg_len, ++ enum dma_transfer_direction direction) ++{ ++ struct scatterlist *sg = NULL; ++ int tmp, ret; ++ size_t length; ++ dma_addr_t addr; ++ if (sgl == NULL) { ++ edmacv310_error("sgl is null!\n"); ++ return -ENOMEM; ++ } ++ ++ for_each_sg(sgl, sg, sg_len, tmp) { ++ addr = sg_dma_address(sg); ++ length = sg_dma_len(sg); ++ ret = edmac_add_sg_slave(sg_head, slave_addr, addr, length, direction); ++ if (ret) ++ break; ++ } ++ return ret; ++} ++ ++static inline int edmac_fill_sg_for_m2m_copy(struct list_head *sg_head, ++ dma_addr_t dst, dma_addr_t src, ++ size_t len) ++{ ++ return edmac_add_sg(sg_head, dst, src, len); ++} ++ ++struct edmac_cyclic_args { ++ dma_addr_t slave_addr; ++ dma_addr_t buf_addr; ++ size_t buf_len; ++ size_t period_len; ++ enum dma_transfer_direction direction; ++}; ++ ++static int edmac_fill_sg_for_cyclic(struct list_head *sg_head, ++ struct edmac_cyclic_args args) ++{ ++ size_t count_in_sg = 0; ++ size_t trans_bytes; ++ int ret; ++ while (count_in_sg < args.buf_len) { ++ trans_bytes = min(args.period_len, args.buf_len - count_in_sg); ++ count_in_sg += trans_bytes; ++ ret = edmac_add_sg_slave(sg_head, args.slave_addr, args.buf_addr + count_in_sg, count_in_sg, args.direction); ++ if (ret) ++ return ret; ++ } ++ return 0; ++} ++ ++static unsigned short get_max_width(dma_addr_t ccfg) ++{ ++ unsigned short src_width = (ccfg & EDMAC_CONTROL_SRC_WIDTH_MASK) >> ++ EDMAC_CONFIG_SRC_WIDTH_SHIFT; ++ unsigned short dst_width = (ccfg & EDMAC_CONTROL_DST_WIDTH_MASK) >> ++ EDMAC_CONFIG_DST_WIDTH_SHIFT; ++ return 1 << max(src_width, dst_width); /* to byte */ ++} ++ ++static int edmac_fill_asg_lli_for_desc(struct edmac_sg *dsg, ++ struct transfer_desc *tsf_desc, ++ unsigned int *lli_count) ++{ ++ int ret; ++ unsigned short width = get_max_width(tsf_desc->ccfg); ++ ++ while (dsg->len != 0) { ++ size_t lli_len = MAX_TRANSFER_BYTES; ++ lli_len = (lli_len / width) * width; /* bus width align */ ++ lli_len = min(lli_len, dsg->len); ++ ret = edmac_fill_desc(dsg, tsf_desc, lli_len, *lli_count); ++ if (ret) ++ return ret; ++ ++ if (tsf_desc->ccfg & EDMAC_CONFIG_SRC_INC) ++ dsg->src_addr += lli_len; ++ if (tsf_desc->ccfg & EDMAC_CONFIG_DST_INC) ++ dsg->dst_addr += lli_len; ++ dsg->len -= lli_len; ++ (*lli_count)++; ++ } ++ return 0; ++} ++ ++static int edmac_fill_lli_for_desc(const struct list_head *sg_head, ++ struct transfer_desc *tsf_desc) ++{ ++ struct edmac_sg *dsg = NULL; ++ struct edmac_lli *last_plli = NULL; ++ unsigned int lli_count = 0; ++ int ret; ++ ++ list_for_each_entry(dsg, sg_head, node) { ++ ret = edmac_fill_asg_lli_for_desc(dsg, tsf_desc, &lli_count); ++ if (ret) ++ return ret; ++ } ++ ++ if (tsf_desc->cyclic) { ++ last_plli = (edmac_lli *)((uintptr_t)tsf_desc->llis_vaddr + ++ (lli_count - 1) * sizeof(*last_plli)); ++ last_plli->next_lli = tsf_desc->llis_busaddr | EDMAC_LLI_ENABLE; ++ } else { ++ last_plli = (edmac_lli *)((uintptr_t)tsf_desc->llis_vaddr + ++ (lli_count - 1) * sizeof(*last_plli)); ++ last_plli->next_lli = 0; ++ } ++ dump_lli(tsf_desc->llis_vaddr, lli_count); ++ return 0; ++} ++ ++static struct dma_async_tx_descriptor *edmac_prep_slave_sg( ++ struct dma_chan *chan, struct scatterlist *sgl, ++ unsigned int sg_len, enum dma_transfer_direction direction, ++ unsigned long flags, void *context) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct transfer_desc *tsf_desc = NULL; ++ dma_addr_t slave_addr = 0; ++ int ret; ++ LIST_HEAD(sg_head); ++ if (sgl == NULL) { ++ edmacv310_error("sgl is null!\n"); ++ return NULL; ++ } ++ ++ tsf_desc = edmac_init_tsf_desc(chan, direction, &slave_addr); ++ if (!tsf_desc) ++ return NULL; ++ ++ tsf_desc->llis_vaddr = dma_pool_alloc(edmac->pool, GFP_NOWAIT, ++ &tsf_desc->llis_busaddr); ++ if (!tsf_desc->llis_vaddr) { ++ edmacv310_error("malloc memory from pool fail !\n"); ++ goto err_alloc_lli; ++ } ++ ++ ret = edmac_fill_sg_for_slave(&sg_head, slave_addr, sgl, sg_len, direction); ++ if (ret) ++ goto err_fill_sg; ++ ret = edmac_fill_lli_for_desc(&sg_head, tsf_desc); ++ free_dsg(&sg_head); ++ if (ret) ++ goto err_fill_sg; ++ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags); ++ ++err_fill_sg: ++ dma_pool_free(edmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr); ++err_alloc_lli: ++ kfree(tsf_desc); ++ return NULL; ++} ++ ++static struct dma_async_tx_descriptor *edmac_prep_dma_m2m_copy( ++ struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, ++ size_t len, unsigned long flags) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct transfer_desc *tsf_desc = NULL; ++ LIST_HEAD(sg_head); ++ u32 config = 0; ++ int ret; ++ ++ if (!len) ++ return NULL; ++ ++ tsf_desc = kzalloc(sizeof(*tsf_desc), GFP_NOWAIT); ++ if (tsf_desc == NULL) { ++ edmacv310_error("get tsf desc fail!\n"); ++ return NULL; ++ } ++ ++ tsf_desc->llis_vaddr = dma_pool_alloc(edmac->pool, GFP_NOWAIT, ++ &tsf_desc->llis_busaddr); ++ if (!tsf_desc->llis_vaddr) { ++ edmacv310_error("malloc memory from pool fail !\n"); ++ goto err_alloc_lli; ++ } ++ ++ config |= EDMAC_CONFIG_SRC_INC | EDMAC_CONFIG_DST_INC; ++ config |= EDMAC_CXCONFIG_MEM_TYPE << EDMAC_CXCONFIG_TSF_TYPE_SHIFT; ++ /* max burst width is 16 ,but reg value set 0xf */ ++ config |= (EDMAC_MAX_BURST_WIDTH - 1) << EDMAC_CONFIG_SRC_BURST_SHIFT; ++ config |= (EDMAC_MAX_BURST_WIDTH - 1) << EDMAC_CONFIG_DST_BURST_SHIFT; ++ config |= EDMAC_MEM_BIT_WIDTH << EDMAC_CONFIG_SRC_WIDTH_SHIFT; ++ config |= EDMAC_MEM_BIT_WIDTH << EDMAC_CONFIG_DST_WIDTH_SHIFT; ++ tsf_desc->ccfg = config; ++ ret = edmac_fill_sg_for_m2m_copy(&sg_head, dst, src, len); ++ if (ret) ++ goto err_fill_sg; ++ ret = edmac_fill_lli_for_desc(&sg_head, tsf_desc); ++ free_dsg(&sg_head); ++ if (ret) ++ goto err_fill_sg; ++ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags); ++ ++err_fill_sg: ++ dma_pool_free(edmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr); ++err_alloc_lli: ++ kfree(tsf_desc); ++ return NULL; ++} ++ ++static struct dma_async_tx_descriptor *edmac_prep_dma_cyclic( ++ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, ++ size_t period_len, enum dma_transfer_direction direction, ++ unsigned long flags) ++{ ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(chan); ++ struct edmacv310_driver_data *edmac = edmac_dma_chan->host; ++ struct transfer_desc *tsf_desc = NULL; ++ struct edmac_cyclic_args args = { ++ .slave_addr = 0, ++ .buf_addr = buf_addr, ++ .buf_len = buf_len, ++ .period_len = period_len, ++ .direction = direction ++ }; ++ LIST_HEAD(sg_head); ++ int ret; ++ ++ tsf_desc = edmac_init_tsf_desc(chan, direction, &(args.slave_addr)); ++ if (!tsf_desc) ++ return NULL; ++ ++ tsf_desc->llis_vaddr = dma_pool_alloc(edmac->pool, GFP_NOWAIT, ++ &tsf_desc->llis_busaddr); ++ if (!tsf_desc->llis_vaddr) { ++ edmacv310_error("malloc memory from pool fail !\n"); ++ goto err_alloc_lli; ++ } ++ ++ tsf_desc->cyclic = true; ++ ret = edmac_fill_sg_for_cyclic(&sg_head, args); ++ if (ret) ++ goto err_fill_sg; ++ ret = edmac_fill_lli_for_desc(&sg_head, tsf_desc); ++ free_dsg(&sg_head); ++ if (ret) ++ goto err_fill_sg; ++ return vchan_tx_prep(&edmac_dma_chan->virt_chan, &tsf_desc->virt_desc, flags); ++ ++err_fill_sg: ++ dma_pool_free(edmac->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr); ++err_alloc_lli: ++ kfree(tsf_desc); ++ return NULL; ++} ++ ++static void edmac_phy_reassign(struct edmacv310_phy_chan *phy_chan, ++ struct edmacv310_dma_chan *chan) ++{ ++ phy_chan->serving = chan; ++ chan->phychan = phy_chan; ++ chan->state = EDMAC_CHAN_RUNNING; ++ ++ edmac_start_next_txd(chan); ++} ++ ++static void edmac_terminate_phy_chan(const struct edmacv310_driver_data *edmac, ++ const struct edmacv310_dma_chan *edmac_dma_chan) ++{ ++ unsigned int val; ++ struct edmacv310_phy_chan *phychan = edmac_dma_chan->phychan; ++ edmac_pause_phy_chan(edmac_dma_chan); ++ val = 0x1 << phychan->id; ++ edmacv310_writel(val, edmac->base + EDMAC_INT_TC1_RAW); ++ edmacv310_writel(val, edmac->base + EDMAC_INT_ERR1_RAW); ++ edmacv310_writel(val, edmac->base + EDMAC_INT_ERR2_RAW); ++} ++ ++void edmac_phy_free(struct edmacv310_dma_chan *chan) ++{ ++ struct edmacv310_driver_data *edmac = chan->host; ++ struct edmacv310_dma_chan *p = NULL; ++ struct edmacv310_dma_chan *next = NULL; ++ ++ list_for_each_entry(p, &edmac->memcpy.channels, virt_chan.chan.device_node) { ++ if (p->state == EDMAC_CHAN_WAITING) { ++ next = p; ++ break; ++ } ++ } ++ ++ if (!next) { ++ list_for_each_entry(p, &edmac->slave.channels, virt_chan.chan.device_node) { ++ if (p->state == EDMAC_CHAN_WAITING) { ++ next = p; ++ break; ++ } ++ } ++ } ++ edmac_terminate_phy_chan(edmac, chan); ++ ++ if (next) { ++ spin_lock(&next->virt_chan.lock); ++ edmac_phy_reassign(chan->phychan, next); ++ spin_unlock(&next->virt_chan.lock); ++ } else { ++ chan->phychan->serving = NULL; ++ } ++ ++ chan->phychan = NULL; ++ chan->state = EDMAC_CHAN_IDLE; ++} ++ ++bool handle_irq(const struct edmacv310_driver_data *edmac, int chan_id) ++{ ++ struct edmacv310_dma_chan *chan = NULL; ++ struct edmacv310_phy_chan *phy_chan = NULL; ++ struct transfer_desc *tsf_desc = NULL; ++ unsigned int channel_tc_status, channel_err_status[ERR_STATUS_REG_NUM]; ++ ++ phy_chan = &edmac->phy_chans[chan_id]; ++ chan = phy_chan->serving; ++ if (!chan) { ++ edmacv310_error("error interrupt on chan: %d!\n", chan_id); ++ return 0; ++ } ++ tsf_desc = chan->at; ++ ++ channel_tc_status = edmacv310_readl(edmac->base + EDMAC_INT_TC1_RAW); ++ channel_tc_status = (channel_tc_status >> chan_id) & 0x01; ++ if (channel_tc_status) ++ edmacv310_writel(channel_tc_status << chan_id, edmac->base + EDMAC_INT_TC1_RAW); ++ ++ channel_tc_status = edmacv310_readl(edmac->base + EDMAC_INT_TC2); ++ channel_tc_status = (channel_tc_status >> chan_id) & 0x01; ++ if (channel_tc_status) ++ edmacv310_writel(channel_tc_status << chan_id, edmac->base + EDMAC_INT_TC2_RAW); ++ ++ channel_err_status[0] = edmacv310_readl(edmac->base + EDMAC_INT_ERR1); ++ channel_err_status[1] = edmacv310_readl(edmac->base + EDMAC_INT_ERR2); ++ channel_err_status[2] = edmacv310_readl(edmac->base + EDMAC_INT_ERR3); ++ if ((channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) & (1 << chan_id)) { ++ edmacv310_error("Error in edmac %d!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n", ++ chan_id, channel_err_status[0], ++ channel_err_status[1], channel_err_status[2]); ++ edmacv310_writel(1 << chan_id, edmac->base + EDMAC_INT_ERR1_RAW); ++ edmacv310_writel(1 << chan_id, edmac->base + EDMAC_INT_ERR2_RAW); ++ edmacv310_writel(1 << chan_id, edmac->base + EDMAC_INT_ERR3_RAW); ++ } ++ ++ spin_lock(&chan->virt_chan.lock); ++ ++ if (tsf_desc->cyclic) { ++ vchan_cyclic_callback(&tsf_desc->virt_desc); ++ spin_unlock(&chan->virt_chan.lock); ++ return 1; ++ } ++ chan->at = NULL; ++ tsf_desc->done = true; ++ vchan_cookie_complete(&tsf_desc->virt_desc); ++ ++ if (vchan_next_desc(&chan->virt_chan)) ++ edmac_start_next_txd(chan); ++ else ++ edmac_phy_free(chan); ++ spin_unlock(&chan->virt_chan.lock); ++ return 1; ++} ++ ++static irqreturn_t emdacv310_irq(int irq, void *dev) ++{ ++ struct edmacv310_driver_data *edmac = (struct edmacv310_driver_data *)dev; ++ u32 mask = 0; ++ unsigned int channel_status, temp, i; ++ ++ channel_status = edmacv310_readl(edmac->base + EDMAC_INT_STAT); ++ if (!channel_status) { ++ edmacv310_error("channel_status = 0x%x\n", channel_status); ++ return IRQ_NONE; ++ } ++ ++ for (i = 0; i < edmac->channels; i++) { ++ temp = (channel_status >> i) & 0x1; ++ if (temp) ++ mask |= handle_irq(edmac, i) << i; ++ } ++ return mask ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static inline void edmac_dma_slave_init(struct edmacv310_dma_chan *chan) ++{ ++ chan->slave = true; ++} ++ ++static void edmac_desc_free(struct virt_dma_desc *vd) ++{ ++ struct transfer_desc *tsf_desc = to_edmac_transfer_desc(&vd->tx); ++ struct edmacv310_dma_chan *edmac_dma_chan = to_edamc_chan(vd->tx.chan); ++ dma_descriptor_unmap(&vd->tx); ++ dma_pool_free(edmac_dma_chan->host->pool, tsf_desc->llis_vaddr, tsf_desc->llis_busaddr); ++ kfree(tsf_desc); ++} ++ ++static int edmac_init_virt_channels(struct edmacv310_driver_data *edmac, ++ struct dma_device *dmadev, ++ unsigned int channels, bool slave) ++{ ++ struct edmacv310_dma_chan *chan = NULL; ++ int i; ++ INIT_LIST_HEAD(&dmadev->channels); ++ ++ for (i = 0; i < channels; i++) { ++ chan = kzalloc(sizeof(struct edmacv310_dma_chan), GFP_KERNEL); ++ if (!chan) { ++ edmacv310_error("fail to allocate memory for virt channels!"); ++ return -1; ++ } ++ ++ chan->host = edmac; ++ chan->state = EDMAC_CHAN_IDLE; ++ chan->signal = -1; ++ ++ if (slave) { ++ chan->id = i; ++ edmac_dma_slave_init(chan); ++ } ++ chan->virt_chan.desc_free = edmac_desc_free; ++ vchan_init(&chan->virt_chan, dmadev); ++ } ++ return 0; ++} ++ ++void edmac_free_virt_channels(struct dma_device *dmadev) ++{ ++ struct edmacv310_dma_chan *chan = NULL; ++ struct edmacv310_dma_chan *next = NULL; ++ ++ list_for_each_entry_safe(chan, next, &dmadev->channels, virt_chan.chan.device_node) { ++ list_del(&chan->virt_chan.chan.device_node); ++ kfree(chan); ++ } ++} ++ ++static void edmacv310_prep_dma_device(struct platform_device *pdev, ++ struct edmacv310_driver_data *edmac) ++{ ++ dma_cap_set(DMA_MEMCPY, edmac->memcpy.cap_mask); ++ edmac->memcpy.dev = &pdev->dev; ++ edmac->memcpy.device_free_chan_resources = edmac_free_chan_resources; ++ edmac->memcpy.device_prep_dma_memcpy = edmac_prep_dma_m2m_copy; ++ edmac->memcpy.device_tx_status = edmac_tx_status; ++ edmac->memcpy.device_issue_pending = edmac_issue_pending; ++ edmac->memcpy.device_config = edmac_config; ++ edmac->memcpy.device_pause = edmac_pause; ++ edmac->memcpy.device_resume = edmac_resume; ++ edmac->memcpy.device_terminate_all = edmac_terminate_all; ++ edmac->memcpy.directions = BIT(DMA_MEM_TO_MEM); ++ edmac->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; ++ ++ dma_cap_set(DMA_SLAVE, edmac->slave.cap_mask); ++ dma_cap_set(DMA_CYCLIC, edmac->slave.cap_mask); ++ edmac->slave.dev = &pdev->dev; ++ edmac->slave.device_free_chan_resources = edmac_free_chan_resources; ++ edmac->slave.device_tx_status = edmac_tx_status; ++ edmac->slave.device_issue_pending = edmac_issue_pending; ++ edmac->slave.device_prep_slave_sg = edmac_prep_slave_sg; ++ edmac->slave.device_prep_dma_cyclic = edmac_prep_dma_cyclic; ++ edmac->slave.device_config = edmac_config; ++ edmac->slave.device_resume = edmac_resume; ++ edmac->slave.device_pause = edmac_pause; ++ edmac->slave.device_terminate_all = edmac_terminate_all; ++ edmac->slave.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); ++ edmac->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; ++} ++ ++static int edmacv310_init_chan(struct edmacv310_driver_data *edmac) ++{ ++ int i, ret; ++ edmac->phy_chans = kzalloc((edmac->channels * sizeof( ++ struct edmacv310_phy_chan)), ++ GFP_KERNEL); ++ if (!edmac->phy_chans) { ++ edmacv310_error("malloc for phy chans fail!"); ++ return -ENOMEM; ++ } ++ ++ for (i = 0; i < edmac->channels; i++) { ++ struct edmacv310_phy_chan *phy_ch = &edmac->phy_chans[i]; ++ phy_ch->id = i; ++ phy_ch->base = edmac->base + edmac_cx_base(i); ++ spin_lock_init(&phy_ch->lock); ++ phy_ch->serving = NULL; ++ } ++ ++ ret = edmac_init_virt_channels(edmac, &edmac->memcpy, edmac->channels, ++ false); ++ if (ret) { ++ edmacv310_error("fail to init memory virt channels!"); ++ goto free_phychans; ++ } ++ ++ ret = edmac_init_virt_channels(edmac, &edmac->slave, edmac->slave_requests, ++ true); ++ if (ret) { ++ edmacv310_error("fail to init slave virt channels!"); ++ goto free_memory_virt_channels; ++ } ++ return 0; ++ ++free_memory_virt_channels: ++ edmac_free_virt_channels(&edmac->memcpy); ++free_phychans: ++ kfree(edmac->phy_chans); ++ return -ENOMEM; ++} ++ ++static void edmacv310_free_chan(struct edmacv310_driver_data *edmac) ++{ ++ edmac_free_virt_channels(&edmac->slave); ++ edmac_free_virt_channels(&edmac->memcpy); ++ kfree(edmac->phy_chans); ++} ++ ++static void edmacv310_prep_phy_device(const struct edmacv310_driver_data *edmac) ++{ ++ clk_prepare_enable(edmac->clk); ++ clk_prepare_enable(edmac->axi_clk); ++ reset_control_deassert(edmac->rstc); ++ ++ edmacv310_writel(EDMAC_ALL_CHAN_CLR, edmac->base + EDMAC_INT_TC1_RAW); ++ edmacv310_writel(EDMAC_ALL_CHAN_CLR, edmac->base + EDMAC_INT_TC2_RAW); ++ edmacv310_writel(EDMAC_ALL_CHAN_CLR, edmac->base + EDMAC_INT_ERR1_RAW); ++ edmacv310_writel(EDMAC_ALL_CHAN_CLR, edmac->base + EDMAC_INT_ERR2_RAW); ++ edmacv310_writel(EDMAC_ALL_CHAN_CLR, edmac->base + EDMAC_INT_ERR3_RAW); ++ edmacv310_writel(EDMAC_INT_ENABLE_ALL_CHAN, ++ edmac->base + EDMAC_INT_TC1_MASK); ++ edmacv310_writel(EDMAC_INT_ENABLE_ALL_CHAN, ++ edmac->base + EDMAC_INT_TC2_MASK); ++ edmacv310_writel(EDMAC_INT_ENABLE_ALL_CHAN, ++ edmac->base + EDMAC_INT_ERR1_MASK); ++ edmacv310_writel(EDMAC_INT_ENABLE_ALL_CHAN, ++ edmac->base + EDMAC_INT_ERR2_MASK); ++ edmacv310_writel(EDMAC_INT_ENABLE_ALL_CHAN, ++ edmac->base + EDMAC_INT_ERR3_MASK); ++} ++ ++static struct edmacv310_driver_data *edmacv310_prep_edmac_device(struct platform_device *pdev) ++{ ++ int ret; ++ struct edmacv310_driver_data *edmac = NULL; ++ ssize_t trasfer_size; ++ ++ ret = dma_set_mask_and_coherent(&(pdev->dev), DMA_BIT_MASK(64)); ++ if (ret) ++ return NULL; ++ ++ edmac = kzalloc(sizeof(*edmac), GFP_KERNEL); ++ if (!edmac) { ++ edmacv310_error("malloc for edmac fail!"); ++ return NULL; ++ } ++ ++ edmac->dev = pdev; ++ ++ ret = get_of_probe(edmac); ++ if (ret) { ++ edmacv310_error("get dts info fail!"); ++ goto free_edmac; ++ } ++ ++ edmacv310_prep_dma_device(pdev, edmac); ++ edmac->max_transfer_size = MAX_TRANSFER_BYTES; ++ trasfer_size = MAX_TSFR_LLIS * EDMACV300_LLI_WORDS * sizeof(u32); ++ ++ edmac->pool = dma_pool_create(DRIVER_NAME, &(pdev->dev), ++ trasfer_size, EDMACV300_POOL_ALIGN, 0); ++ if (!edmac->pool) { ++ edmacv310_error("create pool fail!"); ++ goto free_edmac; ++ } ++ ++ ret = edmacv310_init_chan(edmac); ++ if (ret) ++ goto free_pool; ++ ++ return edmac; ++ ++free_pool: ++ dma_pool_destroy(edmac->pool); ++free_edmac: ++ kfree(edmac); ++ return NULL; ++} ++ ++static void free_edmac_device(struct edmacv310_driver_data *edmac) ++{ ++ edmacv310_free_chan(edmac); ++ dma_pool_destroy(edmac->pool); ++ kfree(edmac); ++} ++ ++static int __init edmacv310_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct edmacv310_driver_data *edmac = NULL; ++ ++ edmac = edmacv310_prep_edmac_device(pdev); ++ if (edmac == NULL) ++ return -ENOMEM; ++ ++ ret = request_irq(edmac->irq, emdacv310_irq, 0, DRIVER_NAME, edmac); ++ if (ret) { ++ edmacv310_error("fail to request irq"); ++ goto free_edmac; ++ } ++ edmacv310_prep_phy_device(edmac); ++ ret = dma_async_device_register(&edmac->memcpy); ++ if (ret) { ++ edmacv310_error("%s failed to register memcpy as an async device - %d\n", __func__, ret); ++ goto free_irq_res; ++ } ++ ++ ret = dma_async_device_register(&edmac->slave); ++ if (ret) { ++ edmacv310_error("%s failed to register slave as an async device - %d\n", __func__, ret); ++ goto free_memcpy_device; ++ } ++ return 0; ++ ++free_memcpy_device: ++ dma_async_device_unregister(&edmac->memcpy); ++free_irq_res: ++ free_irq(edmac->irq, edmac); ++free_edmac: ++ free_edmac_device(edmac); ++ return -ENOMEM; ++} ++ ++static int emda_remove(struct platform_device *pdev) ++{ ++ int err = 0; ++ return err; ++} ++ ++static const struct of_device_id edmacv310_match[] = { ++ { .compatible = "vendor,edmacv310" }, ++ {}, ++}; ++ ++static struct platform_driver edmacv310_driver = { ++ .remove = emda_remove, ++ .driver = { ++ .name = "edmacv310", ++ .of_match_table = edmacv310_match, ++ }, ++}; ++ ++static int __init edmacv310_init(void) ++{ ++ return platform_driver_probe(&edmacv310_driver, edmacv310_probe); ++} ++subsys_initcall(edmacv310_init); ++ ++static void __exit edmacv310_exit(void) ++{ ++ platform_driver_unregister(&edmacv310_driver); ++} ++module_exit(edmacv310_exit); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/dma/edmacv310.h b/drivers/dma/edmacv310.h +new file mode 100644 +index 000000000000..2a266f3a0767 +--- /dev/null ++++ b/drivers/dma/edmacv310.h +@@ -0,0 +1,147 @@ ++/* ++ * ++ * Copyright (c) 2015-2021 Shenshu Technologies Co., Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef __EDMACV310_H__ ++#define __EDMACV310_H__ ++ ++/* debug control */ ++#define EDMACV310_CONFIG_TRACE_LEVEL 3 ++#define EDMACV310_TRACE_LEVEL 0 ++#define EDMACV310_REG_TRACE_LEVEL 3 ++#define EDMACV310_TRACE_FMT KERN_INFO ++ ++#ifdef DEBUG_EDMAC ++#define edmacv310_trace(level, msg...) do { \ ++ if ((level) >= EDMACV310_TRACE_LEVEL) { \ ++ printk(EDMACV310_TRACE_FMT"%s:%d: ", __func__, __LINE__); \ ++ printk(msg); \ ++ printk("\n"); \ ++ } \ ++} while (0) ++ ++ ++#define edmacv310_assert(cond) do { \ ++ if (!(cond)) { \ ++ printk(KERN_ERR "Assert:edmacv310:%s:%d\n", \ ++ __func__, \ ++ __LINE__); \ ++ BUG(); \ ++ } \ ++} while (0) ++ ++#define edmacv310_error(s...) do { \ ++ printk(KERN_ERR "edmacv310:%s:%d: ", __func__, __LINE__); \ ++ printk(s); \ ++ printk("\n"); \ ++} while (0) ++ ++#else ++ ++#define edmacv310_trace(level, msg...) ++#define edmacv310_assert(level, msg...) ++#define edmacv310_error(level, msg...) ++ ++#endif ++ ++#define edmacv310_readl(addr) ((unsigned int)readl((void *)(addr))) ++ ++#define edmacv310_writel(v, addr) do { writel(v, (void *)(addr)); \ ++} while (0) ++ ++ ++#define MAX_TRANSFER_BYTES 0xffff ++ ++/* reg offset */ ++#define EDMAC_INT_STAT 0x0 ++#define EDMAC_INT_TC1 0x4 ++#define EDMAC_INT_TC2 0x8 ++#define EDMAC_INT_ERR1 0xc ++#define EDMAC_INT_ERR2 0x10 ++#define EDMAC_INT_ERR3 0x14 ++ ++#define EDMAC_INT_TC1_MASK 0x18 ++#define EDMAC_INT_TC2_MASK 0x1c ++#define EDMAC_INT_ERR1_MASK 0x20 ++#define EDMAC_INT_ERR2_MASK 0x24 ++#define EDMAC_INT_ERR3_MASK 0x28 ++ ++#define EDMAC_INT_TC1_RAW 0x600 ++#define EDMAC_INT_TC2_RAW 0x608 ++#define EDMAC_INT_ERR1_RAW 0x610 ++#define EDMAC_INT_ERR2_RAW 0x618 ++#define EDMAC_INT_ERR3_RAW 0x620 ++ ++#define edmac_cx_curr_cnt0(cn) (0x404 + (cn) * 0x20) ++#define edmac_cx_curr_src_addr_l(cn) (0x408 + (cn) * 0x20) ++#define edmac_cx_curr_src_addr_h(cn) (0x40c + (cn) * 0x20) ++#define edmac_cx_curr_dest_addr_l(cn) (0x410 + (cn) * 0x20) ++#define edmac_cx_curr_dest_addr_h(cn) (0x414 + (cn) * 0x20) ++ ++#define EDMAC_CH_PRI 0x688 ++#define EDMAC_CH_STAT 0x690 ++#define EDMAC_DMA_CTRL 0x698 ++ ++#define edmac_cx_base(cn) (0x800 + (cn) * 0x40) ++#define edmac_cx_lli_l(cn) (0x800 + (cn) * 0x40) ++#define edmac_cx_lli_h(cn) (0x804 + (cn) * 0x40) ++#define edmac_cx_cnt0(cn) (0x81c + (cn) * 0x40) ++#define edmac_cx_src_addr_l(cn) (0x820 + (cn) * 0x40) ++#define edmac_cx_src_addr_h(cn) (0x824 + (cn) * 0x40) ++#define edmac_cx_dest_addr_l(cn) (0x828 + (cn) * 0x40) ++#define edmac_cx_dest_addr_h(cn) (0x82c + (cn) * 0x40) ++#define edmac_cx_config(cn) (0x830 + (cn) * 0x40) ++ ++#define EDMAC_ALL_CHAN_CLR 0xff ++#define EDMAC_INT_ENABLE_ALL_CHAN 0xff ++ ++ ++#define EDMAC_CONFIG_SRC_INC (1 << 31) ++#define EDMAC_CONFIG_DST_INC (1 << 30) ++ ++#define EDMAC_CONFIG_SRC_WIDTH_SHIFT 16 ++#define EDMAC_CONFIG_DST_WIDTH_SHIFT 12 ++#define EDMAC_WIDTH_8BIT 0b0 ++#define EDMAC_WIDTH_16BIT 0b1 ++#define EDMAC_WIDTH_32BIT 0b10 ++#define EDMAC_WIDTH_64BIT 0b11 ++#ifdef CONFIG_64BIT ++#define EDMAC_MEM_BIT_WIDTH EDMAC_WIDTH_64BIT ++#else ++#define EDMAC_MEM_BIT_WIDTH EDMAC_WIDTH_32BIT ++#endif ++ ++#define EDMAC_MAX_BURST_WIDTH 16 ++#define EDMAC_MIN_BURST_WIDTH 1 ++#define EDMAC_CONFIG_SRC_BURST_SHIFT 24 ++#define EDMAC_CONFIG_DST_BURST_SHIFT 20 ++ ++#define EDMAC_LLI_ALIGN 0x40 ++#define EDMAC_LLI_DISABLE 0x0 ++#define EDMAC_LLI_ENABLE 0x2 ++ ++#define EDMAC_CXCONFIG_SIGNAL_SHIFT 0x4 ++#define EDMAC_CXCONFIG_MEM_TYPE 0x0 ++#define EDMAC_CXCONFIG_DEV_MEM_TYPE 0x1 ++#define EDMAC_CXCONFIG_TSF_TYPE_SHIFT 0x2 ++#define EDMAC_CXCONFIG_LLI_START 0x1 ++ ++#define EDMAC_CXCONFIG_ITC_EN 0x1 ++#define EDMAC_CXCONFIG_ITC_EN_SHIFT 0x1 ++ ++#define CCFG_EN 0x1 ++ ++#define EDMAC_CONTROL_SRC_WIDTH_MASK GENMASK(18, 16) ++#define EDMAC_CONTROL_DST_WIDTH_MASK GENMASK(14, 12) ++#endif +diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c +index f1b53dd1df1a..602c9c4eab41 100644 +--- a/drivers/gpio/gpio-pl061.c ++++ b/drivers/gpio/gpio-pl061.c +@@ -289,6 +289,9 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) + struct pl061 *pl061; + struct gpio_irq_chip *girq; + int ret, irq; ++#ifdef CONFIG_ARCH_BSP ++ int gpio_idx; ++#endif + + pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); + if (pl061 == NULL) +@@ -301,7 +304,19 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) + raw_spin_lock_init(&pl061->lock); + pl061->gc.request = gpiochip_generic_request; + pl061->gc.free = gpiochip_generic_free; ++#ifdef CONFIG_ARCH_BSP ++ if (dev->of_node) { ++ gpio_idx = of_alias_get_id(dev->of_node, "gpio"); ++ if (gpio_idx < 0) ++ return -ENOMEM; ++ pl061->gc.base = gpio_idx * PL061_GPIO_NR; ++ } ++ ++ if (pl061->gc.base < 0) ++ pl061->gc.base = -1; ++#else + pl061->gc.base = -1; ++#endif + pl061->gc.get_direction = pl061_get_direction; + pl061->gc.direction_input = pl061_direction_input; + pl061->gc.direction_output = pl061_direction_output; +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 5763a1e9360b..027957dc0a20 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -649,6 +649,16 @@ config I2C_GPIO_FAULT_INJECTOR + faults to an I2C bus, so another bus master can be stress-tested. + This is for debugging. If unsure, say 'no'. + ++config I2C_BSP ++ tristate "Vendor I2C Controller" ++ depends on ARCH_BSP ++ help ++ Say Y here to include support for Vendor I2C controller in the ++ Vendor SoCs. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-bsp. ++ + config I2C_HIGHLANDER + tristate "Highlander FPGA SMBus interface" + depends on SH_HIGHLANDER || COMPILE_TEST +@@ -1448,4 +1458,21 @@ config I2C_FSI + This driver can also be built as a module. If so, the module will be + called as i2c-fsi. + ++config DMA_MSG_MIN_LEN ++ int "Vendor I2C support DMA minimum LEN" ++ depends on I2C_BSP ++ range 1 4090 ++ default 5 ++ help ++ The i2c_msg minimum LEN of i2c support DMA,range from 1 to 4091 ++ ++config DMA_MSG_MAX_LEN ++ int "Vendor I2C support DMA maximum LEN" ++ depends on I2C_BSP ++ range DMA_MSG_MIN_LEN 4090 ++ default 4090 ++ help ++ The i2c_msg maximum LEN of i2c support DMA,range from i2c_msg minimum LEN to 4090, ++ because DMA for 0xFFC one-time largest data transfers; ++ + endmenu +diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile +index 280e05622d50..ca908fffc09b 100644 +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -67,6 +67,7 @@ obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o + obj-$(CONFIG_I2C_EMEV2) += i2c-emev2.o + obj-$(CONFIG_I2C_EXYNOS5) += i2c-exynos5.o + obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o ++obj-$(CONFIG_I2C_BSP) += i2c-bsp.o + obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o + obj-$(CONFIG_I2C_HISI) += i2c-hisi.o + obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o +diff --git a/drivers/i2c/busses/i2c-bsp.c b/drivers/i2c/busses/i2c-bsp.c +new file mode 100644 +index 000000000000..4147d18911ce +--- /dev/null ++++ b/drivers/i2c/busses/i2c-bsp.c +@@ -0,0 +1,1534 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_EDMAC) ++#include ++#include ++ ++/* ++ * In the case of enable edmacv310_n, msg->buf must be continuous memory, for DMA processing. ++ * Mostly dma_xfer_* have to handle the uncontinuous memory. So i2c_bsp allocate ++ * continuous memory for msg->buf and use highmem_buf_list to manage msg->buf allocated by i2c_bsp. ++ */ ++struct highmem_buf_list_node { ++ __u8 *buf; ++ __u8 *highmem_buf; ++ struct i2c_msg *msg; ++ struct list_head node; ++}; ++ ++static LIST_HEAD(highmem_buf_list); ++ ++static struct highmem_buf_list_node *search_in_highmem_buf_list(struct i2c_msg *msg) ++{ ++ struct highmem_buf_list_node *highmem_buf_node = NULL; ++ struct highmem_buf_list_node *_highmem_buf_node = NULL; ++ ++ list_for_each_entry_safe(highmem_buf_node, _highmem_buf_node, &highmem_buf_list, node) { ++ if (highmem_buf_node->msg == msg) { ++ return highmem_buf_node; ++ } ++ } ++ return NULL; ++} ++#endif ++ ++#ifdef DEBUG_BSP_I2C ++#define debug_dump_i2c_msg(msg) \ ++ do { \ ++ printk("%s::%d\n", __FILE__, __LINE__); \ ++ dump_i2c_msg(msg); \ ++ } while(0) ++ ++static void dump_i2c_msg(struct i2c_msg *msg) ++{ ++ int i = 0; ++ printk("msg->addr: %u\n", (unsigned int)msg->addr); ++ printk("msg->flags:%u\n", (unsigned int)msg->flags); ++ printk("msg->len: %u\n", (unsigned int)msg->len); ++ for (; i < msg->len; i++) { ++ printk("%d %x\n", i, msg->buf[i]); ++ } ++} ++#else ++#define debug_dump_i2c_msg(msg) ++#endif ++ ++/* ++ * I2C Registers offsets ++ */ ++#define BSP_I2C_GLB 0x0 ++#define BSP_I2C_SCL_H 0x4 ++#define BSP_I2C_SCL_L 0x8 ++#define BSP_I2C_DATA1 0x10 ++#define BSP_I2C_TXF 0x20 ++#define BSP_I2C_RXF 0x24 ++#define BSP_I2C_CMD_BASE 0x30 ++#define BSP_I2C_LOOP1 0xb0 ++#define BSP_I2C_DST1 0xb4 ++#define BSP_I2C_LOOP2 0xb8 ++#define BSP_I2C_DST2 0xbc ++#define BSP_I2C_TX_WATER 0xc8 ++#define BSP_I2C_RX_WATER 0xcc ++#define BSP_I2C_CTRL1 0xd0 ++#define BSP_I2C_CTRL2 0xd4 ++#define BSP_I2C_STAT 0xd8 ++#define BSP_I2C_INTR_RAW 0xe0 ++#define BSP_I2C_INTR_EN 0xe4 ++#define BSP_I2C_INTR_STAT 0xe8 ++ ++/* ++ * I2C Global Config Register -- BSP_I2C_GLB ++ */ ++#define GLB_EN_MASK BIT(0) ++#define GLB_SDA_HOLD_MASK GENMASK(23, 8) ++#define GLB_SDA_HOLD_SHIFT (8) ++#define should_copy_to_continuous_mem(addr) true ++ ++/* ++ * I2C Timing CMD Register -- BSP_I2C_CMD_BASE + n * 4 (n = 0, 1, 2, ... 31) ++ */ ++#define CMD_EXIT 0x0 ++#define CMD_TX_S 0x1 ++#define CMD_TX_D1_2 0x4 ++#define CMD_TX_D1_1 0x5 ++#define CMD_TX_FIFO 0x9 ++#define CMD_RX_FIFO 0x12 ++#define CMD_RX_ACK 0x13 ++#define CMD_IGN_ACK 0x15 ++#define CMD_TX_ACK 0x16 ++#define CMD_TX_NACK 0x17 ++#define CMD_JMP1 0x18 ++#define CMD_JMP2 0x19 ++#define CMD_UP_TXF 0x1d ++#define CMD_TX_RS 0x1e ++#define CMD_TX_P 0x1f ++ ++/* ++ * I2C Control Register 1 -- BSP_I2C_CTRL1 ++ */ ++#define CTRL1_CMD_START_MASK BIT(0) ++#define CTRL1_DMA_OP_MASK (0x3 << 8) ++#define CTRL1_DMA_R (0x3 << 8) ++#define CTRL1_DMA_W (0x2 << 8) ++ ++/* ++ * I2C Status Register -- BSP_I2C_STAT ++ */ ++#define STAT_RXF_NOE_MASK BIT(16) /* RX FIFO not empty flag */ ++#define STAT_TXF_NOF_MASK BIT(19) /* TX FIFO not full flag */ ++ ++/* ++ * I2C Interrupt status and mask Register -- ++ * BSP_I2C_INTR_RAW, BSP_I2C_STAT, BSP_I2C_INTR_STAT ++ */ ++#define INTR_ABORT_MASK (BIT(0) | BIT(11)) ++#define INTR_RX_MASK BIT(2) ++#define INTR_TX_MASK BIT(4) ++#define INTR_CMD_DONE_MASK BIT(12) ++#define INTR_USE_MASK (INTR_ABORT_MASK \ ++ |INTR_RX_MASK \ ++ | INTR_TX_MASK \ ++ | INTR_CMD_DONE_MASK) ++#define INTR_ALL_MASK GENMASK(31, 0) ++ ++#define I2C_DEFAULT_FREQUENCY 100000 ++#define I2C_TXF_DEPTH 64 ++#define I2C_RXF_DEPTH 64 ++#define I2C_TXF_WATER 32 ++#define I2C_RXF_WATER 32 ++#define I2C_WAIT_TIMEOUT 0x400 ++#define I2C_IRQ_TIMEOUT (msecs_to_jiffies(1000)) ++ ++struct bsp_i2c_dev { ++ struct device *dev; ++ struct i2c_adapter adap; ++ resource_size_t phybase; ++ void __iomem *base; ++ struct clk *clk; ++ int irq; ++ ++ unsigned int freq; ++ struct i2c_msg *msg; ++ unsigned int msg_num; ++ unsigned int msg_idx; ++ unsigned int msg_buf_ptr; ++ struct completion msg_complete; ++ ++ spinlock_t lock; ++ int status; ++}; ++static inline void bsp_i2c_disable(const struct bsp_i2c_dev *i2c); ++static inline void bsp_i2c_cfg_irq(const struct bsp_i2c_dev *i2c, ++ unsigned int flag); ++static inline unsigned int bsp_i2c_clr_irq(const struct bsp_i2c_dev *i2c); ++static inline void bsp_i2c_enable(const struct bsp_i2c_dev *i2c); ++ ++#define CHECK_SDA_IN_SHIFT (16) ++#define GPIO_MODE_SHIFT (8) ++#define FORCE_SCL_OEN_SHIFT (4) ++#define FORCE_SDA_OEN_SHIFT (0) ++ ++static void bsp_i2c_rescue(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int val; ++ unsigned int time_cnt; ++ int index; ++ ++ bsp_i2c_disable(i2c); ++ bsp_i2c_cfg_irq(i2c, 0); ++ bsp_i2c_clr_irq(i2c); ++ ++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | ++ (0x1 << FORCE_SDA_OEN_SHIFT); ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++ ++ time_cnt = 0; ++ do { ++ for (index = 0; index < 9; index++) { /* Cycle ten times */ ++ val = (0x1 << GPIO_MODE_SHIFT) | 0x1; ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++ ++ udelay(5); /* delay 5 us */ ++ ++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | ++ (0x1 << FORCE_SDA_OEN_SHIFT); ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++ ++ udelay(5); /* delay 5 us */ ++ } ++ ++ time_cnt++; ++ if (time_cnt > I2C_WAIT_TIMEOUT) { ++ dev_err(i2c->dev, "wait Timeout!\n"); ++ goto disable_rescue; ++ } ++ ++ val = readl(i2c->base + BSP_I2C_CTRL2); ++ } while (!(val & (0x1 << CHECK_SDA_IN_SHIFT))); ++ ++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | ++ (0x1 << FORCE_SDA_OEN_SHIFT); ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++ ++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT); ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++ ++ udelay(10); /* delay 10 us */ ++ ++ val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) | ++ (0x1 << FORCE_SDA_OEN_SHIFT); ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++ ++disable_rescue: ++ val = (0x1 << FORCE_SCL_OEN_SHIFT) | 0x1; ++ writel(val, i2c->base + BSP_I2C_CTRL2); ++} ++ ++static inline void bsp_i2c_disable(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int val; ++ ++ val = readl(i2c->base + BSP_I2C_GLB); ++ val &= ~GLB_EN_MASK; ++ writel(val, i2c->base + BSP_I2C_GLB); ++} ++ ++static inline void bsp_i2c_enable(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int val; ++ ++ val = readl(i2c->base + BSP_I2C_GLB); ++ val |= GLB_EN_MASK; ++ writel(val, i2c->base + BSP_I2C_GLB); ++} ++ ++static inline void bsp_i2c_cfg_irq(const struct bsp_i2c_dev *i2c, ++ unsigned int flag) ++{ ++ writel(flag, i2c->base + BSP_I2C_INTR_EN); ++} ++ ++static void bsp_i2c_disable_irq(const struct bsp_i2c_dev *i2c, ++ unsigned int flag) ++{ ++ unsigned int val; ++ ++ val = readl(i2c->base + BSP_I2C_INTR_EN); ++ val &= ~flag; ++ writel(val, i2c->base + BSP_I2C_INTR_EN); ++} ++ ++static unsigned int bsp_i2c_clr_irq(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int val; ++ ++ val = readl(i2c->base + BSP_I2C_INTR_STAT); ++ writel(INTR_ALL_MASK, i2c->base + BSP_I2C_INTR_RAW); ++ ++ return val; ++} ++ ++static inline void bsp_i2c_cmdreg_set(const struct bsp_i2c_dev *i2c, ++ unsigned int cmd, unsigned int *offset) ++{ ++ dev_dbg(i2c->dev, "i2c reg: offset=0x%x, cmd=0x%x...\n", *offset * 4, cmd); ++ /* Register bit width */ ++ writel(cmd, i2c->base + BSP_I2C_CMD_BASE + *offset * 4); ++ (*offset)++; ++} ++ ++/* ++ * config i2c slave addr ++ */ ++static void bsp_i2c_set_addr(const struct bsp_i2c_dev *i2c) ++{ ++ struct i2c_msg *msg = i2c->msg; ++ u16 addr; ++ ++ if (msg->flags & I2C_M_TEN) { ++ /* First byte is 11110XX0 where XX is upper 2 bits */ ++ addr = ((msg->addr & 0x300) << 1) | 0xf000; ++ if (msg->flags & I2C_M_RD) ++ addr |= 1 << 8; /* Shift the read flag to the left by eight bits */ ++ ++ /* Second byte is the remaining 8 bits */ ++ addr |= msg->addr & 0xff; ++ } else { ++ addr = (msg->addr & 0x7f) << 1; ++ if (msg->flags & I2C_M_RD) ++ addr |= 1; ++ } ++ ++ writel(addr, i2c->base + BSP_I2C_DATA1); ++} ++ ++/* ++ * Start command sequence ++ */ ++static inline void bsp_i2c_start_cmd(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int val; ++ ++ val = readl(i2c->base + BSP_I2C_CTRL1); ++ val |= CTRL1_CMD_START_MASK; ++ writel(val, i2c->base + BSP_I2C_CTRL1); ++} ++ ++static int bsp_i2c_wait_rx_noempty(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int time_cnt = 0; ++ unsigned int val; ++ ++ do { ++ val = readl(i2c->base + BSP_I2C_STAT); ++ if (val & STAT_RXF_NOE_MASK) ++ return 0; ++ ++ udelay(50); /* delay 50 us */ ++ } while (time_cnt++ < I2C_WAIT_TIMEOUT); ++ ++ bsp_i2c_rescue(i2c); ++ ++ dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n", ++ readl(i2c->base + BSP_I2C_INTR_RAW), val); ++ return -EIO; ++} ++ ++static int bsp_i2c_wait_tx_nofull(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int time_cnt = 0; ++ unsigned int val; ++ ++ do { ++ val = readl(i2c->base + BSP_I2C_STAT); ++ if (val & STAT_TXF_NOF_MASK) ++ return 0; ++ ++ udelay(50); /* delay 50 us */ ++ } while (time_cnt++ < I2C_WAIT_TIMEOUT); ++ ++ bsp_i2c_rescue(i2c); ++ ++ dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n", ++ readl(i2c->base + BSP_I2C_INTR_RAW), val); ++ return -EIO; ++} ++ ++static int bsp_i2c_wait_idle(const struct bsp_i2c_dev *i2c) ++{ ++ unsigned int time_cnt = 0; ++ unsigned int val; ++ ++ do { ++ val = readl(i2c->base + BSP_I2C_INTR_RAW); ++ if (val & (INTR_ABORT_MASK)) { ++ dev_err(i2c->dev, "wait idle abort!, RIS: 0x%x\n", ++ val); ++ return -EIO; ++ } ++ ++ if (val & INTR_CMD_DONE_MASK) ++ return 0; ++ ++ udelay(50); /* delay 50 us */ ++ } while (time_cnt++ < I2C_WAIT_TIMEOUT); ++ ++ bsp_i2c_rescue(i2c); ++ ++ dev_err(i2c->dev, "wait idle timeout, RIS: 0x%x, SR: 0x%x\n", ++ val, readl(i2c->base + BSP_I2C_STAT)); ++ ++ return -EIO; ++} ++ ++static void bsp_i2c_set_freq(struct bsp_i2c_dev *i2c) ++{ ++ unsigned int max_freq, freq; ++ unsigned int clk_rate; ++ unsigned int val; ++ ++ freq = i2c->freq; ++ clk_rate = clk_get_rate(i2c->clk); ++ max_freq = clk_rate >> 1; ++ ++ if (freq > max_freq) { ++ i2c->freq = max_freq; ++ freq = i2c->freq; ++ } ++ ++ if (!freq) { ++ pr_err("bsp_i2c_set_freq:freq can't be zero!"); ++ return; ++ } ++ /* If the frequency band is less than or equal to 100 MHz, the standard mode is used */ ++ if (freq <= 100000) { ++ /* in normal mode F_scl: freq ++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5 ++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.5 ++ */ ++ val = clk_rate / (freq * 2); ++ writel(val, i2c->base + BSP_I2C_SCL_H); ++ writel(val, i2c->base + BSP_I2C_SCL_L); ++ } else { ++ /* in fast mode F_scl: freq ++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.36 ++ i2c_scl_hcnt = (F_i2c / F_scl) * 0.64 ++ */ ++ val = ((clk_rate / 100) * 36) / freq; ++ writel(val, i2c->base + BSP_I2C_SCL_H); ++ val = ((clk_rate / 100) * 64) / freq; ++ writel(val, i2c->base + BSP_I2C_SCL_L); ++ } ++ ++ val = readl(i2c->base + BSP_I2C_GLB); ++ val &= ~GLB_SDA_HOLD_MASK; ++ val |= ((0xa << GLB_SDA_HOLD_SHIFT) & GLB_SDA_HOLD_MASK); ++ writel(val, i2c->base + BSP_I2C_GLB); ++} ++ ++/* ++ * set i2c controller TX and RX FIFO water ++ */ ++static inline void bsp_i2c_set_water(const struct bsp_i2c_dev *i2c) ++{ ++ writel(I2C_TXF_WATER, i2c->base + BSP_I2C_TX_WATER); ++ writel(I2C_RXF_WATER, i2c->base + BSP_I2C_RX_WATER); ++} ++ ++/* ++ * initialise the controller, set i2c bus interface freq ++ */ ++static void bsp_i2c_hw_init(struct bsp_i2c_dev *i2c) ++{ ++ bsp_i2c_disable(i2c); ++ bsp_i2c_disable_irq(i2c, INTR_ALL_MASK); ++ bsp_i2c_set_freq(i2c); ++ bsp_i2c_set_water(i2c); ++} ++ ++/* ++ * bsp_i2c_cfg_cmd - config i2c controller command sequence ++ * ++ * After all the timing command is configured, ++ * and then start the command, you can i2c communication, ++ * and then only need to read and write i2c fifo. ++ */ ++static void bsp_i2c_cfg_cmd(const struct bsp_i2c_dev *i2c) ++{ ++ struct i2c_msg *msg = i2c->msg; ++ int offset = 0; ++ ++ if (i2c->msg_idx == 0) ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_S, &offset); ++ else ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_RS, &offset); ++ ++ if (msg->flags & I2C_M_TEN) { ++ if (i2c->msg_idx == 0) { ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset); ++ } else { ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset); ++ } ++ } else { ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset); ++ } ++ ++ if (msg->flags & I2C_M_IGNORE_NAK) ++ bsp_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset); ++ else ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset); ++ ++ if (msg->flags & I2C_M_RD) { ++ /* The extended address occupies two bytes */ ++ if (msg->len >= 2) { ++ writel(offset, i2c->base + BSP_I2C_DST1); ++ /* The extended address occupies two bytes */ ++ writel(msg->len - 2, i2c->base + BSP_I2C_LOOP1); ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_ACK, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_JMP1, &offset); ++ } ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_NACK, &offset); ++ } else { ++ writel(offset, i2c->base + BSP_I2C_DST1); ++ writel(msg->len - 1, i2c->base + BSP_I2C_LOOP1); ++ bsp_i2c_cmdreg_set(i2c, CMD_UP_TXF, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_FIFO, &offset); ++ ++ if (msg->flags & I2C_M_IGNORE_NAK) ++ bsp_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset); ++ else ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset); ++ ++ bsp_i2c_cmdreg_set(i2c, CMD_JMP1, &offset); ++ } ++ ++ if ((i2c->msg_idx == (i2c->msg_num - 1)) || (msg->flags & I2C_M_STOP)) { ++ dev_dbg(i2c->dev, "run to %s %d...TX STOP\n", ++ __func__, __LINE__); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_P, &offset); ++ } ++ ++ bsp_i2c_cmdreg_set(i2c, CMD_EXIT, &offset); ++} ++ ++static void bsp_i2c_cfg_cmd_mul_reg(struct bsp_i2c_dev *i2c,unsigned int reg_data_width) ++{ ++ struct i2c_msg *msg = i2c->msg; ++ int offset = 0; ++ int i; ++ ++ if (i2c->msg_idx == 0) ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_S, &offset); ++ else ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_RS, &offset); ++ ++ if (msg->flags & I2C_M_TEN) { ++ if (i2c->msg_idx == 0) { ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset); ++ } else { ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_2, &offset); ++ } ++ } else { ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_D1_1, &offset); ++ } ++ ++ if (msg->flags & I2C_M_IGNORE_NAK) ++ bsp_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset); ++ else ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset); ++ ++ if (msg->flags & I2C_M_RD) { ++ /* The extended address occupies two bytes */ ++ if (msg->len >= 2) { ++ writel(offset, i2c->base + BSP_I2C_DST1); ++ /* The extended address occupies two bytes */ ++ writel(msg->len - 2, i2c->base + BSP_I2C_LOOP1); ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_ACK, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_JMP1, &offset); ++ } ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_FIFO, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_NACK, &offset); ++ } else { ++ for(i = 0; i < reg_data_width - 1; i++){ ++ bsp_i2c_cmdreg_set(i2c, CMD_UP_TXF, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_FIFO, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_RX_ACK, &offset); ++ } ++ bsp_i2c_cmdreg_set(i2c, CMD_UP_TXF, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_FIFO, &offset); ++ bsp_i2c_cmdreg_set(i2c, CMD_IGN_ACK, &offset); ++ } ++ ++ bsp_i2c_cmdreg_set(i2c, CMD_TX_P, &offset); ++ if(((msg->len / reg_data_width) - 1) > 0){ ++ writel(0, i2c->base + BSP_I2C_DST2); ++ writel((msg->len / reg_data_width) - 1, i2c->base + BSP_I2C_LOOP2); ++ bsp_i2c_cmdreg_set(i2c, CMD_JMP2, &offset); ++ } ++ bsp_i2c_cmdreg_set(i2c, CMD_EXIT, &offset); ++} ++ ++static inline void check_i2c_send_complete(struct bsp_i2c_dev *i2c) ++{ ++ unsigned int val; ++ val = readl(i2c->base + BSP_I2C_GLB); ++ if(val & GLB_EN_MASK){ ++ bsp_i2c_wait_idle(i2c); ++ bsp_i2c_disable(i2c); ++ } ++} ++ ++#if defined(CONFIG_EDMAC) ++int dma_to_i2c(unsigned long src, unsigned int dst, unsigned int length) ++{ ++ int chan; ++ ++ chan = do_dma_m2p(src, dst, length); ++ if (chan == -1) ++ pr_err("dma_to_i2c error\n"); ++ ++ return chan; ++} ++ ++int i2c_to_dma(unsigned int src, unsigned long dst, ++ unsigned int length) ++{ ++ int chan; ++ ++ chan = do_dma_p2m(dst, src, length); ++ if (chan == -1) ++ pr_err("dma_p2m error...\n"); ++ ++ return chan; ++} ++ ++static int bsp_i2c_do_dma_write(struct bsp_i2c_dev *i2c, ++ unsigned long dma_dst_addr) ++{ ++ int chan, val; ++ int status = 0; ++ struct i2c_msg *msg = i2c->msg; ++ ++ check_i2c_send_complete(i2c); ++ bsp_i2c_set_freq(i2c); ++ writel(0x1, i2c->base + BSP_I2C_TX_WATER); ++ bsp_i2c_enable(i2c); ++ bsp_i2c_clr_irq(i2c); ++ bsp_i2c_set_addr(i2c); ++ bsp_i2c_cfg_cmd(i2c); ++ ++ /* transmit DATA from DMAC to I2C in DMA mode */ ++ chan = dma_to_i2c(dma_dst_addr, (i2c->phybase + BSP_I2C_TXF), ++ msg->len); ++ if (chan == -1) { ++ status = -1; ++ goto fail_0; ++ } ++ ++ val = readl(i2c->base + BSP_I2C_CTRL1); ++ val &= ~CTRL1_DMA_OP_MASK; ++ val |= CTRL1_DMA_W | CTRL1_CMD_START_MASK; ++ writel(val, i2c->base + BSP_I2C_CTRL1); ++ ++ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) { ++ status = -1; ++ goto fail_1; ++ } ++ ++ status = bsp_i2c_wait_idle(i2c); ++ ++fail_1: ++ dmac_channel_free((unsigned int)chan); ++fail_0: ++ bsp_i2c_disable(i2c); ++ ++ return status; ++} ++ ++static int bsp_i2c_do_dma_write_mul_reg(struct bsp_i2c_dev *i2c, ++ unsigned long dma_dst_addr, unsigned int reg_data_width) ++{ ++ int chan; ++ int val = 0; ++ struct i2c_msg *msg = i2c->msg; ++ ++ check_i2c_send_complete(i2c); ++ bsp_i2c_set_freq(i2c); ++ writel(0x1, i2c->base + BSP_I2C_TX_WATER); ++ bsp_i2c_enable(i2c); ++ bsp_i2c_clr_irq(i2c); ++ bsp_i2c_set_addr(i2c); ++ bsp_i2c_cfg_cmd_mul_reg(i2c, reg_data_width); ++ ++ /* transmit DATA from DMAC to I2C in DMA mode */ ++ chan = dma_to_i2c(dma_dst_addr, (i2c->phybase + BSP_I2C_TXF), ++ msg->len); ++ if (chan == -1) ++ return -1; ++ ++ val = readl(i2c->base + BSP_I2C_CTRL1); ++ val &= ~CTRL1_DMA_OP_MASK; ++ val |= CTRL1_DMA_W | CTRL1_CMD_START_MASK; ++ writel(val, i2c->base + BSP_I2C_CTRL1); ++ ++ return 0; ++} ++ ++static int bsp_i2c_do_dma_read(struct bsp_i2c_dev *i2c, ++ unsigned long dma_dst_addr) ++{ ++ int val, chan; ++ int status = 0; ++ struct i2c_msg *msg = i2c->msg; ++ ++ check_i2c_send_complete(i2c); ++ bsp_i2c_set_freq(i2c); ++ writel(0x0, i2c->base + BSP_I2C_RX_WATER); ++ bsp_i2c_enable(i2c); ++ bsp_i2c_clr_irq(i2c); ++ bsp_i2c_set_addr(i2c); ++ bsp_i2c_cfg_cmd(i2c); ++ ++ /* transmit DATA from I2C to DMAC in DMA mode */ ++ chan = i2c_to_dma((i2c->phybase + BSP_I2C_RXF), ++ dma_dst_addr, msg->len); ++ if (chan == -1) { ++ status = -1; ++ goto fail_0; ++ } ++ ++ val = readl(i2c->base + BSP_I2C_CTRL1); ++ val &= ~CTRL1_DMA_OP_MASK; ++ val |= CTRL1_CMD_START_MASK | CTRL1_DMA_R; ++ writel(val, i2c->base + BSP_I2C_CTRL1); ++ ++ if (dmac_wait(chan) != DMAC_CHN_SUCCESS) { ++ status = -1; ++ goto fail_1; ++ } ++ ++ status = bsp_i2c_wait_idle(i2c); ++ ++fail_1: ++ dmac_channel_free((unsigned int)chan); ++fail_0: ++ bsp_i2c_disable(i2c); ++ ++ return status; ++} ++ ++/* ++ * Before the DMA transfer, the buffer allocated in high memory is copied to contiguous memory allocated ++ * by i2c_bsp and managed by the highmem_buf_list. ++ */ ++static int copy_to_continuous_mem(struct bsp_i2c_dev *i2c) ++{ ++ int ret; ++ ++ struct highmem_buf_list_node *highmem_node = NULL; ++ if (should_copy_to_continuous_mem(i2c->msg->buf) && search_in_highmem_buf_list(i2c->msg) == NULL) { ++ highmem_node = (struct highmem_buf_list_node *)kzalloc(sizeof(*highmem_node), GFP_KERNEL | __GFP_ATOMIC); ++ if (highmem_node == NULL) { ++ dev_err(i2c->dev, "Allocate memory fail.\n"); ++ return -EINVAL; ++ } ++ ++ highmem_node->msg = i2c->msg; ++ highmem_node->highmem_buf = i2c->msg->buf; ++ i2c->msg->buf = kmalloc(i2c->msg->len, GFP_KERNEL | __GFP_ATOMIC); ++ highmem_node->buf = i2c->msg->buf; ++ ret = memcpy_s(highmem_node->buf, i2c->msg->len, ++ highmem_node->highmem_buf, i2c->msg->len); ++ if (ret) { ++ dev_err(i2c->dev, "%s, memcpy_s failed!\n", __func__); ++ return ret; ++ } ++ ++ if (i2c->msg->buf == NULL) { ++ i2c->msg->buf = highmem_node->highmem_buf; ++ kfree(highmem_node); ++ dev_err(i2c->dev, "Allocate continuous memory fail.\n"); ++ return -EINVAL; ++ } ++ ++ list_add_tail(&highmem_node->node, &highmem_buf_list); ++ } ++ return 0; ++} ++ ++/* ++ * When the DMA transfer ends, the high memory buf is returned to the ++ * i2c->msg so that the user mode can read and release the buffer, ++ * and the contiguous memory allocated by i2c_bsp will be released. ++ */ ++static void released_contiguous_buf_from_list(struct i2c_msg *msg) ++{ ++ struct highmem_buf_list_node *highmem_node = NULL; ++ int ret; ++ ++ debug_dump_i2c_msg(msg); ++ highmem_node = search_in_highmem_buf_list(msg); ++ if (highmem_node != NULL) { ++ ret = memcpy_s(highmem_node->highmem_buf, msg->len, ++ highmem_node->buf, msg->len); ++ if (ret) { ++ printk("%s, memcpy_s failed\n", __func__); ++ return; ++ } ++ ++ list_del(&highmem_node->node); ++ kfree(highmem_node->buf); ++ msg->buf = highmem_node->highmem_buf; ++ kfree(highmem_node); ++ } ++ ++ debug_dump_i2c_msg(msg); ++} ++ ++static int bsp_i2c_dma_xfer_one_msg(struct bsp_i2c_dev *i2c) ++{ ++ unsigned int status; ++ struct i2c_msg *msg = i2c->msg; ++ dma_addr_t dma_dst_addr; ++ ++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n", ++ __func__, __LINE__, msg->flags, msg->len); ++ ++ debug_dump_i2c_msg(msg); ++ if (copy_to_continuous_mem(i2c)) ++ return -EINVAL; ++ ++ debug_dump_i2c_msg(msg); ++ if (msg->flags & I2C_M_RD) { ++ mb(); ++ dma_dst_addr = dma_map_single(i2c->dev, msg->buf, ++ msg->len, DMA_FROM_DEVICE); ++ status = dma_mapping_error(i2c->dev, dma_dst_addr); ++ if (status) { ++ dev_err(i2c->dev, "DMA mapping failed\n"); ++ goto out; ++ } ++ ++ status = bsp_i2c_do_dma_read(i2c, dma_dst_addr); ++ ++ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_FROM_DEVICE); ++ mb(); ++ } else { ++ mb(); ++ dma_dst_addr = dma_map_single(i2c->dev, msg->buf, ++ msg->len, DMA_TO_DEVICE); ++ status = dma_mapping_error(i2c->dev, dma_dst_addr); ++ if (status) { ++ dev_err(i2c->dev, "DMA mapping failed\n"); ++ goto out; ++ } ++ ++ status = bsp_i2c_do_dma_write(i2c, dma_dst_addr); ++ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_TO_DEVICE); ++ mb(); ++ } ++ ++out: ++ released_contiguous_buf_from_list(i2c->msg); ++ if (!status) { ++ status = bsp_i2c_wait_idle(i2c); ++ bsp_i2c_disable(i2c); ++ } ++ ++ return status; ++} ++ ++static int bsp_i2c_dma_xfer_one_msg_mul_reg(struct bsp_i2c_dev *i2c, ++ unsigned int reg_data_width) ++{ ++ unsigned int status; ++ struct i2c_msg *msg = i2c->msg; ++ dma_addr_t dma_dst_addr; ++ ++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n", ++ __func__, __LINE__, msg->flags, msg->len); ++ ++ if (copy_to_continuous_mem(i2c)) ++ return -EINVAL; ++ ++ if (msg->flags & I2C_M_RD) { ++ debug_dump_i2c_msg(i2c->msg); ++ mb(); ++ dma_dst_addr = dma_map_single(i2c->dev, msg->buf, ++ msg->len, DMA_FROM_DEVICE); ++ status = dma_mapping_error(i2c->dev, dma_dst_addr); ++ if (status) { ++ dev_err(i2c->dev, "DMA mapping failed\n"); ++ goto out; ++ } ++ ++ status = bsp_i2c_do_dma_read(i2c, dma_dst_addr); ++ ++ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_FROM_DEVICE); ++ mb(); ++ } else { ++ mb(); ++ dma_dst_addr = dma_map_single(i2c->dev, msg->buf, ++ msg->len, DMA_TO_DEVICE); ++ status = dma_mapping_error(i2c->dev, dma_dst_addr); ++ if (status) { ++ dev_err(i2c->dev, "DMA mapping failed\n"); ++ goto out; ++ } ++ ++ status = bsp_i2c_do_dma_write_mul_reg(i2c, dma_dst_addr, reg_data_width); ++ dma_unmap_single(i2c->dev, dma_dst_addr, msg->len, DMA_TO_DEVICE); ++ mb(); ++ debug_dump_i2c_msg(i2c->msg); ++ } ++ ++out: ++ released_contiguous_buf_from_list(i2c->msg); ++ return status; ++} ++#endif ++static int bsp_i2c_polling_xfer_one_msg(struct bsp_i2c_dev *i2c) ++{ ++ int status; ++ unsigned int val; ++ struct i2c_msg *msg = i2c->msg; ++ ++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n", ++ __func__, __LINE__, msg->flags, msg->len); ++ ++ check_i2c_send_complete(i2c); ++ bsp_i2c_enable(i2c); ++ bsp_i2c_clr_irq(i2c); ++ bsp_i2c_set_addr(i2c); ++ bsp_i2c_cfg_cmd(i2c); ++ bsp_i2c_start_cmd(i2c); ++ ++ i2c->msg_buf_ptr = 0; ++ ++ if (msg->flags & I2C_M_RD) { ++ while (i2c->msg_buf_ptr < msg->len) { ++ status = bsp_i2c_wait_rx_noempty(i2c); ++ if (status) ++ goto end; ++ ++ val = readl(i2c->base + BSP_I2C_RXF); ++ msg->buf[i2c->msg_buf_ptr] = val; ++ i2c->msg_buf_ptr++; ++ } ++ } else { ++ while (i2c->msg_buf_ptr < msg->len) { ++ status = bsp_i2c_wait_tx_nofull(i2c); ++ if (status) ++ goto end; ++ ++ val = msg->buf[i2c->msg_buf_ptr]; ++ writel(val, i2c->base + BSP_I2C_TXF); ++ i2c->msg_buf_ptr++; ++ } ++ } ++ ++ status = bsp_i2c_wait_idle(i2c); ++end: ++ bsp_i2c_disable(i2c); ++ ++ return status; ++} ++ ++static int bsp_i2c_polling_xfer_one_msg_mul_reg(struct bsp_i2c_dev *i2c, ++ unsigned int reg_data_width) ++{ ++ int status; ++ unsigned int val; ++ struct i2c_msg *msg = i2c->msg; ++ ++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n", ++ __func__, __LINE__, msg->flags, msg->len); ++ ++ check_i2c_send_complete(i2c); ++ bsp_i2c_enable(i2c); ++ bsp_i2c_clr_irq(i2c); ++ bsp_i2c_set_addr(i2c); ++ bsp_i2c_cfg_cmd_mul_reg(i2c, reg_data_width); ++ bsp_i2c_start_cmd(i2c); ++ ++ i2c->msg_buf_ptr = 0; ++ ++ if (msg->flags & I2C_M_RD) { ++ while (i2c->msg_buf_ptr < msg->len) { ++ status = bsp_i2c_wait_rx_noempty(i2c); ++ if (status) ++ goto end; ++ ++ val = readl(i2c->base + BSP_I2C_RXF); ++ msg->buf[i2c->msg_buf_ptr] = val; ++ i2c->msg_buf_ptr++; ++ ++ } ++ } else { ++ while (i2c->msg_buf_ptr < msg->len) { ++ status = bsp_i2c_wait_tx_nofull(i2c); ++ if (status) ++ goto end; ++ ++ val = msg->buf[i2c->msg_buf_ptr]; ++ writel(val, i2c->base + BSP_I2C_TXF); ++ i2c->msg_buf_ptr++; ++ } ++ } ++ ++end: ++ return status; ++} ++ ++static irqreturn_t bsp_i2c_isr(int irq, void *dev_id) ++{ ++ struct bsp_i2c_dev *i2c = dev_id; ++ unsigned int irq_status; ++ struct i2c_msg *msg = i2c->msg; ++ ++ spin_lock(&i2c->lock); ++ ++ irq_status = bsp_i2c_clr_irq(i2c); ++ dev_dbg(i2c->dev, "%s RIS: 0x%x\n", __func__, irq_status); ++ ++ if (!irq_status) { ++ dev_dbg(i2c->dev, "no irq\n"); ++ goto end; ++ } ++ ++ if (irq_status & INTR_ABORT_MASK) { ++ dev_err(i2c->dev, "irq handle abort, RIS: 0x%x\n", ++ irq_status); ++ i2c->status = -EIO; ++ bsp_i2c_disable_irq(i2c, INTR_ALL_MASK); ++ ++ complete(&i2c->msg_complete); ++ goto end; ++ } ++ ++ if (msg->flags & I2C_M_RD) { ++ while ((readl(i2c->base + BSP_I2C_STAT) & STAT_RXF_NOE_MASK) ++ && (i2c->msg_buf_ptr < msg->len)) { ++ msg->buf[i2c->msg_buf_ptr] = ++ readl(i2c->base + BSP_I2C_RXF); ++ i2c->msg_buf_ptr++; ++ } ++ } else { ++ while ((readl(i2c->base + BSP_I2C_STAT) & STAT_TXF_NOF_MASK) ++ && (i2c->msg_buf_ptr < msg->len)) { ++ writel(msg->buf[i2c->msg_buf_ptr], ++ i2c->base + BSP_I2C_TXF); ++ i2c->msg_buf_ptr++; ++ } ++ } ++ ++ if (i2c->msg_buf_ptr >= msg->len) ++ bsp_i2c_disable_irq(i2c, INTR_TX_MASK | INTR_RX_MASK); ++ ++ if (irq_status & INTR_CMD_DONE_MASK) { ++ dev_dbg(i2c->dev, "cmd done\n"); ++ i2c->status = 0; ++ bsp_i2c_disable_irq(i2c, INTR_ALL_MASK); ++ ++ complete(&i2c->msg_complete); ++ } ++ ++end: ++ spin_unlock(&i2c->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bsp_i2c_interrupt_xfer_one_msg(struct bsp_i2c_dev *i2c) ++{ ++ int status; ++ struct i2c_msg *msg = i2c->msg; ++ unsigned long timeout; ++ unsigned long flags; ++ ++ dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n", ++ __func__, __LINE__, msg->flags, msg->len); ++ ++ reinit_completion(&i2c->msg_complete); ++ i2c->msg_buf_ptr = 0; ++ i2c->status = -EIO; ++ ++ spin_lock_irqsave(&i2c->lock, flags); ++ check_i2c_send_complete(i2c); ++ bsp_i2c_enable(i2c); ++ bsp_i2c_clr_irq(i2c); ++ if (msg->flags & I2C_M_RD) ++ bsp_i2c_cfg_irq(i2c, INTR_USE_MASK & ~INTR_TX_MASK); ++ else ++ bsp_i2c_cfg_irq(i2c, INTR_USE_MASK & ~INTR_RX_MASK); ++ ++ bsp_i2c_set_addr(i2c); ++ bsp_i2c_cfg_cmd(i2c); ++ bsp_i2c_start_cmd(i2c); ++ spin_unlock_irqrestore(&i2c->lock, flags); ++ ++ timeout = wait_for_completion_timeout(&i2c->msg_complete, ++ I2C_IRQ_TIMEOUT); ++ ++ spin_lock_irqsave(&i2c->lock, flags); ++ if (timeout == 0) { ++ bsp_i2c_disable_irq(i2c, INTR_ALL_MASK); ++ status = -EIO; ++ dev_err(i2c->dev, "%s timeout\n", ++ msg->flags & I2C_M_RD ? "rx" : "tx"); ++ } else { ++ status = i2c->status; ++ } ++ ++ bsp_i2c_disable(i2c); ++ ++ spin_unlock_irqrestore(&i2c->lock, flags); ++ return status; ++} ++ ++/* ++ * Master transfer function ++ */ ++static int bsp_i2c_xfer(struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct bsp_i2c_dev *i2c = i2c_get_adapdata(adap); ++ int status = -EINVAL; ++ unsigned long flags; ++ ++ if (msgs == NULL || (num <= 0)) { ++ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n"); ++ return -EINVAL; ++ } ++ ++ spin_lock_irqsave(&i2c->lock, flags); ++ ++ i2c->msg = msgs; ++ i2c->msg_num = num; ++ i2c->msg_idx = 0; ++ ++ while (i2c->msg_idx < i2c->msg_num) { ++#if defined(CONFIG_EDMAC) ++ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && ++ (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) { ++ status = bsp_i2c_dma_xfer_one_msg(i2c); ++ if (status) ++ break; ++ } else if (i2c->irq >= 0) { ++#else ++ if (i2c->irq >= 0) { ++#endif ++ spin_unlock_irqrestore(&i2c->lock, flags); ++ status = bsp_i2c_interrupt_xfer_one_msg(i2c); ++ spin_lock_irqsave(&i2c->lock, flags); ++ if (status) ++ break; ++ } else { ++ status = bsp_i2c_polling_xfer_one_msg(i2c); ++ if (status) ++ break; ++ } ++ i2c->msg++; ++ i2c->msg_idx++; ++ } ++ ++ if (!status || i2c->msg_idx > 0) ++ status = i2c->msg_idx; ++ ++ spin_unlock_irqrestore(&i2c->lock, flags); ++ return status; ++} ++ ++/* bsp_i2c_break_polling_xfer ++ * ++ * I2c polling independent branch, Shielding interrupt interface ++ */ ++static int bsp_i2c_break_polling_xfer(const struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct bsp_i2c_dev *i2c = i2c_get_adapdata(adap); ++ int status = -EINVAL; ++ unsigned long flags; ++ if (msgs == NULL || (num <= 0)) { ++ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n"); ++ return -EINVAL; ++ } ++ spin_lock_irqsave(&i2c->lock, flags); ++ i2c->msg = msgs; ++ i2c->msg_num = num; ++ i2c->msg_idx = 0; ++ while (i2c->msg_idx < i2c->msg_num) { ++#if defined(CONFIG_EDMAC) ++ debug_dump_i2c_msg(msgs); ++ ++ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && ++ (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN)) { ++ status = bsp_i2c_dma_xfer_one_msg(i2c); ++ if (status) ++ break; ++ } ++#else ++ status = bsp_i2c_polling_xfer_one_msg(i2c); ++ if (status) ++ break; ++#endif ++ i2c->msg++; ++ i2c->msg_idx++; ++ } ++ if (!status || i2c->msg_idx > 0) ++ status = i2c->msg_idx; ++ spin_unlock_irqrestore(&i2c->lock, flags); ++ return status; ++} ++ ++static int bsp_i2c_mul_reg_xfer(struct i2c_adapter* const adap, ++ struct i2c_msg *msgs, int num, unsigned int reg_data_width) ++{ ++ struct bsp_i2c_dev *i2c = i2c_get_adapdata(adap); ++ int status = -EINVAL; ++ unsigned long flags; ++ if (msgs == NULL || (num <= 0)) { ++ dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n"); ++ return -EINVAL; ++ } ++ spin_lock_irqsave(&i2c->lock, flags); ++ i2c->msg = msgs; ++ i2c->msg_num = num; ++ i2c->msg_idx = 0; ++ while (i2c->msg_idx < i2c->msg_num) { ++ if ((i2c->msg->len >= CONFIG_DMA_MSG_MIN_LEN) && ++ (i2c->msg->len <= CONFIG_DMA_MSG_MAX_LEN) && (i2c->msg->flags & I2C_M_DMA)) { ++#if defined(CONFIG_EDMAC) && defined(CONFIG_EDMAC_INTERRUPT) ++ status = bsp_i2c_dma_xfer_one_msg_mul_reg(i2c, reg_data_width); ++#endif ++ if (status) ++ break; ++ } else { ++ status = bsp_i2c_polling_xfer_one_msg_mul_reg(i2c, reg_data_width); ++ if (status) ++ break; ++ } ++ i2c->msg++; ++ i2c->msg_idx++; ++ } ++ if (!status || i2c->msg_idx > 0) ++ status = i2c->msg_idx; ++ ++ spin_unlock_irqrestore(&i2c->lock, flags); ++ return status; ++} ++/* I2C READ * ++ * bsp_i2c_master_recv - issue a single I2C message in master receive mode ++ * @client: Handle to slave device ++ * @buf: Where to store data read from slave ++ * @count: How many bytes to read, must be less than 64k since msg.len is u16 ++ * ++ * Returns negative errno, or else the number of bytes read. ++ */ ++int bsp_i2c_master_recv(const struct i2c_client* const client, char* const buf, ++ int count) ++{ ++ printk("Wrong interface call" ++ "bsp_i2c_transfer is the only interface to i2c read!!!\n"); ++ ++ return -EIO; ++} ++EXPORT_SYMBOL(bsp_i2c_master_recv); ++ ++/* I2C WRITE * ++ * bsp_i2c_master_send - issue a single I2C message in master transmit mode ++ * @client: Handle to slave device ++ * @buf: Data that will be written to the slave ++ * @count: How many bytes to write, must be less than 64k since msg.len is u16 ++ * ++ * Returns negative errno, or else the number of bytes written. ++ */ ++int bsp_i2c_master_send(const struct i2c_client *client, ++ const char *buf, int count) ++{ ++ struct i2c_adapter *adap = NULL; ++ struct i2c_msg msg; ++ int msgs_count; ++ ++ if ((client == NULL) || (buf == NULL) || (client->adapter == NULL) || ++ (count < 0)) { ++ printk(KERN_ERR "invalid args\n"); ++ return -EINVAL; ++ } ++ ++ if ((client->addr > 0x3ff) || ++ (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) { ++ printk(KERN_ERR "dev address out of range\n"); ++ return -EINVAL; ++ } ++ ++ adap = client->adapter; ++ msg.addr = client->addr; ++ msg.flags = client->flags; ++ msg.len = count; ++ ++ msg.buf = (__u8 *)buf; ++ ++ debug_dump_i2c_msg(&msg); ++ ++ msgs_count = bsp_i2c_break_polling_xfer(adap, &msg, 1); ++ ++ return (msgs_count == 1) ? count : -EIO; ++} ++EXPORT_SYMBOL(bsp_i2c_master_send); ++ ++ ++int bsp_i2c_master_send_mul_reg(const struct i2c_client *client, ++ const char *buf, unsigned int count, unsigned int reg_data_width) ++{ ++ struct i2c_adapter *adap = client->adapter; ++ struct i2c_msg msg; ++ int msgs_count; ++ ++ if ((client->addr > 0x3ff) ++ || (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) { ++ printk(KERN_ERR "dev address out of range\n"); ++ return -EINVAL; ++ } ++ ++ msg.addr = client->addr; ++ msg.flags = client->flags; ++ msg.len = count; ++ ++ if ((!buf) || (count < 0)) { ++ printk(KERN_ERR "buf == NULL || count < 0, Invalid argument!\n"); ++ return -EINVAL; ++ } ++ msg.buf = (__u8 *)buf; ++ ++ msgs_count = bsp_i2c_mul_reg_xfer(adap, &msg, 1,reg_data_width); ++ ++ return (msgs_count == 1) ? count : -EIO; ++} ++EXPORT_SYMBOL(bsp_i2c_master_send_mul_reg); ++/** ++ * bsp_i2c_transfer - execute a single or combined I2C message ++ * @adap: Handle to I2C bus ++ * @msgs: One or more messages to execute before STOP is issued to ++ * terminate the operation; each message begins with a START. ++ * @num: Number of messages to be executed. ++ * ++ * Returns negative errno, else the number of messages executed. ++ * ++ * Note that there is no requirement that each message be sent to ++ * the same slave address, although that is the most common model. ++ */ ++int bsp_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, ++ int num) ++{ ++ int msgs_count; ++ ++ if ((!adap) || (!msgs)) { ++ printk(KERN_ERR "adap == NULL || msgs == NULL, Invalid argument!\n"); ++ return -EINVAL; ++ } ++ ++ if ((msgs[0].addr > 0x3ff) || ++ (((msgs[0].flags & I2C_M_TEN) == 0) && (msgs[0].addr > 0x7f))) { ++ printk(KERN_ERR "msgs[0] dev address out of range\n"); ++ return -EINVAL; ++ } ++ ++ if ((msgs[1].addr > 0x3ff) || ++ (((msgs[1].flags & I2C_M_TEN) == 0) && (msgs[1].addr > 0x7f))) { ++ printk(KERN_ERR "msgs[1] dev address out of range\n"); ++ return -EINVAL; ++ } ++ ++ msgs_count = bsp_i2c_xfer(adap, msgs, num); ++ ++ return msgs_count; ++} ++EXPORT_SYMBOL(bsp_i2c_transfer); ++ ++static u32 bsp_i2c_func(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_PROTOCOL_MANGLING | ++ I2C_FUNC_SMBUS_WORD_DATA | ++ I2C_FUNC_SMBUS_BYTE_DATA | ++ I2C_FUNC_SMBUS_BYTE | ++ I2C_FUNC_SMBUS_I2C_BLOCK; ++} ++ ++static const struct i2c_algorithm bsp_i2c_algo = { ++ .master_xfer = bsp_i2c_xfer, ++ .functionality = bsp_i2c_func, ++}; ++ ++static int bsp_i2c_init_adap(struct i2c_adapter* const adap, struct bsp_i2c_dev* const i2c, ++ struct platform_device* const pdev) ++{ ++ int status; ++ ++ i2c_set_adapdata(adap, i2c); ++ adap->owner = THIS_MODULE; ++ strlcpy(adap->name, "bsp-i2c", sizeof(adap->name)); ++ adap->dev.parent = &pdev->dev; ++ adap->dev.of_node = pdev->dev.of_node; ++ adap->algo = &bsp_i2c_algo; ++ ++ /* Add the i2c adapter */ ++ status = i2c_add_adapter(adap); ++ if (status) ++ dev_err(i2c->dev, "failed to add bus to i2c core\n"); ++ ++ return status; ++} ++ ++static void try_deassert_i2c_reset(const struct bsp_i2c_dev *i2c) ++{ ++ struct reset_control *i2c_rst = NULL; ++ ++ i2c_rst = devm_reset_control_get(i2c->dev, "i2c_reset"); ++ if (IS_ERR_OR_NULL(i2c_rst)) ++ return; ++ ++ /* deassert reset if "resets" property is set */ ++ dev_info(i2c->dev, "deassert reset\n"); ++ reset_control_deassert(i2c_rst); ++} ++ ++static int bsp_i2c_probe(struct platform_device *pdev) ++{ ++ int status; ++ struct bsp_i2c_dev *i2c; ++ struct i2c_adapter *adap = NULL; ++ struct resource *res = NULL; ++ ++ i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); ++ if (i2c == NULL) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, i2c); ++ i2c->dev = &pdev->dev; ++ spin_lock_init(&i2c->lock); ++ init_completion(&i2c->msg_complete); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ dev_err(i2c->dev, "Invalid mem resource./n"); ++ return -ENODEV; ++ } ++ ++ i2c->phybase = res->start; ++ i2c->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(i2c->base)) { ++ dev_err(i2c->dev, "cannot ioremap resource\n"); ++ return -ENOMEM; ++ } ++ ++ i2c->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(i2c->clk)) { ++ dev_err(i2c->dev, "cannot get clock\n"); ++ return -ENOENT; ++ } ++ clk_prepare_enable(i2c->clk); ++ ++ try_deassert_i2c_reset(i2c); ++ ++ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", &i2c->freq)) { ++ dev_warn(i2c->dev, "setting default clock-frequency@%dHz\n", I2C_DEFAULT_FREQUENCY); ++ i2c->freq = I2C_DEFAULT_FREQUENCY; ++ } ++ ++ /* i2c controller initialization, disable interrupt */ ++ bsp_i2c_hw_init(i2c); ++ ++ i2c->irq = platform_get_irq(pdev, 0); ++ status = devm_request_irq(&pdev->dev, i2c->irq, bsp_i2c_isr, ++ IRQF_SHARED, dev_name(&pdev->dev), i2c); ++ if (status) { ++ dev_dbg(i2c->dev, "falling back to polling mode"); ++ i2c->irq = -1; ++ } ++ ++ adap = &i2c->adap; ++ status = bsp_i2c_init_adap(adap, i2c, pdev); ++ if (status) ++ clk_disable_unprepare(i2c->clk); ++ ++ return status; ++} ++ ++static int bsp_i2c_remove(struct platform_device *pdev) ++{ ++ struct bsp_i2c_dev *i2c = platform_get_drvdata(pdev); ++ ++ clk_disable_unprepare(i2c->clk); ++ i2c_del_adapter(&i2c->adap); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int bsp_i2c_suspend(struct device *dev) ++{ ++ struct bsp_i2c_dev *i2c = dev_get_drvdata(dev); ++ ++ i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER); ++ clk_disable_unprepare(i2c->clk); ++ i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER); ++ ++ return 0; ++} ++ ++static int bsp_i2c_resume(struct device *dev) ++{ ++ struct bsp_i2c_dev *i2c = dev_get_drvdata(dev); ++ ++ i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER); ++ clk_prepare_enable(i2c->clk); ++ bsp_i2c_hw_init(i2c); ++ i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER); ++ ++ return 0; ++} ++#endif ++ ++static SIMPLE_DEV_PM_OPS(bsp_i2c_dev_pm, bsp_i2c_suspend, ++ bsp_i2c_resume); ++ ++static const struct of_device_id bsp_i2c_match[] = { ++ { .compatible = "vendor,i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bsp_i2c_match); ++ ++static struct platform_driver bsp_i2c_driver = { ++ .driver = { ++ .name = "bsp-i2c", ++ .of_match_table = bsp_i2c_match, ++ .pm = &bsp_i2c_dev_pm, ++ }, ++ .probe = bsp_i2c_probe, ++ .remove = bsp_i2c_remove, ++}; ++ ++module_platform_driver(bsp_i2c_driver); ++ ++MODULE_DESCRIPTION("I2C Bus driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/i2c/i2c-dev.c b/drivers/i2c/i2c-dev.c +index dafad891998e..39ce670c2a15 100644 +--- a/drivers/i2c/i2c-dev.c ++++ b/drivers/i2c/i2c-dev.c +@@ -233,6 +233,43 @@ static int i2cdev_check_addr(struct i2c_adapter *adapter, unsigned int addr) + return result; + } + ++static noinline int i2c_config_mul_reg(struct i2c_client *client, unsigned long arg) ++{ ++ struct i2c_msg msg; ++ unsigned int reg_width; ++ unsigned int data_width; ++ unsigned int reg_data_width; ++ ++ if (copy_from_user(&msg, ++ (struct i2c_msg __user *)arg, ++ sizeof(msg))) ++ return -EFAULT; ++ ++ if(client->flags & I2C_M_16BIT_REG) ++ reg_width = 2; ++ else ++ reg_width = 1; ++ ++ if(client->flags & I2C_M_16BIT_DATA) ++ data_width = 2; ++ else ++ data_width = 1; ++ ++ reg_data_width = reg_width + data_width; ++ ++ msg.buf = memdup_user(msg.buf,msg.len); ++ ++ if(msg.len == 0 || reg_data_width > msg.len || msg.len % reg_data_width != 0){ ++ printk(KERN_ERR "msg.len err!!!\n"); ++ return -EINVAL; ++ } ++ ++ bsp_i2c_master_send_mul_reg(client, msg.buf, msg.len, reg_data_width); ++ ++ return 0; ++ ++} ++ + static noinline int i2cdev_ioctl_rdwr(struct i2c_client *client, + unsigned nmsgs, struct i2c_msg *msgs) + { +@@ -485,6 +522,24 @@ static long i2cdev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) + */ + client->adapter->timeout = msecs_to_jiffies(arg * 10); + break; ++ case I2C_CONFIG_FLAGS: ++ if (arg & I2C_M_16BIT_REG) ++ client->flags |= I2C_M_16BIT_REG; ++ else ++ client->flags &= ~I2C_M_16BIT_REG; ++ ++ if (arg & I2C_M_16BIT_DATA) ++ client->flags |= I2C_M_16BIT_DATA; ++ else ++ client->flags &= ~I2C_M_16BIT_DATA; ++ ++ if (arg & I2C_M_DMA) ++ client->flags |= I2C_M_DMA; ++ else ++ client->flags &= ~I2C_M_DMA; ++ return 0; ++ case I2C_CONFIG_MUL_REG: ++ return i2c_config_mul_reg(client, arg); + default: + /* NOTE: returning a fault code here could cause trouble + * in buggy userspace code. Some old kernel bugs returned +diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig +index e39b679126a2..a72d2d224669 100644 +--- a/drivers/iio/adc/Kconfig ++++ b/drivers/iio/adc/Kconfig +@@ -468,6 +468,16 @@ config HI8435 + This driver can also be built as a module. If so, the module will be + called hi8435. + ++config VENDOR_LSADC ++ tristate "VENDOR LSADC driver" ++ depends on ARCH_BSP || COMPILE_TEST ++ help ++ Say yes here to build support for the LSADC found in SoCs from ++ vendor chip. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called vendor_lsadc. ++ + config HX711 + tristate "AVIA HX711 ADC for weight cells" + depends on GPIOLIB +diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile +index 90f94ada7b30..8375619f83bc 100644 +--- a/drivers/iio/adc/Makefile ++++ b/drivers/iio/adc/Makefile +@@ -44,6 +44,7 @@ obj-$(CONFIG_EP93XX_ADC) += ep93xx_adc.o + obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o + obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o + obj-$(CONFIG_HI8435) += hi8435.o ++obj-$(CONFIG_VENDOR_LSADC) += bsp_lsadc.o + obj-$(CONFIG_HX711) += hx711.o + obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o + obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o +diff --git a/drivers/iio/adc/bsp_lsadc.c b/drivers/iio/adc/bsp_lsadc.c +new file mode 100644 +index 000000000000..90fcfeb216eb +--- /dev/null ++++ b/drivers/iio/adc/bsp_lsadc.c +@@ -0,0 +1,473 @@ ++/* ++ * Vendor Low Speed (LS) A/D Converter ++ * Copyright (C) 2020 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define VENDOR_LSADC_CONFIG 0x00 ++#define VENDOR_CONFIG_DEGLITCH BIT(17) ++#define VENDOR_CONFIG_RESET BIT(15) ++#define VENDOR_CONFIG_MODE BIT(13) ++#define VENDOR_CONFIG_EQU_MODE BIT(12) ++#define VENDOR_CONFIG_CHN3 BIT(11) ++#define VENDOR_CONFIG_CHN2 BIT(10) ++#define VENDOR_CONFIG_CHN1 BIT(9) ++#define VENDOR_CONFIG_CHN0 BIT(8) ++ ++#define VENDOR_CONFIG_EQU_CHN3 BIT(3) ++#define VENDOR_CONFIG_EQU_CHN2 BIT(2) ++#define VENDOR_CONFIG_EQU_CHN1 BIT(1) ++#define VENDOR_CONFIG_EQU_CHN0 BIT(0) ++ ++#define VENDOR_LSADC_TIMESCAN 0x08 ++#define VENDOR_LSADC_INTEN 0x10 ++#define VENDOR_LSADC_INTSTATUS 0x14 ++#define VENDOR_LSADC_INTCLR 0x18 ++#define VENDOR_LSADC_START 0x1C ++#define VENDOR_LSADC_STOP 0x20 ++#define VENDOR_LSADC_ACTBIT 0x24 ++#define VENDOR_LSADC_CHNDATA 0x2C ++#define VENDOR_LSADC_CHN_EQU_DATA 0x50 ++ ++#define VENDOR_LSADC_CON_EN (1u << 0) ++#define VENDOR_LSADC_CON_DEN (0u << 0) ++ ++#define VENDOR_LSADC_NUM_BITS 10 ++#define VENDOR_LSADC_CHN_MASK 0xF ++ ++/* fix clk:3000000, default tscan set 10ms */ ++#define VENDOR_LSADC_TSCAN_MS (10*3000) ++ ++#define VENDOR_LSADC_TIMEOUT msecs_to_jiffies(100) ++ ++/* default voltage scale for every channel */ ++static int g_vendor_lsadc_voltage[] = { ++ 1800, 1800, 1800, 1800 ++}; ++ ++struct vendor_lsadc { ++ void __iomem *regs; ++ struct clk *lsadc_clk; ++ int irq; ++ struct completion completion; ++ struct reset_control *reset; ++ const struct vendor_lsadc_data *data; ++ unsigned int cur_chn; ++ unsigned int value; ++ unsigned int average_value; ++}; ++ ++struct vendor_lsadc_data { ++ int num_bits; ++ const struct iio_chan_spec *channels; ++ int num_channels; ++ ++ void (*clear_irq)(struct vendor_lsadc *info, int mask); ++ void (*start_conv)(struct vendor_lsadc *info); ++ void (*stop_conv)(struct vendor_lsadc *info); ++}; ++ ++static int vendor_lsadc_read_raw(struct iio_dev *indio_dev, ++ struct iio_chan_spec const *chan, ++ int *val, int *val2, long mask) ++{ ++ struct vendor_lsadc *info = iio_priv(indio_dev); ++ ++ switch (mask) { ++ case IIO_CHAN_INFO_RAW: ++ mutex_lock(&indio_dev->mlock); ++ ++ reinit_completion(&info->completion); ++ ++ /* Select the channel to be used */ ++ info->cur_chn = chan->channel; ++ ++ if (info->data->start_conv) ++ info->data->start_conv(info); ++ ++ if (!wait_for_completion_timeout(&info->completion, ++ VENDOR_LSADC_TIMEOUT)) { ++ if (info->data->stop_conv) ++ info->data->stop_conv(info); ++ mutex_unlock(&indio_dev->mlock); ++ return -ETIMEDOUT; ++ } ++ ++ *val = info->value; ++ mutex_unlock(&indio_dev->mlock); ++ return IIO_VAL_INT; ++ case IIO_CHAN_INFO_AVERAGE_RAW: ++ mutex_lock(&indio_dev->mlock); ++ ++ reinit_completion(&info->completion); ++ ++ /* Select the channel to be used */ ++ info->cur_chn = chan->channel; ++ ++ if (info->data->start_conv) ++ info->data->start_conv(info); ++ ++ if (!wait_for_completion_timeout(&info->completion, ++ VENDOR_LSADC_TIMEOUT)) { ++ if (info->data->stop_conv) ++ info->data->stop_conv(info); ++ mutex_unlock(&indio_dev->mlock); ++ return -ETIMEDOUT; ++ } ++ ++ *val = info->average_value; ++ mutex_unlock(&indio_dev->mlock); ++ return IIO_VAL_INT; ++ case IIO_CHAN_INFO_SCALE: ++ *val = g_vendor_lsadc_voltage[chan->channel]; ++ *val2 = info->data->num_bits; ++ return IIO_VAL_FRACTIONAL_LOG2; ++ default: ++ return -EINVAL; ++ } ++} ++ ++static irqreturn_t vendor_lsadc_isr(int irq, void *dev_id) ++{ ++ struct vendor_lsadc *info = (struct vendor_lsadc *)dev_id; ++ int mask; ++ ++ mask = readl(info->regs + VENDOR_LSADC_INTSTATUS); ++ if ((mask & VENDOR_LSADC_CHN_MASK) == 0) ++ return IRQ_NONE; ++ ++ /* Clear irq */ ++ mask &= VENDOR_LSADC_CHN_MASK; ++ if (info->data->clear_irq) ++ info->data->clear_irq(info, mask); ++ ++ /* Read value */ ++ info->value = readl(info->regs + ++ VENDOR_LSADC_CHNDATA + (info->cur_chn << 2)); /* 2: bit 2 */ ++ info->value &= GENMASK(info->data->num_bits - 1, 0); ++ ++ /* Read average value */ ++ info->average_value = readl(info->regs + ++ VENDOR_LSADC_CHN_EQU_DATA + (info->cur_chn << 2)); /* 2: bit 2 */ ++ info->average_value &= GENMASK(info->data->num_bits - 1, 0); ++ ++ /* stop adc */ ++ if (info->data->stop_conv) ++ info->data->stop_conv(info); ++ ++ complete(&info->completion); ++ ++ return IRQ_HANDLED; ++} ++ ++static const struct iio_info vendor_lsadc_iio_info = { ++ .read_raw = vendor_lsadc_read_raw, ++}; ++ ++#define vendor_lsadc_channel(_index, _id) { \ ++ .type = IIO_VOLTAGE, \ ++ .indexed = 1, \ ++ .channel = (_index), \ ++ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ ++ BIT(IIO_CHAN_INFO_SCALE) | \ ++ BIT(IIO_CHAN_INFO_AVERAGE_RAW), \ ++ .datasheet_name = (_id), \ ++} ++ ++static const struct iio_chan_spec vendor_lsadc_iio_channels[] = { ++ vendor_lsadc_channel(0, "adc0"), ++ vendor_lsadc_channel(1, "adc1"), ++ vendor_lsadc_channel(2, "adc2"), ++ vendor_lsadc_channel(3, "adc3"), ++}; ++ ++static void vendor_lsadc_clear_irq(struct vendor_lsadc *info, int mask) ++{ ++ writel(mask, info->regs + VENDOR_LSADC_INTCLR); ++} ++ ++static void vendor_lsadc_start_conv(struct vendor_lsadc *info) ++{ ++ unsigned int con; ++ ++ /* set number bit */ ++ con = GENMASK(info->data->num_bits - 1, 0); ++ writel(con, (info->regs + VENDOR_LSADC_ACTBIT)); ++ ++ /* config */ ++ con = readl(info->regs + VENDOR_LSADC_CONFIG); ++ con &= ~VENDOR_CONFIG_RESET; /* set to 0 */ ++ con &= ~VENDOR_CONFIG_EQU_MODE; /* set to 0 */ ++ con |= (VENDOR_CONFIG_DEGLITCH | VENDOR_CONFIG_MODE); /* set to 1 */ ++ con &= ~(VENDOR_CONFIG_CHN0 | VENDOR_CONFIG_CHN1 | ++ VENDOR_CONFIG_CHN2 | VENDOR_CONFIG_CHN3 | ++ VENDOR_CONFIG_EQU_CHN0 | VENDOR_CONFIG_EQU_CHN1 | ++ VENDOR_CONFIG_EQU_CHN2 | VENDOR_CONFIG_EQU_CHN3); /* set to 0 */ ++ con |= (VENDOR_CONFIG_CHN0 << info->cur_chn); /* set to 1 */ ++ con |= (VENDOR_CONFIG_EQU_CHN0 << info->cur_chn); /* set to 1 */ ++ writel(con, (info->regs + VENDOR_LSADC_CONFIG)); ++ ++ /* set timescan */ ++ writel(VENDOR_LSADC_TSCAN_MS, (info->regs + VENDOR_LSADC_TIMESCAN)); ++ ++ /* clear interrupt */ ++ writel(VENDOR_LSADC_CHN_MASK, info->regs + VENDOR_LSADC_INTCLR); ++ ++ /* enable interrupt */ ++ writel(VENDOR_LSADC_CON_EN, (info->regs + VENDOR_LSADC_INTEN)); ++ ++ /* start scan */ ++ writel(VENDOR_LSADC_CON_EN, (info->regs + VENDOR_LSADC_START)); ++} ++ ++static void vendor_lsadc_stop_conv(struct vendor_lsadc *info) ++{ ++ /* reset the timescan */ ++ writel(VENDOR_LSADC_CON_DEN, (info->regs + VENDOR_LSADC_TIMESCAN)); ++ ++ /* disable interrupt */ ++ writel(VENDOR_LSADC_CON_DEN, (info->regs + VENDOR_LSADC_INTEN)); ++ ++ /* stop scan */ ++ writel(VENDOR_LSADC_CON_EN, (info->regs + VENDOR_LSADC_STOP)); ++} ++ ++static const struct vendor_lsadc_data lsadc_data = { ++ .num_bits = VENDOR_LSADC_NUM_BITS, ++ .channels = vendor_lsadc_iio_channels, ++ .num_channels = ARRAY_SIZE(vendor_lsadc_iio_channels), ++ ++ .clear_irq = vendor_lsadc_clear_irq, ++ .start_conv = vendor_lsadc_start_conv, ++ .stop_conv = vendor_lsadc_stop_conv, ++}; ++ ++static const struct of_device_id vendor_lsadc_match[] = { ++ { ++ .compatible = "vendor,lsadc", ++ .data = &lsadc_data, ++ }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, vendor_lsadc_match); ++ ++/* Reset LSADC Controller */ ++static void vendor_lsadc_reset_controller(struct reset_control *reset) ++{ ++ reset_control_assert(reset); ++ usleep_range(10, 20); /* 10, 20: us*/ ++ reset_control_deassert(reset); ++} ++ ++static int vendor_lsadc_device_alloc(struct platform_device *pdev, struct iio_dev **indio_dev) ++{ ++ struct vendor_lsadc *info = NULL; ++ struct device_node *np = pdev->dev.of_node; ++ ++ if (np == NULL) ++ return -ENODEV; ++ ++ (*indio_dev) = devm_iio_device_alloc(&pdev->dev, sizeof(*info)); ++ if ((*indio_dev) == NULL) { ++ dev_err(&pdev->dev, "failed allocating iio device\n"); ++ return -ENOMEM; ++ } ++ return 0; ++} ++ ++static void vendor_lsadc_device_free(struct platform_device *pdev, struct iio_dev *indio_dev) ++{ ++ devm_iio_device_free(&pdev->dev, indio_dev); ++} ++ ++static int vendor_lsadc_clk_prepare_enable(struct platform_device *pdev, struct iio_dev *indio_dev, ++ struct vendor_lsadc **info) ++{ ++ struct resource *mem = NULL; ++ const struct of_device_id *match = NULL; ++ int ret; ++ ++ *info = iio_priv(indio_dev); ++ (*info)->lsadc_clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR((*info)->lsadc_clk)) { ++ dev_err(&pdev->dev, "getting clock failed with %ld\n", ++ PTR_ERR((*info)->lsadc_clk)); ++ return PTR_ERR((*info)->lsadc_clk); ++ } ++ ++ match = of_match_device(vendor_lsadc_match, &pdev->dev); ++ (*info)->data = match->data; ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ (*info)->regs = devm_ioremap_resource(&pdev->dev, mem); ++ if (IS_ERR((*info)->regs)) ++ return PTR_ERR((*info)->regs); ++ ++ ret = clk_prepare_enable((*info)->lsadc_clk); ++ if (ret < 0) ++ return ret; ++ return 0; ++} ++ ++static void vendor_lsadc_clk_disable_unprepare(struct vendor_lsadc *info) ++{ ++ clk_disable_unprepare(info->lsadc_clk); ++} ++ ++static int vendor_lsadc_requst_irq(struct platform_device *pdev, struct vendor_lsadc *info) ++{ ++ int ret; ++ ++ /* ++ * The reset should be an optional property, as it should work ++ * with old devicetrees as well ++ */ ++ info->reset = devm_reset_control_get(&pdev->dev, "lsadc-crg"); ++ if (IS_ERR(info->reset)) { ++ ret = PTR_ERR(info->reset); ++ if (ret != -ENOENT) ++ return ret; ++ ++ dev_dbg(&pdev->dev, "no reset control found\n"); ++ info->reset = NULL; ++ } ++ ++ init_completion(&info->completion); ++ ++ info->irq = platform_get_irq(pdev, 0); ++ if (info->irq < 0) { ++ dev_err(&pdev->dev, "no irq resource?\n"); ++ ret = info->irq; ++ return ret; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, info->irq, vendor_lsadc_isr, ++ IRQF_SHARED, dev_name(&pdev->dev), info); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed requesting irq %d\n", info->irq); ++ return ret; ++ } ++ ++ if (info->reset != NULL) ++ vendor_lsadc_reset_controller(info->reset); ++ ++ return 0; ++} ++ ++static void vendor_lsadc_free_irq(struct platform_device *pdev, struct vendor_lsadc *info) ++{ ++ devm_free_irq(&pdev->dev, info->irq, info); ++} ++ ++static int vendor_lsadc_device_register(struct platform_device *pdev, struct iio_dev *indio_dev, ++ struct vendor_lsadc *info) ++{ ++ int ret; ++ ++ platform_set_drvdata(pdev, indio_dev); ++ ++ indio_dev->name = dev_name(&pdev->dev); ++ indio_dev->dev.parent = &pdev->dev; ++ indio_dev->dev.of_node = pdev->dev.of_node; ++ indio_dev->info = &vendor_lsadc_iio_info; ++ indio_dev->modes = INDIO_DIRECT_MODE; ++ indio_dev->driver_module = THIS_MODULE; ++ ++ indio_dev->channels = info->data->channels; ++ indio_dev->num_channels = info->data->num_channels; ++ ++ ret = devm_iio_device_register(&pdev->dev, indio_dev); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "failed register iio device\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int vendor_lsadc_probe(struct platform_device *pdev) ++{ ++ struct vendor_lsadc *info = NULL; ++ struct iio_dev *indio_dev = NULL; ++ int ret; ++ ++ ret = vendor_lsadc_device_alloc(pdev, &indio_dev); ++ if (ret != 0) ++ return ret; ++ ++ ret = vendor_lsadc_clk_prepare_enable(pdev, indio_dev, &info); ++ if (ret != 0) ++ goto vendor_lsadc_out0; ++ ++ ret = vendor_lsadc_requst_irq(pdev, info); ++ if (ret != 0) ++ goto vendor_lsadc_out1; ++ ++ vendor_lsadc_device_register(pdev, indio_dev, info); ++ if (ret != 0) ++ goto vendor_lsadc_out2; ++ ++ return 0; ++ ++vendor_lsadc_out2: ++ vendor_lsadc_free_irq(pdev, info); ++vendor_lsadc_out1: ++ vendor_lsadc_clk_disable_unprepare(info); ++vendor_lsadc_out0: ++ vendor_lsadc_device_free(pdev, indio_dev); ++ ++ return ret; ++} ++ ++static int vendor_lsadc_remove(struct platform_device *pdev) ++{ ++ struct vendor_lsadc *info = NULL; ++ struct iio_dev *indio_dev = NULL; ++ ++ indio_dev = platform_get_drvdata(pdev); ++ info = iio_priv(indio_dev); ++ ++ devm_iio_device_unregister(&pdev->dev, indio_dev); ++ devm_free_irq(&pdev->dev, info->irq, info); ++ clk_disable_unprepare(info->lsadc_clk); ++ devm_iio_device_free(&pdev->dev, indio_dev); ++ ++ return 0; ++} ++ ++static struct platform_driver vendor_lsadc_driver = { ++ .probe = vendor_lsadc_probe, ++ .remove = vendor_lsadc_remove, ++ .driver = { ++ .name = "vendor-lsadc", ++ .of_match_table = vendor_lsadc_match, ++ }, ++}; ++ ++module_platform_driver(vendor_lsadc_driver); ++ ++MODULE_AUTHOR("Vendor multimedia software group"); ++MODULE_DESCRIPTION("Vendor multimedia software group lsadc driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c +index ea98aad9fb81..206505261eac 100644 +--- a/drivers/iio/industrialio-core.c ++++ b/drivers/iio/industrialio-core.c +@@ -1843,6 +1843,54 @@ int __devm_iio_device_register(struct device *dev, struct iio_dev *indio_dev, + } + EXPORT_SYMBOL_GPL(__devm_iio_device_register); + ++#ifdef CONFIG_ARCH_BSP ++ ++int devm_iio_device_match(struct device *dev, void *res, void *data) ++{ ++ struct iio_dev **r = res; ++ if (!r || !*r) { ++ WARN_ON(!r || !*r); ++ return 0; ++ } ++ return *r == data; ++} ++EXPORT_SYMBOL_GPL(devm_iio_device_match); ++ ++/** ++ * devm_iio_device_free - Resource-managed iio_device_free() ++ * @dev: Device this iio_dev belongs to ++ * @iio_dev: the iio_dev associated with the device ++ * ++ * Free iio_dev allocated with devm_iio_device_alloc(). ++ */ ++void devm_iio_device_free(struct device *dev, struct iio_dev *iio_dev) ++{ ++ int rc; ++ ++ rc = devres_release(dev, devm_iio_device_release, ++ devm_iio_device_match, iio_dev); ++ WARN_ON(rc); ++} ++EXPORT_SYMBOL_GPL(devm_iio_device_free); ++ ++/** ++ * devm_iio_device_unregister - Resource-managed iio_device_unregister() ++ * @dev: Device this iio_dev belongs to ++ * @indio_dev: the iio_dev associated with the device ++ * ++ * Unregister iio_dev registered with devm_iio_device_register(). ++ */ ++void devm_iio_device_unregister(struct device *dev, struct iio_dev *indio_dev) ++{ ++ int rc; ++ ++ rc = devres_release(dev, devm_iio_device_unreg, ++ devm_iio_device_match, indio_dev); ++ WARN_ON(rc); ++} ++EXPORT_SYMBOL_GPL(devm_iio_device_unregister); ++#endif ++ + /** + * iio_device_claim_direct_mode - Keep device in direct mode + * @indio_dev: the iio_dev associated with the device +diff --git a/drivers/iommu/Kconfig b/drivers/iommu/Kconfig +index b630e58c49b6..b01313108df2 100644 +--- a/drivers/iommu/Kconfig ++++ b/drivers/iommu/Kconfig +@@ -58,6 +58,23 @@ config IOMMU_IO_PGTABLE_ARMV7S + 2-level tables with 4KB pages/1MB sections, and contiguous entries + for 64KB pages/16MB supersections if indicated by the IOMMU driver. + ++menu "Generic PASID table support" ++ ++config IOMMU_PASID_TABLE ++ bool ++ ++config ARM_SMMU_V3_CONTEXT ++ bool "ARM SMMU v3 Context Descriptor tables" ++ select IOMMU_PASID_TABLE ++ depends on ARM64 ++ help ++ Enable support for ARM SMMU v3 Context Descriptor tables, used for ++ DMA and PASID support. ++ ++ If unsure, say N here. ++ ++endmenu ++ + config IOMMU_IO_PGTABLE_ARMV7S_SELFTEST + bool "ARMv7s selftests" + depends on IOMMU_IO_PGTABLE_ARMV7S +@@ -103,10 +120,14 @@ config IOMMU_DMA + select IRQ_MSI_IOMMU + select NEED_SG_DMA_LENGTH + +-# Shared Virtual Addressing +-config IOMMU_SVA ++# Shared Virtual Addressing library ++config IOMMU_SVA_LIB ++ bool ++ select IOASID ++ ++config IOMMU_PAGE_FAULT + bool +- select IOASID ++ select IOMMU_API + + config FSL_PAMU + bool "Freescale IOMMU support" +@@ -136,7 +157,6 @@ config MSM_IOMMU + + source "drivers/iommu/amd/Kconfig" + source "drivers/iommu/intel/Kconfig" +-source "drivers/iommu/sw64/Kconfig" + + config IRQ_REMAP + bool "Support for Interrupt Remapping" +@@ -304,9 +324,11 @@ config ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT + config ARM_SMMU_V3 + tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support" + depends on ARM64 +- select IOASID + select IOMMU_API ++ select IOMMU_SVA ++ select IOMMU_PAGE_FAULT + select IOMMU_IO_PGTABLE_LPAE ++ select ARM_SMMU_V3_CONTEXT + select GENERIC_MSI_IRQ_DOMAIN + help + Support for implementations of the ARM System MMU architecture +@@ -318,7 +340,7 @@ config ARM_SMMU_V3 + config ARM_SMMU_V3_SVA + bool "Shared Virtual Addressing support for the ARM SMMUv3" + depends on ARM_SMMU_V3 +- select IOMMU_SVA ++ select IOMMU_SVA_LIB + select MMU_NOTIFIER + help + Support for sharing process address spaces with devices using the +@@ -327,22 +349,6 @@ config ARM_SMMU_V3_SVA + Say Y here if your system supports SVA extensions such as PCIe PASID + and PRI. + +-config AGENT_SMMU_ATOS +- bool "An implementation of ATOS feature support for the ARM SMMUv3" +- depends on ARM_SMMU_V3 +- help +- Support for ARM SMMUv3 ATOS feature which can translating IPA to PA. +- +- Say Y here if your system will be used in Ascend Advanced Accelerator +- with HCCS bus. Or want use the ATOS of SMMU. +- +-config ARM_SMMU_V3_PM +- bool "Add arm_smmu_v3 suspend and resume support" +- depends on ARM_SMMU_V3 && PM_SLEEP +- default n +- help +- Add support for suspend and resume support for arm smmu v3. +- + config S390_IOMMU + def_bool y if S390 && PCI + depends on S390 && PCI +@@ -426,26 +432,4 @@ config VIRTIO_IOMMU + + Say Y here if you intend to run this kernel as a guest. + +-config SMMU_BYPASS_DEV +- bool "SMMU bypass streams for some specific devices" +- depends on ARM_SMMU_V3=y +- help +- Using the smmu.bypassdev cmdline, to collect the devices that SMMU +- performs attribute transformation only, with no address translation. +- E.g:SMMU allow iMR3408/3416 Raid bypass at DMA default domain to +- support other devices to use virtualization such as VFIO. +- +- This feature will be replaced by ACPI IORT RMR node, which will be +- upstreamed in mainline. +- + endif # IOMMU_SUPPORT +- +-config IOVA_MAX_GLOBAL_MAGS +- int "Set the max iova global magzines in iova rcache" +- range 16 2048 +- default "32" +- help +- Iova rcache global magizine is shared among every cpu. The size of +- it can be a bottle neck when lots of cpus are contending to use it. +- If you are suffering from the speed of allocing iova with more than +- 128 cpus, try to tune this config larger. +diff --git a/drivers/iommu/Makefile b/drivers/iommu/Makefile +index ae38d815537e..60fafc23dee6 100644 +--- a/drivers/iommu/Makefile ++++ b/drivers/iommu/Makefile +@@ -1,5 +1,5 @@ + # SPDX-License-Identifier: GPL-2.0 +-obj-y += amd/ intel/ arm/ sw64/ ++obj-y += amd/ intel/ arm/ + obj-$(CONFIG_IOMMU_API) += iommu.o + obj-$(CONFIG_IOMMU_API) += iommu-traces.o + obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o +@@ -27,4 +27,5 @@ obj-$(CONFIG_FSL_PAMU) += fsl_pamu.o fsl_pamu_domain.o + obj-$(CONFIG_S390_IOMMU) += s390-iommu.o + obj-$(CONFIG_HYPERV_IOMMU) += hyperv-iommu.o + obj-$(CONFIG_VIRTIO_IOMMU) += virtio-iommu.o +-obj-$(CONFIG_IOMMU_SVA) += iommu-sva-lib.o io-pgfault.o ++obj-$(CONFIG_IOMMU_SVA_LIB) += iommu-sva-lib.o ++obj-$(CONFIG_IOMMU_SVA_LIB) += io-pgfault.o +diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h +index 0c40d22409f2..b4adab698563 100644 +--- a/drivers/iommu/amd/amd_iommu.h ++++ b/drivers/iommu/amd/amd_iommu.h +@@ -17,7 +17,6 @@ extern int amd_iommu_init_passthrough(void); + extern irqreturn_t amd_iommu_int_thread(int irq, void *data); + extern irqreturn_t amd_iommu_int_handler(int irq, void *data); + extern void amd_iommu_apply_erratum_63(u16 devid); +-extern void amd_iommu_restart_event_logging(struct amd_iommu *iommu); + extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu); + extern int amd_iommu_init_devices(void); + extern void amd_iommu_uninit_devices(void); +diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h +index 690c5976575c..33446c9d3bac 100644 +--- a/drivers/iommu/amd/amd_iommu_types.h ++++ b/drivers/iommu/amd/amd_iommu_types.h +@@ -109,7 +109,6 @@ + #define PASID_MASK 0x0000ffff + + /* MMIO status bits */ +-#define MMIO_STATUS_EVT_OVERFLOW_INT_MASK (1 << 0) + #define MMIO_STATUS_EVT_INT_MASK (1 << 1) + #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) + #define MMIO_STATUS_PPR_INT_MASK (1 << 6) +diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c +index ce822347f747..cc9869cc48e4 100644 +--- a/drivers/iommu/amd/init.c ++++ b/drivers/iommu/amd/init.c +@@ -20,7 +20,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -84,11 +83,7 @@ + #define ACPI_DEVFLAG_LINT1 0x80 + #define ACPI_DEVFLAG_ATSDIS 0x10000000 + +-#define LOOP_TIMEOUT 2000000 +- +-#define IVRS_GET_SBDF_ID(seg, bus, dev, fd) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \ +- | ((dev & 0x1f) << 3) | (fn & 0x7)) +- ++#define LOOP_TIMEOUT 100000 + /* + * ACPI table definitions + * +@@ -303,22 +298,6 @@ int amd_iommu_get_num_iommus(void) + return amd_iommus_present; + } + +-#ifdef CONFIG_IRQ_REMAP +-static bool check_feature_on_all_iommus(u64 mask) +-{ +- bool ret = false; +- struct amd_iommu *iommu; +- +- for_each_iommu(iommu) { +- ret = iommu_feature(iommu, mask); +- if (!ret) +- return false; +- } +- +- return true; +-} +-#endif +- + /* + * For IVHD type 0x11/0x40, EFR is also available via IVHD. + * Default to IVHD EFR since it is available sooner +@@ -660,16 +639,6 @@ static int __init alloc_command_buffer(struct amd_iommu *iommu) + return iommu->cmd_buf ? 0 : -ENOMEM; + } + +-/* +- * This function restarts event logging in case the IOMMU experienced +- * an event log buffer overflow. +- */ +-void amd_iommu_restart_event_logging(struct amd_iommu *iommu) +-{ +- iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); +- iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); +-} +- + /* + * This function resets the command buffer if the IOMMU stopped fetching + * commands from it. +@@ -820,26 +789,15 @@ static int iommu_ga_log_enable(struct amd_iommu *iommu) + { + #ifdef CONFIG_IRQ_REMAP + u32 status, i; +- u64 entry; + + if (!iommu->ga_log) + return -EINVAL; + +- /* Check if already running */ + status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); +- if (WARN_ON(status & (MMIO_STATUS_GALOG_RUN_MASK))) +- return 0; +- +- entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; +- memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, +- &entry, sizeof(entry)); +- entry = (iommu_virt_to_phys(iommu->ga_log_tail) & +- (BIT_ULL(52)-1)) & ~7ULL; +- memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, +- &entry, sizeof(entry)); +- writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); +- writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); + ++ /* Check if already running */ ++ if (status & (MMIO_STATUS_GALOG_RUN_MASK)) ++ return 0; + + iommu_feature_enable(iommu, CONTROL_GAINT_EN); + iommu_feature_enable(iommu, CONTROL_GALOG_EN); +@@ -848,18 +806,19 @@ static int iommu_ga_log_enable(struct amd_iommu *iommu) + status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); + if (status & (MMIO_STATUS_GALOG_RUN_MASK)) + break; +- udelay(10); + } + +- if (WARN_ON(i >= LOOP_TIMEOUT)) ++ if (i >= LOOP_TIMEOUT) + return -EINVAL; + #endif /* CONFIG_IRQ_REMAP */ + return 0; + } + ++#ifdef CONFIG_IRQ_REMAP + static int iommu_init_ga_log(struct amd_iommu *iommu) + { +-#ifdef CONFIG_IRQ_REMAP ++ u64 entry; ++ + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + return 0; + +@@ -873,13 +832,39 @@ static int iommu_init_ga_log(struct amd_iommu *iommu) + if (!iommu->ga_log_tail) + goto err_out; + ++ entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; ++ memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, ++ &entry, sizeof(entry)); ++ entry = (iommu_virt_to_phys(iommu->ga_log_tail) & ++ (BIT_ULL(52)-1)) & ~7ULL; ++ memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, ++ &entry, sizeof(entry)); ++ writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); ++ writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); ++ + return 0; + err_out: + free_ga_log(iommu); + return -EINVAL; +-#else +- return 0; ++} ++#endif /* CONFIG_IRQ_REMAP */ ++ ++static int iommu_init_ga(struct amd_iommu *iommu) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_IRQ_REMAP ++ /* Note: We have already checked GASup from IVRS table. ++ * Now, we need to make sure that GAMSup is set. ++ */ ++ if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && ++ !iommu_feature(iommu, FEATURE_GAM_VAPIC)) ++ amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; ++ ++ ret = iommu_init_ga_log(iommu); + #endif /* CONFIG_IRQ_REMAP */ ++ ++ return ret; + } + + static int __init alloc_cwwb_sem(struct amd_iommu *iommu) +@@ -1866,7 +1851,7 @@ static int __init iommu_init_pci(struct amd_iommu *iommu) + if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) + return -ENOMEM; + +- ret = iommu_init_ga_log(iommu); ++ ret = iommu_init_ga(iommu); + if (ret) + return ret; + +@@ -1929,8 +1914,8 @@ static void print_iommu_info(void) + pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); + + if (iommu->cap & (1 << IOMMU_CAP_EFR)) { +- pr_info("Extended features (%#llx):", iommu->features); +- ++ pci_info(pdev, "Extended features (%#llx):", ++ iommu->features); + for (i = 0; i < ARRAY_SIZE(feat_str); ++i) { + if (iommu_feature(iommu, (1ULL << i))) + pr_cont(" %s", feat_str[i]); +@@ -2411,14 +2396,6 @@ static void early_enable_iommus(void) + } + + #ifdef CONFIG_IRQ_REMAP +- /* +- * Note: We have already checked GASup from IVRS table. +- * Now, we need to make sure that GAMSup is set. +- */ +- if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && +- !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) +- amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA; +- + if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP); + #endif +@@ -3050,32 +3027,24 @@ static int __init parse_amd_iommu_options(char *str) + + static int __init parse_ivrs_ioapic(char *str) + { +- u32 seg = 0, bus, dev, fn; +- int id, i; +- u32 devid; ++ unsigned int bus, dev, fn; ++ int ret, id, i; ++ u16 devid; + +- if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || +- sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) +- goto found; ++ ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); + +- if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || +- sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { +- pr_warn("ivrs_ioapic%s option format deprecated; use ivrs_ioapic=%d@%04x:%02x:%02x.%d instead\n", +- str, id, seg, bus, dev, fn); +- goto found; ++ if (ret != 4) { ++ pr_err("Invalid command line: ivrs_ioapic%s\n", str); ++ return 1; + } + +- pr_err("Invalid command line: ivrs_ioapic%s\n", str); +- return 1; +- +-found: + if (early_ioapic_map_size == EARLY_MAP_SIZE) { + pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n", + str); + return 1; + } + +- devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); ++ devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); + + cmdline_maps = true; + i = early_ioapic_map_size++; +@@ -3088,32 +3057,24 @@ static int __init parse_ivrs_ioapic(char *str) + + static int __init parse_ivrs_hpet(char *str) + { +- u32 seg = 0, bus, dev, fn; +- int id, i; +- u32 devid; ++ unsigned int bus, dev, fn; ++ int ret, id, i; ++ u16 devid; + +- if (sscanf(str, "=%d@%x:%x.%x", &id, &bus, &dev, &fn) == 4 || +- sscanf(str, "=%d@%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) +- goto found; ++ ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn); + +- if (sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn) == 4 || +- sscanf(str, "[%d]=%x:%x:%x.%x", &id, &seg, &bus, &dev, &fn) == 5) { +- pr_warn("ivrs_hpet%s option format deprecated; use ivrs_hpet=%d@%04x:%02x:%02x.%d instead\n", +- str, id, seg, bus, dev, fn); +- goto found; ++ if (ret != 4) { ++ pr_err("Invalid command line: ivrs_hpet%s\n", str); ++ return 1; + } + +- pr_err("Invalid command line: ivrs_hpet%s\n", str); +- return 1; +- +-found: + if (early_hpet_map_size == EARLY_MAP_SIZE) { + pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n", + str); + return 1; + } + +- devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); ++ devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); + + cmdline_maps = true; + i = early_hpet_map_size++; +@@ -3126,37 +3087,17 @@ static int __init parse_ivrs_hpet(char *str) + + static int __init parse_ivrs_acpihid(char *str) + { +- u32 seg = 0, bus, dev, fn; +- char *hid, *uid, *p, *addr; ++ u32 bus, dev, fn; ++ char *hid, *uid, *p; + char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0}; +- int i; ++ int ret, i; + +- addr = strchr(str, '@'); +- if (!addr) { +- if (sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid) == 4 || +- sscanf(str, "[%x:%x:%x.%x]=%s", &seg, &bus, &dev, &fn, acpiid) == 5) { +- pr_warn("ivrs_acpihid%s option format deprecated; use ivrs_acpihid=%s@%04x:%02x:%02x.%d instead\n", +- str, acpiid, seg, bus, dev, fn); +- goto found; +- } +- goto not_found; ++ ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid); ++ if (ret != 4) { ++ pr_err("Invalid command line: ivrs_acpihid(%s)\n", str); ++ return 1; + } + +- /* We have the '@', make it the terminator to get just the acpiid */ +- *addr++ = 0; +- +- if (sscanf(str, "=%s", acpiid) != 1) +- goto not_found; +- +- if (sscanf(addr, "%x:%x.%x", &bus, &dev, &fn) == 3 || +- sscanf(addr, "%x:%x:%x.%x", &seg, &bus, &dev, &fn) == 4) +- goto found; +- +-not_found: +- pr_err("Invalid command line: ivrs_acpihid%s\n", str); +- return 1; +- +-found: + p = acpiid; + hid = strsep(&p, ":"); + uid = p; +@@ -3166,17 +3107,11 @@ static int __init parse_ivrs_acpihid(char *str) + return 1; + } + +- /* +- * Ignore leading zeroes after ':', so e.g., AMDI0095:00 +- * will match AMDI0095:0 in the second strcmp in acpi_dev_hid_uid_match +- */ +- while (*uid == '0' && *(uid + 1)) +- uid++; +- + i = early_acpihid_map_size++; + memcpy(early_acpihid_map[i].hid, hid, strlen(hid)); + memcpy(early_acpihid_map[i].uid, uid, strlen(uid)); +- early_acpihid_map[i].devid = IVRS_GET_SBDF_ID(seg, bus, dev, fn); ++ early_acpihid_map[i].devid = ++ ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7); + early_acpihid_map[i].cmd_line = true; + + return 1; +diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c +index f216a86d9c81..5f1195791cb1 100644 +--- a/drivers/iommu/amd/iommu.c ++++ b/drivers/iommu/amd/iommu.c +@@ -813,8 +813,7 @@ amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { } + #endif /* !CONFIG_IRQ_REMAP */ + + #define AMD_IOMMU_INT_MASK \ +- (MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \ +- MMIO_STATUS_EVT_INT_MASK | \ ++ (MMIO_STATUS_EVT_INT_MASK | \ + MMIO_STATUS_PPR_INT_MASK | \ + MMIO_STATUS_GALOG_INT_MASK) + +@@ -824,7 +823,7 @@ irqreturn_t amd_iommu_int_thread(int irq, void *data) + u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); + + while (status & AMD_IOMMU_INT_MASK) { +- /* Enable interrupt sources again */ ++ /* Enable EVT and PPR and GA interrupts again */ + writel(AMD_IOMMU_INT_MASK, + iommu->mmio_base + MMIO_STATUS_OFFSET); + +@@ -845,11 +844,6 @@ irqreturn_t amd_iommu_int_thread(int irq, void *data) + } + #endif + +- if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) { +- pr_info_ratelimited("IOMMU event log overflow\n"); +- amd_iommu_restart_event_logging(iommu); +- } +- + /* + * Hardware bug: ERBT1312 + * When re-enabling interrupt (by writing 1 +@@ -923,8 +917,7 @@ static void build_completion_wait(struct iommu_cmd *cmd, + memset(cmd, 0, sizeof(*cmd)); + cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK; + cmd->data[1] = upper_32_bits(paddr); +- cmd->data[2] = lower_32_bits(data); +- cmd->data[3] = upper_32_bits(data); ++ cmd->data[2] = data; + CMD_SET_TYPE(cmd, CMD_COMPL_WAIT); + } + +diff --git a/drivers/iommu/amd/iommu_v2.c b/drivers/iommu/amd/iommu_v2.c +index 16776e3c6eab..5ecc0bc608ec 100644 +--- a/drivers/iommu/amd/iommu_v2.c ++++ b/drivers/iommu/amd/iommu_v2.c +@@ -587,7 +587,6 @@ static int ppr_notifier(struct notifier_block *nb, unsigned long e, void *data) + put_device_state(dev_state); + + out: +- pci_dev_put(pdev); + return ret; + } + +@@ -928,8 +927,10 @@ static int __init amd_iommu_v2_init(void) + { + int ret; + ++ pr_info("AMD IOMMUv2 driver by Joerg Roedel \n"); ++ + if (!amd_iommu_v2_supported()) { +- pr_info("AMD IOMMUv2 functionality not available on this system - This is not a bug.\n"); ++ pr_info("AMD IOMMUv2 functionality not available on this system\n"); + /* + * Load anyway to provide the symbols to other modules + * which may use AMD IOMMUv2 optionally. +@@ -946,8 +947,6 @@ static int __init amd_iommu_v2_init(void) + + amd_iommu_register_ppr_notifier(&ppr_nb); + +- pr_info("AMD IOMMUv2 loaded and initialized\n"); +- + return 0; + + out: +diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile +index 1338466d4d0d..54feb1ecccad 100644 +--- a/drivers/iommu/arm/arm-smmu-v3/Makefile ++++ b/drivers/iommu/arm/arm-smmu-v3/Makefile +@@ -3,4 +3,3 @@ obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o + arm_smmu_v3-objs-y += arm-smmu-v3.o + arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o + arm_smmu_v3-objs := $(arm_smmu_v3-objs-y) +-obj-$(CONFIG_AGENT_SMMU_ATOS) += ascend_smmu.o +diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +index a8e8fd9d7c8b..01094d348774 100644 +--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c ++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +@@ -351,13 +351,15 @@ __arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm) + bond->smmu_mn = arm_smmu_mmu_notifier_get(smmu_domain, mm); + if (IS_ERR(bond->smmu_mn)) { + ret = PTR_ERR(bond->smmu_mn); +- goto err_free_bond; ++ goto err_free_pasid; + } + + list_add(&bond->list, &master->bonds); + trace_smmu_bind_alloc(dev, mm->pasid); + return &bond->sva; + ++err_free_pasid: ++ iommu_sva_free_pasid(mm); + err_free_bond: + kfree(bond); + return ERR_PTR(ret); +@@ -401,6 +403,7 @@ void arm_smmu_sva_unbind(struct iommu_sva *handle) + trace_smmu_unbind_free(handle->dev, bond->mm->pasid); + list_del(&bond->list); + arm_smmu_mmu_notifier_put(bond->smmu_mn); ++ iommu_sva_free_pasid(bond->mm); + kfree(bond); + } else { + trace_smmu_unbind_put(handle->dev, bond->mm->pasid); +@@ -420,6 +423,8 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) + unsigned long reg, fld; + unsigned long oas; + unsigned long asid_bits; ++ ++#ifndef CONFIG_VENDOR_NPU + u32 feat_mask = ARM_SMMU_FEAT_COHERENCY; + + if (vabits_actual == 52) +@@ -427,6 +432,7 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) + + if ((smmu->features & feat_mask) != feat_mask) + return false; ++#endif + + if (!(smmu->pgsize_bitmap & PAGE_SIZE)) + return false; +@@ -591,3 +597,13 @@ void arm_smmu_sva_notifier_synchronize(void) + */ + mmu_notifier_synchronize(); + } ++ ++void arm_smmu_sva_mm_invalidate_range(struct iommu_domain *domain, ++ struct mm_struct *mm, unsigned long start, unsigned long size) ++{ ++ unsigned long asid = arm64_mm_context_get(mm); ++ struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); ++ arm_smmu_tlb_inv_range_asid(start, size, asid, ++ PAGE_SIZE, false, smmu_domain); ++ arm64_mm_context_put(mm); ++} +diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +index 1ee14a59a3d6..14dbc7785605 100644 +--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c ++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +@@ -11,7 +11,6 @@ + + #include + #include +-#include + #include + #include + #include +@@ -30,11 +29,10 @@ + #include + #include + #include +- + #include + +-#include "arm-smmu-v3.h" + #include "../../iommu-sva-lib.h" ++#include "arm-smmu-v3.h" + + static bool disable_bypass = true; + module_param(disable_bypass, bool, 0444); +@@ -46,42 +44,6 @@ module_param(disable_msipolling, bool, 0444); + MODULE_PARM_DESC(disable_msipolling, + "Disable MSI-based polling for CMD_SYNC completion."); + +-#ifdef CONFIG_SMMU_BYPASS_DEV +-struct smmu_bypass_device { +- unsigned short vendor; +- unsigned short device; +-}; +-#define MAX_CMDLINE_SMMU_BYPASS_DEV 16 +- +-static struct smmu_bypass_device smmu_bypass_devices[MAX_CMDLINE_SMMU_BYPASS_DEV]; +-static int smmu_bypass_devices_num; +- +-static int __init arm_smmu_bypass_dev_setup(char *str) +-{ +- unsigned short vendor; +- unsigned short device; +- int ret; +- +- if (!str) +- return -EINVAL; +- +- ret = sscanf(str, "%hx:%hx", &vendor, &device); +- if (ret != 2) +- return -EINVAL; +- +- if (smmu_bypass_devices_num >= MAX_CMDLINE_SMMU_BYPASS_DEV) +- return -ERANGE; +- +- smmu_bypass_devices[smmu_bypass_devices_num].vendor = vendor; +- smmu_bypass_devices[smmu_bypass_devices_num].device = device; +- smmu_bypass_devices_num++; +- +- return 0; +-} +- +-__setup("smmu.bypassdev=", arm_smmu_bypass_dev_setup); +-#endif +- + enum arm_smmu_msi_index { + EVTQ_MSI_INDEX, + GERROR_MSI_INDEX, +@@ -89,6 +51,7 @@ enum arm_smmu_msi_index { + ARM_SMMU_MAX_MSIS, + }; + ++#ifdef CONFIG_ACPI + static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { + [EVTQ_MSI_INDEX] = { + ARM_SMMU_EVTQ_IRQ_CFG0, +@@ -106,6 +69,7 @@ static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { + ARM_SMMU_PRIQ_IRQ_CFG2, + }, + }; ++#endif + + struct arm_smmu_option_prop { + u32 opt; +@@ -123,7 +87,7 @@ static DECLARE_IOASID_SET(private_ioasid); + struct arm_smmu_ctx_desc quiet_cd = { 0 }; + + static struct arm_smmu_option_prop arm_smmu_options[] = { +- { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" }, ++ { ARM_SMMU_OPT_SKIP_PREFETCH, "vendor,broken-prefetch-cmd" }, + { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"}, + { 0, NULL}, + }; +@@ -273,18 +237,6 @@ static int queue_remove_raw(struct arm_smmu_queue *q, u64 *ent) + return 0; + } + +-static void arm_smmu_preempt_disable(struct arm_smmu_device *smmu) +-{ +- if (smmu->ecmdq_enabled) +- preempt_disable(); +-} +- +-static void arm_smmu_preempt_enable(struct arm_smmu_device *smmu) +-{ +- if (smmu->ecmdq_enabled) +- preempt_enable(); +-} +- + /* High-level queue accessors */ + static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) + { +@@ -381,22 +333,10 @@ static int arm_smmu_cmdq_build_cmd(u64 *cmd, struct arm_smmu_cmdq_ent *ent) + return 0; + } + +-static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu) +-{ +- if (smmu->ecmdq_enabled) { +- struct arm_smmu_ecmdq *ecmdq; +- +- ecmdq = *this_cpu_ptr(smmu->ecmdqs); +- +- return &ecmdq->cmdq; +- } +- +- return &smmu->cmdq; +-} +- + static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, +- struct arm_smmu_queue *q, u32 prod) ++ u32 prod) + { ++ struct arm_smmu_queue *q = &smmu->cmdq.q; + struct arm_smmu_cmdq_ent ent = { + .opcode = CMDQ_OP_CMD_SYNC, + }; +@@ -413,8 +353,7 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, + arm_smmu_cmdq_build_cmd(cmd, &ent); + } + +-static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, +- struct arm_smmu_queue *q) ++static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) + { + static const char *cerror_str[] = { + [CMDQ_ERR_CERROR_NONE_IDX] = "No error", +@@ -425,6 +364,7 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, + + int i; + u64 cmd[CMDQ_ENT_DWORDS]; ++ struct arm_smmu_queue *q = &smmu->cmdq.q; + u32 cons = readl_relaxed(q->cons_reg); + u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons); + struct arm_smmu_cmdq_ent cmd_sync = { +@@ -470,43 +410,6 @@ static void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, + queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); + } + +-static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) +-{ +- __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq.q); +-} +- +-static void arm_smmu_ecmdq_skip_err(struct arm_smmu_device *smmu) +-{ +- int i; +- u32 prod, cons; +- struct arm_smmu_queue *q; +- struct arm_smmu_ecmdq *ecmdq; +- +- for (i = 0; i < smmu->nr_ecmdq; i++) { +- unsigned long flags; +- +- ecmdq = *per_cpu_ptr(smmu->ecmdqs, i); +- q = &ecmdq->cmdq.q; +- +- prod = readl_relaxed(q->prod_reg); +- cons = readl_relaxed(q->cons_reg); +- if (((prod ^ cons) & ECMDQ_CONS_ERR) == 0) +- continue; +- +- __arm_smmu_cmdq_skip_err(smmu, q); +- +- write_lock_irqsave(&q->ecmdq_lock, flags); +- q->ecmdq_prod &= ~ECMDQ_PROD_ERRACK; +- q->ecmdq_prod |= cons & ECMDQ_CONS_ERR; +- +- prod = readl_relaxed(q->prod_reg); +- prod &= ~ECMDQ_PROD_ERRACK; +- prod |= cons & ECMDQ_CONS_ERR; +- writel(prod, q->prod_reg); +- write_unlock_irqrestore(&q->ecmdq_lock, flags); +- } +-} +- + /* + * Command queue locking. + * This is a form of bastardised rwlock with the following major changes: +@@ -673,7 +576,7 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, + { + unsigned long flags; + struct arm_smmu_queue_poll qp; +- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); ++ struct arm_smmu_cmdq *cmdq = &smmu->cmdq; + int ret = 0; + + /* +@@ -689,7 +592,7 @@ static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, + + queue_poll_init(smmu, &qp); + do { +- llq->val = READ_ONCE(cmdq->q.llq.val); ++ llq->val = READ_ONCE(smmu->cmdq.q.llq.val); + if (!queue_full(llq)) + break; + +@@ -708,7 +611,7 @@ static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, + { + int ret = 0; + struct arm_smmu_queue_poll qp; +- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); ++ struct arm_smmu_cmdq *cmdq = &smmu->cmdq; + u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); + + queue_poll_init(smmu, &qp); +@@ -731,12 +634,12 @@ static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, + struct arm_smmu_ll_queue *llq) + { + struct arm_smmu_queue_poll qp; +- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); ++ struct arm_smmu_cmdq *cmdq = &smmu->cmdq; + u32 prod = llq->prod; + int ret = 0; + + queue_poll_init(smmu, &qp); +- llq->val = READ_ONCE(cmdq->q.llq.val); ++ llq->val = READ_ONCE(smmu->cmdq.q.llq.val); + do { + if (queue_consumed(llq, prod)) + break; +@@ -803,87 +706,6 @@ static void arm_smmu_cmdq_write_entries(struct arm_smmu_cmdq *cmdq, u64 *cmds, + } + } + +-/* +- * The function is used when the current core exclusively occupies an ECMDQ. +- * This is a reduced version of arm_smmu_cmdq_issue_cmdlist(), which eliminates +- * a lot of unnecessary inter-core competition considerations. +- */ +-static int arm_smmu_ecmdq_issue_cmdlist(struct arm_smmu_device *smmu, +- struct arm_smmu_cmdq *cmdq, +- u64 *cmds, int n, bool sync) +-{ +- u32 prod; +- unsigned long flags; +- struct arm_smmu_ll_queue llq = { +- .max_n_shift = cmdq->q.llq.max_n_shift, +- }, head; +- int ret = 0; +- +- /* 1. Allocate some space in the queue */ +- local_irq_save(flags); +- llq.val = READ_ONCE(cmdq->q.llq.val); +- do { +- u64 old; +- +- while (!queue_has_space(&llq, n + sync)) { +- local_irq_restore(flags); +- if (arm_smmu_cmdq_poll_until_not_full(smmu, &llq)) +- dev_err_ratelimited(smmu->dev, "ECMDQ timeout\n"); +- local_irq_save(flags); +- } +- +- head.cons = llq.cons; +- head.prod = queue_inc_prod_n(&llq, n + sync); +- +- old = cmpxchg_relaxed(&cmdq->q.llq.val, llq.val, head.val); +- if (old == llq.val) +- break; +- +- llq.val = old; +- } while (1); +- +- /* 2. Write our commands into the queue */ +- arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); +- if (sync) { +- u64 cmd_sync[CMDQ_ENT_DWORDS]; +- +- prod = queue_inc_prod_n(&llq, n); +- arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); +- queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); +- } +- +- /* 3. Ensuring commands are visible first */ +- dma_wmb(); +- +- /* 4. Advance the hardware prod pointer */ +- read_lock(&cmdq->q.ecmdq_lock); +- writel_relaxed(head.prod | cmdq->q.ecmdq_prod, cmdq->q.prod_reg); +- read_unlock(&cmdq->q.ecmdq_lock); +- +- /* 5. If we are inserting a CMD_SYNC, we must wait for it to complete */ +- if (sync) { +- llq.prod = queue_inc_prod_n(&llq, n); +- ret = arm_smmu_cmdq_poll_until_sync(smmu, &llq); +- if (ret) { +- dev_err_ratelimited(smmu->dev, +- "CMD_SYNC timeout at 0x%08x [hwprod 0x%08x, hwcons 0x%08x]\n", +- llq.prod, +- readl_relaxed(cmdq->q.prod_reg), +- readl_relaxed(cmdq->q.cons_reg)); +- } +- +- /* +- * Update cmdq->q.llq.cons, to improve the success rate of +- * queue_has_space() when some new commands are inserted next +- * time. +- */ +- WRITE_ONCE(cmdq->q.llq.cons, llq.cons); +- } +- +- local_irq_restore(flags); +- return ret; +-} +- + /* + * This is the actual insertion function, and provides the following + * ordering guarantees to callers: +@@ -907,15 +729,12 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + u32 prod; + unsigned long flags; + bool owner; +- struct arm_smmu_cmdq *cmdq = arm_smmu_get_cmdq(smmu); ++ struct arm_smmu_cmdq *cmdq = &smmu->cmdq; + struct arm_smmu_ll_queue llq = { + .max_n_shift = cmdq->q.llq.max_n_shift, + }, head = llq; + int ret = 0; + +- if (!cmdq->shared) +- return arm_smmu_ecmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); +- + /* 1. Allocate some space in the queue */ + local_irq_save(flags); + llq.val = READ_ONCE(cmdq->q.llq.val); +@@ -950,7 +769,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + arm_smmu_cmdq_write_entries(cmdq, cmds, llq.prod, n); + if (sync) { + prod = queue_inc_prod_n(&llq, n); +- arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, &cmdq->q, prod); ++ arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, prod); + queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); + + /* +@@ -987,13 +806,7 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + * d. Advance the hardware prod pointer + * Control dependency ordering from the entries becoming valid. + */ +- if (smmu->ecmdq_enabled) { +- read_lock(&cmdq->q.ecmdq_lock); +- writel_relaxed(prod | cmdq->q.ecmdq_prod, cmdq->q.prod_reg); +- read_unlock(&cmdq->q.ecmdq_lock); +- } else { +- writel_relaxed(prod, cmdq->q.prod_reg); +- } ++ writel_relaxed(prod, cmdq->q.prod_reg); + + /* + * e. Tell the next owner we're done +@@ -1029,9 +842,8 @@ static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + return ret; + } + +-static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, +- struct arm_smmu_cmdq_ent *ent, +- bool sync) ++static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, ++ struct arm_smmu_cmdq_ent *ent) + { + u64 cmd[CMDQ_ENT_DWORDS]; + +@@ -1041,19 +853,12 @@ static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, + return -EINVAL; + } + +- return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, sync); +-} +- +-static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, +- struct arm_smmu_cmdq_ent *ent) +-{ +- return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); ++ return arm_smmu_cmdq_issue_cmdlist(smmu, cmd, 1, false); + } + +-static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, +- struct arm_smmu_cmdq_ent *ent) ++static int arm_smmu_cmdq_issue_sync(struct arm_smmu_device *smmu) + { +- return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); ++ return arm_smmu_cmdq_issue_cmdlist(smmu, NULL, 0, true); + } + + static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, +@@ -1144,7 +949,8 @@ void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) + .tlbi.asid = asid, + }; + +- arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); ++ arm_smmu_cmdq_issue_cmd(smmu, &cmd); ++ arm_smmu_cmdq_issue_sync(smmu); + } + + static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, +@@ -1163,7 +969,6 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, + }, + }; + +- arm_smmu_preempt_disable(smmu); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + for (i = 0; i < master->num_streams; i++) { +@@ -1174,7 +979,6 @@ static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_cmdq_batch_submit(smmu, &cmds); +- arm_smmu_preempt_enable(smmu); + } + + static int arm_smmu_alloc_cd_leaf_table(struct arm_smmu_device *smmu, +@@ -1438,7 +1242,8 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) + }, + }; + +- arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); ++ arm_smmu_cmdq_issue_cmd(smmu, &cmd); ++ arm_smmu_cmdq_issue_sync(smmu); + } + + static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, +@@ -1764,7 +1569,6 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev) + dev_info(smmu->dev, "\t0x%016llx\n", + (unsigned long long)evt[i]); + +- cond_resched(); + } + + /* +@@ -1981,9 +1785,6 @@ static irqreturn_t arm_smmu_gerror_handler(int irq, void *dev) + if (active & GERROR_CMDQ_ERR) + arm_smmu_cmdq_skip_err(smmu); + +- if (active & GERROR_CMDQP_ERR) +- arm_smmu_ecmdq_skip_err(smmu); +- + writel(gerror, smmu->base + ARM_SMMU_GERRORN); + return IRQ_HANDLED; + } +@@ -1999,11 +1800,55 @@ static irqreturn_t arm_smmu_combined_irq_thread(int irq, void *dev) + return IRQ_HANDLED; + } + ++#ifndef CONFIG_VENDOR_NPU + static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) + { + arm_smmu_gerror_handler(irq, dev); + return IRQ_WAKE_THREAD; + } ++#else ++static irqreturn_t arm_smmu_evtq_handler(int irq, void *dev) ++{ ++ return IRQ_WAKE_THREAD; ++} ++ ++static irqreturn_t arm_smmu_cmdq_sync_handler(int irq, void *dev) ++{ ++ struct arm_smmu_device *smmu = dev; ++ /* We don't actually use CMD_SYNC interrupts for anything */ ++ dev_warn(smmu->dev, "Receive cmdq_sync interrupt=======================>\n"); ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t arm_smmu_combined_irq_handler(int irq, void *dev) ++{ ++ irqreturn_t ret = IRQ_NONE; ++ u32 irq_status = 0; ++ u32 raw_irq_status = 0; ++ u32 reg = (TCU_EVENT_Q_IRQ_CLR | TCU_CMD_SYNC_IRQ_CLR | ++ TCU_GERROR_IRQ_CLR | TCU_EVENTTO_CLR); ++ struct arm_smmu_device *smmu = (struct arm_smmu_device *)dev; ++ ++ irq_status = readl_relaxed(smmu->base + SMMU_IRPT_STAT_NS); ++ raw_irq_status = readl_relaxed(smmu->base + SMMU_IRPT_RAW_NS); ++ dev_dbg(smmu->dev, "irq info: status:0x%x,raw_status:0x%x\n", irq_status, raw_irq_status); ++ writel_relaxed(reg, smmu->base + SMMU_IRPT_CLR_NS); ++ ++ if (irq_status & TCU_EVENT_Q_IRQ) ++ ret = arm_smmu_evtq_handler(irq, smmu); ++ ++ if (irq_status & TCU_CMD_SYNC_IRQ) ++ ret |= arm_smmu_cmdq_sync_handler(irq, dev); ++ ++ if (irq_status & TCU_GERROR_IRQ) ++ ret |= arm_smmu_gerror_handler(irq, dev); ++ ++ if (ret & IRQ_WAKE_THREAD) ++ return IRQ_WAKE_THREAD; ++ else ++ return ret; ++} ++#endif + + static void + arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, +@@ -2074,36 +1919,29 @@ arm_smmu_atc_inv_to_cmd(int ssid, unsigned long iova, size_t size, + + static int arm_smmu_atc_inv_master(struct arm_smmu_master *master, unsigned int ssid) + { +- int i, ret; ++ int i; + struct arm_smmu_cmdq_ent cmd; +- struct arm_smmu_cmdq_batch cmds = {}; +- struct arm_smmu_device *smmu = master->smmu; + + arm_smmu_atc_inv_to_cmd(ssid, 0, 0, &cmd); + +- arm_smmu_preempt_disable(smmu); + for (i = 0; i < master->num_streams; i++) { + cmd.atc.sid = master->streams[i].id; +- arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); ++ arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); + } + +- ret = arm_smmu_cmdq_batch_submit(smmu, &cmds); +- arm_smmu_preempt_enable(smmu); +- +- return ret; ++ return arm_smmu_cmdq_issue_sync(master->smmu); + } + + int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, + unsigned long iova, size_t size) + { +- int i, ret; ++ int i; + unsigned long flags; + struct arm_smmu_cmdq_ent cmd; + struct arm_smmu_master *master; + struct arm_smmu_cmdq_batch cmds = {}; +- struct arm_smmu_device *smmu = smmu_domain->smmu; + +- if (!(smmu->features & ARM_SMMU_FEAT_ATS)) ++ if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) + return 0; + + /* +@@ -2125,7 +1963,6 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, + + arm_smmu_atc_inv_to_cmd(ssid, iova, size, &cmd); + +- arm_smmu_preempt_disable(smmu); + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + if (!master->ats_enabled) +@@ -2133,15 +1970,12 @@ int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, + + for (i = 0; i < master->num_streams; i++) { + cmd.atc.sid = master->streams[i].id; +- arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); ++ arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + +- ret = arm_smmu_cmdq_batch_submit(smmu, &cmds); +- arm_smmu_preempt_enable(smmu); +- +- return ret; ++ return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); + } + + /* IO_PGTABLE API */ +@@ -2163,7 +1997,8 @@ static void arm_smmu_tlb_inv_context(void *cookie) + } else { + cmd.opcode = CMDQ_OP_TLBI_S12_VMALL; + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; +- arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); ++ arm_smmu_cmdq_issue_cmd(smmu, &cmd); ++ arm_smmu_cmdq_issue_sync(smmu); + } + if (smmu_domain->parent) + arm_smmu_atc_inv_domain(smmu_domain->parent, smmu_domain->ssid, +@@ -2199,7 +2034,6 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, + num_pages = size >> tg; + } + +- arm_smmu_preempt_disable(smmu); + while (iova < end) { + if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { + /* +@@ -2231,7 +2065,6 @@ static void __arm_smmu_tlb_inv_range(struct arm_smmu_cmdq_ent *cmd, + iova += inv_range; + } + arm_smmu_cmdq_batch_submit(smmu, &cmds); +- arm_smmu_preempt_enable(smmu); + } + + static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, +@@ -2385,7 +2218,7 @@ static void arm_smmu_domain_free(struct iommu_domain *domain) + arm_smmu_free_asid(&cfg->cd); + mutex_unlock(&arm_smmu_asid_lock); + if (smmu_domain->ssid) +- ioasid_free(smmu_domain->ssid); ++ ioasid_put(smmu_domain->ssid); + } else { + struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; + if (cfg->vmid) +@@ -2420,7 +2253,6 @@ static int arm_smmu_domain_finalise_cd(struct arm_smmu_domain *smmu_domain, + FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | + FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | + FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | +- CTXDESC_CD_0_TCR_HA | CTXDESC_CD_0_TCR_HD | + CTXDESC_CD_0_TCR_EPD1 | CTXDESC_CD_0_AA64; + cfg->cd.mair = pgtbl_cfg->arm_lpae_s1_cfg.mair; + return 0; +@@ -2552,13 +2384,6 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, + + if (smmu_domain->non_strict) + pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_NON_STRICT; +- if (smmu->features & ARM_SMMU_FEAT_HD) +- pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_HD; +- +- if (smmu->features & ARM_SMMU_FEAT_BBML1) +- pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_BBML1; +- else if (smmu->features & ARM_SMMU_FEAT_BBML2) +- pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_BBML2; + + pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain); + if (!pgtbl_ops) +@@ -2912,7 +2737,6 @@ static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, + static void arm_smmu_flush_iotlb_all(struct iommu_domain *domain) + { + struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- + if (smmu_domain->smmu) + arm_smmu_tlb_inv_context(smmu_domain); + } +@@ -3059,10 +2883,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) + struct arm_smmu_device *smmu; + struct arm_smmu_master *master; + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); +-#ifdef CONFIG_ASCEND_FEATURES +- u32 sid; +- const union acpi_object *obj = NULL; +-#endif + + if (!fwspec || fwspec->ops != &arm_smmu_ops) + return ERR_PTR(-ENODEV); +@@ -3109,16 +2929,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) + smmu->features & ARM_SMMU_FEAT_STALL_FORCE) + master->stall_enabled = true; + +-#ifdef CONFIG_ASCEND_FEATURES +- if (!acpi_dev_get_property(ACPI_COMPANION(dev), +- "streamid", ACPI_TYPE_INTEGER, &obj) && obj) { +- sid = obj->integer.value; +- if (iommu_fwspec_add_ids(dev, &sid, 1)) +- dev_info(dev, "failed to add ids\n"); +- master->stall_enabled = true; +- master->ssid_bits = 0x10; +- } +-#endif + arm_smmu_init_pri(master); + + return &smmu->iommu; +@@ -3239,274 +3049,73 @@ static int arm_smmu_domain_set_attr(struct iommu_domain *domain, + return ret; + } + +-static int arm_smmu_split_block(struct iommu_domain *domain, +- unsigned long iova, size_t size) ++static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) + { +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- struct arm_smmu_device *smmu = smmu_domain->smmu; +- struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; +- size_t handled_size; +- +- if (!(smmu->features & (ARM_SMMU_FEAT_BBML1 | ARM_SMMU_FEAT_BBML2))) { +- dev_err(smmu->dev, "don't support BBML1/2, can't split block\n"); +- return -ENODEV; +- } +- if (!ops || !ops->split_block) { +- pr_err("io-pgtable don't realize split block\n"); +- return -ENODEV; +- } +- +- handled_size = ops->split_block(ops, iova, size); +- if (handled_size != size) { +- pr_err("split block failed\n"); +- return -EFAULT; +- } +- +- return 0; ++ return iommu_fwspec_add_ids(dev, args->args, 1); + } + +-static int __arm_smmu_merge_page(struct iommu_domain *domain, +- unsigned long iova, phys_addr_t paddr, +- size_t size, int prot) ++static void arm_smmu_get_resv_regions(struct device *dev, ++ struct list_head *head) + { +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; +- size_t handled_size; +- +- if (!ops || !ops->merge_page) { +- pr_err("io-pgtable don't realize merge page\n"); +- return -ENODEV; +- } +- +- while (size) { +- size_t pgsize = iommu_pgsize(domain, iova | paddr, size); +- +- handled_size = ops->merge_page(ops, iova, paddr, pgsize, prot); +- if (handled_size != pgsize) { +- pr_err("merge page failed\n"); +- return -EFAULT; +- } ++ struct iommu_resv_region *region; ++ int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; + +- pr_debug("merge handled: iova 0x%lx pa %pa size 0x%zx\n", +- iova, &paddr, pgsize); ++ region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, ++ prot, IOMMU_RESV_SW_MSI); ++ if (!region) ++ return; + +- iova += pgsize; +- paddr += pgsize; +- size -= pgsize; +- } ++ list_add_tail(®ion->list, head); + +- return 0; ++ iommu_dma_get_resv_regions(dev, head); + } + +-static int arm_smmu_merge_page(struct iommu_domain *domain, unsigned long iova, +- size_t size, int prot) ++static bool arm_smmu_dev_has_feature(struct device *dev, ++ enum iommu_dev_features feat) + { +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- struct arm_smmu_device *smmu = smmu_domain->smmu; +- struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; +- phys_addr_t phys; +- dma_addr_t p, i; +- size_t cont_size; +- int ret = 0; +- +- if (!(smmu->features & (ARM_SMMU_FEAT_BBML1 | ARM_SMMU_FEAT_BBML2))) { +- dev_err(smmu->dev, "don't support BBML1/2, can't merge page\n"); +- return -ENODEV; +- } +- +- if (!ops || !ops->iova_to_phys) +- return -ENODEV; +- +- while (size) { +- phys = ops->iova_to_phys(ops, iova); +- cont_size = PAGE_SIZE; +- p = phys + cont_size; +- i = iova + cont_size; +- +- while (cont_size < size && p == ops->iova_to_phys(ops, i)) { +- p += PAGE_SIZE; +- i += PAGE_SIZE; +- cont_size += PAGE_SIZE; +- } ++ struct arm_smmu_master *master = dev_iommu_priv_get(dev); + +- if (cont_size != PAGE_SIZE) { +- ret = __arm_smmu_merge_page(domain, iova, phys, +- cont_size, prot); +- if (ret) +- break; +- } ++ if (!master) ++ return false; + +- iova += cont_size; +- size -= cont_size; ++ switch (feat) { ++ case IOMMU_DEV_FEAT_IOPF: ++ return arm_smmu_master_iopf_supported(master); ++ case IOMMU_DEV_FEAT_SVA: ++ return arm_smmu_master_sva_supported(master); ++ case IOMMU_DEV_FEAT_AUX: ++ return master->ssid_bits != 0; ++ default: ++ return false; + } +- +- return ret; + } + +-static bool arm_smmu_support_dirty_log(struct iommu_domain *domain) ++static bool arm_smmu_dev_feature_enabled(struct device *dev, ++ enum iommu_dev_features feat) + { +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); ++ struct arm_smmu_master *master = dev_iommu_priv_get(dev); ++ ++ if (!master) ++ return false; + +- return !!(smmu_domain->smmu->features & ARM_SMMU_FEAT_HD); ++ switch (feat) { ++ case IOMMU_DEV_FEAT_IOPF: ++ return master->iopf_enabled; ++ case IOMMU_DEV_FEAT_SVA: ++ return arm_smmu_master_sva_enabled(master); ++ case IOMMU_DEV_FEAT_AUX: ++ return master->auxd_enabled; ++ default: ++ return false; ++ } + } + +-static int arm_smmu_switch_dirty_log(struct iommu_domain *domain, bool enable, +- unsigned long iova, size_t size, int prot) ++static int arm_smmu_dev_enable_feature(struct device *dev, ++ enum iommu_dev_features feat) + { +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- struct arm_smmu_device *smmu = smmu_domain->smmu; ++ struct arm_smmu_master *master = dev_iommu_priv_get(dev); + +- if (!(smmu->features & ARM_SMMU_FEAT_HD)) +- return -ENODEV; +- if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) +- return -EINVAL; +- +- if (enable) { +- /* +- * For SMMU, the hardware dirty management is always enabled if +- * hardware supports HTTU HD. The action to start dirty log is +- * spliting block mapping. +- * +- * We don't return error even if the split operation fail, as we +- * can still track dirty at block granule, which is still a much +- * better choice compared to full dirty policy. +- */ +- arm_smmu_split_block(domain, iova, size); +- } else { +- /* +- * For SMMU, the hardware dirty management is always enabled if +- * hardware supports HTTU HD. The action to stop dirty log is +- * merging page mapping. +- * +- * We don't return error even if the merge operation fail, as it +- * just effects performace of DMA transaction. +- */ +- arm_smmu_merge_page(domain, iova, size, prot); +- } +- +- return 0; +-} +- +-static int arm_smmu_sync_dirty_log(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; +- struct arm_smmu_device *smmu = smmu_domain->smmu; +- +- if (!(smmu->features & ARM_SMMU_FEAT_HD)) +- return -ENODEV; +- if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) +- return -EINVAL; +- +- if (!ops || !ops->sync_dirty_log) { +- pr_err("io-pgtable don't realize sync dirty log\n"); +- return -ENODEV; +- } +- +- /* +- * Flush iotlb to ensure all inflight transactions are completed. +- * See doc IHI0070Da 3.13.4 "HTTU behavior summary". +- */ +- arm_smmu_flush_iotlb_all(domain); +- return ops->sync_dirty_log(ops, iova, size, bitmap, base_iova, +- bitmap_pgshift); +-} +- +-static int arm_smmu_clear_dirty_log(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); +- struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; +- struct arm_smmu_device *smmu = smmu_domain->smmu; +- +- if (!(smmu->features & ARM_SMMU_FEAT_HD)) +- return -ENODEV; +- if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) +- return -EINVAL; +- +- if (!ops || !ops->clear_dirty_log) { +- pr_err("io-pgtable don't realize clear dirty log\n"); +- return -ENODEV; +- } +- +- return ops->clear_dirty_log(ops, iova, size, bitmap, base_iova, +- bitmap_pgshift); +-} +- +-static int arm_smmu_of_xlate(struct device *dev, struct of_phandle_args *args) +-{ +- return iommu_fwspec_add_ids(dev, args->args, 1); +-} +- +-static void arm_smmu_get_resv_regions(struct device *dev, +- struct list_head *head) +-{ +- struct iommu_resv_region *region; +- int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO; +- +- region = iommu_alloc_resv_region(MSI_IOVA_BASE, MSI_IOVA_LENGTH, +- prot, IOMMU_RESV_SW_MSI); +- if (!region) +- return; +- +- list_add_tail(®ion->list, head); +- +- iommu_dma_get_resv_regions(dev, head); +-} +- +-static bool arm_smmu_dev_has_feature(struct device *dev, +- enum iommu_dev_features feat) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- +- if (!master) +- return false; +- +- switch (feat) { +- case IOMMU_DEV_FEAT_IOPF: +- return arm_smmu_master_iopf_supported(master); +- case IOMMU_DEV_FEAT_SVA: +- return arm_smmu_master_sva_supported(master); +- case IOMMU_DEV_FEAT_AUX: +- return master->ssid_bits != 0; +- default: +- return false; +- } +-} +- +-static bool arm_smmu_dev_feature_enabled(struct device *dev, +- enum iommu_dev_features feat) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- +- if (!master) +- return false; +- +- switch (feat) { +- case IOMMU_DEV_FEAT_IOPF: +- return master->iopf_enabled; +- case IOMMU_DEV_FEAT_SVA: +- return arm_smmu_master_sva_enabled(master); +- case IOMMU_DEV_FEAT_AUX: +- return master->auxd_enabled; +- default: +- return false; +- } +-} +- +-static int arm_smmu_dev_enable_feature(struct device *dev, +- enum iommu_dev_features feat) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- +- if (!arm_smmu_dev_has_feature(dev, feat)) ++ if (!arm_smmu_dev_has_feature(dev, feat)) + return -ENODEV; + + if (arm_smmu_dev_feature_enabled(dev, feat)) +@@ -3590,7 +3199,7 @@ static int arm_smmu_aux_attach_dev(struct iommu_domain *domain, struct device *d + smmu_domain->smmu = NULL; + smmu_domain->ssid = 0; + smmu_domain->parent = NULL; +- ioasid_free(ssid); ++ ioasid_put(ssid); + goto out_unlock; + } + } else if (smmu_domain->parent != parent_smmu_domain) { +@@ -3662,290 +3271,6 @@ static int arm_smmu_aux_get_pasid(struct iommu_domain *domain, struct device *de + return smmu_domain->ssid ?: -EINVAL; + } + +-static int arm_smmu_set_mpam(struct arm_smmu_device *smmu, +- int sid, int ssid, int partid, int pmg, int s1mpam) +-{ +- struct arm_smmu_master *master = arm_smmu_find_master(smmu, sid); +- struct arm_smmu_domain *domain = master ? master->domain : NULL; +- u64 val; +- __le64 *ste, *cd; +- +- struct arm_smmu_cmdq_ent prefetch_cmd = { +- .opcode = CMDQ_OP_PREFETCH_CFG, +- .prefetch = { +- .sid = sid, +- }, +- }; +- +- if (WARN_ON(!domain)) +- return -EINVAL; +- if (WARN_ON(domain->stage != ARM_SMMU_DOMAIN_S1)) +- return -EINVAL; +- if (WARN_ON(ssid >= (1 << domain->s1_cfg.s1cdmax))) +- return -E2BIG; +- +- if (!(smmu->features & ARM_SMMU_FEAT_MPAM)) +- return -ENODEV; +- +- if (partid > smmu->mpam_partid_max || pmg > smmu->mpam_pmg_max) { +- dev_err(smmu->dev, +- "mpam rmid out of range: partid[0, %d] pmg[0, %d]\n", +- smmu->mpam_partid_max, smmu->mpam_pmg_max); +- return -ERANGE; +- } +- +- /* get ste ptr */ +- ste = arm_smmu_get_step_for_sid(smmu, sid); +- +- /* write s1mpam to ste */ +- val = le64_to_cpu(ste[1]); +- val &= ~STRTAB_STE_1_S1MPAM; +- val |= FIELD_PREP(STRTAB_STE_1_S1MPAM, s1mpam); +- WRITE_ONCE(ste[1], cpu_to_le64(val)); +- +- val = le64_to_cpu(ste[4]); +- val &= ~STRTAB_STE_4_PARTID_MASK; +- val |= FIELD_PREP(STRTAB_STE_4_PARTID_MASK, partid); +- WRITE_ONCE(ste[4], cpu_to_le64(val)); +- +- val = le64_to_cpu(ste[5]); +- val &= ~STRTAB_STE_5_PMG_MASK; +- val |= FIELD_PREP(STRTAB_STE_5_PMG_MASK, pmg); +- WRITE_ONCE(ste[5], cpu_to_le64(val)); +- arm_smmu_sync_ste_for_sid(smmu, sid); +- +- /* do not modify cd table which owned by guest */ +- if (domain->stage == ARM_SMMU_DOMAIN_NESTED) { +- dev_err(smmu->dev, +- "mpam: smmu cd is owned by guest, not modified\n"); +- return 0; +- } +- +- /* get cd ptr */ +- cd = arm_smmu_get_cd_ptr(domain, ssid); +- if (s1mpam && WARN_ON(!cd)) +- return -ENOMEM; +- +- val = le64_to_cpu(cd[5]); +- val &= ~CTXDESC_CD_5_PARTID_MASK; +- val &= ~CTXDESC_CD_5_PMG_MASK; +- val |= FIELD_PREP(CTXDESC_CD_5_PARTID_MASK, partid); +- val |= FIELD_PREP(CTXDESC_CD_5_PMG_MASK, pmg); +- WRITE_ONCE(cd[5], cpu_to_le64(val)); +- arm_smmu_sync_cd(domain, ssid, true); +- +- /* It's likely that we'll want to use the new STE soon */ +- if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) +- arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); +- +- dev_info(smmu->dev, "partid %d, pmg %d\n", partid, pmg); +- +- return 0; +-} +- +-static int arm_smmu_set_dev_user_mpam_en(struct device *dev, int user_mpam_en) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- struct arm_smmu_device *smmu; +- u32 reg, __iomem *cfg; +- +- if (WARN_ON(!master)) +- return -EINVAL; +- +- smmu = master->domain->smmu; +- cfg = smmu->base + ARM_SMMU_USER_CFG0; +- +- reg = readl_relaxed(cfg); +- reg &= ~ARM_SMMU_USER_MPAM_EN; +- reg |= FIELD_PREP(ARM_SMMU_USER_MPAM_EN, user_mpam_en); +- writel(reg, cfg); +- return 0; +-} +- +-static int arm_smmu_device_set_mpam(struct device *dev, +- struct arm_smmu_mpam *mpam) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- int ret; +- +- if (WARN_ON(!master) || WARN_ON(!mpam)) +- return -EINVAL; +- +- if (mpam->flags & ARM_SMMU_DEV_SET_MPAM) { +- ret = arm_smmu_set_mpam(master->domain->smmu, +- master->streams->id, +- mpam->pasid, +- mpam->partid, +- mpam->pmg, +- mpam->s1mpam); +- if (ret < 0) +- return ret; +- } +- +- if (mpam->flags & ARM_SMMU_DEV_SET_USER_MPAM_EN) { +- ret = arm_smmu_set_dev_user_mpam_en(dev, mpam->user_mpam_en); +- if (ret < 0) +- return ret; +- } +- +- return 0; +- +-} +- +-static int arm_smmu_get_mpam(struct arm_smmu_device *smmu, +- int sid, int ssid, int *partid, int *pmg, int *s1mpam) +-{ +- struct arm_smmu_master *master = arm_smmu_find_master(smmu, sid); +- struct arm_smmu_domain *domain = master ? master->domain : NULL; +- u64 val; +- __le64 *ste, *cd; +- +- if (WARN_ON(!domain)) +- return -EINVAL; +- if (WARN_ON(domain->stage != ARM_SMMU_DOMAIN_S1)) +- return -EINVAL; +- if (WARN_ON(ssid >= (1 << domain->s1_cfg.s1cdmax))) +- return -E2BIG; +- +- if (!(smmu->features & ARM_SMMU_FEAT_MPAM)) +- return -ENODEV; +- +- /* get ste ptr */ +- ste = arm_smmu_get_step_for_sid(smmu, sid); +- +- val = le64_to_cpu(ste[4]); +- *partid = FIELD_GET(STRTAB_STE_4_PARTID_MASK, val); +- +- val = le64_to_cpu(ste[5]); +- *pmg = FIELD_GET(STRTAB_STE_5_PMG_MASK, val); +- +- val = le64_to_cpu(ste[1]); +- *s1mpam = FIELD_GET(STRTAB_STE_1_S1MPAM, val); +- /* return STE mpam configuration when s1mpam == 0 */ +- if (!(*s1mpam)) +- return 0; +- +- /* get cd ptr */ +- cd = arm_smmu_get_cd_ptr(domain, ssid); +- if (WARN_ON(!cd)) +- return -ENOMEM; +- +- val = le64_to_cpu(cd[5]); +- *partid = FIELD_GET(CTXDESC_CD_5_PARTID_MASK, val); +- *pmg = FIELD_GET(CTXDESC_CD_5_PMG_MASK, val); +- +- return 0; +-} +- +-static int arm_smmu_get_dev_user_mpam_en(struct device *dev, int *user_mpam_en) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- struct arm_smmu_device *smmu; +- u32 reg; +- +- if (WARN_ON(!master)) +- return -EINVAL; +- +- smmu = master->domain->smmu; +- +- reg = readl_relaxed(smmu->base + ARM_SMMU_USER_CFG0); +- *user_mpam_en = FIELD_GET(ARM_SMMU_USER_MPAM_EN, reg); +- return 0; +-} +- +-static int arm_smmu_device_get_mpam(struct device *dev, +- struct arm_smmu_mpam *mpam) +-{ +- struct arm_smmu_master *master = dev_iommu_priv_get(dev); +- int ret; +- +- if (WARN_ON(!master) || WARN_ON(!mpam)) +- return -EINVAL; +- +- if (mpam->flags & ARM_SMMU_DEV_GET_MPAM) { +- ret = arm_smmu_get_mpam(master->domain->smmu, +- master->streams->id, +- mpam->pasid, +- &mpam->partid, +- &mpam->pmg, +- &mpam->s1mpam); +- if (ret < 0) +- return ret; +- } +- +- if (mpam->flags & ARM_SMMU_DEV_GET_USER_MPAM_EN) { +- ret = arm_smmu_get_dev_user_mpam_en(dev, &mpam->user_mpam_en); +- if (ret < 0) +- return ret; +- } +- +- return 0; +-} +- +-static int arm_smmu_device_get_config(struct device *dev, int type, void *data) +-{ +- switch (type) { +- case ARM_SMMU_MPAM: +- return arm_smmu_device_get_mpam(dev, data); +- default: +- return -EINVAL; +- } +-} +- +-static int arm_smmu_device_set_config(struct device *dev, int type, void *data) +-{ +- switch (type) { +- case ARM_SMMU_MPAM: +- return arm_smmu_device_set_mpam(dev, data); +- default: +- return -EINVAL; +- } +-} +- +-/* +- * HiSilicon PCIe tune and trace device can be used to trace TLP headers on the +- * PCIe link and save the data to memory by DMA. The hardware is restricted to +- * use identity mapping only. +- */ +-#define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \ +- (pdev)->device == 0xa12e) +- +-#ifdef CONFIG_SMMU_BYPASS_DEV +-static int arm_smmu_bypass_dev_domain_type(struct device *dev) +-{ +- int i; +- struct pci_dev *pdev = to_pci_dev(dev); +- +- for (i = 0; i < smmu_bypass_devices_num; i++) { +- if ((smmu_bypass_devices[i].vendor == pdev->vendor) && +- (smmu_bypass_devices[i].device == pdev->device)) { +- dev_info(dev, "device 0x%hx:0x%hx uses identity mapping.", +- pdev->vendor, pdev->device); +- return IOMMU_DOMAIN_IDENTITY; +- } +- } +- +- return 0; +-} +-#endif +- +-static int arm_smmu_def_domain_type(struct device *dev) +-{ +- int ret = 0; +- +- if (dev_is_pci(dev)) { +- struct pci_dev *pdev = to_pci_dev(dev); +- +- if (IS_HISI_PTT_DEVICE(pdev)) +- return IOMMU_DOMAIN_IDENTITY; +- #ifdef CONFIG_SMMU_BYPASS_DEV +- ret = arm_smmu_bypass_dev_domain_type(dev); +- #endif +- } +- +- return ret; +-} +- + static struct iommu_ops arm_smmu_ops = { + .capable = arm_smmu_capable, + .domain_alloc = arm_smmu_domain_alloc, +@@ -3954,6 +3279,7 @@ static struct iommu_ops arm_smmu_ops = { + .map = arm_smmu_map, + .unmap = arm_smmu_unmap, + .flush_iotlb_all = arm_smmu_flush_iotlb_all, ++ .inv_iotlb_range = arm_smmu_sva_mm_invalidate_range, + .iotlb_sync = arm_smmu_iotlb_sync, + .iova_to_phys = arm_smmu_iova_to_phys, + .probe_device = arm_smmu_probe_device, +@@ -3961,10 +3287,6 @@ static struct iommu_ops arm_smmu_ops = { + .device_group = arm_smmu_device_group, + .domain_get_attr = arm_smmu_domain_get_attr, + .domain_set_attr = arm_smmu_domain_set_attr, +- .support_dirty_log = arm_smmu_support_dirty_log, +- .switch_dirty_log = arm_smmu_switch_dirty_log, +- .sync_dirty_log = arm_smmu_sync_dirty_log, +- .clear_dirty_log = arm_smmu_clear_dirty_log, + .of_xlate = arm_smmu_of_xlate, + .get_resv_regions = arm_smmu_get_resv_regions, + .put_resv_regions = generic_iommu_put_resv_regions, +@@ -3976,12 +3298,9 @@ static struct iommu_ops arm_smmu_ops = { + .sva_unbind = arm_smmu_sva_unbind, + .sva_get_pasid = arm_smmu_sva_get_pasid, + .page_response = arm_smmu_page_response, +- .def_domain_type = arm_smmu_def_domain_type, + .aux_attach_dev = arm_smmu_aux_attach_dev, + .aux_detach_dev = arm_smmu_aux_detach_dev, + .aux_get_pasid = arm_smmu_aux_get_pasid, +- .dev_get_config = arm_smmu_device_get_config, +- .dev_set_config = arm_smmu_device_set_config, + .pgsize_bitmap = -1UL, /* Restricted during device attach */ + }; + +@@ -4042,7 +3361,6 @@ static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) + unsigned int nents = 1 << cmdq->q.llq.max_n_shift; + atomic_long_t *bitmap; + +- cmdq->shared = 1; + atomic_set(&cmdq->owner_prod, 0); + atomic_set(&cmdq->lock, 0); + +@@ -4058,20 +3376,6 @@ static int arm_smmu_cmdq_init(struct arm_smmu_device *smmu) + return ret; + } + +-static int arm_smmu_ecmdq_init(struct arm_smmu_cmdq *cmdq) +-{ +- unsigned int nents = 1 << cmdq->q.llq.max_n_shift; +- +- atomic_set(&cmdq->owner_prod, 0); +- atomic_set(&cmdq->lock, 0); +- +- cmdq->valid_map = (atomic_long_t *)bitmap_zalloc(nents, GFP_KERNEL); +- if (!cmdq->valid_map) +- return -ENOMEM; +- +- return 0; +-} +- + static int arm_smmu_init_queues(struct arm_smmu_device *smmu) + { + int ret; +@@ -4140,58 +3444,12 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu) + return 0; + } + +-#ifdef CONFIG_SMMU_BYPASS_DEV +-static void arm_smmu_install_bypass_ste_for_dev(struct arm_smmu_device *smmu, +- u32 sid) +-{ +- u64 val; +- __le64 *step = arm_smmu_get_step_for_sid(smmu, sid); +- +- if (!step) +- return; +- +- val = STRTAB_STE_0_V; +- val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS); +- step[0] = cpu_to_le64(val); +- step[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, +- STRTAB_STE_1_SHCFG_INCOMING)); +- step[2] = 0; +-} +- +-static int arm_smmu_prepare_init_l2_strtab(struct device *dev, void *data) +-{ +- u32 sid; +- int ret; +- struct pci_dev *pdev; +- struct arm_smmu_device *smmu = (struct arm_smmu_device *)data; +- +- if (!arm_smmu_def_domain_type(dev)) +- return 0; +- +- pdev = to_pci_dev(dev); +- sid = PCI_DEVID(pdev->bus->number, pdev->devfn); +- if (!arm_smmu_sid_in_range(smmu, sid)) +- return -ERANGE; +- +- ret = arm_smmu_init_l2_strtab(smmu, sid); +- if (ret) +- return ret; +- +- arm_smmu_install_bypass_ste_for_dev(smmu, sid); +- +- return 0; +-} +-#endif +- + static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) + { + void *strtab; + u64 reg; + u32 size, l1size; + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; +-#ifdef CONFIG_SMMU_BYPASS_DEV +- int ret; +-#endif + + /* Calculate the L1 size, capped to the SIDSIZE. */ + size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3); +@@ -4220,20 +3478,8 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) + reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, size); + reg |= FIELD_PREP(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT); + cfg->strtab_base_cfg = reg; +-#ifdef CONFIG_SMMU_BYPASS_DEV +- ret = arm_smmu_init_l1_strtab(smmu); +- if (ret) +- return ret; +- +- if (smmu_bypass_devices_num) { +- ret = bus_for_each_dev(&pci_bus_type, NULL, (void *)smmu, +- arm_smmu_prepare_init_l2_strtab); +- } + +- return ret; +-#else + return arm_smmu_init_l1_strtab(smmu); +-#endif + } + + static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu) +@@ -4333,6 +3579,7 @@ static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) + return ret; + } + ++#ifdef CONFIG_ACPI + static void arm_smmu_free_msis(void *data) + { + struct device *dev = data; +@@ -4349,13 +3596,6 @@ static void arm_smmu_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) + doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; + doorbell &= MSI_CFG0_ADDR_MASK; + +-#ifdef CONFIG_ARM_SMMU_V3_PM +- /* Saves the msg (base addr of msi irq) and restores it during resume */ +- desc->msg.address_lo = msg->address_lo; +- desc->msg.address_hi = msg->address_hi; +- desc->msg.data = msg->data; +-#endif +- + writeq_relaxed(doorbell, smmu->base + cfg[0]); + writel_relaxed(msg->data, smmu->base + cfg[1]); + writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); +@@ -4410,53 +3650,14 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) + /* Add callback to free MSIs on teardown */ + devm_add_action(dev, arm_smmu_free_msis, dev); + } +- +-#ifdef CONFIG_ARM_SMMU_V3_PM +-static void arm_smmu_resume_msis(struct arm_smmu_device *smmu) +-{ +- struct msi_desc *desc; +- struct device *dev = smmu->dev; +- +- for_each_msi_entry(desc, dev) { +- switch (desc->platform.msi_index) { +- case EVTQ_MSI_INDEX: +- case GERROR_MSI_INDEX: +- case PRIQ_MSI_INDEX: { +- phys_addr_t *cfg = arm_smmu_msi_cfg[desc->platform.msi_index]; +- struct msi_msg *msg = &desc->msg; +- phys_addr_t doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; +- +- doorbell &= MSI_CFG0_ADDR_MASK; +- writeq_relaxed(doorbell, smmu->base + cfg[0]); +- writel_relaxed(msg->data, smmu->base + cfg[1]); +- writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, +- smmu->base + cfg[2]); +- break; +- } +- default: +- continue; +- +- } +- } +-} +-#else +-static void arm_smmu_resume_msis(struct arm_smmu_device *smmu) +-{ +-} + #endif + +-static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu, bool resume) ++static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) + { + int irq, ret; +- +- if (!resume) +- arm_smmu_setup_msis(smmu); +- else { +- /* The irq doesn't need to be re-requested during resume */ +- arm_smmu_resume_msis(smmu); +- return; +- } +- ++#ifdef CONFIG_ACPI ++ arm_smmu_setup_msis(smmu); ++#endif + /* Request interrupt lines */ + irq = smmu->evtq.q.irq; + if (irq) { +@@ -4497,7 +3698,7 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu, bool resume + } + } + +-static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume) ++static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool for_suspend) + { + int ret, irq; + u32 irqen_flags = IRQ_CTRL_EVTQ_IRQEN | IRQ_CTRL_GERROR_IRQEN; +@@ -4510,6 +3711,9 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume) + return ret; + } + ++ if (for_suspend) ++ goto irq_requested; ++ + irq = smmu->combined_irq; + if (irq) { + /* +@@ -4524,17 +3728,20 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu, bool resume) + if (ret < 0) + dev_warn(smmu->dev, "failed to enable combined irq\n"); + } else +- arm_smmu_setup_unique_irqs(smmu, resume); ++ arm_smmu_setup_unique_irqs(smmu); + + if (smmu->features & ARM_SMMU_FEAT_PRI) + irqen_flags |= IRQ_CTRL_PRIQ_IRQEN; +- ++irq_requested: + /* Enable interrupt generation on the SMMU */ + ret = arm_smmu_write_reg_sync(smmu, irqen_flags, + ARM_SMMU_IRQ_CTRL, ARM_SMMU_IRQ_CTRLACK); + if (ret) + dev_warn(smmu->dev, "failed to enable irqs\n"); + ++ writel_relaxed(VENDOR_VAL_MASK, smmu->base + SMMU_IRPT_CLR_NS); ++ writel_relaxed(TCU_EVENT_TO_MASK, smmu->base + SMMU_IRPT_MASK_NS); ++ + return 0; + } + +@@ -4549,49 +3756,7 @@ static int arm_smmu_device_disable(struct arm_smmu_device *smmu) + return ret; + } + +-static int arm_smmu_ecmdq_reset(struct arm_smmu_device *smmu) +-{ +- int i, cpu, ret = 0; +- u32 reg; +- +- if (!smmu->nr_ecmdq) +- return 0; +- +- i = 0; +- for_each_possible_cpu(cpu) { +- struct arm_smmu_ecmdq *ecmdq; +- struct arm_smmu_queue *q; +- +- ecmdq = *per_cpu_ptr(smmu->ecmdqs, cpu); +- if (ecmdq != per_cpu_ptr(smmu->ecmdq, cpu)) +- continue; +- +- q = &ecmdq->cmdq.q; +- i++; +- +- if (WARN_ON(q->llq.prod != q->llq.cons)) { +- q->llq.prod = 0; +- q->llq.cons = 0; +- } +- writeq_relaxed(q->q_base, ecmdq->base + ARM_SMMU_ECMDQ_BASE); +- writel_relaxed(q->llq.prod, ecmdq->base + ARM_SMMU_ECMDQ_PROD); +- writel_relaxed(q->llq.cons, ecmdq->base + ARM_SMMU_ECMDQ_CONS); +- +- /* enable ecmdq */ +- writel(ECMDQ_PROD_EN | q->llq.prod, q->prod_reg); +- ret = readl_relaxed_poll_timeout(q->cons_reg, reg, reg & ECMDQ_CONS_ENACK, +- 1, ARM_SMMU_POLL_TIMEOUT_US); +- if (ret) { +- dev_err(smmu->dev, "ecmdq[%d] enable failed\n", i); +- smmu->ecmdq_enabled = 0; +- break; +- } +- } +- +- return ret; +-} +- +-static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume) ++static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool for_suspend) + { + int ret; + u32 reg, enables; +@@ -4640,8 +3805,6 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume) + writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); + writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); + +- arm_smmu_ecmdq_reset(smmu); +- + enables = CR0_CMDQEN; + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); +@@ -4652,16 +3815,18 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume) + + /* Invalidate any cached configuration */ + cmd.opcode = CMDQ_OP_CFGI_ALL; +- arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); ++ arm_smmu_cmdq_issue_cmd(smmu, &cmd); ++ arm_smmu_cmdq_issue_sync(smmu); + + /* Invalidate any stale TLB entries */ + if (smmu->features & ARM_SMMU_FEAT_HYP) { + cmd.opcode = CMDQ_OP_TLBI_EL2_ALL; +- arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); ++ arm_smmu_cmdq_issue_cmd(smmu, &cmd); + } + + cmd.opcode = CMDQ_OP_TLBI_NSNH_ALL; +- arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); ++ arm_smmu_cmdq_issue_cmd(smmu, &cmd); ++ arm_smmu_cmdq_issue_sync(smmu); + + /* Event queue */ + writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); +@@ -4672,263 +3837,60 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu, bool resume) + ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, + ARM_SMMU_CR0ACK); + if (ret) { +- dev_err(smmu->dev, "failed to enable event queue\n"); +- return ret; +- } +- +- /* PRI queue */ +- if (smmu->features & ARM_SMMU_FEAT_PRI) { +- writeq_relaxed(smmu->priq.q.q_base, +- smmu->base + ARM_SMMU_PRIQ_BASE); +- writel_relaxed(smmu->priq.q.llq.prod, +- smmu->page1 + ARM_SMMU_PRIQ_PROD); +- writel_relaxed(smmu->priq.q.llq.cons, +- smmu->page1 + ARM_SMMU_PRIQ_CONS); +- +- enables |= CR0_PRIQEN; +- ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, +- ARM_SMMU_CR0ACK); +- if (ret) { +- dev_err(smmu->dev, "failed to enable PRI queue\n"); +- return ret; +- } +- } +- +- if (smmu->features & ARM_SMMU_FEAT_ATS) { +- enables |= CR0_ATSCHK; +- ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, +- ARM_SMMU_CR0ACK); +- if (ret) { +- dev_err(smmu->dev, "failed to enable ATS check\n"); +- return ret; +- } +- } +- +- ret = arm_smmu_setup_irqs(smmu, resume); +- if (ret) { +- dev_err(smmu->dev, "failed to setup irqs\n"); +- return ret; +- } +- +- if (is_kdump_kernel()) +- enables &= ~(CR0_EVTQEN | CR0_PRIQEN); +- +- /* Enable the SMMU interface, or ensure bypass */ +- if (!smmu->bypass || disable_bypass) { +- enables |= CR0_SMMUEN; +- } else { +- ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT); +- if (ret) +- return ret; +- } +- ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, +- ARM_SMMU_CR0ACK); +- if (ret) { +- dev_err(smmu->dev, "failed to enable SMMU interface\n"); +- return ret; +- } +- +- return 0; +-} +- +-static int arm_smmu_ecmdq_layout(struct arm_smmu_device *smmu) +-{ +- int cpu, node, nr_remain, nr_nodes = 0; +- int *nr_ecmdqs; +- struct arm_smmu_ecmdq *ecmdq, **ecmdqs; +- +- ecmdq = devm_alloc_percpu(smmu->dev, *ecmdq); +- if (!ecmdq) +- return -ENOMEM; +- smmu->ecmdq = ecmdq; +- +- if (num_possible_cpus() <= smmu->nr_ecmdq) { +- for_each_possible_cpu(cpu) +- *per_cpu_ptr(smmu->ecmdqs, cpu) = per_cpu_ptr(ecmdq, cpu); +- +- /* A core requires at most one ECMDQ */ +- smmu->nr_ecmdq = num_possible_cpus(); +- +- return 0; +- } +- +- for_each_node(node) +- if (nr_cpus_node(node)) +- nr_nodes++; +- +- if (nr_nodes >= smmu->nr_ecmdq) { +- dev_err(smmu->dev, "%d ECMDQs is less than %d nodes\n", smmu->nr_ecmdq, nr_nodes); +- return -ENOSPC; +- } +- +- nr_ecmdqs = kcalloc(MAX_NUMNODES, sizeof(int), GFP_KERNEL); +- if (!nr_ecmdqs) +- return -ENOMEM; +- +- ecmdqs = kcalloc(smmu->nr_ecmdq, sizeof(*ecmdqs), GFP_KERNEL); +- if (!ecmdqs) { +- kfree(nr_ecmdqs); +- return -ENOMEM; +- } +- +- /* [1] Ensure that each node has at least one ECMDQ */ +- nr_remain = smmu->nr_ecmdq - nr_nodes; +- for_each_node(node) { +- /* +- * Calculate the number of ECMDQs to be allocated to this node. +- * NR_ECMDQS_PER_CPU = nr_remain / num_possible_cpus(); +- * When nr_cpus_node(node) is not zero, less than one ECMDQ +- * may be left due to truncation rounding. +- */ +- nr_ecmdqs[node] = nr_cpus_node(node) * nr_remain / num_possible_cpus(); +- } +- +- for_each_node(node) { +- if (!nr_cpus_node(node)) +- continue; +- +- nr_remain -= nr_ecmdqs[node]; +- +- /* An ECMDQ has been reserved for each node at above [1] */ +- nr_ecmdqs[node]++; +- } +- +- /* Divide the remaining ECMDQs */ +- while (nr_remain) { +- for_each_node(node) { +- if (!nr_remain) +- break; +- +- if (nr_ecmdqs[node] >= nr_cpus_node(node)) +- continue; +- +- nr_ecmdqs[node]++; +- nr_remain--; +- } +- } +- +- for_each_node(node) { +- int i, round, shared; +- +- if (!nr_cpus_node(node)) +- continue; +- +- shared = 0; +- if (nr_ecmdqs[node] < nr_cpus_node(node)) +- shared = 1; +- +- i = 0; +- for_each_cpu(cpu, cpumask_of_node(node)) { +- round = i % nr_ecmdqs[node]; +- if (i++ < nr_ecmdqs[node]) +- ecmdqs[round] = per_cpu_ptr(ecmdq, cpu); +- else +- ecmdqs[round]->cmdq.shared = shared; +- *per_cpu_ptr(smmu->ecmdqs, cpu) = ecmdqs[round]; +- } +- } +- +- kfree(nr_ecmdqs); +- kfree(ecmdqs); +- +- return 0; +-} +- +-static int arm_smmu_ecmdq_probe(struct arm_smmu_device *smmu) +-{ +- int ret, cpu; +- u32 i, nump, numq, gap; +- u32 reg, shift_increment; +- u64 addr, smmu_dma_base; +- void __iomem *cp_regs, *cp_base; +- +- /* IDR6 */ +- reg = readl_relaxed(smmu->base + ARM_SMMU_IDR6); +- nump = 1 << FIELD_GET(IDR6_LOG2NUMP, reg); +- numq = 1 << FIELD_GET(IDR6_LOG2NUMQ, reg); +- smmu->nr_ecmdq = nump * numq; +- gap = ECMDQ_CP_RRESET_SIZE >> FIELD_GET(IDR6_LOG2NUMQ, reg); +- if (!smmu->nr_ecmdq) +- return -EOPNOTSUPP; +- +- smmu_dma_base = (vmalloc_to_pfn(smmu->base) << PAGE_SHIFT); +- cp_regs = ioremap(smmu_dma_base + ARM_SMMU_ECMDQ_CP_BASE, PAGE_SIZE); +- if (!cp_regs) +- return -ENOMEM; ++ dev_err(smmu->dev, "failed to enable event queue\n"); ++ return ret; ++ } + +- for (i = 0; i < nump; i++) { +- u64 val, pre_addr; ++ /* PRI queue */ ++ if (smmu->features & ARM_SMMU_FEAT_PRI) { ++ writeq_relaxed(smmu->priq.q.q_base, ++ smmu->base + ARM_SMMU_PRIQ_BASE); ++ writel_relaxed(smmu->priq.q.llq.prod, ++ smmu->page1 + ARM_SMMU_PRIQ_PROD); ++ writel_relaxed(smmu->priq.q.llq.cons, ++ smmu->page1 + ARM_SMMU_PRIQ_CONS); + +- val = readq_relaxed(cp_regs + 32 * i); +- if (!(val & ECMDQ_CP_PRESET)) { +- iounmap(cp_regs); +- dev_err(smmu->dev, "ecmdq control page %u is memory mode\n", i); +- return -EFAULT; ++ enables |= CR0_PRIQEN; ++ ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ++ ARM_SMMU_CR0ACK); ++ if (ret) { ++ dev_err(smmu->dev, "failed to enable PRI queue\n"); ++ return ret; + } ++ } + +- if (i && ((val & ECMDQ_CP_ADDR) != (pre_addr + ECMDQ_CP_RRESET_SIZE))) { +- iounmap(cp_regs); +- dev_err(smmu->dev, "ecmdq_cp memory region is not contiguous\n"); +- return -EFAULT; ++ if (smmu->features & ARM_SMMU_FEAT_ATS) { ++ enables |= CR0_ATSCHK; ++ ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ++ ARM_SMMU_CR0ACK); ++ if (ret) { ++ dev_err(smmu->dev, "failed to enable ATS check\n"); ++ return ret; + } +- +- pre_addr = val & ECMDQ_CP_ADDR; + } + +- addr = readl_relaxed(cp_regs) & ECMDQ_CP_ADDR; +- iounmap(cp_regs); +- +- cp_base = devm_ioremap(smmu->dev, smmu_dma_base + addr, ECMDQ_CP_RRESET_SIZE * nump); +- if (!cp_base) +- return -ENOMEM; +- +- smmu->ecmdqs = devm_alloc_percpu(smmu->dev, struct arm_smmu_ecmdq *); +- if (!smmu->ecmdqs) +- return -ENOMEM; +- +- ret = arm_smmu_ecmdq_layout(smmu); +- if (ret) ++ ret = arm_smmu_setup_irqs(smmu, for_suspend); ++ if (ret) { ++ dev_err(smmu->dev, "failed to setup irqs\n"); + return ret; ++ } + +- shift_increment = order_base_2(num_possible_cpus() / smmu->nr_ecmdq); +- +- addr = 0; +- for_each_possible_cpu(cpu) { +- struct arm_smmu_ecmdq *ecmdq; +- struct arm_smmu_queue *q; +- +- ecmdq = *per_cpu_ptr(smmu->ecmdqs, cpu); +- q = &ecmdq->cmdq.q; +- +- /* +- * The boot option "maxcpus=" can limit the number of online +- * CPUs. The CPUs that are not selected are not showed in +- * cpumask_of_node(node), their 'ecmdq' may be NULL. +- * +- * (ecmdq != per_cpu_ptr(smmu->ecmdq, cpu)) indicates that the +- * ECMDQ is shared by multiple cores and should be initialized +- * only by the first owner. +- */ +- if (!ecmdq || (ecmdq != per_cpu_ptr(smmu->ecmdq, cpu))) +- continue; +- ecmdq->base = cp_base + addr; ++ if (is_kdump_kernel()) ++ enables &= ~(CR0_EVTQEN | CR0_PRIQEN); + +- q->llq.max_n_shift = ECMDQ_MAX_SZ_SHIFT + shift_increment; +- ret = arm_smmu_init_one_queue(smmu, q, ecmdq->base, ARM_SMMU_ECMDQ_PROD, +- ARM_SMMU_ECMDQ_CONS, CMDQ_ENT_DWORDS, "ecmdq"); ++ /* Enable the SMMU interface, or ensure bypass */ ++ if (!smmu->bypass || disable_bypass) { ++ enables |= CR0_SMMUEN; ++ } else { ++ ret = arm_smmu_update_gbpa(smmu, 0, GBPA_ABORT); + if (ret) + return ret; +- +- q->ecmdq_prod = ECMDQ_PROD_EN; +- rwlock_init(&q->ecmdq_lock); +- +- ret = arm_smmu_ecmdq_init(&ecmdq->cmdq); +- if (ret) { +- dev_err(smmu->dev, "ecmdq[%d] init failed\n", i); +- return ret; +- } +- +- addr += gap; ++ } ++ ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, ++ ARM_SMMU_CR0ACK); ++ if (ret) { ++ dev_err(smmu->dev, "failed to enable SMMU interface\n"); ++ return ret; + } + + return 0; +@@ -4965,12 +3927,14 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) + /* IDR0 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); + ++#ifndef CONFIG_VENDOR_NPU + /* 2-level structures */ + if (FIELD_GET(IDR0_ST_LVL, reg) == IDR0_ST_LVL_2LVL) + smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; + + if (reg & IDR0_CD2L) + smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; ++#endif + + /* + * Translation table endianness. +@@ -5078,9 +4042,6 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) + return -ENXIO; + } + +- if (reg & IDR1_ECMDQ) +- smmu->features |= ARM_SMMU_FEAT_ECMDQ; +- + /* Queue sizes, capped to ensure natural alignment */ + smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, + FIELD_GET(IDR1_CMDQS, reg)); +@@ -5104,6 +4065,8 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) + /* SID/SSID sizes */ + smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); + smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); ++ smmu->sid_bits = 6; /* set sid to 6 bits */ ++ smmu->ssid_bits = 6; /* set ssid to 6 bits */ + + /* + * If the SMMU supports fewer bits than would fill a single L2 stream +@@ -5114,31 +4077,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) + + /* IDR3 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); +- switch (FIELD_GET(IDR3_BBML, reg)) { +- case IDR3_BBML0: +- break; +- case IDR3_BBML1: +- smmu->features |= ARM_SMMU_FEAT_BBML1; +- break; +- case IDR3_BBML2: +- smmu->features |= ARM_SMMU_FEAT_BBML2; +- break; +- default: +- dev_err(smmu->dev, "unknown/unsupported BBM behavior level\n"); +- return -ENXIO; +- } +- + if (FIELD_GET(IDR3_RIL, reg)) + smmu->features |= ARM_SMMU_FEAT_RANGE_INV; + +- if (reg & IDR3_MPAM) { +- reg = readl_relaxed(smmu->base + ARM_SMMU_MPAMIDR); +- smmu->mpam_partid_max = FIELD_GET(MPAMIDR_PARTID_MAX, reg); +- smmu->mpam_pmg_max = FIELD_GET(MPAMIDR_PMG_MAX, reg); +- if (smmu->mpam_partid_max || smmu->mpam_pmg_max) +- smmu->features |= ARM_SMMU_FEAT_MPAM; +- } +- + /* IDR5 */ + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); + +@@ -5201,18 +4142,11 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) + if (arm_smmu_sva_supported(smmu)) + smmu->features |= ARM_SMMU_FEAT_SVA; + ++ if (smmu->features & ARM_SMMU_FEAT_SVA) ++ printk("support SVA===================>\n"); ++ + dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", + smmu->ias, smmu->oas, smmu->features); +- +- if (smmu->features & ARM_SMMU_FEAT_ECMDQ) { +- int err; +- +- err = arm_smmu_ecmdq_probe(smmu); +- if (err) { +- dev_err(smmu->dev, "suppress ecmdq feature, errno=%d\n", err); +- smmu->ecmdq_enabled = 0; +- } +- } + return 0; + } + +@@ -5296,6 +4230,59 @@ static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu) + return SZ_128K; + } + ++#define ARM_SMMMU_DEVICE_MAX 2 ++#define ARM_SMMMU_DEVICE_NAME_LEN 64 ++struct smmu_dev_wl_mng { ++ char smmu_name[ARM_SMMMU_DEVICE_NAME_LEN]; ++ void *pdev; ++ bool is_probe; ++ bool is_poweron; ++}; ++ ++static struct smmu_dev_wl_mng smmu_dev_white_list[ARM_SMMMU_DEVICE_MAX] = { ++ { "smmu_npu", NULL, false, false}, ++#if defined(CONFIG_ARCH_SS000V100) ++ { "smmu_svp_npu", NULL, false, false} ++#elif defined(CONFIG_ARCH_SS928V100) ++ { "smmu_pqp", NULL, false, false} ++#endif ++}; ++ ++static int smmu_device_wl_process(struct platform_device *pdev) ++{ ++ int i; ++ ++ for (i = 0; i < ARM_SMMMU_DEVICE_MAX; i++) { ++ if (strnstr(pdev->name, smmu_dev_white_list[i].smmu_name, ARM_SMMMU_DEVICE_NAME_LEN) != NULL) { ++ smmu_dev_white_list[i].pdev = (void *)pdev; ++ return 0; ++ } ++ } ++ return -1; ++} ++ ++static int arm_smmu_device_poweron_probe(struct arm_smmu_device *smmu, struct device *dev) ++{ ++ int ret; ++ ++ /* Probe the h/w */ ++ ret = arm_smmu_device_hw_probe(smmu); ++ if (ret) ++ return ret; ++ ++ /* Initialise in-memory data structures */ ++ ret = arm_smmu_init_structures(smmu); ++ if (ret) ++ return ret; ++ ++ /* Reset the device */ ++ ret = arm_smmu_device_reset(smmu, false); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ + static int arm_smmu_set_bus_ops(struct iommu_ops *ops) + { + int err; +@@ -5341,81 +4328,6 @@ static void __iomem *arm_smmu_ioremap(struct device *dev, resource_size_t start, + return devm_ioremap_resource(dev, &res); + } + +-#ifdef CONFIG_ARM_SMMU_V3_PM +-static int arm_smmu_ecmdq_disable(struct device *dev) +-{ +- int i, j; +- int ret, nr_fail = 0, n = 100; +- u32 reg, prod, cons; +- struct arm_smmu_ecmdq *ecmdq; +- struct arm_smmu_queue *q; +- struct arm_smmu_device *smmu = dev_get_drvdata(dev); +- +- for (i = 0; i < smmu->nr_ecmdq; i++) { +- ecmdq = *per_cpu_ptr(smmu->ecmdqs, i); +- q = &ecmdq->cmdq.q; +- +- prod = readl_relaxed(q->prod_reg); +- cons = readl_relaxed(q->cons_reg); +- if ((prod & ECMDQ_PROD_EN) == 0) +- continue; +- +- for (j = 0; j < n; j++) { +- if (Q_IDX(&q->llq, prod) == Q_IDX(&q->llq, cons) && +- Q_WRP(&q->llq, prod) == Q_WRP(&q->llq, cons)) +- break; +- +- /* Wait a moment, so ECMDQ has a chance to finish */ +- udelay(1); +- cons = readl_relaxed(q->cons_reg); +- } +- WARN_ON(prod != readl_relaxed(q->prod_reg)); +- if (j >= n) +- dev_warn(smmu->dev, +- "Forcibly disabling ecmdq[%d]: prod=%08x, cons=%08x\n", +- i, prod, cons); +- +- /* disable ecmdq */ +- prod &= ~ECMDQ_PROD_EN; +- writel(prod, q->prod_reg); +- ret = readl_relaxed_poll_timeout(q->cons_reg, reg, !(reg & ECMDQ_CONS_ENACK), +- 1, ARM_SMMU_POLL_TIMEOUT_US); +- if (ret) { +- nr_fail++; +- dev_err(smmu->dev, "ecmdq[%d] disable failed\n", i); +- } +- } +- +- if (nr_fail) { +- smmu->ecmdq_enabled = 0; +- pr_warn("Suppress ecmdq feature, switch to normal cmdq\n"); +- return -EIO; +- } +- +- return 0; +-} +- +-static int arm_smmu_suspend(struct device *dev) +-{ +- arm_smmu_ecmdq_disable(dev); +- +- /* +- * The smmu is powered off and related registers are automatically +- * cleared when suspend. No need to do anything. +- */ +- return 0; +-} +- +-static int arm_smmu_resume(struct device *dev) +-{ +- struct arm_smmu_device *smmu = dev_get_drvdata(dev); +- +- arm_smmu_device_reset(smmu, true); +- +- return 0; +-} +-#endif +- + static int arm_smmu_device_probe(struct platform_device *pdev) + { + int irq, ret; +@@ -5444,8 +4356,6 @@ static int arm_smmu_device_probe(struct platform_device *pdev) + + /* Base address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res) +- return -EINVAL; + if (resource_size(res) < arm_smmu_resource_size(smmu)) { + dev_err(dev, "MMIO region too small (%pr)\n", res); + return -EINVAL; +@@ -5456,10 +4366,12 @@ static int arm_smmu_device_probe(struct platform_device *pdev) + * Don't map the IMPLEMENTATION DEFINED regions, since they may contain + * the PMCG registers which are reserved by the PMU driver. + */ +- smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); ++#ifdef CONFIG_VENDOR_NPU ++ smmu->base = arm_smmu_ioremap(dev, ioaddr, resource_size(res)); + if (IS_ERR(smmu->base)) + return PTR_ERR(smmu->base); +- ++ smmu->page1 = smmu->base + SZ_64K; ++#else + if (arm_smmu_resource_size(smmu) > SZ_64K) { + smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, + ARM_SMMU_REG_SZ); +@@ -5468,7 +4380,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev) + } else { + smmu->page1 = smmu->base; + } +- ++#endif + /* Interrupt lines */ + + irq = platform_get_irq_byname_optional(pdev, "combined"); +@@ -5487,23 +4399,14 @@ static int arm_smmu_device_probe(struct platform_device *pdev) + if (irq > 0) + smmu->gerr_irq = irq; + } +- /* Probe the h/w */ +- ret = arm_smmu_device_hw_probe(smmu); +- if (ret) +- return ret; +- +- /* Initialise in-memory data structures */ +- ret = arm_smmu_init_structures(smmu); +- if (ret) +- return ret; +- + /* Record our private device structure */ + platform_set_drvdata(pdev, smmu); + +- /* Reset the device */ +- ret = arm_smmu_device_reset(smmu, false); +- if (ret) +- return ret; ++ if (0 != smmu_device_wl_process(pdev)) { ++ ret = arm_smmu_device_poweron_probe(smmu, dev); ++ if (ret) ++ return ret; ++ } + + /* And we're up. Go go go! */ + ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, +@@ -5523,17 +4426,170 @@ static int arm_smmu_device_probe(struct platform_device *pdev) + return arm_smmu_set_bus_ops(&arm_smmu_ops); + } + ++int arm_smmu_device_post_probe(const char *device_name) ++{ ++ int ret, i; ++ struct platform_device *pdev = NULL; ++ struct arm_smmu_device *smmu = NULL; ++ ++ for (i = 0; i < ARM_SMMMU_DEVICE_MAX; i++) { ++ if (strnstr(device_name, smmu_dev_white_list[i].smmu_name, ARM_SMMMU_DEVICE_NAME_LEN) != NULL) { ++ if (smmu_dev_white_list[i].is_probe == true) ++ return 0; ++ ++ pdev = (struct platform_device *)smmu_dev_white_list[i].pdev; ++ break; ++ } ++ } ++ ++ if (pdev == NULL) { ++ dev_err(&pdev->dev, "fail to find smmu device in white list \n"); ++ return -1; ++ } ++ ++ smmu = platform_get_drvdata(pdev); ++ if (smmu == NULL) ++ return -1; ++ ret = arm_smmu_device_poweron_probe(smmu, &pdev->dev); ++ if (ret) { ++ dev_err(&pdev->dev, "Fail to do smmu post probe\n"); ++ return ret; ++ } ++ smmu_dev_white_list[i].is_probe = true; ++ smmu_dev_white_list[i].is_poweron = true; ++ return 0; ++} ++ ++EXPORT_SYMBOL_GPL(arm_smmu_device_post_probe); ++ ++static bool arm_smmu_device_is_in_wl(const char *device_name) ++{ ++ int i; ++ ++ for (i = 0; i < ARM_SMMMU_DEVICE_MAX; i++) { ++ if (strnstr(device_name, smmu_dev_white_list[i].smmu_name, ARM_SMMMU_DEVICE_NAME_LEN) != NULL) ++ return true; ++ } ++ return false; ++} ++ ++#ifndef CONFIG_VENDOR_NPU ++static bool arm_smmu_device_is_poweron(const char *device_name) ++{ ++ int i; ++ ++ for (i = 0; i < ARM_SMMMU_DEVICE_MAX; i++) { ++ if (strnstr(device_name, smmu_dev_white_list[i].smmu_name, ARM_SMMMU_DEVICE_NAME_LEN) != NULL) { ++ if (smmu_dev_white_list[i].is_probe == true && smmu_dev_white_list[i].is_poweron == true) ++ return true; ++ } ++ } ++ return false; ++} ++#endif ++ ++int arm_smmu_device_suspend(const char *device_name) ++{ ++ int i; ++ ++ for (i = 0; i < ARM_SMMMU_DEVICE_MAX; i++) { ++ if (strnstr(device_name, smmu_dev_white_list[i].smmu_name, ARM_SMMMU_DEVICE_NAME_LEN) != NULL) { ++ smmu_dev_white_list[i].is_poweron = false; ++ return 0; ++ } ++ } ++ return -1; ++} ++EXPORT_SYMBOL_GPL(arm_smmu_device_suspend); ++ ++static struct arm_smmu_device *get_smmu_device_data(const char *device_name, int *index) ++{ ++ int i; ++ struct platform_device *pdev = NULL; ++ struct arm_smmu_device *smmu = NULL; ++ ++ for (i = 0; i < ARM_SMMMU_DEVICE_MAX; i++) { ++ if (strnstr(device_name, smmu_dev_white_list[i].smmu_name, ARM_SMMMU_DEVICE_NAME_LEN) != NULL) { ++ if (smmu_dev_white_list[i].is_probe == false) ++ return 0; ++ ++ pdev = (struct platform_device *)smmu_dev_white_list[i].pdev; ++ break; ++ } ++ } ++ ++ if (i >= ARM_SMMMU_DEVICE_MAX || pdev == NULL) { ++ dev_err(&pdev->dev, "fail to find smmu device in white list \n"); ++ return NULL; ++ } ++ ++ *index = i; ++ ++ smmu = platform_get_drvdata(pdev); ++ if (smmu == NULL) ++ return NULL; ++ ++ return smmu; ++} ++ ++int arm_smmu_device_resume(const char *device_name) ++{ ++ int ret; ++ int index = 0; ++ struct arm_smmu_device *smmu = NULL; ++ ++ smmu = get_smmu_device_data(device_name, &index); ++ if (smmu == NULL) ++ return -1; ++ ++ if (index < ARM_SMMMU_DEVICE_MAX) ++ smmu_dev_white_list[index].is_poweron = true; ++ ++ ret = arm_smmu_device_reset(smmu, true); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(arm_smmu_device_resume); ++ ++int arm_smmu_device_reset_ex(const char *device_name) ++{ ++ int ret = -1; ++ int index = 0; ++ struct arm_smmu_device *smmu = NULL; ++ ++ smmu = get_smmu_device_data(device_name, &index); ++ if (smmu == NULL) ++ return -1; ++ ++ if (index < ARM_SMMMU_DEVICE_MAX && smmu_dev_white_list[index].is_poweron == true) ++ ret = arm_smmu_device_reset(smmu, true); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(arm_smmu_device_reset_ex); ++ ++const char *arm_smmu_get_device_name(struct iommu_domain *domain) ++{ ++ struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); ++ struct arm_smmu_device *smmu = smmu_domain->smmu; ++ return dev_name(smmu->dev); ++} ++EXPORT_SYMBOL_GPL(arm_smmu_get_device_name); ++ ++ + static int arm_smmu_device_remove(struct platform_device *pdev) + { + struct arm_smmu_device *smmu = platform_get_drvdata(pdev); ++ const char *device_name = dev_name(smmu->dev); + ++ iopf_queue_free(smmu->evtq.iopf); ++ iopf_queue_free(smmu->priq.iopf); ++ if (arm_smmu_device_is_in_wl(device_name)) { ++ return 0; ++ } + arm_smmu_set_bus_ops(NULL); + iommu_device_unregister(&smmu->iommu); + iommu_device_sysfs_remove(&smmu->iommu); + arm_smmu_device_disable(smmu); +- iopf_queue_free(smmu->evtq.iopf); +- iopf_queue_free(smmu->priq.iopf); +- + return 0; + } + +@@ -5548,16 +4604,6 @@ static const struct of_device_id arm_smmu_of_match[] = { + }; + MODULE_DEVICE_TABLE(of, arm_smmu_of_match); + +-#ifdef CONFIG_ARM_SMMU_V3_PM +-static const struct dev_pm_ops arm_smmu_pm_ops = { +- .suspend = arm_smmu_suspend, +- .resume = arm_smmu_resume, +-}; +-#define ARM_SMMU_PM_OPS (&arm_smmu_pm_ops) +-#else +-#define ARM_SMMU_PM_OPS NULL +-#endif +- + static void arm_smmu_driver_unregister(struct platform_driver *drv) + { + arm_smmu_sva_notifier_synchronize(); +@@ -5569,7 +4615,6 @@ static struct platform_driver arm_smmu_driver = { + .name = "arm-smmu-v3", + .of_match_table = arm_smmu_of_match, + .suppress_bind_attrs = true, +- .pm = ARM_SMMU_PM_OPS, + }, + .probe = arm_smmu_device_probe, + .remove = arm_smmu_device_remove, +diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +index 919473d2217b..15f55092f840 100644 +--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h ++++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +@@ -45,7 +45,6 @@ + #define IDR0_S2P (1 << 0) + + #define ARM_SMMU_IDR1 0x4 +-#define IDR1_ECMDQ (1 << 31) + #define IDR1_TABLES_PRESET (1 << 30) + #define IDR1_QUEUES_PRESET (1 << 29) + #define IDR1_REL (1 << 28) +@@ -56,13 +55,7 @@ + #define IDR1_SIDSIZE GENMASK(5, 0) + + #define ARM_SMMU_IDR3 0xc +-#define IDR3_BBML GENMASK(12, 11) +-#define IDR3_BBML0 0 +-#define IDR3_BBML1 1 +-#define IDR3_BBML2 2 + #define IDR3_RIL (1 << 10) +-#define IDR3_MPAM (1 << 7) +-#define ARM_SMMU_IDR3_CFG 0x140C + + #define ARM_SMMU_IDR5 0x14 + #define IDR5_STALL_MAX GENMASK(31, 16) +@@ -118,7 +111,6 @@ + #define ARM_SMMU_IRQ_CTRLACK 0x54 + + #define ARM_SMMU_GERROR 0x60 +-#define GERROR_CMDQP_ERR (1 << 9) + #define GERROR_SFM_ERR (1 << 8) + #define GERROR_MSI_GERROR_ABT_ERR (1 << 7) + #define GERROR_MSI_PRIQ_ABT_ERR (1 << 6) +@@ -164,33 +156,6 @@ + #define ARM_SMMU_PRIQ_IRQ_CFG1 0xd8 + #define ARM_SMMU_PRIQ_IRQ_CFG2 0xdc + +-#define ARM_SMMU_MPAMIDR 0x130 +-#define MPAMIDR_PMG_MAX GENMASK(23, 16) +-#define MPAMIDR_PARTID_MAX GENMASK(15, 0) +- +-#define ARM_SMMU_USER_CFG0 0xe00 +-#define ARM_SMMU_USER_MPAM_EN (1UL << 30) +- +-#define ARM_SMMU_IDR6 0x190 +-#define IDR6_LOG2NUMP GENMASK(27, 24) +-#define IDR6_LOG2NUMQ GENMASK(19, 16) +-#define IDR6_BA_DOORBELLS GENMASK(9, 0) +- +-#define ARM_SMMU_ECMDQ_BASE 0x00 +-#define ARM_SMMU_ECMDQ_PROD 0x08 +-#define ARM_SMMU_ECMDQ_CONS 0x0c +-#define ECMDQ_MAX_SZ_SHIFT 8 +-#define ECMDQ_PROD_EN (1 << 31) +-#define ECMDQ_CONS_ENACK (1 << 31) +-#define ECMDQ_CONS_ERR (1 << 23) +-#define ECMDQ_PROD_ERRACK (1 << 23) +- +-#define ARM_SMMU_ECMDQ_CP_BASE 0x4000 +-#define ECMDQ_CP_ADDR GENMASK_ULL(51, 12) +-#define ECMDQ_CP_CMDQGS GENMASK_ULL(2, 1) +-#define ECMDQ_CP_PRESET (1UL << 0) +-#define ECMDQ_CP_RRESET_SIZE 0x10000 +- + #define ARM_SMMU_REG_SZ 0xe00 + + /* Common MSI config fields */ +@@ -266,7 +231,6 @@ + #define STRTAB_STE_1_S1CSH GENMASK_ULL(7, 6) + + #define STRTAB_STE_1_PPAR (1UL << 18) +-#define STRTAB_STE_1_S1MPAM (1UL << 26) + #define STRTAB_STE_1_S1STALLD (1UL << 27) + + #define STRTAB_STE_1_EATS GENMASK_ULL(29, 28) +@@ -297,11 +261,6 @@ + + #define STRTAB_STE_3_S2TTB_MASK GENMASK_ULL(51, 4) + +-#define STRTAB_STE_4_PARTID_MASK GENMASK_ULL(31, 16) +- +-#define STRTAB_STE_5_MPAM_NS (1UL << 8) +-#define STRTAB_STE_5_PMG_MASK GENMASK_ULL(7, 0) +- + /* + * Context descriptors. + * +@@ -343,9 +302,6 @@ + + #define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4) + +-#define CTXDESC_CD_5_PARTID_MASK GENMASK_ULL(47, 32) +-#define CTXDESC_CD_5_PMG_MASK GENMASK_ULL(55, 48) +- + /* + * When the SMMU only supports linear context descriptor tables, pick a + * reasonable size limit (64kB). +@@ -475,6 +431,25 @@ + #define MSI_IOVA_BASE 0x8000000 + #define MSI_IOVA_LENGTH 0x100000 + ++#define VENDOR_TOP_CTL_BASE (0x30000) ++ ++#define SMMU_IRPT_MASK_NS (VENDOR_TOP_CTL_BASE + 0x70) ++#define TCU_EVENT_TO_MASK BIT(5) ++#define VENDOR_VAL_MASK 0xffffffff ++ ++#define SMMU_IRPT_RAW_NS (VENDOR_TOP_CTL_BASE + 0x74) ++ ++#define SMMU_IRPT_STAT_NS (VENDOR_TOP_CTL_BASE + 0x78) ++#define TCU_EVENT_Q_IRQ BIT(0) ++#define TCU_CMD_SYNC_IRQ BIT(1) ++#define TCU_GERROR_IRQ BIT(2) ++ ++#define SMMU_IRPT_CLR_NS (VENDOR_TOP_CTL_BASE + 0x7c) ++#define TCU_EVENT_Q_IRQ_CLR BIT(0) ++#define TCU_CMD_SYNC_IRQ_CLR BIT(1) ++#define TCU_GERROR_IRQ_CLR BIT(2) ++#define TCU_EVENTTO_CLR BIT(5) ++ + struct arm_smmu_cmdq_ent { + /* Common fields */ + u8 opcode; +@@ -572,8 +547,6 @@ struct arm_smmu_ll_queue { + struct arm_smmu_queue { + struct arm_smmu_ll_queue llq; + int irq; /* Wired interrupt */ +- u32 ecmdq_prod; +- rwlock_t ecmdq_lock; + + __le64 *base; + dma_addr_t base_dma; +@@ -597,12 +570,6 @@ struct arm_smmu_cmdq { + atomic_long_t *valid_map; + atomic_t owner_prod; + atomic_t lock; +- int shared; +-}; +- +-struct arm_smmu_ecmdq { +- struct arm_smmu_cmdq cmdq; +- void __iomem *base; + }; + + struct arm_smmu_cmdq_batch { +@@ -703,10 +670,6 @@ struct arm_smmu_device { + #define ARM_SMMU_FEAT_E2H (1 << 18) + #define ARM_SMMU_FEAT_HA (1 << 19) + #define ARM_SMMU_FEAT_HD (1 << 20) +-#define ARM_SMMU_FEAT_BBML1 (1 << 21) +-#define ARM_SMMU_FEAT_BBML2 (1 << 22) +-#define ARM_SMMU_FEAT_ECMDQ (1 << 23) +-#define ARM_SMMU_FEAT_MPAM (1 << 24) + u32 features; + + #define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0) +@@ -714,13 +677,6 @@ struct arm_smmu_device { + #define ARM_SMMU_OPT_MSIPOLL (1 << 2) + u32 options; + +- union { +- u32 nr_ecmdq; +- u32 ecmdq_enabled; +- }; +- struct arm_smmu_ecmdq *__percpu *ecmdqs; +- struct arm_smmu_ecmdq __percpu *ecmdq; +- + struct arm_smmu_cmdq cmdq; + struct arm_smmu_evtq evtq; + struct arm_smmu_priq priq; +@@ -749,10 +705,6 @@ struct arm_smmu_device { + + struct rb_root streams; + struct mutex streams_mutex; +- +- unsigned int mpam_partid_max; +- unsigned int mpam_pmg_max; +- + bool bypass; + }; + +@@ -828,14 +780,14 @@ extern struct mutex arm_smmu_asid_lock; + extern struct arm_smmu_ctx_desc quiet_cd; + + int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, int ssid, +- struct arm_smmu_ctx_desc *cd); ++ struct arm_smmu_ctx_desc *cd); + void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid); + void arm_smmu_tlb_inv_range_asid(unsigned long iova, size_t size, int asid, +- size_t granule, bool leaf, +- struct arm_smmu_domain *smmu_domain); ++ size_t granule, bool leaf, ++ struct arm_smmu_domain *smmu_domain); + bool arm_smmu_free_asid(struct arm_smmu_ctx_desc *cd); + int arm_smmu_atc_inv_domain(struct arm_smmu_domain *smmu_domain, int ssid, +- unsigned long iova, size_t size); ++ unsigned long iova, size_t size); + int arm_smmu_enable_pri(struct arm_smmu_master *master); + void arm_smmu_disable_pri(struct arm_smmu_master *master); + int arm_smmu_flush_priq(struct arm_smmu_device *smmu); +@@ -850,10 +802,12 @@ bool arm_smmu_master_iopf_supported(struct arm_smmu_master *master); + int arm_smmu_master_enable_iopf(struct arm_smmu_master *master); + int arm_smmu_master_disable_iopf(struct arm_smmu_master *master); + struct iommu_sva *arm_smmu_sva_bind(struct device *dev, struct mm_struct *mm, +- void *drvdata); ++ void *drvdata); + void arm_smmu_sva_unbind(struct iommu_sva *handle); + u32 arm_smmu_sva_get_pasid(struct iommu_sva *handle); + void arm_smmu_sva_notifier_synchronize(void); ++void arm_smmu_sva_mm_invalidate_range(struct iommu_domain *domain, ++ struct mm_struct *mm, unsigned long start, unsigned long size); + #else /* CONFIG_ARM_SMMU_V3_SVA */ + static inline bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) + { +diff --git a/drivers/iommu/arm/arm-smmu-v3/ascend_smmu.c b/drivers/iommu/arm/arm-smmu-v3/ascend_smmu.c +deleted file mode 100644 +index 5e9ed6add9dc..000000000000 +--- a/drivers/iommu/arm/arm-smmu-v3/ascend_smmu.c ++++ /dev/null +@@ -1,434 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* +- * Huawei Ascend accelerator common code for SMMUv3 ATOS feature implementations. +- * +- * Copyright (C) 2020-2021 Huawei Technologies Co., Ltd +- * +- * Author: Binfeng Wu +- * +- * This driver is intended to provide an interface for translating IPA to PA +- * based on the SMMUv3 ATOS feature. +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define AGENT_SMMU_IDR1 0x4 +-#define IDR1_SSIDSIZE GENMASK(10, 6) +-#define IDR1_SIDSIZE GENMASK(5, 0) +- +-#define AGENT_SMMU_CR0 0x20 +-#define CR0_SMMUEN (1 << 0) +- +-#define AGENT_SMMU_ATOS_CTRL 0x100 +- +-#define ENHANCED_ATOS_UNIT_ADDR 0x1700 /* first unit */ +-#define ENHANCED_ATOS_UNIT_SIZE 0x18 +- +-#define ENHANCED_ATOS_SID 0x0 +-#define ENHANCED_ATOS_STREAMID_MASK GENMASK_ULL(31, 0) +-#define ENHANCED_ATOS_SUBSTREAMID_MASK GENMASK_ULL(51, 32) +-#define ENHANCED_ATOS_SSID_VALID_MASK GENMASK_ULL(52, 52) +- +-#define ENHANCED_ATOS_ADDR 0x8 +-#define ENHANCED_ATOS_ADDR_ADDR_MASK GENMASK_ULL(63, 12) +-#define ENHANCED_ATOS_ADDR_TYPE_MASK GENMASK_ULL(11, 10) +-#define ENHANCED_ATOS_ADDR_TYPE_S1 0x01 +-#define ENHANCED_ATOS_ADDR_HTTUI_MASK (1 << 6) +-#define ENHANCED_ATOS_ADDR_ATTR_MASK GENMASK_ULL(9, 6) +- +-#define ENHANCED_ATOS_PAR 0x10 +-#define ENHANCED_ATOS_PAR_FAULT (1 << 0) +-#define ENHANCED_ATOS_PAR_SIZE (1 << 11) +-#define ENHANCED_ATOS_PAR_ADDR_MASK GENMASK_ULL(51, 12) +-#define ENHANCED_ATOS_PAR_FAULTCODE GENMASK_ULL(11, 4) +-#define ENHANCED_ATOS_PAR_REASON GENMASK_ULL(2, 1) +- +-#define AGENT_SMMU_POLL_US 5 +-#define AGENT_SMMU_TIMEOUT_US 250 +-#define MAX_REGISTERS 32 +- +-static LIST_HEAD(agent_smmu_list); +-static DEFINE_SPINLOCK(agent_smmu_lock); +- +-struct agent_smmu { +- struct device *dev; +- void __iomem *base; +- unsigned int max_sid; +- unsigned int max_ssid; +- rwlock_t rw_lock; +- DECLARE_BITMAP(regs, MAX_REGISTERS); +- +- struct list_head list; +- u64 device_id; /* DIE id */ +-}; +- +-struct agent_smmu *agent_smmu_unlocked_find(u64 device_id) +-{ +- struct agent_smmu *temp = NULL; +- +- list_for_each_entry(temp, &agent_smmu_list, list) { +- if (temp->device_id == device_id) { +- return temp; +- } +- } +- return NULL; +-} +- +-static int agent_smmu_register(struct agent_smmu *agent) +-{ +- struct device *dev = agent->dev; +- +- spin_lock(&agent_smmu_lock); +- if (agent_smmu_unlocked_find(agent->device_id)) { +- dev_err(dev, "already added for %lld.\n", agent->device_id); +- spin_unlock(&agent_smmu_lock); +- return -EFAULT; +- } +- list_add_tail(&agent->list, &agent_smmu_list); +- spin_unlock(&agent_smmu_lock); +- +- return 0; +-} +- +-static void agent_smmu_unregister(struct agent_smmu *agent) +-{ +- spin_lock(&agent_smmu_lock); +- list_del(&agent->list); +- spin_unlock(&agent_smmu_lock); +-} +- +-static int agent_smmu_platform_probe(struct platform_device *pdev) +-{ +- struct agent_smmu *agent = NULL; +- struct device *dev = &pdev->dev; +- struct resource *res = NULL; +- u32 reg = 0; +- int ret = 0; +- acpi_status status = AE_OK; +- +- agent = devm_kzalloc(dev, sizeof(*agent), GFP_KERNEL); +- if (!agent) { +- dev_err(dev, "failed to allocate agent smmu.\n"); +- return -ENOMEM; +- } +- +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- if (!res || resource_size(res) + 1 < ENHANCED_ATOS_UNIT_ADDR + +- ENHANCED_ATOS_UNIT_SIZE * MAX_REGISTERS) { +- dev_err(dev, "MMIO region is null or too small, check it.\n"); +- ret = -EINVAL; +- goto err_free; +- } +- +- // agent smmu may probe as smmu in device, so keep using ioreamp +- agent->base = ioremap(res->start, resource_size(res)); +- if (!agent->base) { +- dev_err(dev, "unable to map agent smmu.\n"); +- ret = -ENOMEM; +- goto err_free; +- } +- +- /* check agent smmu is enabled */ +- reg = readl_relaxed(agent->base + AGENT_SMMU_CR0); +- if (!(reg & CR0_SMMUEN)) { +- dev_err(dev, "agent smmu is not enabled, check it.\n"); +- ret = -EPERM; +- goto err_iounmap; +- } +- +- status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev), METHOD_NAME__UID, +- NULL, &agent->device_id); +- if (ACPI_FAILURE(status)) { +- dev_err(dev, "Unable to get agent smmu _UID.\n"); +- ret = -ENODEV; +- goto err_iounmap; +- } +- +- if (agent_smmu_register(agent)) { +- ret = -EINVAL; +- goto err_iounmap; +- } +- +- reg = readl_relaxed(agent->base + AGENT_SMMU_IDR1); +- agent->max_sid = (1U << FIELD_GET(IDR1_SIDSIZE, reg)) - 1; +- agent->max_ssid = (1U << FIELD_GET(IDR1_SSIDSIZE, reg)) - 1; +- bitmap_zero(agent->regs, MAX_REGISTERS); +- rwlock_init(&agent->rw_lock); +- agent->dev = dev; +- platform_set_drvdata(pdev, agent); +- +- dev_info(dev, "agent smmu 0x%llx probed successfully.\n", agent->device_id); +- return ret; +-err_iounmap: +- iounmap(agent->base); +- agent->base = NULL; +-err_free: +- devm_kfree(dev, agent); +- return ret; +-} +- +-static int agent_smmu_platform_remove(struct platform_device *pdev) +-{ +- struct agent_smmu *agent = platform_get_drvdata(pdev); +- +- agent_smmu_unregister(agent); +- iounmap(agent->base); +- agent->dev = NULL; +- agent->base = NULL; +- dev_info(&pdev->dev, "agent smmu removed successfully.\n"); +- return 0; +-} +- +-static void set_registers_unlocked(struct agent_smmu *agent, unsigned long *avl_regs, +- unsigned long *loc_regs, int nr) +-{ +- int idx = 0; +- +- while (nr > 0) { +- idx = find_next_bit(avl_regs, MAX_REGISTERS, idx); +- set_bit(idx, loc_regs); +- set_bit(idx, agent->regs); +- nr--; +- idx++; +- } +-} +- +-/** +- * registers_acquire - take up available registers(some reg may keep unavailable +- * state) from agent smmu according to the number of 'need', mark them in +- * 'loc_regs' and return the number of registers in procession +- * +- * @agent: agent smmu +- * @loc_regs: bitmap recored user's available registers +- * @need: the number of task still need to be processed +- */ +-static int registers_acquire(struct agent_smmu *agent, unsigned long *loc_regs, +- int need) +-{ +- int rest = 0; +- u32 avl_regs_state = 0; +- DECLARE_BITMAP(avl_regs, MAX_REGISTERS); +- +- write_lock(&agent->rw_lock); +- if (bitmap_full(agent->regs, MAX_REGISTERS)) { +- rest = 0; +- } else { +- avl_regs_state = readl_relaxed(agent->base + AGENT_SMMU_ATOS_CTRL); +- avl_regs_state = ~avl_regs_state; +- bitmap_from_arr32(avl_regs, &avl_regs_state, MAX_REGISTERS); +- bitmap_andnot(avl_regs, avl_regs, agent->regs, MAX_REGISTERS); +- rest = bitmap_weight(avl_regs, MAX_REGISTERS); +- } +- set_registers_unlocked(agent, avl_regs, loc_regs, need > rest ? rest : need); +- write_unlock(&agent->rw_lock); +- +- return bitmap_weight(loc_regs, MAX_REGISTERS); +-} +- +-static void write_enhanced_atos(struct agent_smmu *agent, int regs_idx, u64 sid, +- u64 addr, dma_addr_t iova) +-{ +- void __iomem *unit_base; +- +- unit_base = agent->base + ENHANCED_ATOS_UNIT_ADDR + +- ENHANCED_ATOS_UNIT_SIZE * regs_idx; +- addr |= iova & ENHANCED_ATOS_ADDR_ADDR_MASK; +- +- writeq_relaxed(addr, unit_base + ENHANCED_ATOS_ADDR); +- writeq_relaxed(sid, unit_base + ENHANCED_ATOS_SID); +-} +- +-static int get_section_mask(u64 par, u64 *section_mask) +-{ +- int i = 0; +- +- // using default page size 4KB according to spec +- *section_mask = ~((1 << 12) - 1); +- +- // e.g. PAR[Size] is 1 && PAR[14:12] is 0 && PAR[15] is 1, then lowest +- // bit is 15, so section size is 2^(12+3+1) = 64KB +- if (par & ENHANCED_ATOS_PAR_SIZE) { +- par = FIELD_GET(ENHANCED_ATOS_PAR_ADDR_MASK, par); +- if (!par) { +- pr_err("agent smmu: err happen in agent smmu PAR[11]\n"); +- return -EFAULT; +- } +- +- par = (par ^ (par - 1)) >> 1; +- for (i = 0; par; i++) { +- par >>= 1; +- } +- *section_mask = ~((1 << (12 + i + 1)) - 1); +- } +- return 0; +-} +- +-static int read_enhanced_atos(struct agent_smmu *agent, int regs_idx, int idx, +- u32 state, struct agent_smmu_atos_data *data) +-{ +- void __iomem *unit_base = NULL; +- u64 par = 0; +- int ret = 0; +- u64 section_mask = 0; +- u64 section = 0; +- int i = 0; +- +- unit_base = agent->base + ENHANCED_ATOS_UNIT_ADDR + +- ENHANCED_ATOS_UNIT_SIZE * regs_idx; +- par = readq_relaxed(unit_base + ENHANCED_ATOS_PAR); +- +- if (state & (1 << regs_idx)) { +- return -EBUSY; +- } else if (par & ENHANCED_ATOS_PAR_FAULT) { +- data->pa[idx] = par & ENHANCED_ATOS_PAR_FAULTCODE; +- data->pa[idx] |= par & ENHANCED_ATOS_PAR_REASON; +- pr_err("agent smmu: err happened, get PAR 0x%llx\n", par); +- return -EFAULT; +- } else { +- ret = get_section_mask(par, §ion_mask); +- if (ret) +- return ret; +- // use ENHANCED_ATOS_PAR_ADDR_MASK not section_mask +- // since ADDR[63,52] is ATTR or IMPDEF which we don't want +- data->pa[idx] = (par & ENHANCED_ATOS_PAR_ADDR_MASK & section_mask) | +- (data->iova[idx] & ~section_mask); +- section = data->iova[idx] & section_mask; +- +- for (i = idx + 1; i < data->nr; i++) { +- if ((data->iova[i] & section_mask) != section) +- break; +- data->pa[i] = (par & ENHANCED_ATOS_PAR_ADDR_MASK & section_mask) | +- (data->iova[i] & ~section_mask); +- } +- } +- return 0; +-} +- +-#define bitmap_for_each_set_bit(i, src, nbits) \ +- for ((i) = 0; ((i) = find_next_bit((src), (nbits), (i))) < (nbits); (i) += 1) +- +-int agent_smmu_iova_to_phys(struct agent_smmu_atos_data *data, int *succeed) +-{ +- struct agent_smmu *agent = NULL; +- int ret = 0; +- int i; +- u64 sid = 0; +- u64 addr = 0; +- int idx = 0; +- u32 state = 0; +- DECLARE_BITMAP(loc_regs, MAX_REGISTERS); +- DECLARE_BITMAP(bitmask, MAX_REGISTERS); +- u32 bitmask_u32; +- +- if (!data || !data->iova || !data->pa || data->nr <= 0 || !succeed) { +- return -EINVAL; +- } +- +- // now only HTTUI = 1 is allowed +- if (!(data->flag & ENHANCED_ATOS_ADDR_HTTUI_MASK)) { +- pr_err("agent smmu: check httui, make sure is valid\n"); +- return -EINVAL; +- } +- +- spin_lock(&agent_smmu_lock); +- agent = agent_smmu_unlocked_find(data->device_id); +- if (!agent || !get_device(agent->dev)) { +- pr_err("agent smmu: %lld has been removed or hasn't initialized.\n", +- data->device_id); +- spin_unlock(&agent_smmu_lock); +- return -EINVAL; +- } +- spin_unlock(&agent_smmu_lock); +- +- if (data->sid > agent->max_sid || data->ssid > agent->max_ssid) { +- pr_err("agent smmu: sid or ssid out of acceptable range.\n"); +- ret = -EINVAL; +- goto put_device; +- } +- +- *succeed = 0; +- /* make sure default return is 0 because 0 make sence too */ +- for (i = 0; i < data->nr; i++) { +- data->pa[i] = 0; +- } +- /* joint sid and addr first*/ +- sid = FIELD_PREP(ENHANCED_ATOS_STREAMID_MASK, data->sid); +- sid |= FIELD_PREP(ENHANCED_ATOS_SUBSTREAMID_MASK, data->ssid); +- sid |= FIELD_PREP(ENHANCED_ATOS_SSID_VALID_MASK, data->ssid ? 1 : 0); +- addr |= FIELD_PREP(ENHANCED_ATOS_ADDR_TYPE_MASK, ENHANCED_ATOS_ADDR_TYPE_S1); +- addr |= (u64) data->flag & ENHANCED_ATOS_ADDR_ATTR_MASK; +- bitmap_zero(loc_regs, MAX_REGISTERS); +- if (!registers_acquire(agent, loc_regs, data->nr)) { +- pr_err("agent smmu: busy now, try again later.\n"); +- ret = -EBUSY; +- goto put_device; +- } +- +- idx = *succeed; +- while (idx < data->nr) { +- bitmap_zero(bitmask, MAX_REGISTERS); +- +- bitmap_for_each_set_bit(i, loc_regs, MAX_REGISTERS) { +- if (idx >= data->nr) +- break; +- write_enhanced_atos(agent, i, sid, addr, data->iova[idx++]); +- bitmap_set(bitmask, i, MAX_REGISTERS); +- } +- +- bitmap_to_arr32(&bitmask_u32, bitmask, MAX_REGISTERS); +- writel(bitmask_u32, agent->base + AGENT_SMMU_ATOS_CTRL); +- readl_poll_timeout(agent->base + AGENT_SMMU_ATOS_CTRL, state, +- !(state & bitmask_u32), AGENT_SMMU_POLL_US, +- AGENT_SMMU_TIMEOUT_US); +- +- idx = *succeed; +- bitmap_for_each_set_bit(i, bitmask, MAX_REGISTERS) { +- if (idx >= data->nr) +- break; +- +- if (data->pa[idx] != 0) { +- idx++; +- continue; +- } +- ret = read_enhanced_atos(agent, i, idx, state, data); +- if (ret) { +- *succeed = idx; +- pr_err("agent smmu: translate failed, reason %d\n", ret); +- goto free_bits; +- } +- idx++; +- } +- *succeed = idx; +- } +- +-free_bits: +- write_lock(&agent->rw_lock); +- bitmap_andnot(agent->regs, agent->regs, loc_regs, MAX_REGISTERS); +- write_unlock(&agent->rw_lock); +-put_device: +- put_device(agent->dev); +- return ret; +-} +-EXPORT_SYMBOL_GPL(agent_smmu_iova_to_phys); +- +-static const struct acpi_device_id agent_smmu_acpi_match[] = { +- {"SMMU0000", 0}, +- {} +-}; +-MODULE_DEVICE_TABLE(acpi, agent_smmu_acpi_match); +- +-static struct platform_driver agent_smmu_driver = { +- .driver = { +- .name = "agent_smmu_platform", +- .acpi_match_table = ACPI_PTR(agent_smmu_acpi_match), +- }, +- .probe = agent_smmu_platform_probe, +- .remove = agent_smmu_platform_remove, +-}; +-module_platform_driver(agent_smmu_driver); +diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c +index b57536b024ac..ea89d63370d8 100644 +--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c ++++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c +@@ -43,9 +43,6 @@ + + #include "arm-smmu.h" + +-#ifdef CONFIG_ARCH_PHYTIUM +-#include +-#endif + /* + * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU + * global register space are still, in fact, using a hypervisor to mediate it +@@ -57,7 +54,6 @@ + + #define MSI_IOVA_BASE 0x8000000 + #define MSI_IOVA_LENGTH 0x100000 +-#define SMR_MASK_SHIFT 16 + + static int force_stage; + module_param(force_stage, int, S_IRUGO); +@@ -1376,20 +1372,6 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) + return ERR_PTR(-ENODEV); + } + +-#ifdef CONFIG_ARCH_PHYTIUM +- /* ft2000+ */ +- if (typeof_ft2000plus()) { +- int num = fwspec->num_ids; +- +- for (i = 0; i < num; i++) { +-#define FWID_READ(id) (((u16)(id) >> 3) | (((id) >> SMR_MASK_SHIFT | 0x7000) << SMR_MASK_SHIFT)) +- u32 fwid = FWID_READ(fwspec->ids[i]); +- +- iommu_fwspec_add_ids(dev, &fwid, 1); +- } +- } +-#endif +- + ret = -EINVAL; + for (i = 0; i < fwspec->num_ids; i++) { + u16 sid = FIELD_GET(ARM_SMMU_SMR_ID, fwspec->ids[i]); +@@ -1478,12 +1460,6 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev) + if (group && smmu->s2crs[idx].group && + group != smmu->s2crs[idx].group) + return ERR_PTR(-EINVAL); +-#ifdef CONFIG_ARCH_PHYTIUM +- if (typeof_s2500()) +- break; +- if (typeof_ft2000plus() && !smmu->s2crs[idx].group) +- continue; +-#endif + + group = smmu->s2crs[idx].group; + } +@@ -1609,29 +1585,11 @@ static void arm_smmu_get_resv_regions(struct device *dev, + iommu_dma_get_resv_regions(dev, head); + } + +-#ifdef CONFIG_ARCH_PHYTIUM +-static bool cpu_using_identity_iommu_domain(struct device *dev) +-{ +- if (typeof_ft2000plus() || typeof_s2500()) +- return true; +- +- return false; +-} +-#else +-static bool cpu_using_identity_iommu_domain(struct device *dev) +-{ +- return false; +-} +-#endif +- + static int arm_smmu_def_domain_type(struct device *dev) + { + struct arm_smmu_master_cfg *cfg = dev_iommu_priv_get(dev); + const struct arm_smmu_impl *impl = cfg->smmu->impl; + +- if (cpu_using_identity_iommu_domain(dev)) +- return IOMMU_DOMAIN_IDENTITY; +- + if (impl && impl->def_domain_type) + return impl->def_domain_type(dev); + +@@ -2146,10 +2104,11 @@ static int arm_smmu_device_probe(struct platform_device *pdev) + if (err) + return err; + +- smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ioaddr = res->start; ++ smmu->base = devm_ioremap_resource(dev, res); + if (IS_ERR(smmu->base)) + return PTR_ERR(smmu->base); +- ioaddr = res->start; + /* + * The resource size should effectively match the value of SMMU_TOP; + * stash that temporarily until we know PAGESIZE to validate it with. +diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c +index 38641110be00..7f280c8d5c53 100644 +--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c ++++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c +@@ -758,12 +758,9 @@ static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu) + { + struct device_node *child; + +- for_each_child_of_node(qcom_iommu->dev->of_node, child) { +- if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) { +- of_node_put(child); ++ for_each_child_of_node(qcom_iommu->dev->of_node, child) ++ if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) + return true; +- } +- } + + return false; + } +diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c +index d1539b7399a9..0cbcd3fc3e7e 100644 +--- a/drivers/iommu/dma-iommu.c ++++ b/drivers/iommu/dma-iommu.c +@@ -216,11 +216,9 @@ static int iova_reserve_pci_windows(struct pci_dev *dev, + lo = iova_pfn(iovad, start); + hi = iova_pfn(iovad, end); + reserve_iova(iovad, lo, hi); +- } else if (end < start) { ++ } else { + /* dma_ranges list should be sorted */ +- dev_err(&dev->dev, +- "Failed to reserve IOVA [%pa-%pa]\n", +- &start, &end); ++ dev_err(&dev->dev, "Failed to reserve IOVA\n"); + return -EINVAL; + } + +diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c +index 0cdb5493a464..de324b4eedfe 100644 +--- a/drivers/iommu/exynos-iommu.c ++++ b/drivers/iommu/exynos-iommu.c +@@ -635,7 +635,7 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) + + ret = iommu_device_register(&data->iommu); + if (ret) +- goto err_iommu_register; ++ return ret; + + platform_set_drvdata(pdev, data); + +@@ -662,10 +662,6 @@ static int exynos_sysmmu_probe(struct platform_device *pdev) + pm_runtime_enable(dev); + + return 0; +- +-err_iommu_register: +- iommu_device_sysfs_remove(&data->iommu); +- return ret; + } + + static int __maybe_unused exynos_sysmmu_suspend(struct device *dev) +diff --git a/drivers/iommu/fsl_pamu.c b/drivers/iommu/fsl_pamu.c +index 25689bdf812e..b9a974d97831 100644 +--- a/drivers/iommu/fsl_pamu.c ++++ b/drivers/iommu/fsl_pamu.c +@@ -1122,7 +1122,7 @@ static int fsl_pamu_probe(struct platform_device *pdev) + ret = create_csd(ppaact_phys, mem_size, csd_port_id); + if (ret) { + dev_err(dev, "could not create coherence subdomain\n"); +- goto error; ++ return ret; + } + } + +diff --git a/drivers/iommu/intel/Kconfig b/drivers/iommu/intel/Kconfig +index cecdad7f2aba..5337ee1584b0 100644 +--- a/drivers/iommu/intel/Kconfig ++++ b/drivers/iommu/intel/Kconfig +@@ -40,7 +40,6 @@ config INTEL_IOMMU_SVM + select PCI_PRI + select MMU_NOTIFIER + select IOASID +- select IOMMU_SVA + help + Shared Virtual Memory (SVM) provides a facility for devices + to access DMA resources through process address space by +diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c +index 9e591594183e..02e7c10a4224 100644 +--- a/drivers/iommu/intel/dmar.c ++++ b/drivers/iommu/intel/dmar.c +@@ -215,7 +215,7 @@ static bool dmar_match_pci_path(struct dmar_pci_notify_info *info, int bus, + } + + /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */ +-int dmar_pci_insert_dev_scope(struct dmar_pci_notify_info *info, ++int dmar_insert_dev_scope(struct dmar_pci_notify_info *info, + void *start, void*end, u16 segment, + struct dmar_dev_scope *devices, + int devices_cnt) +@@ -304,7 +304,7 @@ static int dmar_pci_bus_add_dev(struct dmar_pci_notify_info *info) + + drhd = container_of(dmaru->hdr, + struct acpi_dmar_hardware_unit, header); +- ret = dmar_pci_insert_dev_scope(info, (void *)(drhd + 1), ++ ret = dmar_insert_dev_scope(info, (void *)(drhd + 1), + ((void *)drhd) + drhd->header.length, + dmaru->segment, + dmaru->devices, dmaru->devices_cnt); +@@ -385,7 +385,7 @@ static int dmar_pci_bus_notifier(struct notifier_block *nb, + + static struct notifier_block dmar_pci_bus_nb = { + .notifier_call = dmar_pci_bus_notifier, +- .priority = 1, ++ .priority = INT_MIN, + }; + + static struct dmar_drhd_unit * +@@ -497,7 +497,7 @@ static int dmar_parse_one_rhsa(struct acpi_dmar_header *header, void *arg) + if (drhd->reg_base_addr == rhsa->base_address) { + int node = pxm_to_node(rhsa->proximity_domain); + +- if (node != NUMA_NO_NODE && !node_online(node)) ++ if (!node_online(node)) + node = NUMA_NO_NODE; + drhd->iommu->node = node; + return 0; +@@ -719,58 +719,47 @@ dmar_find_matched_drhd_unit(struct pci_dev *dev) + return dmaru; + } + +-/* Return: > 0 if match found, 0 if no match found */ +-bool dmar_acpi_insert_dev_scope(u8 device_number, +- struct acpi_device *adev, +- void *start, void *end, +- struct dmar_dev_scope *devices, +- int devices_cnt) ++static void __init dmar_acpi_insert_dev_scope(u8 device_number, ++ struct acpi_device *adev) + { ++ struct dmar_drhd_unit *dmaru; ++ struct acpi_dmar_hardware_unit *drhd; + struct acpi_dmar_device_scope *scope; + struct device *tmp; + int i; + struct acpi_dmar_pci_path *path; + +- for (; start < end; start += scope->length) { +- scope = start; +- if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) +- continue; +- if (scope->enumeration_id != device_number) +- continue; +- path = (void *)(scope + 1); +- for_each_dev_scope(devices, devices_cnt, i, tmp) +- if (tmp == NULL) { +- devices[i].bus = scope->bus; +- devices[i].devfn = PCI_DEVFN(path->device, path->function); +- rcu_assign_pointer(devices[i].dev, +- get_device(&adev->dev)); +- return true; +- } +- WARN_ON(i >= devices_cnt); +- } +- return false; +-} +- +-static int dmar_acpi_bus_add_dev(u8 device_number, struct acpi_device *adev) +-{ +- struct dmar_drhd_unit *dmaru; +- struct acpi_dmar_hardware_unit *drhd; +- int ret; +- + for_each_drhd_unit(dmaru) { + drhd = container_of(dmaru->hdr, + struct acpi_dmar_hardware_unit, + header); +- ret = dmar_acpi_insert_dev_scope(device_number, adev, (void *)(drhd+1), +- ((void *)drhd)+drhd->header.length, +- dmaru->devices, dmaru->devices_cnt); +- if (ret) +- break; +- } +- if (ret > 0) +- ret = dmar_rmrr_add_acpi_dev(device_number, adev); + +- return ret; ++ for (scope = (void *)(drhd + 1); ++ (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; ++ scope = ((void *)scope) + scope->length) { ++ if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) ++ continue; ++ if (scope->enumeration_id != device_number) ++ continue; ++ ++ path = (void *)(scope + 1); ++ pr_info("ACPI device \"%s\" under DMAR at %llx as %02x:%02x.%d\n", ++ dev_name(&adev->dev), dmaru->reg_base_addr, ++ scope->bus, path->device, path->function); ++ for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) ++ if (tmp == NULL) { ++ dmaru->devices[i].bus = scope->bus; ++ dmaru->devices[i].devfn = PCI_DEVFN(path->device, ++ path->function); ++ rcu_assign_pointer(dmaru->devices[i].dev, ++ get_device(&adev->dev)); ++ return; ++ } ++ BUG_ON(i >= dmaru->devices_cnt); ++ } ++ } ++ pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", ++ device_number, dev_name(&adev->dev)); + } + + static int __init dmar_acpi_dev_scope_init(void) +@@ -799,7 +788,7 @@ static int __init dmar_acpi_dev_scope_init(void) + andd->device_name); + continue; + } +- dmar_acpi_bus_add_dev(andd->device_number, adev); ++ dmar_acpi_insert_dev_scope(andd->device_number, adev); + } + } + return 0; +@@ -827,7 +816,6 @@ int __init dmar_dev_scope_init(void) + info = dmar_alloc_pci_notify_info(dev, + BUS_NOTIFY_ADD_DEVICE); + if (!info) { +- pci_dev_put(dev); + return dmar_dev_scope_status; + } else { + dmar_pci_bus_add_dev(info); +@@ -1149,7 +1137,7 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) + + err = iommu_device_register(&iommu->iommu); + if (err) +- goto err_sysfs; ++ goto err_unmap; + } + + drhd->iommu = iommu; +@@ -1157,8 +1145,6 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd) + + return 0; + +-err_sysfs: +- iommu_device_sysfs_remove(&iommu->iommu); + err_unmap: + unmap_iommu(iommu); + error_free_seq_id: +diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c +index a19dbb9483eb..e3a7e3f546a0 100644 +--- a/drivers/iommu/intel/iommu.c ++++ b/drivers/iommu/intel/iommu.c +@@ -560,36 +560,14 @@ static inline int domain_pfn_supported(struct dmar_domain *domain, + return !(addr_width < BITS_PER_LONG && pfn >> addr_width); + } + +-/* +- * Calculate the Supported Adjusted Guest Address Widths of an IOMMU. +- * Refer to 11.4.2 of the VT-d spec for the encoding of each bit of +- * the returned SAGAW. +- */ +-static unsigned long __iommu_calculate_sagaw(struct intel_iommu *iommu) +-{ +- unsigned long fl_sagaw, sl_sagaw; +- +- fl_sagaw = BIT(2) | (cap_5lp_support(iommu->cap) ? BIT(3) : 0); +- sl_sagaw = cap_sagaw(iommu->cap); +- +- /* Second level only. */ +- if (!sm_supported(iommu) || !ecap_flts(iommu->ecap)) +- return sl_sagaw; +- +- /* First level only. */ +- if (!ecap_slts(iommu->ecap)) +- return fl_sagaw; +- +- return fl_sagaw & sl_sagaw; +-} +- + static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) + { + unsigned long sagaw; + int agaw = -1; + +- sagaw = __iommu_calculate_sagaw(iommu); +- for (agaw = width_to_agaw(max_gaw); agaw >= 0; agaw--) { ++ sagaw = cap_sagaw(iommu->cap); ++ for (agaw = width_to_agaw(max_gaw); ++ agaw >= 0; agaw--) { + if (test_bit(agaw, &sagaw)) + break; + } +@@ -755,8 +733,6 @@ static int domain_update_device_node(struct dmar_domain *domain) + return nid; + } + +-static void domain_update_iotlb(struct dmar_domain *domain); +- + /* Some capabilities may be different across iommus */ + static void domain_update_iommu_cap(struct dmar_domain *domain) + { +@@ -782,8 +758,6 @@ static void domain_update_iommu_cap(struct dmar_domain *domain) + domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw - 1); + else + domain->domain.geometry.aperture_end = __DOMAIN_MAX_ADDR(domain->gaw); +- +- domain_update_iotlb(domain); + } + + struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus, +@@ -1519,21 +1493,16 @@ static void domain_update_iotlb(struct dmar_domain *domain) + + assert_spin_locked(&device_domain_lock); + +- list_for_each_entry(info, &domain->devices, link) +- if (info->ats_enabled) { +- has_iotlb_device = true; +- break; +- } ++ list_for_each_entry(info, &domain->devices, link) { ++ struct pci_dev *pdev; + +- if (!has_iotlb_device) { +- struct subdev_domain_info *sinfo; ++ if (!info->dev || !dev_is_pci(info->dev)) ++ continue; + +- list_for_each_entry(sinfo, &domain->subdevices, link_domain) { +- info = get_domain_info(sinfo->pdev); +- if (info && info->ats_enabled) { +- has_iotlb_device = true; +- break; +- } ++ pdev = to_pci_dev(info->dev); ++ if (pdev->ats_enabled) { ++ has_iotlb_device = true; ++ break; + } + } + +@@ -1615,37 +1584,25 @@ static void iommu_disable_dev_iotlb(struct device_domain_info *info) + #endif + } + +-static void __iommu_flush_dev_iotlb(struct device_domain_info *info, +- u64 addr, unsigned int mask) +-{ +- u16 sid, qdep; +- +- if (!info || !info->ats_enabled) +- return; +- +- sid = info->bus << 8 | info->devfn; +- qdep = info->ats_qdep; +- qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, +- qdep, addr, mask); +-} +- + static void iommu_flush_dev_iotlb(struct dmar_domain *domain, + u64 addr, unsigned mask) + { ++ u16 sid, qdep; + unsigned long flags; + struct device_domain_info *info; +- struct subdev_domain_info *sinfo; + + if (!domain->has_iotlb_device) + return; + + spin_lock_irqsave(&device_domain_lock, flags); +- list_for_each_entry(info, &domain->devices, link) +- __iommu_flush_dev_iotlb(info, addr, mask); ++ list_for_each_entry(info, &domain->devices, link) { ++ if (!info->ats_enabled) ++ continue; + +- list_for_each_entry(sinfo, &domain->subdevices, link_domain) { +- info = get_domain_info(sinfo->pdev); +- __iommu_flush_dev_iotlb(info, addr, mask); ++ sid = info->bus << 8 | info->devfn; ++ qdep = info->ats_qdep; ++ qi_flush_dev_iotlb(info->iommu, sid, info->pfsid, ++ qdep, addr, mask); + } + spin_unlock_irqrestore(&device_domain_lock, flags); + } +@@ -1669,8 +1626,7 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, + unsigned long pfn, unsigned int pages, + int ih, int map) + { +- unsigned int aligned_pages = __roundup_pow_of_two(pages); +- unsigned int mask = ilog2(aligned_pages); ++ unsigned int mask = ilog2(__roundup_pow_of_two(pages)); + uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; + u16 did = domain->iommu_did[iommu->seq_id]; + +@@ -1682,30 +1638,10 @@ static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, + if (domain_use_first_level(domain)) { + domain_flush_piotlb(iommu, domain, addr, pages, ih); + } else { +- unsigned long bitmask = aligned_pages - 1; +- +- /* +- * PSI masks the low order bits of the base address. If the +- * address isn't aligned to the mask, then compute a mask value +- * needed to ensure the target range is flushed. +- */ +- if (unlikely(bitmask & pfn)) { +- unsigned long end_pfn = pfn + pages - 1, shared_bits; +- +- /* +- * Since end_pfn <= pfn + bitmask, the only way bits +- * higher than bitmask can differ in pfn and end_pfn is +- * by carrying. This means after masking out bitmask, +- * high bits starting with the first set bit in +- * shared_bits are all equal in both pfn and end_pfn. +- */ +- shared_bits = ~(pfn ^ end_pfn) & ~bitmask; +- mask = shared_bits ? __ffs(shared_bits) : BITS_PER_LONG; +- } +- + /* + * Fallback to domain selective flush if no PSI support or +- * the size is too big. ++ * the size is too big. PSI requires page size to be 2 ^ x, ++ * and the base address is naturally aligned to the size. + */ + if (!cap_pgsel_inv(iommu->cap) || + mask > cap_max_amask_val(iommu->cap)) +@@ -1972,7 +1908,6 @@ static struct dmar_domain *alloc_domain(int flags) + domain->flags |= DOMAIN_FLAG_USE_FIRST_LEVEL; + domain->has_iotlb_device = false; + INIT_LIST_HEAD(&domain->devices); +- INIT_LIST_HEAD(&domain->subdevices); + + return domain; + } +@@ -2570,11 +2505,10 @@ static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long i + return domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); + } + +-static void domain_context_clear_one(struct device_domain_info *info, u8 bus, u8 devfn) ++static void domain_context_clear_one(struct intel_iommu *iommu, u8 bus, u8 devfn) + { +- struct intel_iommu *iommu = info->iommu; +- struct context_entry *context; + unsigned long flags; ++ struct context_entry *context; + u16 did_old; + + if (!iommu) +@@ -2586,16 +2520,7 @@ static void domain_context_clear_one(struct device_domain_info *info, u8 bus, u8 + spin_unlock_irqrestore(&iommu->lock, flags); + return; + } +- +- if (sm_supported(iommu)) { +- if (hw_pass_through && domain_type_is_si(info->domain)) +- did_old = FLPT_DEFAULT_DID; +- else +- did_old = info->domain->iommu_did[iommu->seq_id]; +- } else { +- did_old = context_domain_id(context); +- } +- ++ did_old = context_domain_id(context); + context_clear_entry(context); + __iommu_flush_cache(iommu, context, sizeof(*context)); + spin_unlock_irqrestore(&iommu->lock, flags); +@@ -2613,8 +2538,6 @@ static void domain_context_clear_one(struct device_domain_info *info, u8 bus, u8 + 0, + 0, + DMA_TLB_DSI_FLUSH); +- +- __iommu_flush_dev_iotlb(info, 0, MAX_AGAW_PFN_WIDTH); + } + + static inline void unlink_domain_info(struct device_domain_info *info) +@@ -2683,9 +2606,9 @@ static int domain_setup_first_level(struct intel_iommu *iommu, + struct device *dev, + u32 pasid) + { ++ int flags = PASID_FLAG_SUPERVISOR_MODE; + struct dma_pte *pgd = domain->pgd; + int agaw, level; +- int flags = 0; + + /* + * Skip top levels of page tables for iommu which has +@@ -2701,10 +2624,7 @@ static int domain_setup_first_level(struct intel_iommu *iommu, + if (level != 4 && level != 5) + return -EINVAL; + +- if (pasid != PASID_RID2PASID) +- flags |= PASID_FLAG_SUPERVISOR_MODE; +- if (level == 5) +- flags |= PASID_FLAG_FL5LP; ++ flags |= (level == 5) ? PASID_FLAG_FL5LP : 0; + + if (domain->domain.type == IOMMU_DOMAIN_UNMANAGED) + flags |= PASID_FLAG_PAGE_SNOOP; +@@ -2754,7 +2674,7 @@ static struct dmar_domain *dmar_insert_one_dev_info(struct intel_iommu *iommu, + info->iommu = iommu; + info->pasid_table = NULL; + info->auxd_enabled = 0; +- INIT_LIST_HEAD(&info->subdevices); ++ INIT_LIST_HEAD(&info->auxiliary_domains); + + if (dev && dev_is_pci(dev)) { + struct pci_dev *pdev = to_pci_dev(info->dev); +@@ -2880,7 +2800,6 @@ static int __init si_domain_init(int hw) + + if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { + domain_exit(si_domain); +- si_domain = NULL; + return -EFAULT; + } + +@@ -3540,10 +3459,6 @@ static int __init init_dmars(void) + disable_dmar_iommu(iommu); + free_dmar_iommu(iommu); + } +- if (si_domain) { +- domain_exit(si_domain); +- si_domain = NULL; +- } + + kfree(g_iommus); + +@@ -4682,25 +4597,6 @@ int dmar_find_matched_atsr_unit(struct pci_dev *dev) + return ret; + } + +-int dmar_rmrr_add_acpi_dev(u8 device_number, struct acpi_device *adev) +-{ +- int ret; +- struct dmar_rmrr_unit *rmrru; +- struct acpi_dmar_reserved_memory *rmrr; +- +- list_for_each_entry(rmrru, &dmar_rmrr_units, list) { +- rmrr = container_of(rmrru->hdr, +- struct acpi_dmar_reserved_memory, +- header); +- ret = dmar_acpi_insert_dev_scope(device_number, adev, (void *)(rmrr + 1), +- ((void *)rmrr) + rmrr->header.length, +- rmrru->devices, rmrru->devices_cnt); +- if (ret) +- break; +- } +- return 0; +-} +- + int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) + { + int ret; +@@ -4716,7 +4612,7 @@ int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) + rmrr = container_of(rmrru->hdr, + struct acpi_dmar_reserved_memory, header); + if (info->event == BUS_NOTIFY_ADD_DEVICE) { +- ret = dmar_pci_insert_dev_scope(info, (void *)(rmrr + 1), ++ ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), + ((void *)rmrr) + rmrr->header.length, + rmrr->segment, rmrru->devices, + rmrru->devices_cnt); +@@ -4734,7 +4630,7 @@ int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) + + atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); + if (info->event == BUS_NOTIFY_ADD_DEVICE) { +- ret = dmar_pci_insert_dev_scope(info, (void *)(atsr + 1), ++ ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), + (void *)atsr + atsr->header.length, + atsr->segment, atsru->devices, + atsru->devices_cnt); +@@ -4946,10 +4842,8 @@ static inline bool has_external_pci(void) + struct pci_dev *pdev = NULL; + + for_each_pci_dev(pdev) +- if (pdev->external_facing) { +- pci_dev_put(pdev); ++ if (pdev->external_facing) + return true; +- } + + return false; + } +@@ -4975,22 +4869,6 @@ static int __init platform_optin_force_iommu(void) + return 1; + } + +-static int acpi_device_create_direct_mappings(struct device *pn_dev, struct device *acpi_device) +-{ +- struct iommu_group *group; +- +- acpi_device->bus->iommu_ops = &intel_iommu_ops; +- group = iommu_group_get(pn_dev); +- if (!group) { +- pr_warn("ACPI name space devices create direct mappings wrong!\n"); +- return -EINVAL; +- } +- printk(KERN_INFO "pn_dev:%s enter to %s\n", dev_name(pn_dev), __func__); +- __acpi_device_create_direct_mappings(group, acpi_device); +- +- return 0; +-} +- + static int __init probe_acpi_namespace_devices(void) + { + struct dmar_drhd_unit *drhd; +@@ -4998,7 +4876,6 @@ static int __init probe_acpi_namespace_devices(void) + struct intel_iommu *iommu __maybe_unused; + struct device *dev; + int i, ret = 0; +- u8 bus, devfn; + + for_each_active_iommu(iommu, drhd) { + for_each_active_dev_scope(drhd->devices, +@@ -5007,8 +4884,6 @@ static int __init probe_acpi_namespace_devices(void) + struct iommu_group *group; + struct acpi_device *adev; + +- struct device *pn_dev = NULL; +- struct device_domain_info *info = NULL; + if (dev->bus != &acpi_bus_type) + continue; + +@@ -5018,57 +4893,19 @@ static int __init probe_acpi_namespace_devices(void) + &adev->physical_node_list, node) { + group = iommu_group_get(pn->dev); + if (group) { +- pn_dev = pn->dev; + iommu_group_put(group); + continue; + } + +- iommu = device_to_iommu(dev, &bus, &devfn); +- if (!iommu) { +- ret = -ENODEV; +- goto unlock; +- } +- info = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); +- if (!info) { +- pn->dev->bus->iommu_ops = &intel_iommu_ops; +- ret = iommu_probe_device(pn->dev); +- if (ret) { +- pr_err("pn->dev:%s probe fail! ret:%d\n", +- dev_name(pn->dev), ret); +- goto unlock; +- } +- } +- pn_dev = pn->dev; +- } +- if (!pn_dev) { +- iommu = device_to_iommu(dev, &bus, &devfn); +- if (!iommu) { +- ret = -ENODEV; +- goto unlock; +- } +- info = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); +- if (!info) { +- dev->bus->iommu_ops = &intel_iommu_ops; +- ret = iommu_probe_device(dev); +- if (ret) { +- pr_err("dev:%s probe fail! ret:%d\n", +- dev_name(dev), ret); +- goto unlock; +- } +- goto unlock; +- } ++ pn->dev->bus->iommu_ops = &intel_iommu_ops; ++ ret = iommu_probe_device(pn->dev); ++ if (ret) ++ break; + } +- if (!info) +- ret = acpi_device_create_direct_mappings(pn_dev, dev); +- else +- ret = acpi_device_create_direct_mappings(info->dev, dev); +-unlock: + mutex_unlock(&adev->physical_node_lock); + +- if (ret) { +- pr_err("%s fail! ret:%d\n", __func__, ret); ++ if (ret) + return ret; +- } + } + } + +@@ -5217,9 +5054,9 @@ int __init intel_iommu_init(void) + + static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *opaque) + { +- struct device_domain_info *info = opaque; ++ struct intel_iommu *iommu = opaque; + +- domain_context_clear_one(info, PCI_BUS_NUM(alias), alias & 0xff); ++ domain_context_clear_one(iommu, PCI_BUS_NUM(alias), alias & 0xff); + return 0; + } + +@@ -5229,13 +5066,12 @@ static int domain_context_clear_one_cb(struct pci_dev *pdev, u16 alias, void *op + * devices, unbinding the driver from any one of them will possibly leave + * the others unable to operate. + */ +-static void domain_context_clear(struct device_domain_info *info) ++static void domain_context_clear(struct intel_iommu *iommu, struct device *dev) + { +- if (!info->iommu || !info->dev || !dev_is_pci(info->dev)) ++ if (!iommu || !dev || !dev_is_pci(dev)) + return; + +- pci_for_each_dma_alias(to_pci_dev(info->dev), +- &domain_context_clear_one_cb, info); ++ pci_for_each_dma_alias(to_pci_dev(dev), &domain_context_clear_one_cb, iommu); + } + + static void __dmar_remove_one_dev_info(struct device_domain_info *info) +@@ -5252,13 +5088,14 @@ static void __dmar_remove_one_dev_info(struct device_domain_info *info) + iommu = info->iommu; + domain = info->domain; + +- if (info->dev && !dev_is_real_dma_subdevice(info->dev)) { ++ if (info->dev) { + if (dev_is_pci(info->dev) && sm_supported(iommu)) + intel_pasid_tear_down_entry(iommu, info->dev, + PASID_RID2PASID, false); + + iommu_disable_dev_iotlb(info); +- domain_context_clear(info); ++ if (!dev_is_real_dma_subdevice(info->dev)) ++ domain_context_clear(iommu, info->dev); + intel_pasid_free_table(info->dev); + } + +@@ -5373,63 +5210,33 @@ is_aux_domain(struct device *dev, struct iommu_domain *domain) + domain->type == IOMMU_DOMAIN_UNMANAGED; + } + +-static inline struct subdev_domain_info * +-lookup_subdev_info(struct dmar_domain *domain, struct device *dev) +-{ +- struct subdev_domain_info *sinfo; +- +- if (!list_empty(&domain->subdevices)) { +- list_for_each_entry(sinfo, &domain->subdevices, link_domain) { +- if (sinfo->pdev == dev) +- return sinfo; +- } +- } +- +- return NULL; +-} +- +-static int auxiliary_link_device(struct dmar_domain *domain, +- struct device *dev) ++static void auxiliary_link_device(struct dmar_domain *domain, ++ struct device *dev) + { + struct device_domain_info *info = get_domain_info(dev); +- struct subdev_domain_info *sinfo = lookup_subdev_info(domain, dev); + + assert_spin_locked(&device_domain_lock); + if (WARN_ON(!info)) +- return -EINVAL; +- +- if (!sinfo) { +- sinfo = kzalloc(sizeof(*sinfo), GFP_ATOMIC); +- if (!sinfo) +- return -ENOMEM; +- sinfo->domain = domain; +- sinfo->pdev = dev; +- list_add(&sinfo->link_phys, &info->subdevices); +- list_add(&sinfo->link_domain, &domain->subdevices); +- } ++ return; + +- return ++sinfo->users; ++ domain->auxd_refcnt++; ++ list_add(&domain->auxd, &info->auxiliary_domains); + } + +-static int auxiliary_unlink_device(struct dmar_domain *domain, +- struct device *dev) ++static void auxiliary_unlink_device(struct dmar_domain *domain, ++ struct device *dev) + { + struct device_domain_info *info = get_domain_info(dev); +- struct subdev_domain_info *sinfo = lookup_subdev_info(domain, dev); +- int ret; + + assert_spin_locked(&device_domain_lock); +- if (WARN_ON(!info || !sinfo || sinfo->users <= 0)) +- return -EINVAL; ++ if (WARN_ON(!info)) ++ return; + +- ret = --sinfo->users; +- if (!ret) { +- list_del(&sinfo->link_phys); +- list_del(&sinfo->link_domain); +- kfree(sinfo); +- } ++ list_del(&domain->auxd); ++ domain->auxd_refcnt--; + +- return ret; ++ if (!domain->auxd_refcnt && domain->default_pasid > 0) ++ ioasid_put(domain->default_pasid); + } + + static int aux_domain_add_dev(struct dmar_domain *domain, +@@ -5458,19 +5265,6 @@ static int aux_domain_add_dev(struct dmar_domain *domain, + } + + spin_lock_irqsave(&device_domain_lock, flags); +- ret = auxiliary_link_device(domain, dev); +- if (ret <= 0) +- goto link_failed; +- +- /* +- * Subdevices from the same physical device can be attached to the +- * same domain. For such cases, only the first subdevice attachment +- * needs to go through the full steps in this function. So if ret > +- * 1, just goto out. +- */ +- if (ret > 1) +- goto out; +- + /* + * iommu->lock must be held to attach domain to iommu and setup the + * pasid entry for second level translation. +@@ -5489,9 +5283,10 @@ static int aux_domain_add_dev(struct dmar_domain *domain, + domain->default_pasid); + if (ret) + goto table_failed; +- + spin_unlock(&iommu->lock); +-out: ++ ++ auxiliary_link_device(domain, dev); ++ + spin_unlock_irqrestore(&device_domain_lock, flags); + + return 0; +@@ -5500,11 +5295,9 @@ static int aux_domain_add_dev(struct dmar_domain *domain, + domain_detach_iommu(domain, iommu); + attach_failed: + spin_unlock(&iommu->lock); +- auxiliary_unlink_device(domain, dev); +-link_failed: + spin_unlock_irqrestore(&device_domain_lock, flags); +- if (list_empty(&domain->subdevices) && domain->default_pasid > 0) +- ioasid_free(domain->default_pasid); ++ if (!domain->auxd_refcnt && domain->default_pasid > 0) ++ ioasid_put(domain->default_pasid); + + return ret; + } +@@ -5523,18 +5316,14 @@ static void aux_domain_remove_dev(struct dmar_domain *domain, + info = get_domain_info(dev); + iommu = info->iommu; + +- if (!auxiliary_unlink_device(domain, dev)) { +- spin_lock(&iommu->lock); +- intel_pasid_tear_down_entry(iommu, dev, +- domain->default_pasid, false); +- domain_detach_iommu(domain, iommu); +- spin_unlock(&iommu->lock); +- } ++ auxiliary_unlink_device(domain, dev); + +- spin_unlock_irqrestore(&device_domain_lock, flags); ++ spin_lock(&iommu->lock); ++ intel_pasid_tear_down_entry(iommu, dev, domain->default_pasid, false); ++ domain_detach_iommu(domain, iommu); ++ spin_unlock(&iommu->lock); + +- if (list_empty(&domain->subdevices) && domain->default_pasid > 0) +- ioasid_free(domain->default_pasid); ++ spin_unlock_irqrestore(&device_domain_lock, flags); + } + + static int prepare_domain_attach_device(struct iommu_domain *domain, +@@ -6251,12 +6040,6 @@ intel_iommu_dev_enable_feat(struct device *dev, enum iommu_dev_features feat) + if (!info) + return -EINVAL; + +- if (intel_iommu_enable_pasid(info->iommu, dev)) +- return -ENODEV; +- +- if (!info->pasid_enabled || !info->pri_enabled || !info->ats_enabled) +- return -EINVAL; +- + if (info->iommu->flags & VTD_FLAG_SVM_CAPABLE) + return 0; + } +@@ -6494,7 +6277,7 @@ static void quirk_igfx_skip_te_disable(struct pci_dev *dev) + ver = (dev->device >> 8) & 0xff; + if (ver != 0x45 && ver != 0x46 && ver != 0x4c && + ver != 0x4e && ver != 0x8a && ver != 0x98 && +- ver != 0x9a && ver != 0xa7) ++ ver != 0x9a) + return; + + if (risky_device(dev)) +diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c +index b853888774e6..aedaae4630bc 100644 +--- a/drivers/iommu/intel/irq_remapping.c ++++ b/drivers/iommu/intel/irq_remapping.c +@@ -576,8 +576,9 @@ static int intel_setup_irq_remapping(struct intel_iommu *iommu) + fn, &intel_ir_domain_ops, + iommu); + if (!iommu->ir_domain) { ++ irq_domain_free_fwnode(fn); + pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id); +- goto out_free_fwnode; ++ goto out_free_bitmap; + } + iommu->ir_msi_domain = + arch_create_remap_msi_irq_domain(iommu->ir_domain, +@@ -601,7 +602,7 @@ static int intel_setup_irq_remapping(struct intel_iommu *iommu) + + if (dmar_enable_qi(iommu)) { + pr_err("Failed to enable queued invalidation\n"); +- goto out_free_ir_domain; ++ goto out_free_bitmap; + } + } + +@@ -625,14 +626,6 @@ static int intel_setup_irq_remapping(struct intel_iommu *iommu) + + return 0; + +-out_free_ir_domain: +- if (iommu->ir_msi_domain) +- irq_domain_remove(iommu->ir_msi_domain); +- iommu->ir_msi_domain = NULL; +- irq_domain_remove(iommu->ir_domain); +- iommu->ir_domain = NULL; +-out_free_fwnode: +- irq_domain_free_fwnode(fn); + out_free_bitmap: + bitmap_free(bitmap); + out_free_pages: +diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c +index 86fd49ae7f61..ce4ef2d245e3 100644 +--- a/drivers/iommu/intel/pasid.c ++++ b/drivers/iommu/intel/pasid.c +@@ -466,6 +466,20 @@ pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, + qi_submit_sync(iommu, &desc, 1, 0); + } + ++static void ++iotlb_invalidation_with_pasid(struct intel_iommu *iommu, u16 did, u32 pasid) ++{ ++ struct qi_desc desc; ++ ++ desc.qw0 = QI_EIOTLB_PASID(pasid) | QI_EIOTLB_DID(did) | ++ QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE; ++ desc.qw1 = 0; ++ desc.qw2 = 0; ++ desc.qw3 = 0; ++ ++ qi_submit_sync(iommu, &desc, 1, 0); ++} ++ + static void + devtlb_invalidation_with_pasid(struct intel_iommu *iommu, + struct device *dev, u32 pasid) +@@ -497,26 +511,20 @@ void intel_pasid_tear_down_entry(struct intel_iommu *iommu, struct device *dev, + u32 pasid, bool fault_ignore) + { + struct pasid_entry *pte; +- u16 did, pgtt; ++ u16 did; + + pte = intel_pasid_get_entry(dev, pasid); + if (WARN_ON(!pte)) + return; + + did = pasid_get_domain_id(pte); +- pgtt = pasid_pte_get_pgtt(pte); +- + intel_pasid_clear_entry(dev, pasid, fault_ignore); + + if (!ecap_coherent(iommu->ecap)) + clflush_cache_range(pte, sizeof(*pte)); + + pasid_cache_invalidation_with_pasid(iommu, did, pasid); +- +- if (pgtt == PASID_ENTRY_PGTT_PT || pgtt == PASID_ENTRY_PGTT_FL_ONLY) +- qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); +- else +- iommu->flush.flush_iotlb(iommu, did, 0, 0, DMA_TLB_DSI_FLUSH); ++ iotlb_invalidation_with_pasid(iommu, did, pasid); + + /* Device IOTLB doesn't need to be flushed in caching mode. */ + if (!cap_caching_mode(iommu->cap)) +@@ -532,7 +540,7 @@ static void pasid_flush_caches(struct intel_iommu *iommu, + + if (cap_caching_mode(iommu->cap)) { + pasid_cache_invalidation_with_pasid(iommu, did, pasid); +- qi_flush_piotlb(iommu, did, pasid, 0, -1, 0); ++ iotlb_invalidation_with_pasid(iommu, did, pasid); + } else { + iommu_flush_write_buffer(iommu); + } +@@ -669,8 +677,7 @@ int intel_pasid_setup_second_level(struct intel_iommu *iommu, + * Since it is a second level only translation setup, we should + * set SRE bit as well (addresses are expected to be GPAs). + */ +- if (pasid != PASID_RID2PASID && ecap_srs(iommu->ecap)) +- pasid_set_sre(pte); ++ pasid_set_sre(pte); + pasid_set_present(pte); + pasid_flush_caches(iommu, pte, pasid, did); + +@@ -704,8 +711,7 @@ int intel_pasid_setup_pass_through(struct intel_iommu *iommu, + * We should set SRE bit as well since the addresses are expected + * to be GPAs. + */ +- if (ecap_srs(iommu->ecap)) +- pasid_set_sre(pte); ++ pasid_set_sre(pte); + pasid_set_present(pte); + pasid_flush_caches(iommu, pte, pasid, did); + +diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h +index 35963e6bf9fa..086ebd697319 100644 +--- a/drivers/iommu/intel/pasid.h ++++ b/drivers/iommu/intel/pasid.h +@@ -28,12 +28,12 @@ + #define VCMD_CMD_ALLOC 0x1 + #define VCMD_CMD_FREE 0x2 + #define VCMD_VRSP_IP 0x1 +-#define VCMD_VRSP_SC(e) (((e) & 0xff) >> 1) ++#define VCMD_VRSP_SC(e) (((e) >> 1) & 0x3) + #define VCMD_VRSP_SC_SUCCESS 0 +-#define VCMD_VRSP_SC_NO_PASID_AVAIL 16 +-#define VCMD_VRSP_SC_INVALID_PASID 16 +-#define VCMD_VRSP_RESULT_PASID(e) (((e) >> 16) & 0xfffff) +-#define VCMD_CMD_OPERAND(e) ((e) << 16) ++#define VCMD_VRSP_SC_NO_PASID_AVAIL 2 ++#define VCMD_VRSP_SC_INVALID_PASID 2 ++#define VCMD_VRSP_RESULT_PASID(e) (((e) >> 8) & 0xfffff) ++#define VCMD_CMD_OPERAND(e) ((e) << 8) + /* + * Domain ID reserved for pasid entries programmed for first-level + * only and pass-through transfer modes. +@@ -99,12 +99,6 @@ static inline bool pasid_pte_is_present(struct pasid_entry *pte) + return READ_ONCE(pte->val[0]) & PASID_PTE_PRESENT; + } + +-/* Get PGTT field of a PASID table entry */ +-static inline u16 pasid_pte_get_pgtt(struct pasid_entry *pte) +-{ +- return (u16)((READ_ONCE(pte->val[0]) >> 6) & 0x7); +-} +- + extern unsigned int intel_pasid_max_id; + int intel_pasid_alloc_id(void *ptr, int start, int end, gfp_t gfp); + void intel_pasid_free_id(u32 pasid); +diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c +index 0b7f9e39ce3b..4260bb089b2c 100644 +--- a/drivers/iommu/intel/svm.c ++++ b/drivers/iommu/intel/svm.c +@@ -17,37 +17,17 @@ + #include + #include + #include +-#include + #include + #include + #include + + #include "pasid.h" +-#include "../iommu-sva-lib.h" + + static irqreturn_t prq_event_thread(int irq, void *d); + static void intel_svm_drain_prq(struct device *dev, u32 pasid); +-#define to_intel_svm_dev(handle) container_of(handle, struct intel_svm_dev, sva) + + #define PRQ_ORDER 0 + +-static DEFINE_XARRAY_ALLOC(pasid_private_array); +-static int pasid_private_add(ioasid_t pasid, void *priv) +-{ +- return xa_alloc(&pasid_private_array, &pasid, priv, +- XA_LIMIT(pasid, pasid), GFP_ATOMIC); +-} +- +-static void pasid_private_remove(ioasid_t pasid) +-{ +- xa_erase(&pasid_private_array, pasid); +-} +- +-static void *pasid_private_find(ioasid_t pasid) +-{ +- return xa_load(&pasid_private_array, pasid); +-} +- + int intel_svm_enable_prq(struct intel_iommu *iommu) + { + struct page *pages; +@@ -143,16 +123,53 @@ static void __flush_svm_range_dev(struct intel_svm *svm, + unsigned long address, + unsigned long pages, int ih) + { +- struct device_domain_info *info = get_domain_info(sdev->dev); +- +- if (WARN_ON(!pages)) +- return; ++ struct qi_desc desc; + +- qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, address, pages, ih); +- if (info->ats_enabled) +- qi_flush_dev_iotlb_pasid(sdev->iommu, sdev->sid, info->pfsid, +- svm->pasid, sdev->qdep, address, +- order_base_2(pages)); ++ if (pages == -1) { ++ desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | ++ QI_EIOTLB_DID(sdev->did) | ++ QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | ++ QI_EIOTLB_TYPE; ++ desc.qw1 = 0; ++ } else { ++ int mask = ilog2(__roundup_pow_of_two(pages)); ++ ++ desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | ++ QI_EIOTLB_DID(sdev->did) | ++ QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | ++ QI_EIOTLB_TYPE; ++ desc.qw1 = QI_EIOTLB_ADDR(address) | ++ QI_EIOTLB_IH(ih) | ++ QI_EIOTLB_AM(mask); ++ } ++ desc.qw2 = 0; ++ desc.qw3 = 0; ++ qi_submit_sync(sdev->iommu, &desc, 1, 0); ++ ++ if (sdev->dev_iotlb) { ++ desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) | ++ QI_DEV_EIOTLB_SID(sdev->sid) | ++ QI_DEV_EIOTLB_QDEP(sdev->qdep) | ++ QI_DEIOTLB_TYPE; ++ if (pages == -1) { ++ desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | ++ QI_DEV_EIOTLB_SIZE; ++ } else if (pages > 1) { ++ /* The least significant zero bit indicates the size. So, ++ * for example, an "address" value of 0x12345f000 will ++ * flush from 0x123440000 to 0x12347ffff (256KiB). */ ++ unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT); ++ unsigned long mask = __rounddown_pow_of_two(address ^ last); ++ ++ desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) | ++ (mask - 1)) | QI_DEV_EIOTLB_SIZE; ++ } else { ++ desc.qw1 = QI_DEV_EIOTLB_ADDR(address); ++ } ++ desc.qw2 = 0; ++ desc.qw3 = 0; ++ qi_submit_sync(sdev->iommu, &desc, 1, 0); ++ } + } + + static void intel_flush_svm_range_dev(struct intel_svm *svm, +@@ -224,6 +241,7 @@ static const struct mmu_notifier_ops intel_mmuops = { + }; + + static DEFINE_MUTEX(pasid_mutex); ++static LIST_HEAD(global_svm_list); + + #define for_each_svm_dev(sdev, svm, d) \ + list_for_each_entry((sdev), &(svm)->devs, list) \ +@@ -243,7 +261,7 @@ static int pasid_to_svm_sdev(struct device *dev, unsigned int pasid, + if (pasid == INVALID_IOASID || pasid >= PASID_MAX) + return -EINVAL; + +- svm = pasid_private_find(pasid); ++ svm = ioasid_find(NULL, pasid, NULL); + if (IS_ERR(svm)) + return PTR_ERR(svm); + +@@ -353,7 +371,7 @@ int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev, + svm->gpasid = data->gpasid; + svm->flags |= SVM_FLAG_GUEST_PASID; + } +- pasid_private_add(data->hpasid, svm); ++ ioasid_set_data(data->hpasid, svm); + INIT_LIST_HEAD_RCU(&svm->devs); + mmput(svm->mm); + } +@@ -407,7 +425,7 @@ int intel_svm_bind_gpasid(struct iommu_domain *domain, struct device *dev, + list_add_rcu(&sdev->list, &svm->devs); + out: + if (!IS_ERR_OR_NULL(svm) && list_empty(&svm->devs)) { +- pasid_private_remove(data->hpasid); ++ ioasid_set_data(data->hpasid, NULL); + kfree(svm); + } + +@@ -450,7 +468,7 @@ int intel_svm_unbind_gpasid(struct device *dev, u32 pasid) + * the unbind, IOMMU driver will get notified + * and perform cleanup. + */ +- pasid_private_remove(pasid); ++ ioasid_set_data(pasid, NULL); + kfree(svm); + } + } +@@ -460,75 +478,106 @@ int intel_svm_unbind_gpasid(struct device *dev, u32 pasid) + return ret; + } + +-static int intel_svm_alloc_pasid(struct device *dev, struct mm_struct *mm, +- unsigned int flags) ++static void _load_pasid(void *unused) + { +- ioasid_t max_pasid = dev_is_pci(dev) ? +- pci_max_pasids(to_pci_dev(dev)) : intel_pasid_max_id; ++ update_pasid(); ++} ++ ++static void load_pasid(struct mm_struct *mm, u32 pasid) ++{ ++ mutex_lock(&mm->context.lock); ++ ++ /* Synchronize with READ_ONCE in update_pasid(). */ ++ smp_store_release(&mm->pasid, pasid); + +- return iommu_sva_alloc_pasid(mm, PASID_MIN, max_pasid - 1); ++ /* Update PASID MSR on all CPUs running the mm's tasks. */ ++ on_each_cpu_mask(mm_cpumask(mm), _load_pasid, NULL, true); ++ ++ mutex_unlock(&mm->context.lock); + } + +-static struct iommu_sva *intel_svm_bind_mm(struct intel_iommu *iommu, +- struct device *dev, +- struct mm_struct *mm, +- unsigned int flags) ++/* Caller must hold pasid_mutex, mm reference */ ++static int ++intel_svm_bind_mm(struct device *dev, unsigned int flags, ++ struct svm_dev_ops *ops, ++ struct mm_struct *mm, struct intel_svm_dev **sd) + { +- struct device_domain_info *info = get_domain_info(dev); +- unsigned long iflags, sflags; ++ struct intel_iommu *iommu = device_to_iommu(dev, NULL, NULL); ++ struct device_domain_info *info; + struct intel_svm_dev *sdev; +- struct intel_svm *svm; +- int ret = 0; ++ struct intel_svm *svm = NULL; ++ unsigned long iflags; ++ int pasid_max; ++ int ret; + +- svm = pasid_private_find(mm->pasid); +- if (!svm) { +- svm = kzalloc(sizeof(*svm), GFP_KERNEL); +- if (!svm) +- return ERR_PTR(-ENOMEM); ++ if (!iommu || dmar_disabled) ++ return -EINVAL; + +- svm->pasid = mm->pasid; +- svm->mm = mm; +- svm->flags = flags; +- INIT_LIST_HEAD_RCU(&svm->devs); ++ if (!intel_svm_capable(iommu)) ++ return -ENOTSUPP; + +- if (!(flags & SVM_FLAG_SUPERVISOR_MODE)) { +- svm->notifier.ops = &intel_mmuops; +- ret = mmu_notifier_register(&svm->notifier, mm); +- if (ret) { +- kfree(svm); +- return ERR_PTR(ret); +- } +- } ++ if (dev_is_pci(dev)) { ++ pasid_max = pci_max_pasids(to_pci_dev(dev)); ++ if (pasid_max < 0) ++ return -EINVAL; ++ } else ++ pasid_max = 1 << 20; + +- ret = pasid_private_add(svm->pasid, svm); +- if (ret) { +- if (svm->notifier.ops) +- mmu_notifier_unregister(&svm->notifier, mm); +- kfree(svm); +- return ERR_PTR(ret); ++ /* Bind supervisor PASID shuld have mm = NULL */ ++ if (flags & SVM_FLAG_SUPERVISOR_MODE) { ++ if (!ecap_srs(iommu->ecap) || mm) { ++ pr_err("Supervisor PASID with user provided mm.\n"); ++ return -EINVAL; + } + } + +- /* Find the matching device in svm list */ +- for_each_svm_dev(sdev, svm, dev) { +- sdev->users++; +- goto success; ++ if (!(flags & SVM_FLAG_PRIVATE_PASID)) { ++ struct intel_svm *t; ++ ++ list_for_each_entry(t, &global_svm_list, list) { ++ if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID)) ++ continue; ++ ++ svm = t; ++ if (svm->pasid >= pasid_max) { ++ dev_warn(dev, ++ "Limited PASID width. Cannot use existing PASID %d\n", ++ svm->pasid); ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ /* Find the matching device in svm list */ ++ for_each_svm_dev(sdev, svm, dev) { ++ if (sdev->ops != ops) { ++ ret = -EBUSY; ++ goto out; ++ } ++ sdev->users++; ++ goto success; ++ } ++ ++ break; ++ } + } + + sdev = kzalloc(sizeof(*sdev), GFP_KERNEL); + if (!sdev) { + ret = -ENOMEM; +- goto free_svm; ++ goto out; + } +- + sdev->dev = dev; + sdev->iommu = iommu; ++ ++ ret = intel_iommu_enable_pasid(iommu, dev); ++ if (ret) { ++ kfree(sdev); ++ goto out; ++ } ++ ++ info = get_domain_info(dev); + sdev->did = FLPT_DEFAULT_DID; + sdev->sid = PCI_DEVID(info->bus, info->devfn); +- sdev->users = 1; +- sdev->pasid = svm->pasid; +- sdev->sva.dev = dev; +- init_rcu_head(&sdev->rcu); + if (info->ats_enabled) { + sdev->dev_iotlb = 1; + sdev->qdep = info->ats_qdep; +@@ -536,33 +585,96 @@ static struct iommu_sva *intel_svm_bind_mm(struct intel_iommu *iommu, + sdev->qdep = 0; + } + +- /* Setup the pasid table: */ +- sflags = (flags & SVM_FLAG_SUPERVISOR_MODE) ? +- PASID_FLAG_SUPERVISOR_MODE : 0; +- sflags |= cpu_feature_enabled(X86_FEATURE_LA57) ? PASID_FLAG_FL5LP : 0; +- spin_lock_irqsave(&iommu->lock, iflags); +- ret = intel_pasid_setup_first_level(iommu, dev, mm->pgd, mm->pasid, +- FLPT_DEFAULT_DID, sflags); +- spin_unlock_irqrestore(&iommu->lock, iflags); ++ /* Finish the setup now we know we're keeping it */ ++ sdev->users = 1; ++ sdev->ops = ops; ++ init_rcu_head(&sdev->rcu); + +- if (ret) +- goto free_sdev; ++ if (!svm) { ++ svm = kzalloc(sizeof(*svm), GFP_KERNEL); ++ if (!svm) { ++ ret = -ENOMEM; ++ kfree(sdev); ++ goto out; ++ } + ++ if (pasid_max > intel_pasid_max_id) ++ pasid_max = intel_pasid_max_id; ++ ++ /* Do not use PASID 0, reserved for RID to PASID */ ++ svm->pasid = ioasid_alloc(NULL, PASID_MIN, ++ pasid_max - 1, svm); ++ if (svm->pasid == INVALID_IOASID) { ++ kfree(svm); ++ kfree(sdev); ++ ret = -ENOSPC; ++ goto out; ++ } ++ svm->notifier.ops = &intel_mmuops; ++ svm->mm = mm; ++ svm->flags = flags; ++ INIT_LIST_HEAD_RCU(&svm->devs); ++ INIT_LIST_HEAD(&svm->list); ++ ret = -ENOMEM; ++ if (mm) { ++ ret = mmu_notifier_register(&svm->notifier, mm); ++ if (ret) { ++ ioasid_put(svm->pasid); ++ kfree(svm); ++ kfree(sdev); ++ goto out; ++ } ++ } ++ ++ spin_lock_irqsave(&iommu->lock, iflags); ++ ret = intel_pasid_setup_first_level(iommu, dev, ++ mm ? mm->pgd : init_mm.pgd, ++ svm->pasid, FLPT_DEFAULT_DID, ++ (mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) | ++ (cpu_feature_enabled(X86_FEATURE_LA57) ? ++ PASID_FLAG_FL5LP : 0)); ++ spin_unlock_irqrestore(&iommu->lock, iflags); ++ if (ret) { ++ if (mm) ++ mmu_notifier_unregister(&svm->notifier, mm); ++ ioasid_put(svm->pasid); ++ kfree(svm); ++ kfree(sdev); ++ goto out; ++ } ++ ++ list_add_tail(&svm->list, &global_svm_list); ++ if (mm) { ++ /* The newly allocated pasid is loaded to the mm. */ ++ load_pasid(mm, svm->pasid); ++ } ++ } else { ++ /* ++ * Binding a new device with existing PASID, need to setup ++ * the PASID entry. ++ */ ++ spin_lock_irqsave(&iommu->lock, iflags); ++ ret = intel_pasid_setup_first_level(iommu, dev, ++ mm ? mm->pgd : init_mm.pgd, ++ svm->pasid, FLPT_DEFAULT_DID, ++ (mm ? 0 : PASID_FLAG_SUPERVISOR_MODE) | ++ (cpu_feature_enabled(X86_FEATURE_LA57) ? ++ PASID_FLAG_FL5LP : 0)); ++ spin_unlock_irqrestore(&iommu->lock, iflags); ++ if (ret) { ++ kfree(sdev); ++ goto out; ++ } ++ } + list_add_rcu(&sdev->list, &svm->devs); + success: +- return &sdev->sva; +- +-free_sdev: +- kfree(sdev); +-free_svm: +- if (list_empty(&svm->devs)) { +- if (svm->notifier.ops) +- mmu_notifier_unregister(&svm->notifier, mm); +- pasid_private_remove(mm->pasid); +- kfree(svm); +- } +- +- return ERR_PTR(ret); ++ sdev->pasid = svm->pasid; ++ sdev->sva.dev = dev; ++ if (sd) ++ *sd = sdev; ++ ret = 0; ++out: ++ return ret; + } + + /* Caller must hold pasid_mutex */ +@@ -571,7 +683,6 @@ static int intel_svm_unbind_mm(struct device *dev, u32 pasid) + struct intel_svm_dev *sdev; + struct intel_iommu *iommu; + struct intel_svm *svm; +- struct mm_struct *mm; + int ret = -EINVAL; + + iommu = device_to_iommu(dev, NULL, NULL); +@@ -581,7 +692,6 @@ static int intel_svm_unbind_mm(struct device *dev, u32 pasid) + ret = pasid_to_svm_sdev(dev, pasid, &svm, &sdev); + if (ret) + goto out; +- mm = svm->mm; + + if (sdev) { + sdev->users--; +@@ -600,9 +710,13 @@ static int intel_svm_unbind_mm(struct device *dev, u32 pasid) + kfree_rcu(sdev, rcu); + + if (list_empty(&svm->devs)) { +- if (svm->notifier.ops) +- mmu_notifier_unregister(&svm->notifier, mm); +- pasid_private_remove(svm->pasid); ++ ioasid_put(svm->pasid); ++ if (svm->mm) { ++ mmu_notifier_unregister(&svm->notifier, svm->mm); ++ /* Clear mm's pasid. */ ++ load_pasid(svm->mm, PASID_DISABLED); ++ } ++ list_del(&svm->list); + /* We mandate that no page faults may be outstanding + * for the PASID when intel_svm_unbind_mm() is called. + * If that is not obeyed, subtle errors will happen. +@@ -858,7 +972,7 @@ static irqreturn_t prq_event_thread(int irq, void *d) + } + if (!svm || svm->pasid != req->pasid) { + rcu_read_lock(); +- svm = pasid_private_find(req->pasid); ++ svm = ioasid_find(NULL, req->pasid, NULL); + /* It *can't* go away, because the driver is not permitted + * to unbind the mm while any page faults are outstanding. + * So we only need RCU to protect the internal idr code. */ +@@ -929,6 +1043,13 @@ static irqreturn_t prq_event_thread(int irq, void *d) + mmap_read_unlock(svm->mm); + mmput(svm->mm); + bad_req: ++ WARN_ON(!sdev); ++ if (sdev && sdev->ops && sdev->ops->fault_cb) { ++ int rwxp = (req->rd_req << 3) | (req->wr_req << 2) | ++ (req->exe_req << 1) | (req->pm_req); ++ sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, ++ req->priv_data, rwxp, result); ++ } + /* We get here in the error case where the PASID lookup failed, + and these can be NULL. Do not use them below this point! */ + sdev = NULL; +@@ -986,40 +1107,31 @@ static irqreturn_t prq_event_thread(int irq, void *d) + return IRQ_RETVAL(handled); + } + +-struct iommu_sva *intel_svm_bind(struct device *dev, struct mm_struct *mm, void *drvdata) ++#define to_intel_svm_dev(handle) container_of(handle, struct intel_svm_dev, sva) ++struct iommu_sva * ++intel_svm_bind(struct device *dev, struct mm_struct *mm, void *drvdata) + { +- struct intel_iommu *iommu = device_to_iommu(dev, NULL, NULL); ++ struct iommu_sva *sva = ERR_PTR(-EINVAL); ++ struct intel_svm_dev *sdev = NULL; + unsigned int flags = 0; +- struct iommu_sva *sva; + int ret; + ++ /* ++ * TODO: Consolidate with generic iommu-sva bind after it is merged. ++ * It will require shared SVM data structures, i.e. combine io_mm ++ * and intel_svm etc. ++ */ + if (drvdata) + flags = *(unsigned int *)drvdata; +- +- if (flags & SVM_FLAG_SUPERVISOR_MODE) { +- if (!ecap_srs(iommu->ecap)) { +- dev_err(dev, "%s: Supervisor PASID not supported\n", +- iommu->name); +- return ERR_PTR(-EOPNOTSUPP); +- } +- +- if (mm) { +- dev_err(dev, "%s: Supervisor PASID with user provided mm\n", +- iommu->name); +- return ERR_PTR(-EINVAL); +- } +- +- mm = &init_mm; +- } +- + mutex_lock(&pasid_mutex); +- ret = intel_svm_alloc_pasid(dev, mm, flags); +- if (ret) { +- mutex_unlock(&pasid_mutex); +- return ERR_PTR(ret); +- } ++ ret = intel_svm_bind_mm(dev, flags, NULL, mm, &sdev); ++ if (ret) ++ sva = ERR_PTR(ret); ++ else if (sdev) ++ sva = &sdev->sva; ++ else ++ WARN(!sdev, "SVM bind succeeded with no sdev!\n"); + +- sva = intel_svm_bind_mm(iommu, dev, mm, flags); + mutex_unlock(&pasid_mutex); + + return sva; +@@ -1027,9 +1139,10 @@ struct iommu_sva *intel_svm_bind(struct device *dev, struct mm_struct *mm, void + + void intel_svm_unbind(struct iommu_sva *sva) + { +- struct intel_svm_dev *sdev = to_intel_svm_dev(sva); ++ struct intel_svm_dev *sdev; + + mutex_lock(&pasid_mutex); ++ sdev = to_intel_svm_dev(sva); + intel_svm_unbind_mm(sdev->dev, sdev->pasid); + mutex_unlock(&pasid_mutex); + } +diff --git a/drivers/iommu/io-pgfault.c b/drivers/iommu/io-pgfault.c +index 1df8c1dcae77..8fd03a24cb14 100644 +--- a/drivers/iommu/io-pgfault.c ++++ b/drivers/iommu/io-pgfault.c +@@ -12,6 +12,7 @@ + #include + + #include "iommu-sva-lib.h" ++#include "linux/vendor/sva_ext.h" + + /** + * struct iopf_queue - IO Page Fault queue +@@ -118,6 +119,11 @@ iopf_handle_single(struct iopf_fault *iopf) + status = ret & VM_FAULT_ERROR ? IOMMU_PAGE_RESP_INVALID : + IOMMU_PAGE_RESP_SUCCESS; + ++ if (status == IOMMU_PAGE_RESP_SUCCESS) { ++ unsigned long aligned_addr = prm->addr & PAGE_MASK; ++ svm_flush_cache(vma->vm_mm, aligned_addr, PAGE_SIZE); ++ } ++ + out_put_mm: + mmap_read_unlock(mm); + mmput(mm); +diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c +index 701efdbdc12b..3cf72c100add 100644 +--- a/drivers/iommu/io-pgtable-arm-v7s.c ++++ b/drivers/iommu/io-pgtable-arm-v7s.c +@@ -242,17 +242,13 @@ static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp, + __GFP_ZERO | ARM_V7S_TABLE_GFP_DMA, get_order(size)); + else if (lvl == 2) + table = kmem_cache_zalloc(data->l2_tables, gfp); +- +- if (!table) +- return NULL; +- + phys = virt_to_phys(table); + if (phys != (arm_v7s_iopte)phys) { + /* Doesn't fit in PTE */ + dev_err(dev, "Page table does not fit in PTE: %pa", &phys); + goto out_free; + } +- if (!cfg->coherent_walk) { ++ if (table && !cfg->coherent_walk) { + dma = dma_map_single(dev, table, size, DMA_TO_DEVICE); + if (dma_mapping_error(dev, dma)) + goto out_free; +diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c +index 3fc6ae00dc96..34fea518785b 100644 +--- a/drivers/iommu/io-pgtable-arm.c ++++ b/drivers/iommu/io-pgtable-arm.c +@@ -72,19 +72,16 @@ + + #define ARM_LPAE_PTE_NSTABLE (((arm_lpae_iopte)1) << 63) + #define ARM_LPAE_PTE_XN (((arm_lpae_iopte)3) << 53) +-#define ARM_LPAE_PTE_DBM (((arm_lpae_iopte)1) << 51) + #define ARM_LPAE_PTE_AF (((arm_lpae_iopte)1) << 10) + #define ARM_LPAE_PTE_SH_NS (((arm_lpae_iopte)0) << 8) + #define ARM_LPAE_PTE_SH_OS (((arm_lpae_iopte)2) << 8) + #define ARM_LPAE_PTE_SH_IS (((arm_lpae_iopte)3) << 8) + #define ARM_LPAE_PTE_NS (((arm_lpae_iopte)1) << 5) + #define ARM_LPAE_PTE_VALID (((arm_lpae_iopte)1) << 0) +-/* Block descriptor bits */ +-#define ARM_LPAE_PTE_NT (((arm_lpae_iopte)1) << 16) + + #define ARM_LPAE_PTE_ATTR_LO_MASK (((arm_lpae_iopte)0x3ff) << 2) + /* Ignore the contiguous bit for block splitting */ +-#define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)13) << 51) ++#define ARM_LPAE_PTE_ATTR_HI_MASK (((arm_lpae_iopte)6) << 52) + #define ARM_LPAE_PTE_ATTR_MASK (ARM_LPAE_PTE_ATTR_LO_MASK | \ + ARM_LPAE_PTE_ATTR_HI_MASK) + /* Software bit for solving coherency races */ +@@ -305,12 +302,11 @@ static int arm_lpae_init_pte(struct arm_lpae_io_pgtable *data, + static arm_lpae_iopte arm_lpae_install_table(arm_lpae_iopte *table, + arm_lpae_iopte *ptep, + arm_lpae_iopte curr, +- struct arm_lpae_io_pgtable *data) ++ struct io_pgtable_cfg *cfg) + { + arm_lpae_iopte old, new; +- struct io_pgtable_cfg *cfg = &data->iop.cfg; + +- new = paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE; ++ new = __pa(table) | ARM_LPAE_PTE_TYPE_TABLE; + if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) + new |= ARM_LPAE_PTE_NSTABLE; + +@@ -361,7 +357,7 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, + if (!cptep) + return -ENOMEM; + +- pte = arm_lpae_install_table(cptep, ptep, 0, data); ++ pte = arm_lpae_install_table(cptep, ptep, 0, cfg); + if (pte) + __arm_lpae_free_pages(cptep, tblsz, cfg); + } else if (!cfg->coherent_walk && !(pte & ARM_LPAE_PTE_SW_SYNC)) { +@@ -383,7 +379,6 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova, + static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, + int prot) + { +- struct io_pgtable_cfg *cfg = &data->iop.cfg; + arm_lpae_iopte pte; + + if (data->iop.fmt == ARM_64_LPAE_S1 || +@@ -391,10 +386,6 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct arm_lpae_io_pgtable *data, + pte = ARM_LPAE_PTE_nG; + if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) + pte |= ARM_LPAE_PTE_AP_RDONLY; +- else if (data->iop.fmt == ARM_64_LPAE_S1 && +- cfg->quirks & IO_PGTABLE_QUIRK_ARM_HD) +- pte |= ARM_LPAE_PTE_DBM; +- + if (!(prot & IOMMU_PRIV)) + pte |= ARM_LPAE_PTE_AP_UNPRIV; + } else { +@@ -555,7 +546,7 @@ static size_t arm_lpae_split_blk_unmap(struct arm_lpae_io_pgtable *data, + __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]); + } + +- pte = arm_lpae_install_table(tablep, ptep, blk_pte, data); ++ pte = arm_lpae_install_table(tablep, ptep, blk_pte, cfg); + if (pte != blk_pte) { + __arm_lpae_free_pages(tablep, tablesz, cfg); + /* +@@ -683,382 +674,6 @@ static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops, + return iopte_to_paddr(pte, data) | iova; + } + +-static size_t __arm_lpae_split_block(struct arm_lpae_io_pgtable *data, +- unsigned long iova, size_t size, int lvl, +- arm_lpae_iopte *ptep); +- +-static size_t arm_lpae_do_split_blk(struct arm_lpae_io_pgtable *data, +- unsigned long iova, size_t size, +- arm_lpae_iopte blk_pte, int lvl, +- arm_lpae_iopte *ptep) +-{ +- struct io_pgtable_cfg *cfg = &data->iop.cfg; +- arm_lpae_iopte pte, *tablep; +- phys_addr_t blk_paddr; +- size_t tablesz = ARM_LPAE_GRANULE(data); +- size_t split_sz = ARM_LPAE_BLOCK_SIZE(lvl, data); +- int i; +- +- if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) +- return 0; +- +- tablep = __arm_lpae_alloc_pages(tablesz, GFP_ATOMIC, cfg); +- if (!tablep) +- return 0; +- +- blk_paddr = iopte_to_paddr(blk_pte, data); +- pte = iopte_prot(blk_pte); +- for (i = 0; i < tablesz / sizeof(pte); i++, blk_paddr += split_sz) +- __arm_lpae_init_pte(data, blk_paddr, pte, lvl, &tablep[i]); +- +- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_BBML1) { +- /* Race does not exist */ +- blk_pte |= ARM_LPAE_PTE_NT; +- __arm_lpae_set_pte(ptep, blk_pte, cfg); +- io_pgtable_tlb_flush_walk(&data->iop, iova, size, size); +- } +- /* Race does not exist */ +- pte = arm_lpae_install_table(tablep, ptep, blk_pte, data); +- +- /* Have splited it into page? */ +- if (lvl == (ARM_LPAE_MAX_LEVELS - 1)) +- return size; +- +- /* Go back to lvl - 1 */ +- ptep -= ARM_LPAE_LVL_IDX(iova, lvl - 1, data); +- return __arm_lpae_split_block(data, iova, size, lvl - 1, ptep); +-} +- +-static size_t __arm_lpae_split_block(struct arm_lpae_io_pgtable *data, +- unsigned long iova, size_t size, int lvl, +- arm_lpae_iopte *ptep) +-{ +- arm_lpae_iopte pte; +- struct io_pgtable *iop = &data->iop; +- size_t base, next_size, total_size; +- +- if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) +- return 0; +- +- ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); +- pte = READ_ONCE(*ptep); +- if (WARN_ON(!pte)) +- return 0; +- +- if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { +- if (iopte_leaf(pte, lvl, iop->fmt)) { +- if (lvl == (ARM_LPAE_MAX_LEVELS - 1) || +- (pte & ARM_LPAE_PTE_AP_RDONLY)) +- return size; +- +- /* We find a writable block, split it. */ +- return arm_lpae_do_split_blk(data, iova, size, pte, +- lvl + 1, ptep); +- } else { +- /* If it is the last table level, then nothing to do */ +- if (lvl == (ARM_LPAE_MAX_LEVELS - 2)) +- return size; +- +- total_size = 0; +- next_size = ARM_LPAE_BLOCK_SIZE(lvl + 1, data); +- ptep = iopte_deref(pte, data); +- for (base = 0; base < size; base += next_size) +- total_size += __arm_lpae_split_block(data, +- iova + base, next_size, lvl + 1, +- ptep); +- return total_size; +- } +- } else if (iopte_leaf(pte, lvl, iop->fmt)) { +- WARN(1, "Can't split behind a block.\n"); +- return 0; +- } +- +- /* Keep on walkin */ +- ptep = iopte_deref(pte, data); +- return __arm_lpae_split_block(data, iova, size, lvl + 1, ptep); +-} +- +-static size_t arm_lpae_split_block(struct io_pgtable_ops *ops, +- unsigned long iova, size_t size) +-{ +- struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); +- struct io_pgtable_cfg *cfg = &data->iop.cfg; +- arm_lpae_iopte *ptep = data->pgd; +- int lvl = data->start_level; +- long iaext = (s64)iova >> cfg->ias; +- +- if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) +- return 0; +- +- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) +- iaext = ~iaext; +- if (WARN_ON(iaext)) +- return 0; +- +- /* If it is smallest granule, then nothing to do */ +- if (size == ARM_LPAE_BLOCK_SIZE(ARM_LPAE_MAX_LEVELS - 1, data)) +- return size; +- +- return __arm_lpae_split_block(data, iova, size, lvl, ptep); +-} +- +-static size_t __arm_lpae_merge_page(struct arm_lpae_io_pgtable *data, +- unsigned long iova, phys_addr_t paddr, +- size_t size, int lvl, arm_lpae_iopte *ptep, +- arm_lpae_iopte prot) +-{ +- arm_lpae_iopte pte, *tablep; +- struct io_pgtable *iop = &data->iop; +- struct io_pgtable_cfg *cfg = &data->iop.cfg; +- +- if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) +- return 0; +- +- ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); +- pte = READ_ONCE(*ptep); +- if (WARN_ON(!pte)) +- return 0; +- +- if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { +- if (iopte_leaf(pte, lvl, iop->fmt)) +- return size; +- +- /* Race does not exist */ +- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_BBML1) { +- prot |= ARM_LPAE_PTE_NT; +- __arm_lpae_init_pte(data, paddr, prot, lvl, ptep); +- io_pgtable_tlb_flush_walk(iop, iova, size, +- ARM_LPAE_GRANULE(data)); +- +- prot &= ~(ARM_LPAE_PTE_NT); +- __arm_lpae_init_pte(data, paddr, prot, lvl, ptep); +- } else { +- __arm_lpae_init_pte(data, paddr, prot, lvl, ptep); +- } +- +- tablep = iopte_deref(pte, data); +- __arm_lpae_free_pgtable(data, lvl + 1, tablep); +- return size; +- } else if (iopte_leaf(pte, lvl, iop->fmt)) { +- /* The size is too small, already merged */ +- return size; +- } +- +- /* Keep on walkin */ +- ptep = iopte_deref(pte, data); +- return __arm_lpae_merge_page(data, iova, paddr, size, lvl + 1, ptep, prot); +-} +- +-static size_t arm_lpae_merge_page(struct io_pgtable_ops *ops, unsigned long iova, +- phys_addr_t paddr, size_t size, int iommu_prot) +-{ +- struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); +- struct io_pgtable_cfg *cfg = &data->iop.cfg; +- arm_lpae_iopte *ptep = data->pgd; +- int lvl = data->start_level; +- arm_lpae_iopte prot; +- long iaext = (s64)iova >> cfg->ias; +- +- if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) +- return 0; +- +- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) +- iaext = ~iaext; +- if (WARN_ON(iaext || paddr >> cfg->oas)) +- return 0; +- +- /* If no access, then nothing to do */ +- if (!(iommu_prot & (IOMMU_READ | IOMMU_WRITE))) +- return size; +- +- /* If it is smallest granule, then nothing to do */ +- if (size == ARM_LPAE_BLOCK_SIZE(ARM_LPAE_MAX_LEVELS - 1, data)) +- return size; +- +- prot = arm_lpae_prot_to_pte(data, iommu_prot); +- return __arm_lpae_merge_page(data, iova, paddr, size, lvl, ptep, prot); +-} +- +-static int __arm_lpae_sync_dirty_log(struct arm_lpae_io_pgtable *data, +- unsigned long iova, size_t size, +- int lvl, arm_lpae_iopte *ptep, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- arm_lpae_iopte pte; +- struct io_pgtable *iop = &data->iop; +- size_t base, next_size; +- unsigned long offset; +- int nbits, ret; +- +- if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) +- return -EINVAL; +- +- ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); +- pte = READ_ONCE(*ptep); +- if (WARN_ON(!pte)) +- return -EINVAL; +- +- if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { +- if (iopte_leaf(pte, lvl, iop->fmt)) { +- if (pte & ARM_LPAE_PTE_AP_RDONLY) +- return 0; +- +- /* It is writable, set the bitmap */ +- nbits = size >> bitmap_pgshift; +- offset = (iova - base_iova) >> bitmap_pgshift; +- bitmap_set(bitmap, offset, nbits); +- return 0; +- } +- /* Current level is table, traverse next level */ +- next_size = ARM_LPAE_BLOCK_SIZE(lvl + 1, data); +- ptep = iopte_deref(pte, data); +- for (base = 0; base < size; base += next_size) { +- ret = __arm_lpae_sync_dirty_log(data, iova + base, +- next_size, lvl + 1, ptep, bitmap, +- base_iova, bitmap_pgshift); +- if (ret) +- return ret; +- } +- return 0; +- } else if (iopte_leaf(pte, lvl, iop->fmt)) { +- if (pte & ARM_LPAE_PTE_AP_RDONLY) +- return 0; +- +- /* Though the size is too small, also set bitmap */ +- nbits = size >> bitmap_pgshift; +- offset = (iova - base_iova) >> bitmap_pgshift; +- bitmap_set(bitmap, offset, nbits); +- return 0; +- } +- +- /* Keep on walkin */ +- ptep = iopte_deref(pte, data); +- return __arm_lpae_sync_dirty_log(data, iova, size, lvl + 1, ptep, +- bitmap, base_iova, bitmap_pgshift); +-} +- +-static int arm_lpae_sync_dirty_log(struct io_pgtable_ops *ops, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); +- struct io_pgtable_cfg *cfg = &data->iop.cfg; +- arm_lpae_iopte *ptep = data->pgd; +- int lvl = data->start_level; +- long iaext = (s64)iova >> cfg->ias; +- +- if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) +- return -EINVAL; +- +- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) +- iaext = ~iaext; +- if (WARN_ON(iaext)) +- return -EINVAL; +- +- if (data->iop.fmt != ARM_64_LPAE_S1 && +- data->iop.fmt != ARM_32_LPAE_S1) +- return -EINVAL; +- +- return __arm_lpae_sync_dirty_log(data, iova, size, lvl, ptep, +- bitmap, base_iova, bitmap_pgshift); +-} +- +-static int __arm_lpae_clear_dirty_log(struct arm_lpae_io_pgtable *data, +- unsigned long iova, size_t size, +- int lvl, arm_lpae_iopte *ptep, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- arm_lpae_iopte pte; +- struct io_pgtable *iop = &data->iop; +- unsigned long offset; +- size_t base, next_size; +- int nbits, ret, i; +- +- if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS)) +- return -EINVAL; +- +- ptep += ARM_LPAE_LVL_IDX(iova, lvl, data); +- pte = READ_ONCE(*ptep); +- if (WARN_ON(!pte)) +- return -EINVAL; +- +- if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) { +- if (iopte_leaf(pte, lvl, iop->fmt)) { +- if (pte & ARM_LPAE_PTE_AP_RDONLY) +- return 0; +- +- /* Ensure all corresponding bits are set */ +- nbits = size >> bitmap_pgshift; +- offset = (iova - base_iova) >> bitmap_pgshift; +- for (i = offset; i < offset + nbits; i++) { +- if (!test_bit(i, bitmap)) +- return 0; +- } +- +- /* Race does not exist */ +- pte |= ARM_LPAE_PTE_AP_RDONLY; +- __arm_lpae_set_pte(ptep, pte, &iop->cfg); +- return 0; +- } +- /* Current level is table, traverse next level */ +- next_size = ARM_LPAE_BLOCK_SIZE(lvl + 1, data); +- ptep = iopte_deref(pte, data); +- for (base = 0; base < size; base += next_size) { +- ret = __arm_lpae_clear_dirty_log(data, iova + base, +- next_size, lvl + 1, ptep, bitmap, +- base_iova, bitmap_pgshift); +- if (ret) +- return ret; +- } +- return 0; +- } else if (iopte_leaf(pte, lvl, iop->fmt)) { +- /* Though the size is too small, it is already clean */ +- if (pte & ARM_LPAE_PTE_AP_RDONLY) +- return 0; +- +- return -EINVAL; +- } +- +- /* Keep on walkin */ +- ptep = iopte_deref(pte, data); +- return __arm_lpae_clear_dirty_log(data, iova, size, lvl + 1, ptep, +- bitmap, base_iova, bitmap_pgshift); +-} +- +-static int arm_lpae_clear_dirty_log(struct io_pgtable_ops *ops, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops); +- struct io_pgtable_cfg *cfg = &data->iop.cfg; +- arm_lpae_iopte *ptep = data->pgd; +- int lvl = data->start_level; +- long iaext = (s64)iova >> cfg->ias; +- +- if (WARN_ON(!size || (size & cfg->pgsize_bitmap) != size)) +- return -EINVAL; +- +- if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) +- iaext = ~iaext; +- if (WARN_ON(iaext)) +- return -EINVAL; +- +- if (data->iop.fmt != ARM_64_LPAE_S1 && +- data->iop.fmt != ARM_32_LPAE_S1) +- return -EINVAL; +- +- return __arm_lpae_clear_dirty_log(data, iova, size, lvl, ptep, +- bitmap, base_iova, bitmap_pgshift); +-} +- + static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg) + { + unsigned long granule, page_sizes; +@@ -1137,10 +752,6 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) + .map = arm_lpae_map, + .unmap = arm_lpae_unmap, + .iova_to_phys = arm_lpae_iova_to_phys, +- .split_block = arm_lpae_split_block, +- .merge_page = arm_lpae_merge_page, +- .sync_dirty_log = arm_lpae_sync_dirty_log, +- .clear_dirty_log = arm_lpae_clear_dirty_log, + }; + + return data; +@@ -1156,10 +767,7 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *cfg, void *cookie) + + if (cfg->quirks & ~(IO_PGTABLE_QUIRK_ARM_NS | + IO_PGTABLE_QUIRK_NON_STRICT | +- IO_PGTABLE_QUIRK_ARM_TTBR1 | +- IO_PGTABLE_QUIRK_ARM_HD | +- IO_PGTABLE_QUIRK_ARM_BBML1 | +- IO_PGTABLE_QUIRK_ARM_BBML2)) ++ IO_PGTABLE_QUIRK_ARM_TTBR1)) + return NULL; + + data = arm_lpae_alloc_pgtable(cfg); +@@ -1256,10 +864,7 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie) + typeof(&cfg->arm_lpae_s2_cfg.vtcr) vtcr = &cfg->arm_lpae_s2_cfg.vtcr; + + /* The NS quirk doesn't apply at stage 2 */ +- if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT | +- IO_PGTABLE_QUIRK_ARM_HD | +- IO_PGTABLE_QUIRK_ARM_BBML1 | +- IO_PGTABLE_QUIRK_ARM_BBML2)) ++ if (cfg->quirks & ~(IO_PGTABLE_QUIRK_NON_STRICT)) + return NULL; + + data = arm_lpae_alloc_pgtable(cfg); +diff --git a/drivers/iommu/ioasid.c b/drivers/iommu/ioasid.c +index a786c034907c..50ee27bbd04e 100644 +--- a/drivers/iommu/ioasid.c ++++ b/drivers/iommu/ioasid.c +@@ -2,7 +2,7 @@ + /* + * I/O Address Space ID allocator. There is one global IOASID space, split into + * subsets. Users create a subset with DECLARE_IOASID_SET, then allocate and +- * free IOASIDs with ioasid_alloc() and ioasid_free(). ++ * free IOASIDs with ioasid_alloc and ioasid_put. + */ + #include + #include +@@ -15,6 +15,7 @@ struct ioasid_data { + struct ioasid_set *set; + void *private; + struct rcu_head rcu; ++ refcount_t refs; + }; + + /* +@@ -314,6 +315,7 @@ ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max, + + data->set = set; + data->private = private; ++ refcount_set(&data->refs, 1); + + /* + * Custom allocator needs allocator data to perform platform specific +@@ -346,11 +348,34 @@ ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max, + EXPORT_SYMBOL_GPL(ioasid_alloc); + + /** +- * ioasid_free - Free an ioasid ++ * ioasid_get - obtain a reference to the IOASID ++ */ ++void ioasid_get(ioasid_t ioasid) ++{ ++ struct ioasid_data *ioasid_data; ++ ++ spin_lock(&ioasid_allocator_lock); ++ ioasid_data = xa_load(&active_allocator->xa, ioasid); ++ if (ioasid_data) ++ refcount_inc(&ioasid_data->refs); ++ else ++ WARN_ON(1); ++ spin_unlock(&ioasid_allocator_lock); ++} ++EXPORT_SYMBOL_GPL(ioasid_get); ++ ++/** ++ * ioasid_put - Release a reference to an ioasid + * @ioasid: the ID to remove ++ * ++ * Put a reference to the IOASID, free it when the number of references drops to ++ * zero. ++ * ++ * Return: %true if the IOASID was freed, %false otherwise. + */ +-void ioasid_free(ioasid_t ioasid) ++bool ioasid_put(ioasid_t ioasid) + { ++ bool free = false; + struct ioasid_data *ioasid_data; + + spin_lock(&ioasid_allocator_lock); +@@ -360,6 +385,10 @@ void ioasid_free(ioasid_t ioasid) + goto exit_unlock; + } + ++ free = refcount_dec_and_test(&ioasid_data->refs); ++ if (!free) ++ goto exit_unlock; ++ + active_allocator->ops->free(ioasid, active_allocator->ops->pdata); + /* Custom allocator needs additional steps to free the xa element */ + if (active_allocator->flags & IOASID_ALLOCATOR_CUSTOM) { +@@ -369,8 +398,9 @@ void ioasid_free(ioasid_t ioasid) + + exit_unlock: + spin_unlock(&ioasid_allocator_lock); ++ return free; + } +-EXPORT_SYMBOL_GPL(ioasid_free); ++EXPORT_SYMBOL_GPL(ioasid_put); + + /** + * ioasid_find - Find IOASID data +diff --git a/drivers/iommu/iommu-sva-lib.c b/drivers/iommu/iommu-sva-lib.c +index 106506143896..bd41405d34e9 100644 +--- a/drivers/iommu/iommu-sva-lib.c ++++ b/drivers/iommu/iommu-sva-lib.c +@@ -18,7 +18,8 @@ static DECLARE_IOASID_SET(iommu_sva_pasid); + * + * Try to allocate a PASID for this mm, or take a reference to the existing one + * provided it fits within the [@min, @max] range. On success the PASID is +- * available in mm->pasid and will be available for the lifetime of the mm. ++ * available in mm->pasid, and must be released with iommu_sva_free_pasid(). ++ * @min must be greater than 0, because 0 indicates an unused mm->pasid. + * + * Returns 0 on success and < 0 on error. + */ +@@ -32,24 +33,38 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max) + return -EINVAL; + + mutex_lock(&iommu_sva_lock); +- /* Is a PASID already associated with this mm? */ +- if (pasid_valid(mm->pasid)) { +- if (mm->pasid < min || mm->pasid >= max) ++ if (mm->pasid) { ++ if (mm->pasid >= min && mm->pasid <= max) ++ ioasid_get(mm->pasid); ++ else + ret = -EOVERFLOW; +- goto out; ++ } else { ++ pasid = ioasid_alloc(&iommu_sva_pasid, min, max, mm); ++ if (pasid == INVALID_IOASID) ++ ret = -ENOMEM; ++ else ++ mm->pasid = pasid; + } +- +- pasid = ioasid_alloc(&iommu_sva_pasid, min, max, mm); +- if (!pasid_valid(pasid)) +- ret = -ENOMEM; +- else +- mm_pasid_set(mm, pasid); +-out: + mutex_unlock(&iommu_sva_lock); + return ret; + } + EXPORT_SYMBOL_GPL(iommu_sva_alloc_pasid); + ++/** ++ * iommu_sva_free_pasid - Release the mm's PASID ++ * @mm: the mm ++ * ++ * Drop one reference to a PASID allocated with iommu_sva_alloc_pasid() ++ */ ++void iommu_sva_free_pasid(struct mm_struct *mm) ++{ ++ mutex_lock(&iommu_sva_lock); ++ if (ioasid_put(mm->pasid)) ++ mm->pasid = 0; ++ mutex_unlock(&iommu_sva_lock); ++} ++EXPORT_SYMBOL_GPL(iommu_sva_free_pasid); ++ + /* ioasid_find getter() requires a void * argument */ + static bool __mmget_not_zero(void *mm) + { +diff --git a/drivers/iommu/iommu-sva-lib.h b/drivers/iommu/iommu-sva-lib.h +index 8909ea1094e3..031155010ca8 100644 +--- a/drivers/iommu/iommu-sva-lib.h ++++ b/drivers/iommu/iommu-sva-lib.h +@@ -9,6 +9,7 @@ + #include + + int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t min, ioasid_t max); ++void iommu_sva_free_pasid(struct mm_struct *mm); + struct mm_struct *iommu_sva_find(ioasid_t pasid); + + /* I/O Page fault */ +@@ -16,7 +17,7 @@ struct device; + struct iommu_fault; + struct iopf_queue; + +-#ifdef CONFIG_IOMMU_SVA ++#ifdef CONFIG_IOMMU_SVA_LIB + int iommu_queue_iopf(struct iommu_fault *fault, void *cookie); + + int iopf_queue_add_device(struct iopf_queue *queue, struct device *dev); +@@ -27,7 +28,7 @@ struct iopf_queue *iopf_queue_alloc(const char *name); + void iopf_queue_free(struct iopf_queue *queue); + int iopf_queue_discard_partial(struct iopf_queue *queue); + +-#else /* CONFIG_IOMMU_SVA */ ++#else /* CONFIG_IOMMU_SVA_LIB */ + static inline int iommu_queue_iopf(struct iommu_fault *fault, void *cookie) + { + return -ENODEV; +@@ -63,5 +64,5 @@ static inline int iopf_queue_discard_partial(struct iopf_queue *queue) + { + return -ENODEV; + } +-#endif /* CONFIG_IOMMU_SVA */ ++#endif /* CONFIG_IOMMU_SVA_LIB */ + #endif /* _IOMMU_SVA_LIB_H */ +diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c +index b888efd65e92..c71f9321c87a 100644 +--- a/drivers/iommu/iommu.c ++++ b/drivers/iommu/iommu.c +@@ -29,7 +29,7 @@ static struct kset *iommu_group_kset; + static DEFINE_IDA(iommu_group_ida); + + static unsigned int iommu_def_domain_type __read_mostly; +-static bool iommu_dma_strict __read_mostly; ++static bool iommu_dma_strict __read_mostly = true; + static u32 iommu_cmd_line __read_mostly; + + /* +@@ -198,14 +198,9 @@ static struct dev_iommu *dev_iommu_get(struct device *dev) + + static void dev_iommu_free(struct device *dev) + { +- struct dev_iommu *param = dev->iommu; +- ++ iommu_fwspec_free(dev); ++ kfree(dev->iommu); + dev->iommu = NULL; +- if (param->fwspec) { +- fwnode_handle_put(param->fwspec->iommu_fwnode); +- kfree(param->fwspec); +- } +- kfree(param); + } + + static int __iommu_probe_device(struct device *dev, struct list_head *group_list) +@@ -819,12 +814,6 @@ static bool iommu_is_attach_deferred(struct iommu_domain *domain, + return false; + } + +-void __acpi_device_create_direct_mappings(struct iommu_group *group, struct device *acpi_device) +-{ +- iommu_create_device_direct_mappings(group, acpi_device); +-} +-EXPORT_SYMBOL_GPL(__acpi_device_create_direct_mappings); +- + /** + * iommu_group_add_device - add a device to an iommu group + * @group: the group into which to add the device (reference should be held) +@@ -923,9 +912,6 @@ void iommu_group_remove_device(struct device *dev) + struct iommu_group *group = dev->iommu_group; + struct group_device *tmp_device, *device = NULL; + +- if (!group) +- return; +- + dev_info(dev, "Removing from iommu group %d\n", group->id); + + /* Pre-notify listeners that a device is being removed. */ +@@ -1084,6 +1070,39 @@ int iommu_group_unregister_notifier(struct iommu_group *group, + } + EXPORT_SYMBOL_GPL(iommu_group_unregister_notifier); + ++static void iommu_dev_fault_timer_fn(struct timer_list *t) ++{ ++ struct iommu_fault_param *fparam = from_timer(fparam, t, timer); ++ struct iommu_fault_event *evt; ++ struct iommu_fault_page_request *prm; ++ ++ u64 now; ++ ++ now = get_jiffies_64(); ++ ++ /* The goal is to ensure driver or guest page fault handler(via vfio) ++ * send page response on time. Otherwise, limited queue resources ++ * may be occupied by some irresponsive guests or drivers. ++ * When per device pending fault list is not empty, we periodically checks ++ * if any anticipated page response time has expired. ++ * ++ * TODO: ++ * We could do the following if response time expires: ++ * 1. send page response code FAILURE to all pending PRQ ++ * 2. inform device driver or vfio ++ * 3. drain in-flight page requests and responses for this device ++ * 4. clear pending fault list such that driver can unregister fault ++ * handler(otherwise blocked when pending faults are present). ++ */ ++ list_for_each_entry(evt, &fparam->faults, list) { ++ prm = &evt->fault.prm; ++ if (time_after64(now, evt->expire)) ++ pr_err("Page response time expired!, pasid %d gid %d exp %llu now %llu\n", ++ prm->pasid, prm->grpid, evt->expire, now); ++ } ++ mod_timer(t, now + prq_timeout); ++} ++ + /** + * iommu_register_device_fault_handler() - Register a device fault handler + * @dev: the device +@@ -1131,6 +1150,9 @@ int iommu_register_device_fault_handler(struct device *dev, + mutex_init(¶m->fault_param->lock); + INIT_LIST_HEAD(¶m->fault_param->faults); + ++ if (prq_timeout) ++ timer_setup(¶m->fault_param->timer, iommu_dev_fault_timer_fn, ++ TIMER_DEFERRABLE); + done_unlock: + mutex_unlock(¶m->lock); + +@@ -1270,7 +1292,9 @@ int iommu_report_device_fault(struct device *dev, struct iommu_fault_event *evt) + struct dev_iommu *param = dev->iommu; + struct iommu_fault_event *evt_pending = NULL; + struct iommu_fault_param *fparam; ++ struct timer_list *tmr; + int ret = 0; ++ u64 exp; + + if (!param || !evt || WARN_ON_ONCE(!iommu_fault_valid(&evt->fault))) + return -EINVAL; +@@ -1291,7 +1315,17 @@ int iommu_report_device_fault(struct device *dev, struct iommu_fault_event *evt) + ret = -ENOMEM; + goto done_unlock; + } ++ /* Keep track of response expiration time */ ++ exp = get_jiffies_64() + prq_timeout; ++ evt_pending->expire = exp; + mutex_lock(&fparam->lock); ++ if (list_empty(&fparam->faults)) { ++ /* First pending event, start timer */ ++ tmr = &fparam->timer; ++ WARN_ON(timer_pending(tmr)); ++ mod_timer(tmr, exp); ++ } ++ + list_add_tail(&evt_pending->list, &fparam->faults); + mutex_unlock(&fparam->lock); + } +@@ -1369,6 +1403,13 @@ int iommu_page_response(struct device *dev, + break; + } + ++ /* stop response timer if no more pending request */ ++ if (list_empty(¶m->fault_param->faults) && ++ timer_pending(¶m->fault_param->timer)) { ++ pr_debug("no pending PRQ, stop timer\n"); ++ del_timer(¶m->fault_param->timer); ++ } ++ + done_unlock: + mutex_unlock(¶m->fault_param->lock); + return ret; +@@ -2032,7 +2073,6 @@ static struct iommu_domain *__iommu_domain_alloc(struct bus_type *bus, + domain->type = type; + /* Assume all sizes by default; the driver may override this later */ + domain->pgsize_bitmap = bus->iommu_ops->pgsize_bitmap; +- mutex_init(&domain->switch_log_lock); + + return domain; + } +@@ -2476,8 +2516,8 @@ phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova) + } + EXPORT_SYMBOL_GPL(iommu_iova_to_phys); + +-size_t iommu_pgsize(struct iommu_domain *domain, +- unsigned long addr_merge, size_t size) ++static size_t iommu_pgsize(struct iommu_domain *domain, ++ unsigned long addr_merge, size_t size) + { + unsigned int pgsize_idx; + size_t pgsize; +@@ -2507,7 +2547,6 @@ size_t iommu_pgsize(struct iommu_domain *domain, + + return pgsize; + } +-EXPORT_SYMBOL_GPL(iommu_pgsize); + + static int __iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot, gfp_t gfp) +@@ -2851,188 +2890,6 @@ int iommu_domain_set_attr(struct iommu_domain *domain, + } + EXPORT_SYMBOL_GPL(iommu_domain_set_attr); + +-bool iommu_support_dirty_log(struct iommu_domain *domain) +-{ +- const struct iommu_ops *ops = domain->ops; +- +- return ops->support_dirty_log && ops->support_dirty_log(domain); +-} +-EXPORT_SYMBOL_GPL(iommu_support_dirty_log); +- +-int iommu_switch_dirty_log(struct iommu_domain *domain, bool enable, +- unsigned long iova, size_t size, int prot) +-{ +- const struct iommu_ops *ops = domain->ops; +- unsigned long orig_iova = iova; +- unsigned int min_pagesz; +- size_t orig_size = size; +- bool flush = false; +- int ret = 0; +- +- if (unlikely(!ops->switch_dirty_log)) +- return -ENODEV; +- +- min_pagesz = 1 << __ffs(domain->pgsize_bitmap); +- if (!IS_ALIGNED(iova | size, min_pagesz)) { +- pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n", +- iova, size, min_pagesz); +- return -EINVAL; +- } +- +- mutex_lock(&domain->switch_log_lock); +- +- pr_debug("switch_dirty_log %s for: iova 0x%lx size 0x%zx\n", +- enable ? "enable" : "disable", iova, size); +- +- while (size) { +- size_t pgsize = iommu_pgsize(domain, iova, size); +- +- flush = true; +- ret = ops->switch_dirty_log(domain, enable, iova, pgsize, prot); +- if (ret) +- break; +- +- pr_debug("switch_dirty_log handled: iova 0x%lx size 0x%zx\n", +- iova, pgsize); +- +- iova += pgsize; +- size -= pgsize; +- } +- +- if (flush) +- iommu_flush_iotlb_all(domain); +- +- if (!ret) +- trace_switch_dirty_log(orig_iova, orig_size, enable); +- +- mutex_unlock(&domain->switch_log_lock); +- return ret; +-} +-EXPORT_SYMBOL_GPL(iommu_switch_dirty_log); +- +-int iommu_sync_dirty_log(struct iommu_domain *domain, unsigned long iova, +- size_t size, unsigned long *bitmap, +- unsigned long base_iova, unsigned long bitmap_pgshift) +-{ +- const struct iommu_ops *ops = domain->ops; +- unsigned long orig_iova = iova; +- unsigned int min_pagesz; +- size_t orig_size = size; +- int ret = 0; +- +- if (unlikely(!ops->sync_dirty_log)) +- return -ENODEV; +- +- min_pagesz = 1 << __ffs(domain->pgsize_bitmap); +- if (!IS_ALIGNED(iova | size, min_pagesz)) { +- pr_err("unaligned: iova 0x%lx size 0x%zx min_pagesz 0x%x\n", +- iova, size, min_pagesz); +- return -EINVAL; +- } +- +- mutex_lock(&domain->switch_log_lock); +- +- pr_debug("sync_dirty_log for: iova 0x%lx size 0x%zx\n", iova, size); +- +- while (size) { +- size_t pgsize = iommu_pgsize(domain, iova, size); +- +- ret = ops->sync_dirty_log(domain, iova, pgsize, +- bitmap, base_iova, bitmap_pgshift); +- if (ret) +- break; +- +- pr_debug("sync_dirty_log handled: iova 0x%lx size 0x%zx\n", +- iova, pgsize); +- +- iova += pgsize; +- size -= pgsize; +- } +- +- if (!ret) +- trace_sync_dirty_log(orig_iova, orig_size); +- +- mutex_unlock(&domain->switch_log_lock); +- return ret; +-} +-EXPORT_SYMBOL_GPL(iommu_sync_dirty_log); +- +-static int __iommu_clear_dirty_log(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- const struct iommu_ops *ops = domain->ops; +- unsigned long orig_iova = iova; +- size_t orig_size = size; +- int ret = 0; +- +- if (unlikely(!ops->clear_dirty_log)) +- return -ENODEV; +- +- pr_debug("clear_dirty_log for: iova 0x%lx size 0x%zx\n", iova, size); +- +- while (size) { +- size_t pgsize = iommu_pgsize(domain, iova, size); +- +- ret = ops->clear_dirty_log(domain, iova, pgsize, bitmap, +- base_iova, bitmap_pgshift); +- if (ret) +- break; +- +- pr_debug("clear_dirty_log handled: iova 0x%lx size 0x%zx\n", +- iova, pgsize); +- +- iova += pgsize; +- size -= pgsize; +- } +- +- if (!ret) +- trace_clear_dirty_log(orig_iova, orig_size); +- +- return ret; +-} +- +-int iommu_clear_dirty_log(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, unsigned long base_iova, +- unsigned long bitmap_pgshift) +-{ +- unsigned long riova, rsize; +- unsigned int min_pagesz, rs, re, start, end; +- bool flush = false; +- int ret = 0; +- +- min_pagesz = 1 << __ffs(domain->pgsize_bitmap); +- if (!IS_ALIGNED(iova | size, min_pagesz)) { +- pr_err("unaligned: iova 0x%lx min_pagesz 0x%x\n", +- iova, min_pagesz); +- return -EINVAL; +- } +- +- mutex_lock(&domain->switch_log_lock); +- +- start = (iova - base_iova) >> bitmap_pgshift; +- end = start + (size >> bitmap_pgshift); +- bitmap_for_each_set_region(bitmap, rs, re, start, end) { +- flush = true; +- riova = base_iova + ((unsigned long)rs << bitmap_pgshift); +- rsize = (unsigned long)(re - rs) << bitmap_pgshift; +- ret = __iommu_clear_dirty_log(domain, riova, rsize, bitmap, +- base_iova, bitmap_pgshift); +- if (ret) +- break; +- } +- +- if (flush) +- iommu_flush_iotlb_all(domain); +- +- mutex_unlock(&domain->switch_log_lock); +- return ret; +-} +-EXPORT_SYMBOL_GPL(iommu_clear_dirty_log); +- + void iommu_get_resv_regions(struct device *dev, struct list_head *list) + { + const struct iommu_ops *ops = dev->bus->iommu_ops; +@@ -3411,24 +3268,54 @@ u32 iommu_sva_get_pasid(struct iommu_sva *handle) + } + EXPORT_SYMBOL_GPL(iommu_sva_get_pasid); + +-int iommu_dev_set_config(struct device *dev, int type, void *data) ++/* Request that a device is direct mapped by the IOMMU */ ++int iommu_request_dm_for_dev(struct device *dev) + { +- const struct iommu_ops *ops = dev->bus->iommu_ops; ++ struct iommu_domain *dm_domain; ++ struct iommu_group *group; ++ int ret; + +- if (ops && ops->dev_set_config) +- return ops->dev_set_config(dev, type, data); ++ /* Device must already be in a group before calling this function */ ++ group = iommu_group_get_for_dev(dev); ++ if (IS_ERR(group)) ++ return PTR_ERR(group); + +- return -ENODEV; +-} +-EXPORT_SYMBOL_GPL(iommu_dev_set_config); ++ mutex_lock(&group->mutex); + +-int iommu_dev_get_config(struct device *dev, int type, void *data) +-{ +- const struct iommu_ops *ops = dev->bus->iommu_ops; ++ /* Check if the default domain is already direct mapped */ ++ ret = 0; ++ if (group->default_domain && ++ group->default_domain->type == IOMMU_DOMAIN_IDENTITY) ++ goto out; + +- if (ops && ops->dev_get_config) +- return ops->dev_get_config(dev, type, data); ++ /* Don't change mappings of existing devices */ ++ ret = -EBUSY; ++ if (iommu_group_device_count(group) != 1) ++ goto out; + +- return -ENODEV; ++ /* Allocate a direct mapped domain */ ++ ret = -ENOMEM; ++ dm_domain = __iommu_domain_alloc(dev->bus, IOMMU_DOMAIN_IDENTITY); ++ if (!dm_domain) ++ goto out; ++ ++ /* Attach the device to the domain */ ++ ret = __iommu_attach_group(dm_domain, group); ++ if (ret) { ++ iommu_domain_free(dm_domain); ++ goto out; ++ } ++ /* Make the direct mapped domain the default for this group */ ++ if (group->default_domain) ++ iommu_domain_free(group->default_domain); ++ group->default_domain = dm_domain; ++ ++ pr_info("Using direct mapping for device %s\n", dev_name(dev)); ++ ++ ret = 0; ++out: ++ mutex_unlock(&group->mutex); ++ iommu_group_put(group); ++ ++ return ret; + } +-EXPORT_SYMBOL_GPL(iommu_dev_get_config); +diff --git a/drivers/iommu/iova.c b/drivers/iommu/iova.c +index 1246e8f8bf08..30d969a4c5fd 100644 +--- a/drivers/iommu/iova.c ++++ b/drivers/iommu/iova.c +@@ -64,9 +64,9 @@ static void free_iova_flush_queue(struct iova_domain *iovad) + if (!has_iova_flush_queue(iovad)) + return; + +- del_timer_sync(&iovad->fq_timer); ++ if (timer_pending(&iovad->fq_timer)) ++ del_timer(&iovad->fq_timer); + +- flush_work(&iovad->free_iova_work); + fq_destroy_all_entries(iovad); + + free_percpu(iovad->fq); +@@ -76,24 +76,6 @@ static void free_iova_flush_queue(struct iova_domain *iovad) + iovad->entry_dtor = NULL; + } + +-static void fq_ring_free(struct iova_domain *iovad, struct iova_fq *fq); +-static void free_iova_work_func(struct work_struct *work) +-{ +- struct iova_domain *iovad; +- int cpu; +- +- iovad = container_of(work, struct iova_domain, free_iova_work); +- for_each_possible_cpu(cpu) { +- unsigned long flags; +- struct iova_fq *fq; +- +- fq = per_cpu_ptr(iovad->fq, cpu); +- spin_lock_irqsave(&fq->lock, flags); +- fq_ring_free(iovad, fq); +- spin_unlock_irqrestore(&fq->lock, flags); +- } +-} +- + int init_iova_flush_queue(struct iova_domain *iovad, + iova_flush_cb flush_cb, iova_entry_dtor entry_dtor) + { +@@ -124,7 +106,6 @@ int init_iova_flush_queue(struct iova_domain *iovad, + + iovad->fq = queue; + +- INIT_WORK(&iovad->free_iova_work, free_iova_work_func); + timer_setup(&iovad->fq_timer, fq_flush_timeout, 0); + atomic_set(&iovad->fq_timer_on, 0); + +@@ -158,11 +139,10 @@ __cached_rbnode_delete_update(struct iova_domain *iovad, struct iova *free) + cached_iova = rb_entry(iovad->cached32_node, struct iova, node); + if (free == cached_iova || + (free->pfn_hi < iovad->dma_32bit_pfn && +- free->pfn_lo >= cached_iova->pfn_lo)) ++ free->pfn_lo >= cached_iova->pfn_lo)) { + iovad->cached32_node = rb_next(&free->node); +- +- if (free->pfn_lo < iovad->dma_32bit_pfn) + iovad->max32_alloc_size = iovad->dma_32bit_pfn; ++ } + + cached_iova = rb_entry(iovad->cached_node, struct iova, node); + if (free->pfn_lo >= cached_iova->pfn_lo) +@@ -550,11 +530,20 @@ static void fq_destroy_all_entries(struct iova_domain *iovad) + static void fq_flush_timeout(struct timer_list *t) + { + struct iova_domain *iovad = from_timer(iovad, t, fq_timer); ++ int cpu; + + atomic_set(&iovad->fq_timer_on, 0); + iova_domain_flush(iovad); + +- schedule_work(&iovad->free_iova_work); ++ for_each_possible_cpu(cpu) { ++ unsigned long flags; ++ struct iova_fq *fq; ++ ++ fq = per_cpu_ptr(iovad->fq, cpu); ++ spin_lock_irqsave(&fq->lock, flags); ++ fq_ring_free(iovad, fq); ++ spin_unlock_irqrestore(&fq->lock, flags); ++ } + } + + void queue_iova(struct iova_domain *iovad, +diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c +index d9068e8f2db4..d71f10257f15 100644 +--- a/drivers/iommu/ipmmu-vmsa.c ++++ b/drivers/iommu/ipmmu-vmsa.c +@@ -1012,9 +1012,7 @@ static int ipmmu_probe(struct platform_device *pdev) + bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); + mmu->features = of_device_get_match_data(&pdev->dev); + memset(mmu->utlb_ctx, IPMMU_CTX_INVALID, mmu->features->num_utlbs); +- ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); +- if (ret) +- return ret; ++ dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(40)); + + /* Map I/O memory and request IRQ. */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c +index 08947fdd4cb4..040e85f70861 100644 +--- a/drivers/iommu/msm_iommu.c ++++ b/drivers/iommu/msm_iommu.c +@@ -609,19 +609,16 @@ static void insert_iommu_master(struct device *dev, + static int qcom_iommu_of_xlate(struct device *dev, + struct of_phandle_args *spec) + { +- struct msm_iommu_dev *iommu = NULL, *iter; ++ struct msm_iommu_dev *iommu; + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&msm_iommu_lock, flags); +- list_for_each_entry(iter, &qcom_iommu_devices, dev_node) { +- if (iter->dev->of_node == spec->np) { +- iommu = iter; ++ list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) ++ if (iommu->dev->of_node == spec->np) + break; +- } +- } + +- if (!iommu) { ++ if (!iommu || iommu->dev->of_node != spec->np) { + ret = -ENODEV; + goto fail; + } +diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c +index dd0ff2d3cfe4..bfe6ec329f8d 100644 +--- a/drivers/iommu/mtk_iommu.c ++++ b/drivers/iommu/mtk_iommu.c +@@ -767,7 +767,8 @@ static int mtk_iommu_remove(struct platform_device *pdev) + iommu_device_sysfs_remove(&data->iommu); + iommu_device_unregister(&data->iommu); + +- list_del(&data->list); ++ if (iommu_present(&platform_bus_type)) ++ bus_set_iommu(&platform_bus_type, NULL); + + clk_disable_unprepare(data->bclk); + devm_free_irq(&pdev->dev, data->irq, data); +diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c +index 2abbdd71d8d9..82ddfe9170d4 100644 +--- a/drivers/iommu/mtk_iommu_v1.c ++++ b/drivers/iommu/mtk_iommu_v1.c +@@ -618,34 +618,18 @@ static int mtk_iommu_probe(struct platform_device *pdev) + ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, + dev_name(&pdev->dev)); + if (ret) +- goto out_clk_unprepare; ++ return ret; + + iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); + + ret = iommu_device_register(&data->iommu); + if (ret) +- goto out_sysfs_remove; ++ return ret; + +- if (!iommu_present(&platform_bus_type)) { +- ret = bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); +- if (ret) +- goto out_dev_unreg; +- } ++ if (!iommu_present(&platform_bus_type)) ++ bus_set_iommu(&platform_bus_type, &mtk_iommu_ops); + +- ret = component_master_add_with_match(dev, &mtk_iommu_com_ops, match); +- if (ret) +- goto out_bus_set_null; +- return ret; +- +-out_bus_set_null: +- bus_set_iommu(&platform_bus_type, NULL); +-out_dev_unreg: +- iommu_device_unregister(&data->iommu); +-out_sysfs_remove: +- iommu_device_sysfs_remove(&data->iommu); +-out_clk_unprepare: +- clk_disable_unprepare(data->bclk); +- return ret; ++ return component_master_add_with_match(dev, &mtk_iommu_com_ops, match); + } + + static int mtk_iommu_remove(struct platform_device *pdev) +diff --git a/drivers/iommu/omap-iommu-debug.c b/drivers/iommu/omap-iommu-debug.c +index 259f65291d90..a99afb5d9011 100644 +--- a/drivers/iommu/omap-iommu-debug.c ++++ b/drivers/iommu/omap-iommu-debug.c +@@ -32,12 +32,12 @@ static inline bool is_omap_iommu_detached(struct omap_iommu *obj) + ssize_t bytes; \ + const char *str = "%20s: %08x\n"; \ + const int maxcol = 32; \ +- if (len < maxcol) \ +- goto out; \ +- bytes = scnprintf(p, maxcol, str, __stringify(name), \ ++ bytes = snprintf(p, maxcol, str, __stringify(name), \ + iommu_read_reg(obj, MMU_##name)); \ + p += bytes; \ + len -= bytes; \ ++ if (len < maxcol) \ ++ goto out; \ + } while (0) + + static ssize_t +diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c +index ff2c692c0db4..71f29c0927fc 100644 +--- a/drivers/iommu/omap-iommu.c ++++ b/drivers/iommu/omap-iommu.c +@@ -1665,7 +1665,7 @@ static struct iommu_device *omap_iommu_probe_device(struct device *dev) + num_iommus = of_property_count_elems_of_size(dev->of_node, "iommus", + sizeof(phandle)); + if (num_iommus < 0) +- return ERR_PTR(-ENODEV); ++ return 0; + + arch_data = kcalloc(num_iommus + 1, sizeof(*arch_data), GFP_KERNEL); + if (!arch_data) +diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c +index 65aa30d55d3a..ea6db1341916 100644 +--- a/drivers/iommu/sun50i-iommu.c ++++ b/drivers/iommu/sun50i-iommu.c +@@ -28,7 +28,6 @@ + #include + + #define IOMMU_RESET_REG 0x010 +-#define IOMMU_RESET_RELEASE_ALL 0xffffffff + #define IOMMU_ENABLE_REG 0x020 + #define IOMMU_ENABLE_ENABLE BIT(0) + +@@ -272,7 +271,7 @@ static u32 sun50i_mk_pte(phys_addr_t page, int prot) + enum sun50i_iommu_aci aci; + u32 flags = 0; + +- if ((prot & (IOMMU_READ | IOMMU_WRITE)) == (IOMMU_READ | IOMMU_WRITE)) ++ if (prot & (IOMMU_READ | IOMMU_WRITE)) + aci = SUN50I_IOMMU_ACI_RD_WR; + else if (prot & IOMMU_READ) + aci = SUN50I_IOMMU_ACI_RD; +@@ -513,7 +512,7 @@ static u32 *sun50i_dte_get_page_table(struct sun50i_iommu_domain *sun50i_domain, + sun50i_iommu_free_page_table(iommu, drop_pt); + } + +- sun50i_table_flush(sun50i_domain, page_table, NUM_PT_ENTRIES); ++ sun50i_table_flush(sun50i_domain, page_table, PT_SIZE); + sun50i_table_flush(sun50i_domain, dte_addr, 1); + + return page_table; +@@ -603,6 +602,7 @@ static struct iommu_domain *sun50i_iommu_domain_alloc(unsigned type) + struct sun50i_iommu_domain *sun50i_domain; + + if (type != IOMMU_DOMAIN_DMA && ++ type != IOMMU_DOMAIN_IDENTITY && + type != IOMMU_DOMAIN_UNMANAGED) + return NULL; + +@@ -880,8 +880,8 @@ static phys_addr_t sun50i_iommu_handle_perm_irq(struct sun50i_iommu *iommu) + + static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id) + { +- u32 status, l1_status, l2_status, resets; + struct sun50i_iommu *iommu = dev_id; ++ u32 status; + + spin_lock(&iommu->iommu_lock); + +@@ -891,9 +891,6 @@ static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id) + return IRQ_NONE; + } + +- l1_status = iommu_read(iommu, IOMMU_L1PG_INT_REG); +- l2_status = iommu_read(iommu, IOMMU_L2PG_INT_REG); +- + if (status & IOMMU_INT_INVALID_L2PG) + sun50i_iommu_handle_pt_irq(iommu, + IOMMU_INT_ERR_ADDR_L2_REG, +@@ -907,9 +904,8 @@ static irqreturn_t sun50i_iommu_irq(int irq, void *dev_id) + + iommu_write(iommu, IOMMU_INT_CLR_REG, status); + +- resets = (status | l1_status | l2_status) & IOMMU_INT_MASTER_MASK; +- iommu_write(iommu, IOMMU_RESET_REG, ~resets); +- iommu_write(iommu, IOMMU_RESET_REG, IOMMU_RESET_RELEASE_ALL); ++ iommu_write(iommu, IOMMU_RESET_REG, ~status); ++ iommu_write(iommu, IOMMU_RESET_REG, status); + + spin_unlock(&iommu->iommu_lock); + +diff --git a/drivers/iommu/sw64/Kconfig b/drivers/iommu/sw64/Kconfig +deleted file mode 100644 +index a313c6e2d11b..000000000000 +--- a/drivers/iommu/sw64/Kconfig ++++ /dev/null +@@ -1,9 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-# SW64 IOMMU SUPPORT +-config SUNWAY_IOMMU +- bool "Sunway IOMMU Support" +- select IOMMU_API +- select IOMMU_IOVA +- depends on SW64 && PCI +- help +- Support for IOMMU on SW64 platform. +diff --git a/drivers/iommu/sw64/Makefile b/drivers/iommu/sw64/Makefile +deleted file mode 100644 +index e23dbd40a74d..000000000000 +--- a/drivers/iommu/sw64/Makefile ++++ /dev/null +@@ -1,2 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_SUNWAY_IOMMU) += sunway_iommu.o +diff --git a/drivers/iommu/sw64/sunway_iommu.c b/drivers/iommu/sw64/sunway_iommu.c +deleted file mode 100644 +index 86920f88faac..000000000000 +--- a/drivers/iommu/sw64/sunway_iommu.c ++++ /dev/null +@@ -1,1693 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0 +-/* +- * iommu.c: Generic sw64 IOMMU support +- * +- * This is designed and tested for 3231. If there are no changes in hardware +- * in later chips, then it should work just as well. +- * +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "sunway_iommu.h" +- +-#define MAX_DOMAIN_NUM 65536 +-#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) +-#define SW64_DMA_LIMIT (0xe0000000 - 1) +-#define SW64_BAR_ADDRESS (IO_BASE | PCI_BASE) +- +-#define SW64_IOMMU_PGSIZES (((1ULL) << PAGE_SHIFT) | ((1ULL) << PAGE_8M_SHIFT)) +- +-#define IDENTMAP_ALL ((1U) << 0) +-#define DMA_MASK64 ((1U) << 1) +- +-/* IOMMU Exceptional Status */ +-enum exceptype { +- DTE_LEVEL1 = 0x0, +- DTE_LEVEL2, +- PTE_LEVEL1, +- PTE_LEVEL2, +- UNAUTHORIZED_ACCESS, +- ILLEGAL_RESPONSE, +- DTE_LEVEL1_VAL, +- DTE_LEVEL2_VAL, +- PTE_LEVEL1_VAL, +- PTE_LEVEL2_VAL, +-}; +- +-u64 iommu_enable_cmd; /* default IOMMU boot param: 0 */ +- +-unsigned long *sunway_iommu_domain_bitmap; +- +-static DEFINE_SPINLOCK(domain_bitmap_lock); +-static DEFINE_SPINLOCK(sunway_iommu_device_table_lock); +-spinlock_t sunway_domain_lock; +- +-static LLIST_HEAD(dev_data_list); +-LIST_HEAD(sunway_domain_list); +- +-struct dma_domain { +- struct sunway_iommu_domain sdomain; +- struct iova_domain iovad; +-}; +-const struct iommu_ops sunway_iommu_ops; +-static const struct dma_map_ops sunway_dma_ops; +- +- +-/* flush helpers */ +-static void piu_flush_all(struct pci_controller *hose) +-{ +- write_piu_ior0(hose->node, hose->index, DTLB_FLUSHALL, 0); +- write_piu_ior0(hose->node, hose->index, PTLB_FLUSHALL, 0); +- write_piu_ior0(hose->node, hose->index, PCACHE_FLUSHALL, 0); +-} +- +-void dev_flush_dtlb(struct sunway_iommu_domain *sdomain, +- struct sunway_iommu_dev *sdev_data) +-{ +- struct pci_controller *hose; +- int devid; +- +- list_for_each_entry(sdev_data, &sdomain->dev_list, list) { +- hose = sdev_data->pdev->sysdata; +- devid = sdev_data->devid; +- +- write_piu_ior0(hose->node, hose->index, DTLB_FLUSHDEV, devid); +- } +-} +- +-void flush_pcache_by_addr(struct sunway_iommu_domain *sdomain, +- unsigned long flush_addr) +-{ +- struct pci_controller *hose; +- struct sunway_iommu_dev *sdev_data; +- +- list_for_each_entry(sdev_data, &sdomain->dev_list, list) { +- hose = sdev_data->pdev->sysdata; +- +- flush_addr = __pa(flush_addr); +- write_piu_ior0(hose->node, hose->index, +- PCACHE_FLUSHPADDR, flush_addr); +- } +-} +- +-void flush_ptlb_by_addr(struct sunway_iommu_domain *sdomain, +- unsigned long flush_addr) +-{ +- struct pci_controller *hose; +- struct pci_dev *pdev; +- struct sunway_iommu_dev *sdev_data; +- +- list_for_each_entry(sdev_data, &sdomain->dev_list, list) { +- pdev = sdev_data->pdev; +- hose = pdev->sysdata; +- +- flush_addr = (pdev->bus->number << 8) +- | pdev->devfn | (flush_addr << 16); +- write_piu_ior0(hose->node, hose->index, +- PTLB_FLUSHVADDR, flush_addr); +- } +-} +- +-/* domain helpers */ +-static struct sunway_iommu_domain *to_sunway_domain(struct iommu_domain *dom) +-{ +- return container_of(dom, struct sunway_iommu_domain, domain); +-} +- +-static struct dma_domain *to_dma_domain(struct sunway_iommu_domain *sdomain) +-{ +- return container_of(sdomain, struct dma_domain, sdomain); +-} +- +-static void add_domain_to_list(struct sunway_iommu_domain *sdomain) +-{ +- unsigned long flags; +- +- spin_lock_irqsave(&sunway_domain_lock, flags); +- list_add(&sdomain->list, &sunway_domain_list); +- spin_unlock_irqrestore(&sunway_domain_lock, flags); +-} +- +-static void del_domain_from_list(struct sunway_iommu_domain *sdomain) +-{ +- unsigned long flags; +- +- spin_lock_irqsave(&sunway_domain_lock, flags); +- list_del(&sdomain->list); +- spin_unlock_irqrestore(&sunway_domain_lock, flags); +-} +- +-static void free_pagetable(struct sunway_iommu_domain *sdomain) +-{ +- unsigned long pde; +- unsigned long *pde_ptr; +- int i, pdes_one_page; +- +- pde_ptr = sdomain->pt_root; +- if (!pde_ptr) +- return; +- +- pdes_one_page = PAGE_SIZE/sizeof(pde); +- for (i = 0; i < pdes_one_page; i++, pde_ptr++) { +- pde = *pde_ptr; +- if ((pde & SW64_IOMMU_ENTRY_VALID) == 0) +- continue; +- +- pde &= ~(SW64_IOMMU_ENTRY_VALID) & PAGE_MASK; +- pde |= PAGE_OFFSET; +- free_page(pde); +- } +- +- free_page((unsigned long)sdomain->pt_root); +-} +- +-static void domain_id_free(int id) +-{ +- spin_lock(&domain_bitmap_lock); +- if (id > 0) +- __clear_bit(id, sunway_iommu_domain_bitmap); +- spin_unlock(&domain_bitmap_lock); +-} +- +-static void dma_domain_free(struct dma_domain *dma_dom) +-{ +- if (!dma_dom) +- return; +- +- del_domain_from_list(&dma_dom->sdomain); +- put_iova_domain(&dma_dom->iovad); +- free_pagetable(&dma_dom->sdomain); +- if (dma_dom->sdomain.id) +- domain_id_free(dma_dom->sdomain.id); +- +- kfree(dma_dom); +-} +- +-static void sunway_domain_free(struct sunway_iommu_domain *sdomain) +-{ +- if (!sdomain) +- return; +- +- del_domain_from_list(sdomain); +- if (sdomain->id) +- domain_id_free(sdomain->id); +- +- kfree(sdomain); +-} +- +-static u16 sunway_domain_id_alloc(void) +-{ +- int id; +- +- spin_lock(&domain_bitmap_lock); +- id = find_first_zero_bit(sunway_iommu_domain_bitmap, MAX_DOMAIN_NUM); +- if (id > 0 && id < MAX_DOMAIN_NUM) +- __set_bit(id, sunway_iommu_domain_bitmap); +- else +- id = 0; +- spin_unlock(&domain_bitmap_lock); +- +- return id; +-} +- +-static int sunway_domain_init(struct sunway_iommu_domain *sdomain) +-{ +- spin_lock_init(&sdomain->lock); +- mutex_init(&sdomain->api_lock); +- sdomain->id = sunway_domain_id_alloc(); +- if (!sdomain->id) +- return -ENOMEM; +- INIT_LIST_HEAD(&sdomain->dev_list); +- +- return 1; +-} +- +-static struct sunway_iommu_domain *sunway_domain_alloc(void) +-{ +- struct sunway_iommu_domain *sdomain; +- +- sdomain = kzalloc(sizeof(struct sunway_iommu_domain), GFP_KERNEL); +- if (!sdomain) +- return NULL; +- +- if (!sunway_domain_init(sdomain)) { +- kfree(sdomain); +- return NULL; +- } +- +- add_domain_to_list(sdomain); +- return sdomain; +-} +- +-static struct dma_domain *dma_domain_alloc(void) +-{ +- struct dma_domain *dma_dom; +- struct page; +- +- dma_dom = kzalloc(sizeof(struct dma_domain), GFP_KERNEL); +- if (!dma_dom) +- return NULL; +- +- sunway_domain_init(&dma_dom->sdomain); +- dma_dom->sdomain.type = IOMMU_DOMAIN_DMA; +- init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_PFN(SW64_DMA_START)); +- +- dma_dom->sdomain.pt_root = (void *)get_zeroed_page(GFP_KERNEL); +- +- add_domain_to_list(&dma_dom->sdomain); +- +- return dma_dom; +-} +- +-static void device_flush_all(struct sunway_iommu_dev *sdata) +-{ +- struct pci_controller *hose = sdata->pdev->sysdata; +- +- if (hose == NULL) +- return; +- +- write_piu_ior0(hose->node, hose->index, DTLB_FLUSHDEV, sdata->devid); +- write_piu_ior0(hose->node, hose->index, PTLB_FLUSHDEV, sdata->devid); +- write_piu_ior0(hose->node, hose->index, PCACHE_FLUSHDEV, sdata->devid); +-} +- +-/* iommu_ops device attach/unattach helpers */ +-static void +-set_dte_entry(struct sunway_iommu_dev *sdev, struct sunway_iommu_domain *sdomain) +-{ +- struct sunway_iommu *iommu; +- struct pci_dev *pdev; +- struct page *page; +- unsigned long *dte_l1, *dte_l2; +- unsigned long dte_l1_val, dte_l2_base, dte_l2_val; +- +- pdev = sdev->pdev; +- if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) +- return; +- +- sdev->devid = PCI_DEVID(pdev->bus->number, pdev->devfn); +- iommu = sdev->iommu; +- dte_l1 = iommu->iommu_dtbr + (pdev->bus->number); +- dte_l1_val = *dte_l1; +- +- if (!dte_l1_val) { +- /* Alloc a new level-2 device table page */ +- page = alloc_pages_node(iommu->node, __GFP_ZERO, +- get_order(PAGE_SIZE)); +- dte_l2_base = (unsigned long)page_address(page); +- dte_l1_val = (__pa(dte_l2_base) & PAGE_MASK) | SW64_IOMMU_ENTRY_VALID; +- *dte_l1 = dte_l1_val; +- } +- +- dte_l2 = __va(dte_l1_val & ~(SW64_IOMMU_ENTRY_VALID) & PAGE_MASK) + (pdev->devfn << 3); +- BUG_ON(!sdomain->pt_root); +- dte_l2_val = (__pa(sdomain->pt_root) & PAGE_MASK) | SW64_IOMMU_ENTRY_VALID; +- if (sdomain->type == IOMMU_DOMAIN_IDENTITY) { +- dte_l2_val |= 0x1; +- sdev->passthrough = IDENTMAP_ALL; +- } +- *dte_l2 = dte_l2_val; +- +- device_flush_all(sdev); +-} +- +-static void +-do_attach(struct sunway_iommu_dev *sdev_data, struct sunway_iommu_domain *sdomain) +-{ +- sdev_data->domain = sdomain; +- list_add(&sdev_data->list, &sdomain->dev_list); +- +- sdomain->dev_cnt++; +- set_dte_entry(sdev_data, sdomain); +- +- pr_debug("iommu: device %d add to domain: %d\n", +- sdev_data->devid, sdomain->id); +-} +- +-static void do_detach(struct sunway_iommu_dev *sdev_data) +-{ +- struct sunway_iommu_domain *sdomain = sdev_data->domain; +- +- sdev_data->domain = NULL; +- list_del(&sdev_data->list); +- device_flush_all(sdev_data); +- +- sdomain->dev_cnt--; +- pr_debug("iommu: device %d detached from domain %d\n", +- sdev_data->devid, sdomain->id); +-} +- +-static int +-__attach_device(struct sunway_iommu_dev *sdev_data, struct sunway_iommu_domain *sdomain) +-{ +- int ret; +- +- spin_lock(&sdomain->lock); +- ret = -EBUSY; +- if (sdev_data->domain != NULL) +- goto out_unlock; +- +- do_attach(sdev_data, sdomain); +- ret = 0; +- +-out_unlock: +- spin_unlock(&sdomain->lock); +- return ret; +-} +- +-static void __detach_device(struct sunway_iommu_dev *sunway_dev_data) +-{ +- struct sunway_iommu_domain *domain; +- +- domain = sunway_dev_data->domain; +- +- spin_lock(&domain->lock); +- do_detach(sunway_dev_data); +- spin_unlock(&domain->lock); +-} +- +-static int attach_device(struct device *dev, struct sunway_iommu_domain *sdomain) +-{ +- struct sunway_iommu_dev *sdev; +- unsigned long flags; +- int ret; +- +- sdev = dev_iommu_priv_get(dev); +- +- spin_lock_irqsave(&sunway_iommu_device_table_lock, flags); +- ret = __attach_device(sdev, sdomain); +- spin_unlock_irqrestore(&sunway_iommu_device_table_lock, flags); +- +- return ret; +-} +- +-static void detach_device(struct device *dev) +-{ +- struct sunway_iommu_domain *sunway_domain; +- struct sunway_iommu_dev *sdev_data; +- unsigned long flags; +- +- sdev_data = dev_iommu_priv_get(dev); +- sunway_domain = sdev_data->domain; +- +- if (WARN_ON(!sdev_data->domain)) +- return; +- +- spin_lock_irqsave(&sunway_iommu_device_table_lock, flags); +- __detach_device(sdev_data); +- spin_unlock_irqrestore(&sunway_iommu_device_table_lock, flags); +- +- if (!dev_is_pci(dev)) +- return; +-} +- +-static struct sunway_iommu_dev *search_dev_data(u16 devid) +-{ +- struct sunway_iommu_dev *sdev_data; +- struct llist_node *node; +- +- if (llist_empty(&dev_data_list)) +- return NULL; +- +- node = dev_data_list.first; +- llist_for_each_entry(sdev_data, node, dev_data_list) { +- if (sdev_data->devid == devid) +- return sdev_data; +- } +- +- return NULL; +-} +- +-/* dma_ops helpers*/ +-static struct sunway_iommu_domain *get_sunway_domain(struct device *dev) +-{ +- struct sunway_iommu_domain *sdomain; +- struct iommu_domain *domain; +- struct pci_dev *pdev; +- struct sunway_iommu_dev *sdev; +- +- pdev = to_pci_dev(dev); +- if (!pdev) +- return ERR_PTR(-ENODEV); +- +- sdev = dev_iommu_priv_get(dev); +- sdomain = sdev->domain; +- if (sdomain == NULL) { +- domain = iommu_get_domain_for_dev(dev); +- sdomain = to_sunway_domain(domain); +- attach_device(dev, sdomain); +- } +- +- if (sdomain == NULL) +- return ERR_PTR(-EBUSY); +- +- return sdomain; +-} +- +-/********************************************************************** +- * +- * Following functions describe IOMMU init ops +- * +- **********************************************************************/ +- +-static struct sunway_iommu *sunway_iommu_early_init(struct pci_controller *hose) +-{ +- struct sunway_iommu *iommu; +- struct page *page; +- unsigned long base; +- +- hose->pci_iommu = kzalloc(sizeof(struct sunway_iommu), GFP_KERNEL); +- if (!hose->pci_iommu) +- return 0; +- +- iommu = hose->pci_iommu; +- spin_lock_init(&iommu->dt_lock); +- +- iommu->node = hose->node; +- if (!node_online(hose->node)) +- iommu->node = -1; +- +- page = alloc_pages_node(iommu->node, __GFP_ZERO, get_order(PAGE_SIZE)); +- iommu->iommu_dtbr = page_address(page); +- +- iommu->hose_pt = hose; +- iommu->index = hose->index; +- +- iommu->enabled = true; +- +- base = __pa(iommu->iommu_dtbr) & PAGE_MASK; +- write_piu_ior0(hose->node, hose->index, DTBASEADDR, base); +- +- return iommu; +-} +- +-unsigned long fetch_dte(struct sunway_iommu *iommu, unsigned long devid, +- enum exceptype type) +-{ +- unsigned long *dte_l1, *dte_l2; +- unsigned long dte_l1_val, dte_l2_val; +- +- if (!iommu) +- return 0; +- dte_l1 = iommu->iommu_dtbr + (devid >> 8); +- if (type == DTE_LEVEL1) +- return (unsigned long)dte_l1; +- +- dte_l1_val = *dte_l1; +- if (type == DTE_LEVEL1_VAL) +- return dte_l1_val; +- +- dte_l1_val &= (~(SW64_IOMMU_ENTRY_VALID)) & (PAGE_MASK); +- dte_l1_val |= PAGE_OFFSET; +- dte_l2 = (unsigned long *)(dte_l1_val + ((devid & 0xff) << 3)); +- if (type == DTE_LEVEL2) +- return (unsigned long)dte_l2; +- +- dte_l2_val = *dte_l2; +- if (type == DTE_LEVEL2_VAL) +- return dte_l2_val; +- +- return dte_l2_val; +-} +- +-unsigned long fetch_pte(struct sunway_iommu_domain *sdomain, dma_addr_t iova, +- enum exceptype type) +-{ +- unsigned long iova_pfn, pte_l1_val, pte_l2_val; +- unsigned long *pte_l1, *pte_l2; +- unsigned long pte_root; +- unsigned long offset; +- +- if (!sdomain) +- return -EINVAL; +- +- pte_root = __pa(sdomain->pt_root) & PAGE_MASK; +- iova_pfn = iova >> PAGE_SHIFT; +- pte_root = ((pte_root) & (~(SW64_IOMMU_ENTRY_VALID)) & (PAGE_MASK)); +- pte_root |= PAGE_OFFSET; +- offset = ((iova_pfn >> 10) & SW64_IOMMU_LEVEL1_OFFSET) << 3; +- pte_l1 = (unsigned long *)(pte_root + offset); +- if (type == PTE_LEVEL1) +- return (unsigned long)pte_l1; +- +- pte_l1_val = *pte_l1; +- if (type == PTE_LEVEL1_VAL) +- return pte_l1_val; +- +- pte_l1_val &= (~(SW64_IOMMU_ENTRY_VALID)) & (PAGE_MASK); +- pte_l1_val |= PAGE_OFFSET; +- offset = (iova_pfn & SW64_IOMMU_LEVEL2_OFFSET) << 3; +- pte_l2 = (unsigned long *)(pte_l1_val + offset); +- +- if (type == PTE_LEVEL2) +- return (unsigned long)pte_l2; +- +- pte_l2_val = *pte_l2; +- if (type == PTE_LEVEL2_VAL) +- return pte_l2_val; +- +- return pte_l2_val; +-} +- +-/* IOMMU Interrupt handle */ +-irqreturn_t iommu_interrupt(int irq, void *dev) +-{ +- struct pci_controller *hose = (struct pci_controller *)dev; +- struct sunway_iommu_domain *sdomain; +- struct sunway_iommu_dev *sdev; +- unsigned long iommu_status; +- unsigned long type; +- unsigned long devid, dva; +- +- iommu_status = read_piu_ior0(hose->node, hose->index, IOMMUEXCPT_STATUS); +- if (!(iommu_status >> 63)) +- return IRQ_NONE; +- +- type = (iommu_status >> 59) & 0x7; +- devid = (iommu_status >> 37) & 0xffff; +- dva = iommu_status & 0xffffffff; +- pr_info("%s, iommu_status = %#lx, devid %#lx, dva %#lx, ", +- __func__, iommu_status, devid, dva); +- +- sdev = search_dev_data(devid); +- if (sdev == NULL) { +- pr_info("no such dev!!!\n"); +- +- iommu_status &= ~(1UL << 62); +- write_piu_ior0(hose->node, hose->index, +- IOMMUEXCPT_STATUS, iommu_status); +- +- return IRQ_HANDLED; +- } +- +- sdomain = sdev->domain; +- switch (type) { +- case DTE_LEVEL1: +- pr_info("invalid level1 dte, addr:%#lx, val:%#lx\n", +- fetch_dte(hose->pci_iommu, devid, DTE_LEVEL1), +- fetch_dte(hose->pci_iommu, devid, DTE_LEVEL1_VAL)); +- break; +- case DTE_LEVEL2: +- pr_info("invalid level2 dte, addr:%#lx, val:%#lx\n", +- fetch_dte(hose->pci_iommu, devid, DTE_LEVEL2), +- fetch_dte(hose->pci_iommu, devid, DTE_LEVEL2_VAL)); +- break; +- case PTE_LEVEL1: +- pr_info("invalid level1 pte, addr: %#lx, val:%#lx\n", +- fetch_pte(sdomain, dva, PTE_LEVEL1), +- fetch_pte(sdomain, dva, PTE_LEVEL1_VAL)); +- break; +- case PTE_LEVEL2: +- pr_info("invalid level2 pte, addr: %#lx, val: %#lx\n", +- fetch_pte(sdomain, dva, PTE_LEVEL2), +- fetch_pte(sdomain, dva, PTE_LEVEL2_VAL)); +- +- iommu_status &= ~(1UL << 62); +- write_piu_ior0(hose->node, hose->index, +- IOMMUEXCPT_STATUS, iommu_status); +- break; +- +- case UNAUTHORIZED_ACCESS: +- pr_info("unauthorized access\n"); +- break; +- case ILLEGAL_RESPONSE: +- pr_info("illegal response\n"); +- break; +- default: +- pr_info("unknown error\n"); +- break; +- } +- +- return IRQ_HANDLED; +-} +- +-struct irqaction iommu_irqaction = { +- .handler = iommu_interrupt, +- .flags = IRQF_SHARED | IRQF_NO_THREAD, +- .name = "sunway_iommu", +-}; +- +-void sunway_enable_iommu_func(struct pci_controller *hose) +-{ +- unsigned int iommu_irq, err; +- unsigned long iommu_conf, iommu_ctrl; +- +- iommu_irq = hose->int_irq; +- pr_debug("%s node %ld rc %ld iommu_irq %d\n", +- __func__, hose->node, hose->index, iommu_irq); +- err = request_irq(iommu_irq, iommu_interrupt, +- IRQF_SHARED, "sunway_iommu", hose); +- if (err < 0) +- pr_info("sw iommu request irq failed!\n"); +- +- iommu_ctrl = (1UL << 63) | (0x100UL << 10); +- write_piu_ior0(hose->node, hose->index, IOMMUEXCPT_CTRL, iommu_ctrl); +- iommu_conf = read_piu_ior0(hose->node, hose->index, PIUCONFIG0); +- iommu_conf = iommu_conf | (0x3 << 7); +- write_piu_ior0(hose->node, hose->index, PIUCONFIG0, iommu_conf); +- write_piu_ior0(hose->node, hose->index, TIMEOUT_CONFIG, 0xf); +- iommu_conf = read_piu_ior0(hose->node, hose->index, PIUCONFIG0); +- pr_debug("SW arch configure node %ld hose-%ld iommu_conf = %#lx\n", +- hose->node, hose->index, iommu_conf); +-} +- +-static bool is_iommu_enable(struct pci_controller *hose) +-{ +- u64 rc_mask = 0x1; +- +- rc_mask <<= (8 * hose->node + hose->index); +- if (iommu_enable_cmd & rc_mask) +- return true; +- +- return false; +-} +- +-static struct iommu_domain *sunway_iommu_domain_alloc(unsigned type); +- +-int sunway_iommu_init(void) +-{ +- struct pci_controller *hose; +- struct sunway_iommu *iommu; +- int ret; +- int iommu_index = 0; +- +- sunway_iommu_domain_bitmap = +- (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, +- get_order(MAX_DOMAIN_NUM / 8)); +- if (sunway_iommu_domain_bitmap == NULL) +- return 0; +- __set_bit(0, sunway_iommu_domain_bitmap); +- +- /* Do the loop */ +- for (hose = hose_head; hose; hose = hose->next) { +- if (!is_iommu_enable(hose)) { +- hose->iommu_enable = false; +- continue; +- } +- +- iommu = sunway_iommu_early_init(hose); +- iommu_device_sysfs_add(&iommu->iommu, NULL, NULL, "%d", +- iommu_index); +- iommu_device_set_ops(&iommu->iommu, &sunway_iommu_ops); +- iommu_device_register(&iommu->iommu); +- iommu_index++; +- sunway_enable_iommu_func(hose); +- hose->iommu_enable = true; +- } +- +- ret = iova_cache_get(); +- if (ret) +- return ret; +- +- ret = bus_set_iommu(&pci_bus_type, &sunway_iommu_ops); +- if (ret) +- return ret; +- +- for (hose = hose_head; hose; hose = hose->next) +- if (hose->iommu_enable) +- piu_flush_all(hose); +- +- return 1; +-} +-device_initcall(sunway_iommu_init); +- +-/* iommu cpu syscore ops */ +-static int iommu_cpu_suspend(void) +-{ +- return 0; +-} +- +-static void iommu_cpu_resume(void) +-{ +- +-} +- +-struct syscore_ops iommu_cpu_syscore_ops = { +- .suspend = iommu_cpu_suspend, +- .resume = iommu_cpu_resume, +-}; +- +-/******************************************************************************* +- * +- * DMA OPS Functions +- * +- ******************************************************************************/ +- +-struct sunway_iommu *get_first_iommu_from_domain(struct sunway_iommu_domain *sdomain) +-{ +- struct sunway_iommu *iommu; +- struct sunway_iommu_dev *entry; +- +- entry = list_first_entry(&sdomain->dev_list, struct sunway_iommu_dev, list); +- iommu = entry->iommu; +- +- return iommu; +-} +- +-static unsigned long +-sunway_iommu_unmap_page(struct sunway_iommu_domain *sunway_domain, +- unsigned long iova, unsigned long page_size) +-{ +- unsigned long *pte_l2, unmapped; +- +- pr_debug("%s iova %#lx, page_size %#lx\n", __func__, iova, page_size); +- BUG_ON(!is_power_of_2(page_size)); +- +- unmapped = 0; +- while (unmapped < page_size) { +- pte_l2 = (unsigned long *)fetch_pte(sunway_domain, iova, PTE_LEVEL2); +- *pte_l2 = 0; +- +- flush_pcache_by_addr(sunway_domain, (unsigned long)pte_l2); +- flush_ptlb_by_addr(sunway_domain, (iova >> PAGE_SHIFT)); +- +- iova += PAGE_SIZE; +- unmapped += PAGE_SIZE; +- } +- +- return unmapped; +-} +- +-int sunway_iommu_map_page(struct sunway_iommu_domain *sunway_domain, +- unsigned long bus_addr, unsigned long paddr, +- size_t page_size) +-{ +- /* +- * pde: page table entry +- * pte: level 2 page table entry +- * pte_root: page table root +- */ +- struct page *page; +- struct sunway_iommu *iommu; +- unsigned long pde, pte, iova_pfn; +- unsigned long pdebaseaddr; +- u64 *ptebasecond, ptebaseaddr; +- u64 pte_root = (__pa(sunway_domain->pt_root) & PAGE_MASK); +- +- iova_pfn = (unsigned long)(bus_addr >> PAGE_SHIFT); +- +- pdebaseaddr = ((iova_pfn >> 10) & SW64_IOMMU_LEVEL1_OFFSET) << 3; +- pdebaseaddr += ((pte_root) & (~(SW64_IOMMU_ENTRY_VALID)) & (PAGE_MASK)) +- + PAGE_OFFSET; +- +- pde = *(unsigned long *)pdebaseaddr; +- if (pde) { +- ptebaseaddr = (pde & (~SW64_IOMMU_ENTRY_VALID) & PAGE_MASK) + PAGE_OFFSET; +- ptebaseaddr += (iova_pfn & SW64_IOMMU_LEVEL2_OFFSET) << 3; +- +- goto direct_map; +- } +- +- iommu = get_first_iommu_from_domain(sunway_domain); +- if (!iommu) +- return -1; +- page = alloc_pages_node(iommu->node, GFP_ATOMIC | __GFP_ZERO, 0); +- if (!page) { +- pr_err("Allocating pages failed.\n"); +- return -1; +- } +- +- ptebasecond = page_address(page); +- pde = (__pa(ptebasecond) & PAGE_MASK) | SW64_IOMMU_ENTRY_VALID; +- +- /* +- * If pde exists, no need to allocate a new page. +- * Atomic compare and exchange, compare the value the pointer points to +- * with 0UL. If identical, store pde where the pointer points to, return +- * 0UL. Otherwise, return the value the pointer points to. +- */ +- if (cmpxchg64((volatile u64 *)pdebaseaddr, 0ULL, pde)) { +- ptebaseaddr = ((*(volatile u64 *)pdebaseaddr) +- & (~SW64_IOMMU_ENTRY_VALID) & PAGE_MASK) + PAGE_OFFSET; +- ptebaseaddr += (iova_pfn & SW64_IOMMU_LEVEL2_OFFSET) << 3; +- free_page((unsigned long)ptebasecond); +- } else { +- flush_pcache_by_addr(sunway_domain, pdebaseaddr); +- ptebaseaddr = (unsigned long)ptebasecond +- + ((iova_pfn & SW64_IOMMU_LEVEL2_OFFSET) << 3); +- } +- +-direct_map: +- /* case 8K */ +- if (page_size == (1UL << PAGE_SHIFT)) { +- if (*(volatile u64 *)ptebaseaddr) { +- pr_err("IOVA 4G overlap. IOVA is %#lx.\n", bus_addr); +- return -EFAULT; +- } +- +- pte = (paddr & PAGE_MASK) | SW64_IOMMU_ENTRY_VALID +- | SW64_IOMMU_GRN_8K | SW64_IOMMU_ENABLE; +- *(volatile u64 *)ptebaseaddr = pte; +- flush_pcache_by_addr(sunway_domain, ptebaseaddr); +- /* case 8M */ +- } else if (page_size == (1UL << PAGE_8M_SHIFT)) { +- unsigned long *ptr; +- int i, ptes_one_page, ptes_one_cache; +- +- ptr = (unsigned long *)ptebaseaddr; +- ptes_one_page = PAGE_SIZE/sizeof(pte); +- ptes_one_cache = L1_CACHE_BYTES/sizeof(pte); +- +- pte = (paddr & PAGE_MASK) | SW64_IOMMU_ENTRY_VALID +- | SW64_IOMMU_GRN_8M | SW64_IOMMU_ENABLE; +- +- for (i = 0; i < ptes_one_page; i++) { +- if (*ptr) { +- pr_err("IOVA 4G overlap. IOVA is %#lx.\n", bus_addr); +- return -EFAULT; +- } +- +- *ptr = pte; +- +- /* just do once flush per cache line */ +- if (i % ptes_one_cache == (ptes_one_cache - 1)) +- flush_pcache_by_addr(sunway_domain, (unsigned long)ptr); +- ptr++; +- } +- } +-#ifdef CONFIG_SW64_GUEST +- flush_ptlb_by_addr(sunway_domain, pfn | SW64_IOMMU_MAP_FLAG); +-#endif +- return 0; +-} +- +-static unsigned long +-sunway_alloc_iova(struct dma_domain *dma_dom, unsigned int pages) +-{ +- unsigned long pfn = 0; +- +- pages = __roundup_pow_of_two(pages); +- /* IOVA boundary should be 16M ~ 3.5G */ +- pfn = alloc_iova_fast(&dma_dom->iovad, pages, +- IOVA_PFN(SW64_DMA_LIMIT), true); +- if (!pfn) +- return 0; +- +- return (pfn << PAGE_SHIFT); +-} +- +-static void sunway_free_iova(struct dma_domain *dma_dom, +- unsigned long address, unsigned int pages) +-{ +- pages = __roundup_pow_of_two(pages); +- address >>= PAGE_SHIFT; +- +- free_iova_fast(&dma_dom->iovad, address, pages); +-} +- +-static dma_addr_t +-__sunway_map_single(struct dma_domain *dma_dom, +- struct pci_dev *pdev, phys_addr_t paddr, size_t size) +-{ +- struct pci_controller *hose = (struct pci_controller *)pdev->sysdata; +- dma_addr_t ret, address, start; +- long npages; +- int i; +- +- if (hose == NULL) { +- pr_err("%s:hose does not exist!\n", __func__); +- return 0; +- } +- +- npages = iommu_num_pages(paddr, size, PAGE_SIZE); +- +- address = sunway_alloc_iova(dma_dom, npages); +- if (!address) +- return 0; +- +- start = address; +- for (i = 0; i < npages; ++i) { +- ret = sunway_iommu_map_page(&dma_dom->sdomain, start, +- paddr, PAGE_SIZE); +- if (ret) { +- pr_info("error when map page.\n"); +- goto out_unmap; +- } +- +- start += PAGE_SIZE; +- paddr += PAGE_SIZE; +- } +- +- address += paddr & ~PAGE_MASK; +- return address; +- +-out_unmap: +- for (--i; i >= 0; --i) { +- start -= PAGE_SIZE; +- sunway_iommu_unmap_page(&dma_dom->sdomain, start, PAGE_SIZE); +- } +- +- sunway_free_iova(dma_dom, address, npages); +- return 0; +-} +- +-static dma_addr_t +-pci_iommu_map_single(struct pci_dev *pdev, +- struct dma_domain *dma_dom, void *cpu_addr, size_t size) +-{ +- struct pci_controller *hose = pdev->sysdata; +- unsigned long paddr; +- +- if (hose == NULL) { +- pr_err("%s: hose does not exist!\n", __func__); +- return 0; +- } +- +- paddr = __sunway_map_single(dma_dom, pdev, __pa(cpu_addr), size); +- +- pr_debug("pci_alloc_consistent: %zx -> [%px,%lx] from %ps\n", +- size, cpu_addr, paddr, __builtin_return_address(0)); +- +- return paddr; +-} +- +-static void *sunway_alloc_coherent(struct device *dev, +- size_t size, +- dma_addr_t *dma_addr, gfp_t gfp, +- unsigned long attrs) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct pci_controller *hose; +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- struct sunway_iommu_dev *sdev; +- struct page *page; +- void *cpu_addr; +- +- if (!pdev) +- return NULL; +- +- hose = pdev->sysdata; +- if (!hose) +- return NULL; +- +- gfp &= ~GFP_DMA; +- +-try_again: +- page = alloc_pages_node(dev_to_node(dev), gfp | __GFP_ZERO, get_order(size)); +- cpu_addr = page_address(page); +- if (!cpu_addr) { +- pr_info +- ("pci_alloc_consistent: get_free_pages failed from %ps\n", +- __builtin_return_address(0)); +- +- return NULL; +- } +- +- *dma_addr = __pa(cpu_addr); +- if (!(hose->iommu_enable)) +- return cpu_addr; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->passthrough & DMA_MASK64) +- return cpu_addr; +- else if (sdev->passthrough) { +- if (min_not_zero(*dev->dma_mask, dev->coherent_dma_mask) +- > DMA_BIT_MASK(32)) { +- sdev->passthrough |= DMA_MASK64; +- return cpu_addr; +- } +- +- __free_pages(page, get_order(size)); +- set_dma_ops(dev, get_arch_dma_ops(dev->bus)); +- return dev->dma_ops->alloc(dev, size, dma_addr, gfp, attrs); +- } +- +- sdomain = get_sunway_domain(dev); +- dma_dom = to_dma_domain(sdomain); +- +- *dma_addr = pci_iommu_map_single(pdev, dma_dom, cpu_addr, size); +- if (*dma_addr == 0) { +- free_pages((unsigned long)cpu_addr, get_order(size)); +- if (gfp & GFP_DMA) +- return NULL; +- +- gfp |= GFP_DMA; +- goto try_again; +- } +- +- return cpu_addr; +-} +- +-static void +-__sunway_unmap_single(struct dma_domain *dma_dom, dma_addr_t dma_addr, size_t size) +-{ +- dma_addr_t start; +- long npages; +- int i; +- +- npages = iommu_num_pages(dma_addr, size, PAGE_SIZE); +- dma_addr &= PAGE_MASK; +- start = dma_addr; +- +- for (i = 0; i < npages; ++i) { +- sunway_iommu_unmap_page(&dma_dom->sdomain, start, PAGE_SIZE); +- start += PAGE_SIZE; +- } +- +- sunway_free_iova(dma_dom, dma_addr, npages); +- pr_debug("pci_free_consistent: %zx -> [%llx] from %ps\n", +- size, dma_addr, __builtin_return_address(0)); +- +-} +- +-static void +-sunway_free_coherent(struct device *dev, size_t size, +- void *vaddr, dma_addr_t dma_addr, unsigned long attrs) +-{ +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- struct pci_dev *pdev = to_pci_dev(dev); +- struct pci_controller *hose; +- struct sunway_iommu_dev *sdev; +- +- if (!pdev) +- goto out_unmap; +- +- hose = pdev->sysdata; +- if (!hose || !(hose->iommu_enable)) +- goto out_unmap; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->passthrough) +- goto out_unmap; +- +- sdomain = get_sunway_domain(dev); +- dma_dom = to_dma_domain(sdomain); +- __sunway_unmap_single(dma_dom, dma_addr, size); +- goto out_free; +- +-out_unmap: +- pci_unmap_single(pdev, dma_addr, size, PCI_DMA_BIDIRECTIONAL); +- +-out_free: +- pr_debug("sunway_free_consistent: [%llx,%zx] from %ps\n", +- dma_addr, size, __builtin_return_address(0)); +- +- free_pages((unsigned long)vaddr, get_order(size)); +-} +- +-static dma_addr_t +-sunway_map_page(struct device *dev, struct page *page, +- unsigned long offset, size_t size, +- enum dma_data_direction dir, unsigned long attrs) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- struct pci_controller *hose; +- struct sunway_iommu_dev *sdev; +- phys_addr_t paddr = page_to_phys(page) + offset; +- +- if (dir == PCI_DMA_NONE) +- BUG(); +- +- if (!pdev) +- return 0; +- +- hose = pdev->sysdata; +- if (!hose || !(hose->iommu_enable)) +- return paddr; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->passthrough & DMA_MASK64) +- return paddr; +- else if (sdev->passthrough) { +- if (min_not_zero(*dev->dma_mask, dev->coherent_dma_mask) +- > DMA_BIT_MASK(32)) { +- sdev->passthrough |= DMA_MASK64; +- return paddr; +- } +- +- set_dma_ops(dev, get_arch_dma_ops(dev->bus)); +- return dev->dma_ops->map_page(dev, page, offset, +- size, dir, attrs); +- } +- +- sdomain = get_sunway_domain(dev); +- dma_dom = to_dma_domain(sdomain); +- +- return pci_iommu_map_single(pdev, dma_dom, +- (char *)page_address(page) + offset, size); +-} +- +-static void +-sunway_unmap_page(struct device *dev, dma_addr_t dma_addr, +- size_t size, enum dma_data_direction dir, unsigned long attrs) +-{ +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- struct pci_dev *pdev; +- struct pci_controller *hose; +- struct sunway_iommu_dev *sdev; +- +- pdev = to_pci_dev(dev); +- if (!pdev) +- return; +- +- hose = pdev->sysdata; +- if (hose == NULL) +- return; +- +- if (!hose->iommu_enable) +- return; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->passthrough) +- return; +- +- sdomain = get_sunway_domain(dev); +- dma_dom = to_dma_domain(sdomain); +- __sunway_unmap_single(dma_dom, dma_addr, size); +-} +- +-#define SG_ENT_VIRT_ADDRESS(SG) (sg_virt((SG))) +-static int +-sunway_map_sg(struct device *dev, struct scatterlist *sgl, +- int nents, enum dma_data_direction dir, unsigned long attrs) +-{ +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom = NULL; +- struct scatterlist *sg; +- struct pci_dev *pdev = to_pci_dev(dev); +- struct pci_controller *hose; +- struct sunway_iommu_dev *sdev; +- int i, out_nents = 0; +- +- if (dir == PCI_DMA_NONE) +- BUG(); +- +- if (!pdev) +- return 0; +- +- hose = pdev->sysdata; +- if (!hose) +- return 0; +- +- sdomain = get_sunway_domain(dev); +- dma_dom = to_dma_domain(sdomain); +- +- for_each_sg(sgl, sg, nents, i) { +- BUG_ON(!sg_page(sg)); +- +- sg_dma_address(sg) = __pa(SG_ENT_VIRT_ADDRESS(sg)); +- if (!(hose->iommu_enable)) +- goto check; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->passthrough & DMA_MASK64) +- goto check; +- else if (sdev->passthrough) { +- if (min_not_zero(*dev->dma_mask, dev->coherent_dma_mask) +- > DMA_BIT_MASK(32)) { +- sdev->passthrough |= DMA_MASK64; +- goto check; +- } +- +- set_dma_ops(dev, get_arch_dma_ops(dev->bus)); +- return dev->dma_ops->map_sg(dev, sgl, nents, +- dir, attrs); +- } +- +- sg_dma_address(sg) = +- pci_iommu_map_single(pdev, dma_dom, +- SG_ENT_VIRT_ADDRESS(sg), sg->length); +-check: +- if (sg_dma_address(sg) == 0) +- goto error; +- +- sg_dma_len(sg) = sg->length; +- out_nents++; +- } +- +- return nents; +- +-error: +- pr_warn("pci_map_sg failed:"); +- pr_warn("could not allocate dma page tables\n"); +- +- if (out_nents) +- pci_unmap_sg(pdev, sgl, out_nents, dir); +- return 0; +-} +- +-static void +-sunway_unmap_sg(struct device *dev, struct scatterlist *sgl, +- int nents, enum dma_data_direction dir, unsigned long attrs) +-{ +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- struct scatterlist *sg; +- struct pci_dev *pdev; +- struct pci_controller *hose; +- struct sunway_iommu_dev *sdev; +- dma_addr_t dma_addr; +- long size; +- int j; +- +- pdev = to_pci_dev(dev); +- if (!pdev) +- return; +- +- hose = pdev->sysdata; +- if (!hose->iommu_enable) +- return; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->passthrough) +- return; +- +- sdomain = get_sunway_domain(dev); +- dma_dom = to_dma_domain(sdomain); +- +- for_each_sg(sgl, sg, nents, j) { +- dma_addr = sg->dma_address; +- size = sg->dma_length; +- if (!size) +- break; +- +- __sunway_unmap_single(dma_dom, dma_addr, size); +- } +-} +- +-static int sunway_supported(struct device *dev, u64 mask) +-{ +- if (MAX_DMA_ADDRESS - PAGE_OFFSET - 1 <= mask) +- return 1; +- +- return 0; +-} +- +-static const struct dma_map_ops sunway_dma_ops = { +- .alloc = sunway_alloc_coherent, +- .free = sunway_free_coherent, +- .map_sg = sunway_map_sg, +- .unmap_sg = sunway_unmap_sg, +- .map_page = sunway_map_page, +- .unmap_page = sunway_unmap_page, +- .dma_supported = sunway_supported, +-}; +- +-/********************************************************************** +- * +- * IOMMU OPS Functions +- * +- **********************************************************************/ +- +-static struct iommu_domain *sunway_iommu_domain_alloc(unsigned type) +-{ +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- +- switch (type) { +- case IOMMU_DOMAIN_UNMANAGED: +- sdomain = sunway_domain_alloc(); +- if (!sdomain) { +- pr_err("Allocating sunway_domain failed!\n"); +- return NULL; +- } +- +- sdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); +- +- sdomain->domain.geometry.aperture_start = 0ULL; +- sdomain->domain.geometry.aperture_end = (~0ULL); +- sdomain->domain.geometry.force_aperture = true; +- sdomain->type = IOMMU_DOMAIN_UNMANAGED; +- break; +- +- case IOMMU_DOMAIN_DMA: +- dma_dom = dma_domain_alloc(); +- if (!dma_dom) { +- pr_err("Failed to alloc dma domain!\n"); +- return NULL; +- } +- +- sdomain = &dma_dom->sdomain; +- break; +- +- case IOMMU_DOMAIN_IDENTITY: +- sdomain = sunway_domain_alloc(); +- if (!sdomain) +- return NULL; +- +- sdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL); +- if (!sdomain->pt_root) { +- pr_err("Allocating pt_root failed!\n"); +- return NULL; +- } +- +- sdomain->type = IOMMU_DOMAIN_IDENTITY; +- break; +- +- default: +- return NULL; +- } +- +- return &sdomain->domain; +-} +- +-static void clean_domain(struct sunway_iommu_domain *sdomain) +-{ +- struct sunway_iommu_dev *entry; +- unsigned long flags; +- +- spin_lock_irqsave(&sunway_iommu_device_table_lock, flags); +- +- while (!list_empty(&sdomain->dev_list)) { +- entry = list_first_entry(&sdomain->dev_list, +- struct sunway_iommu_dev, list); +- +- BUG_ON(!entry->domain); +- __detach_device(entry); +- } +- +- spin_unlock_irqrestore(&sunway_iommu_device_table_lock, flags); +-} +- +-static void sunway_iommu_domain_free(struct iommu_domain *dom) +-{ +- struct sunway_iommu_domain *sdomain; +- struct dma_domain *dma_dom; +- +- sdomain = to_sunway_domain(dom); +- +- if (sdomain->dev_cnt > 0) +- clean_domain(sdomain); +- +- BUG_ON(sdomain->dev_cnt != 0); +- +- if (!dom) +- return; +- +- switch (dom->type) { +- case IOMMU_DOMAIN_DMA: +- dma_dom = to_dma_domain(sdomain); +- dma_domain_free(dma_dom); +- break; +- +- default: +- free_pagetable(sdomain); +- sunway_domain_free(sdomain); +- break; +- } +- +-} +- +-static int sunway_iommu_attach_device(struct iommu_domain *dom, struct device *dev) +-{ +- struct sunway_iommu_domain *sdomain = to_sunway_domain(dom); +- struct sunway_iommu_dev *sdev_data; +- struct pci_dev *pdev; +- struct pci_controller *hose; +- int ret; +- +- pdev = to_pci_dev(dev); +- if (!pdev) +- return -EINVAL; +- +- hose = pdev->sysdata; +- if (!hose) +- return -EINVAL; +- +- if (!hose->iommu_enable) +- return -EINVAL; +- +- sdev_data = dev_iommu_priv_get(dev); +- if (!sdev_data) +- return -EINVAL; +- +- if (sdev_data->domain) +- detach_device(dev); +- +- ret = attach_device(dev, sdomain); +- +- return ret; +-} +- +-static void sunway_iommu_detach_device(struct iommu_domain *dom, struct device *dev) +-{ +- struct sunway_iommu_dev *sdev; +- struct pci_dev *pdev = to_pci_dev(dev); +- +- if (!pdev) +- return; +- +- sdev = dev_iommu_priv_get(dev); +- if (sdev->domain != NULL) +- detach_device(dev); +-} +- +-static phys_addr_t +-sunway_iommu_iova_to_phys(struct iommu_domain *dom, dma_addr_t iova) +-{ +- struct sunway_iommu_domain *sdomain = to_sunway_domain(dom); +- unsigned long paddr, grn; +- +- if (iova > SW64_BAR_ADDRESS) +- return iova; +- +- paddr = fetch_pte(sdomain, iova, PTE_LEVEL2_VAL); +- +- if ((paddr & SW64_IOMMU_ENTRY_VALID) == 0) +- return 0; +- +- paddr &= ~SW64_IOMMU_ENTRY_VALID; +- grn = paddr & SW64_PTE_GRN_MASK; /* get page granularity */ +- paddr &= PAGE_MASK; +- +- switch (grn) { +- case SW64_IOMMU_GRN_8M: +- paddr += (iova & ~HPAGE_MASK); +- break; +- case SW64_IOMMU_GRN_8K: +- default: +- paddr += (iova & ~PAGE_MASK); +- break; +- } +- +- return paddr; +-} +- +-static int +-sunway_iommu_map(struct iommu_domain *dom, unsigned long iova, +- phys_addr_t paddr, size_t page_size, int iommu_prot, gfp_t gfp) +-{ +- struct sunway_iommu_domain *sdomain = to_sunway_domain(dom); +- int ret; +- +- /* +- * As VFIO cannot distinguish between normal DMA request +- * and pci device BAR, check should be introduced manually +- * to avoid VFIO trying to map pci config space. +- */ +- if (iova > SW64_BAR_ADDRESS) +- return 0; +- +- mutex_lock(&sdomain->api_lock); +- ret = sunway_iommu_map_page(sdomain, iova, paddr, page_size); +- mutex_unlock(&sdomain->api_lock); +- +- return ret; +-} +- +-static size_t +-sunway_iommu_unmap(struct iommu_domain *dom, unsigned long iova, +- size_t page_size, +- struct iommu_iotlb_gather *gather) +-{ +- struct sunway_iommu_domain *sdomain = to_sunway_domain(dom); +- size_t unmap_size; +- +- if (iova > SW64_BAR_ADDRESS) +- return page_size; +- +- mutex_lock(&sdomain->api_lock); +- unmap_size = sunway_iommu_unmap_page(sdomain, iova, page_size); +- mutex_unlock(&sdomain->api_lock); +- +- return unmap_size; +-} +- +-static struct iommu_group *sunway_iommu_device_group(struct device *dev) +-{ +- return pci_device_group(dev); +-} +- +-static int iommu_init_device(struct device *dev) +-{ +- struct sunway_iommu_dev *sdev; +- struct sunway_iommu *iommu; +- struct pci_dev *pdev; +- struct pci_controller *hose; +- +- if (dev_iommu_priv_get(dev)) +- return 0; +- +- sdev = kzalloc(sizeof(struct sunway_iommu_dev), GFP_KERNEL); +- if (!sdev) +- return -ENOMEM; +- +- pdev = to_pci_dev(dev); +- hose = pdev->sysdata; +- iommu = hose->pci_iommu; +- llist_add(&sdev->dev_data_list, &dev_data_list); +- sdev->pdev = pdev; +- sdev->iommu = iommu; +- +- dev_iommu_priv_set(dev, sdev); +- +- return 0; +-} +- +-static void iommu_uninit_device(struct device *dev) +-{ +- struct sunway_iommu_dev *sdev; +- +- sdev = dev_iommu_priv_get(dev); +- if (!sdev) +- return; +- +- if (sdev->domain) +- detach_device(dev); +- +- dev_iommu_priv_set(dev, NULL); +-} +- +-static void sunway_iommu_release_device(struct device *dev) +-{ +- struct pci_dev *pdev; +- struct pci_controller *hose; +- +- pdev = to_pci_dev(dev); +- if (!pdev) +- return; +- +- hose = pdev->sysdata; +- if (!hose->iommu_enable) +- return; +- +- iommu_uninit_device(dev); +-} +- +-static struct iommu_device *sunway_iommu_probe_device(struct device *dev) +-{ +- struct pci_dev *pdev; +- struct pci_controller *hose; +- struct sunway_iommu *iommu; +- int ret; +- +- pdev = to_pci_dev(dev); +- if (!pdev) +- return ERR_PTR(-ENODEV); +- +- if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) +- return ERR_PTR(-ENODEV); +- +- if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) +- return ERR_PTR(-ENODEV); +- +- hose = pdev->sysdata; +- if (!hose) +- return ERR_PTR(-ENODEV); +- +- if (!hose->iommu_enable) +- return ERR_PTR(-ENODEV); +- +- if (dev_iommu_priv_get(dev)) +- return &iommu->iommu; +- +- ret = iommu_init_device(dev); +- if (ret) +- return ERR_PTR(ret); +- +- iommu = hose->pci_iommu; +- +- return &iommu->iommu; +-} +- +-static int sunway_iommu_def_domain_type(struct device *dev) +-{ +- struct sunway_iommu_dev *sdev; +- +- sdev = dev_iommu_priv_get(dev); +- if (!sdev->domain) +- return 0; +- +- return sdev->domain->type; +-} +- +-static bool sunway_iommu_capable(enum iommu_cap cap) +-{ +- switch (cap) { +- case IOMMU_CAP_INTR_REMAP: +- return true; +- default: +- return false; +- } +-} +- +-static void sunway_iommu_probe_finalize(struct device *dev) +-{ +- struct iommu_domain *domain; +- +- domain = iommu_get_domain_for_dev(dev); +- if (domain) +- set_dma_ops(dev, &sunway_dma_ops); +-} +- +-const struct iommu_ops sunway_iommu_ops = { +- .capable = sunway_iommu_capable, +- .domain_alloc = sunway_iommu_domain_alloc, +- .domain_free = sunway_iommu_domain_free, +- .attach_dev = sunway_iommu_attach_device, +- .detach_dev = sunway_iommu_detach_device, +- .probe_device = sunway_iommu_probe_device, +- .probe_finalize = sunway_iommu_probe_finalize, +- .release_device = sunway_iommu_release_device, +- .map = sunway_iommu_map, +- .unmap = sunway_iommu_unmap, +- .iova_to_phys = sunway_iommu_iova_to_phys, +- .device_group = sunway_iommu_device_group, +- .pgsize_bitmap = SW64_IOMMU_PGSIZES, +- .def_domain_type = sunway_iommu_def_domain_type, +-}; +- +-/***************************************************************************** +- * +- * Boot param handle +- * +- *****************************************************************************/ +-static int __init iommu_enable_setup(char *str) +-{ +- int ret; +- unsigned long rc_bitmap = 0xffffffffUL; +- +- ret = kstrtoul(str, 16, &rc_bitmap); +- iommu_enable_cmd = rc_bitmap; +- +- return ret; +-} +-__setup("iommu_enable=", iommu_enable_setup); +diff --git a/drivers/iommu/sw64/sunway_iommu.h b/drivers/iommu/sw64/sunway_iommu.h +deleted file mode 100644 +index 52d6452fa14c..000000000000 +--- a/drivers/iommu/sw64/sunway_iommu.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0 */ +-/* +- * This file contains declarations and inline functions for interfacing +- * with the PCI initialization routines. +- */ +-#include +-#include +-#include +-#include +- +-struct sunway_iommu_bypass_id { +- unsigned int vendor; +- unsigned int device; +-}; +- +-struct sunway_iommu { +- int index; +- bool enabled; +- unsigned long *iommu_dtbr; +- spinlock_t dt_lock; /* Device Table Lock */ +- int node; /* NUMA node */ +- +- struct pci_controller *hose_pt; +- struct pci_dev *pdev; /* PCI device to this IOMMU */ +- struct iommu_device iommu; /* IOMMU core code handle */ +-}; +- +-struct sunway_iommu_dev { +- struct list_head list; /* For domain->dev_list */ +- struct llist_node dev_data_list; /* Global device list */ +- u16 devid; +- int alias; +- unsigned int passthrough; +- struct sunway_iommu *iommu; +- struct pci_dev *pdev; +- +- spinlock_t lock; /* Lock the page table mainly */ +- struct sunway_iommu_domain *domain; /* Domain device is bound to */ +-}; +- +-struct sunway_iommu_domain { +- unsigned type; +- spinlock_t lock; +- struct mutex api_lock; +- u16 id; /* Domain ID */ +- struct list_head list; /* For list of all SW domains */ +- struct list_head dev_list; /* List of devices in this domain */ +- struct iommu_domain domain; /* IOMMU domain handle */ +- unsigned long *pt_root; /* Page Table root */ +- unsigned int dev_cnt; /* Number of devices in this domain */ +-}; +- +-struct sw64dev_table_entry { +- u64 data; +-}; +- +-struct sunway_iommu_group { +- struct pci_dev *dev; +- struct iommu_group *group; +-}; +- +-#define SW64_IOMMU_ENTRY_VALID ((1UL) << 63) +-#define SW64_DMA_START 0x1000000 +-#define SW64_IOMMU_GRN_8K ((0UL) << 4) /* page size as 8KB */ +-#define SW64_IOMMU_GRN_8M ((0x2UL) << 4) /* page size as 8MB */ +-#define SW64_PTE_GRN_MASK ((0x3UL) << 4) +-#define PAGE_8M_SHIFT 23 +-#define SW64_IOMMU_ENABLE 3 +-#define SW64_IOMMU_DISABLE 0 +-#define SW64_IOMMU_LEVEL1_OFFSET 0x1ff +-#define SW64_IOMMU_LEVEL2_OFFSET 0x3ff +-#define SW64_IOMMU_LEVEL3_OFFSET 0x3ff +-#define SW64_IOMMU_BYPASS 0x1 +-#define SW64_IOMMU_MAP_FLAG ((0x1UL) << 20) +- +-#define PAGE_SHIFT_IOMMU 18 +-#define PAGE_SIZE_IOMMU (_AC(1, UL) << PAGE_SHIFT_IOMMU) +diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c +index 3c64cb9fb27d..2bfdd5734844 100644 +--- a/drivers/iommu/virtio-iommu.c ++++ b/drivers/iommu/virtio-iommu.c +@@ -1115,7 +1115,7 @@ static void viommu_remove(struct virtio_device *vdev) + iommu_device_unregister(&viommu->iommu); + + /* Stop all virtqueues */ +- virtio_reset_device(vdev); ++ vdev->config->reset(vdev); + vdev->config->del_vqs(vdev); + + dev_info(&vdev->dev, "device removed\n"); +@@ -1138,7 +1138,6 @@ static struct virtio_device_id id_table[] = { + { VIRTIO_ID_IOMMU, VIRTIO_DEV_ANY_ID }, + { 0 }, + }; +-MODULE_DEVICE_TABLE(virtio, id_table); + + static struct virtio_driver virtio_iommu_drv = { + .driver.name = KBUILD_MODNAME, +diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c +index f479d8971dfb..5e0acabed37a 100644 +--- a/drivers/media/usb/uvc/uvc_ctrl.c ++++ b/drivers/media/usb/uvc/uvc_ctrl.c +@@ -6,6 +6,7 @@ + * Laurent Pinchart (laurent.pinchart@ideasonboard.com) + */ + ++#include + #include + #include + #include +@@ -1275,17 +1276,12 @@ static void uvc_ctrl_send_slave_event(struct uvc_video_chain *chain, + uvc_ctrl_send_event(chain, handle, ctrl, mapping, val, changes); + } + +-static void uvc_ctrl_status_event_work(struct work_struct *work) ++void uvc_ctrl_status_event(struct uvc_video_chain *chain, ++ struct uvc_control *ctrl, const u8 *data) + { +- struct uvc_device *dev = container_of(work, struct uvc_device, +- async_ctrl.work); +- struct uvc_ctrl_work *w = &dev->async_ctrl; +- struct uvc_video_chain *chain = w->chain; + struct uvc_control_mapping *mapping; +- struct uvc_control *ctrl = w->ctrl; + struct uvc_fh *handle; + unsigned int i; +- int ret; + + mutex_lock(&chain->ctrl_mutex); + +@@ -1293,7 +1289,7 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) + ctrl->handle = NULL; + + list_for_each_entry(mapping, &ctrl->info.mappings, list) { +- s32 value = __uvc_ctrl_get_value(mapping, w->data); ++ s32 value = __uvc_ctrl_get_value(mapping, data); + + /* + * handle may be NULL here if the device sends auto-update +@@ -1312,6 +1308,20 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) + } + + mutex_unlock(&chain->ctrl_mutex); ++} ++ ++static void uvc_ctrl_status_event_work(struct work_struct *work) ++{ ++ struct uvc_device *dev = container_of(work, struct uvc_device, ++ async_ctrl.work); ++ struct uvc_ctrl_work *w = &dev->async_ctrl; ++ int ret; ++ ++ uvc_ctrl_status_event(w->chain, w->ctrl, w->data); ++ ++ /* The barrier is needed to synchronize with uvc_status_stop(). */ ++ if (smp_load_acquire(&dev->flush_status)) ++ return; + + /* Resubmit the URB. */ + w->urb->interval = dev->int_ep->desc.bInterval; +@@ -1321,8 +1331,8 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) + ret); + } + +-bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, +- struct uvc_control *ctrl, const u8 *data) ++bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, ++ struct uvc_control *ctrl, const u8 *data) + { + struct uvc_device *dev = chain->dev; + struct uvc_ctrl_work *w = &dev->async_ctrl; +diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c +index 282f3d2388cc..fe5dfb0deaf6 100644 +--- a/drivers/media/usb/uvc/uvc_driver.c ++++ b/drivers/media/usb/uvc/uvc_driver.c +@@ -219,6 +219,11 @@ static struct uvc_format_desc uvc_fmts[] = { + .guid = UVC_GUID_FORMAT_HEVC, + .fcc = V4L2_PIX_FMT_HEVC, + }, ++ { ++ .name = "H.265", ++ .guid = UVC_GUID_FORMAT_H265, ++ .fcc = V4L2_PIX_FMT_H265, ++ }, + }; + + /* ------------------------------------------------------------------------ +@@ -1121,10 +1126,8 @@ static int uvc_parse_vendor_control(struct uvc_device *dev, + + n; + memcpy(unit->extension.bmControls, &buffer[23+p], 2*n); + +- if (buffer[24+p+2*n] != 0) +- usb_string(udev, buffer[24+p+2*n], unit->name, +- sizeof(unit->name)); +- else ++ if (buffer[24+p+2*n] == 0 || ++ usb_string(udev, buffer[24+p+2*n], unit->name, sizeof(unit->name)) < 0) + sprintf(unit->name, "Extension %u", buffer[3]); + + list_add_tail(&unit->list, &dev->entities); +@@ -1249,15 +1252,15 @@ static int uvc_parse_standard_control(struct uvc_device *dev, + memcpy(term->media.bmTransportModes, &buffer[10+n], p); + } + +- if (buffer[7] != 0) +- usb_string(udev, buffer[7], term->name, +- sizeof(term->name)); +- else if (UVC_ENTITY_TYPE(term) == UVC_ITT_CAMERA) +- sprintf(term->name, "Camera %u", buffer[3]); +- else if (UVC_ENTITY_TYPE(term) == UVC_ITT_MEDIA_TRANSPORT_INPUT) +- sprintf(term->name, "Media %u", buffer[3]); +- else +- sprintf(term->name, "Input %u", buffer[3]); ++ if (buffer[7] == 0 || ++ usb_string(udev, buffer[7], term->name, sizeof(term->name)) < 0) { ++ if (UVC_ENTITY_TYPE(term) == UVC_ITT_CAMERA) ++ sprintf(term->name, "Camera %u", buffer[3]); ++ if (UVC_ENTITY_TYPE(term) == UVC_ITT_MEDIA_TRANSPORT_INPUT) ++ sprintf(term->name, "Media %u", buffer[3]); ++ else ++ sprintf(term->name, "Input %u", buffer[3]); ++ } + + list_add_tail(&term->list, &dev->entities); + break; +@@ -1289,10 +1292,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, + + memcpy(term->baSourceID, &buffer[7], 1); + +- if (buffer[8] != 0) +- usb_string(udev, buffer[8], term->name, +- sizeof(term->name)); +- else ++ if (buffer[8] == 0 || ++ usb_string(udev, buffer[8], term->name, sizeof(term->name)) < 0) + sprintf(term->name, "Output %u", buffer[3]); + + list_add_tail(&term->list, &dev->entities); +@@ -1314,10 +1315,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, + + memcpy(unit->baSourceID, &buffer[5], p); + +- if (buffer[5+p] != 0) +- usb_string(udev, buffer[5+p], unit->name, +- sizeof(unit->name)); +- else ++ if (buffer[5+p] == 0 || ++ usb_string(udev, buffer[5+p], unit->name, sizeof(unit->name)) < 0) + sprintf(unit->name, "Selector %u", buffer[3]); + + list_add_tail(&unit->list, &dev->entities); +@@ -1347,10 +1346,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, + if (dev->uvc_version >= 0x0110) + unit->processing.bmVideoStandards = buffer[9+n]; + +- if (buffer[8+n] != 0) +- usb_string(udev, buffer[8+n], unit->name, +- sizeof(unit->name)); +- else ++ if (buffer[8+n] == 0 || ++ usb_string(udev, buffer[8+n], unit->name, sizeof(unit->name)) < 0) + sprintf(unit->name, "Processing %u", buffer[3]); + + list_add_tail(&unit->list, &dev->entities); +@@ -1378,10 +1375,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, + unit->extension.bmControls = (u8 *)unit + sizeof(*unit); + memcpy(unit->extension.bmControls, &buffer[23+p], n); + +- if (buffer[23+p+n] != 0) +- usb_string(udev, buffer[23+p+n], unit->name, +- sizeof(unit->name)); +- else ++ if (buffer[23+p+n] == 0 || ++ usb_string(udev, buffer[23+p+n], unit->name, sizeof(unit->name)) < 0) + sprintf(unit->name, "Extension %u", buffer[3]); + + list_add_tail(&unit->list, &dev->entities); +@@ -2565,6 +2560,24 @@ static const struct usb_device_id uvc_ids[] = { + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 0, + .driver_info = (kernel_ulong_t)&uvc_quirk_probe_minmax }, ++ /* Logitech, Webcam C910 */ ++ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE ++ | USB_DEVICE_ID_MATCH_INT_INFO, ++ .idVendor = 0x046d, ++ .idProduct = 0x0821, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = 1, ++ .bInterfaceProtocol = 0, ++ .driver_info = UVC_INFO_QUIRK(UVC_QUIRK_WAKE_AUTOSUSPEND)}, ++ /* Logitech, Webcam B910 */ ++ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE ++ | USB_DEVICE_ID_MATCH_INT_INFO, ++ .idVendor = 0x046d, ++ .idProduct = 0x0823, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = 1, ++ .bInterfaceProtocol = 0, ++ .driver_info = UVC_INFO_QUIRK(UVC_QUIRK_WAKE_AUTOSUSPEND)}, + /* Logitech Quickcam Fusion */ + { .match_flags = USB_DEVICE_ID_MATCH_DEVICE + | USB_DEVICE_ID_MATCH_INT_INFO, +diff --git a/drivers/media/usb/uvc/uvc_entity.c b/drivers/media/usb/uvc/uvc_entity.c +index ca3a9c2eec27..7c9895377118 100644 +--- a/drivers/media/usb/uvc/uvc_entity.c ++++ b/drivers/media/usb/uvc/uvc_entity.c +@@ -37,7 +37,7 @@ static int uvc_mc_create_links(struct uvc_video_chain *chain, + continue; + + remote = uvc_entity_by_id(chain->dev, entity->baSourceID[i]); +- if (remote == NULL) ++ if (remote == NULL || remote->num_pads == 0) + return -EINVAL; + + source = (UVC_ENTITY_TYPE(remote) == UVC_TT_STREAMING) +diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c +index 2bdb0ff203f8..73725051cc16 100644 +--- a/drivers/media/usb/uvc/uvc_status.c ++++ b/drivers/media/usb/uvc/uvc_status.c +@@ -6,6 +6,7 @@ + * Laurent Pinchart (laurent.pinchart@ideasonboard.com) + */ + ++#include + #include + #include + #include +@@ -179,7 +180,8 @@ static bool uvc_event_control(struct urb *urb, + + switch (status->bAttribute) { + case UVC_CTRL_VALUE_CHANGE: +- return uvc_ctrl_status_event(urb, chain, ctrl, status->bValue); ++ return uvc_ctrl_status_event_async(urb, chain, ctrl, ++ status->bValue); + + case UVC_CTRL_INFO_CHANGE: + case UVC_CTRL_FAILURE_CHANGE: +@@ -309,5 +311,41 @@ int uvc_status_start(struct uvc_device *dev, gfp_t flags) + + void uvc_status_stop(struct uvc_device *dev) + { ++ struct uvc_ctrl_work *w = &dev->async_ctrl; ++ ++ /* ++ * Prevent the asynchronous control handler from requeing the URB. The ++ * barrier is needed so the flush_status change is visible to other ++ * CPUs running the asynchronous handler before usb_kill_urb() is ++ * called below. ++ */ ++ smp_store_release(&dev->flush_status, true); ++ ++ /* ++ * Cancel any pending asynchronous work. If any status event was queued, ++ * process it synchronously. ++ */ ++ if (cancel_work_sync(&w->work)) ++ uvc_ctrl_status_event(w->chain, w->ctrl, w->data); ++ ++ /* Kill the urb. */ + usb_kill_urb(dev->int_urb); ++ ++ /* ++ * The URB completion handler may have queued asynchronous work. This ++ * won't resubmit the URB as flush_status is set, but it needs to be ++ * cancelled before returning or it could then race with a future ++ * uvc_status_start() call. ++ */ ++ if (cancel_work_sync(&w->work)) ++ uvc_ctrl_status_event(w->chain, w->ctrl, w->data); ++ ++ /* ++ * From this point, there are no events on the queue and the status URB ++ * is dead. No events will be queued until uvc_status_start() is called. ++ * The barrier is needed to make sure that flush_status is visible to ++ * uvc_ctrl_status_event_work() when uvc_status_start() will be called ++ * again. ++ */ ++ smp_store_release(&dev->flush_status, false); + } +diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c +index f6373d678d25..03dfe96bceba 100644 +--- a/drivers/media/usb/uvc/uvc_video.c ++++ b/drivers/media/usb/uvc/uvc_video.c +@@ -1308,7 +1308,9 @@ static void uvc_video_decode_meta(struct uvc_streaming *stream, + if (has_scr) + memcpy(stream->clock.last_scr, scr, 6); + +- memcpy(&meta->length, mem, length); ++ meta->length = mem[0]; ++ meta->flags = mem[1]; ++ memcpy(meta->buf, &mem[2], length - 2); + meta_buf->bytesused += length + sizeof(meta->ns) + sizeof(meta->sof); + + uvc_trace(UVC_TRACE_FRAME, +@@ -1903,6 +1905,17 @@ static int uvc_video_start_transfer(struct uvc_streaming *stream, + uvc_trace(UVC_TRACE_VIDEO, "Selecting alternate setting %u " + "(%u B/frame bandwidth).\n", altsetting, best_psize); + ++ /* ++ * Some devices, namely the Logitech C910 and B910, are unable ++ * to recover from a USB autosuspend, unless the alternate ++ * setting of the streaming interface is toggled. ++ */ ++ if (stream->dev->quirks & UVC_QUIRK_WAKE_AUTOSUSPEND) { ++ usb_set_interface(stream->dev->udev, intfnum, ++ altsetting); ++ usb_set_interface(stream->dev->udev, intfnum, 0); ++ } ++ + ret = usb_set_interface(stream->dev->udev, intfnum, altsetting); + if (ret < 0) + return ret; +diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h +index c884020b2878..47768c5353ff 100644 +--- a/drivers/media/usb/uvc/uvcvideo.h ++++ b/drivers/media/usb/uvc/uvcvideo.h +@@ -169,6 +169,9 @@ + { 'H', 'E', 'V', 'C', 0x00, 0x00, 0x10, 0x00, \ + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} + ++#define UVC_GUID_FORMAT_H265 \ ++ { 'H', '2', '6', '5', 0x00, 0x00, 0x10, 0x00, \ ++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71} + + /* ------------------------------------------------------------------------ + * Driver specific constants. +@@ -203,6 +206,7 @@ + #define UVC_QUIRK_RESTORE_CTRLS_ON_INIT 0x00000400 + #define UVC_QUIRK_FORCE_Y8 0x00000800 + #define UVC_QUIRK_FORCE_BPP 0x00001000 ++#define UVC_QUIRK_WAKE_AUTOSUSPEND 0x00002000 + + /* Format flags */ + #define UVC_FMT_FLAG_COMPRESSED 0x00000001 +@@ -669,6 +673,7 @@ struct uvc_device { + /* Status Interrupt Endpoint */ + struct usb_host_endpoint *int_ep; + struct urb *int_urb; ++ bool flush_status; + u8 *status; + struct input_dev *input; + char input_phys[64]; +@@ -838,7 +843,9 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, + int uvc_ctrl_init_device(struct uvc_device *dev); + void uvc_ctrl_cleanup_device(struct uvc_device *dev); + int uvc_ctrl_restore_values(struct uvc_device *dev); +-bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, ++bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, ++ struct uvc_control *ctrl, const u8 *data); ++void uvc_ctrl_status_event(struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data); + + int uvc_ctrl_begin(struct uvc_video_chain *chain); +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index ce8f1c0583d5..b037aa6110e2 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -211,6 +211,7 @@ obj-$(CONFIG_MFD_AT91_USART) += at91-usart.o + obj-$(CONFIG_MFD_ATMEL_FLEXCOM) += atmel-flexcom.o + obj-$(CONFIG_MFD_ATMEL_HLCDC) += atmel-hlcdc.o + obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o ++obj-$(CONFIG_MFD_BSP_FMC) += bsp_fmc.o + obj-$(CONFIG_MFD_INTEL_LPSS) += intel-lpss.o + obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o + obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o +diff --git a/drivers/mfd/bsp_fmc.c b/drivers/mfd/bsp_fmc.c +new file mode 100644 +index 000000000000..e56b341f19fc +--- /dev/null ++++ b/drivers/mfd/bsp_fmc.c +@@ -0,0 +1,134 @@ ++/* Vendor Flash Memory Controller Driver ++ * ++ * Copyright (c) 2016 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++unsigned char fmc_cs_user[FMC_MAX_CHIP_NUM]; ++ ++DEFINE_MUTEX(fmc_switch_mutex); ++EXPORT_SYMBOL_GPL(fmc_switch_mutex); ++ ++/* ------------------------------------------------------------------------ */ ++static const struct mfd_cell bsp_fmc_devs[] = { ++ { ++ .name = "bsp_spi_nor", ++ .of_compatible = "vendor,fmc-spi-nor", ++ }, ++ { ++ .name = "bsp_spi_nand", ++ .of_compatible = "vendor,fmc-spi-nand", ++ }, ++ { ++ .name = "bsp_nand", ++ .of_compatible = "vendor,fmc-nand", ++ }, ++}; ++ ++static int bsp_fmc_probe(struct platform_device *pdev) ++{ ++ struct bsp_fmc *fmc = NULL; ++ struct resource *res = NULL; ++ struct device *dev = &pdev->dev; ++ int ret; ++ ++ fmc = devm_kzalloc(dev, sizeof(*fmc), GFP_KERNEL); ++ if (!fmc) ++ return -ENOMEM; ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); ++ fmc->regbase = devm_ioremap_resource(dev, res); ++ if (IS_ERR(fmc->regbase)) ++ return PTR_ERR(fmc->regbase); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory"); ++ fmc->iobase = devm_ioremap_resource(dev, res); ++ if (IS_ERR(fmc->iobase)) ++ return PTR_ERR(fmc->iobase); ++ ++ fmc->clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(fmc->clk)) ++ return PTR_ERR(fmc->clk); ++ ++ if (of_property_read_u32(dev->of_node, "max-dma-size", &fmc->dma_len)) { ++ dev_err(dev, "Please set the suitable max-dma-size value !!!\n"); ++ return -ENOMEM; ++ } ++ ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); ++ if (ret) { ++ dev_warn(dev, "Unable to set dma mask\n"); ++ return ret; ++ } ++ ++ fmc->buffer = dmam_alloc_coherent(dev, fmc->dma_len, ++ &fmc->dma_buffer, GFP_KERNEL); ++ if (IS_ERR(fmc->buffer)) ++ return PTR_ERR(fmc->buffer); ++ ++ mutex_init(&fmc->lock); ++ ++ platform_set_drvdata(pdev, fmc); ++ ++ ret = mfd_add_devices(dev, 0, bsp_fmc_devs, ++ ARRAY_SIZE(bsp_fmc_devs), NULL, 0, NULL); ++ if (ret) { ++ dev_err(dev, "add mfd devices failed: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int bsp_fmc_remove(struct platform_device *pdev) ++{ ++ struct bsp_fmc *fmc = platform_get_drvdata(pdev); ++ ++ dmam_free_coherent(&pdev->dev, fmc->dma_len, ++ fmc->buffer, fmc->dma_buffer); ++ mfd_remove_devices(&pdev->dev); ++ mutex_destroy(&fmc->lock); ++ ++ return 0; ++} ++ ++static const struct of_device_id bsp_fmc_of_match_tbl[] = { ++ {.compatible = "vendor,fmc"}, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, bsp_fmc_of_match_tbl); ++ ++static struct platform_driver bsp_fmc_driver = { ++ .driver = { ++ .name = "fmc", ++ .of_match_table = bsp_fmc_of_match_tbl, ++ }, ++ .probe = bsp_fmc_probe, ++ .remove = bsp_fmc_remove, ++}; ++module_platform_driver(bsp_fmc_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("Flash Memory Controller Driver"); +diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c +index 8f2465394253..0d861bbf3b75 100644 +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -1352,6 +1352,7 @@ void mmc_power_up(struct mmc_host *host, u32 ocr) + */ + mmc_delay(host->ios.power_delay_ms); + } ++EXPORT_SYMBOL(mmc_power_up); + + void mmc_power_off(struct mmc_host *host) + { +@@ -1374,9 +1375,13 @@ void mmc_power_off(struct mmc_host *host) + */ + mmc_delay(1); + } ++EXPORT_SYMBOL(mmc_power_off); + + void mmc_power_cycle(struct mmc_host *host, u32 ocr) + { ++ if (host->type == MMC_HOST_TYPE_MMC) ++ return; ++ + mmc_power_off(host); + /* Wait at least 1 ms according to SD spec */ + mmc_delay(1); +@@ -2248,6 +2253,17 @@ int mmc_detect_card_removed(struct mmc_host *host) + } + EXPORT_SYMBOL(mmc_detect_card_removed); + ++static int __read_mostly g_wifi1102a = 0; ++ ++static int __init wifi1102a_setup(char *str) ++{ ++ if (!strcasecmp(str, "enable") ) ++ g_wifi1102a = 1; ++ ++ return 0; ++} ++__setup("wifi1102a=", wifi1102a_setup); ++ + void mmc_rescan(struct work_struct *work) + { + struct mmc_host *host = +@@ -2257,9 +2273,11 @@ void mmc_rescan(struct work_struct *work) + if (host->rescan_disable) + return; + +- /* If there is a non-removable card registered, only scan once */ +- if (!mmc_card_is_removable(host) && host->rescan_entered) +- return; ++ if (!g_wifi1102a) ++ /* If there is a non-removable card registered, only scan once */ ++ if (!mmc_card_is_removable(host) && host->rescan_entered) ++ return; ++ + host->rescan_entered = 1; + + if (host->trigger_card_event && host->ops->card_event) { +@@ -2297,9 +2315,12 @@ void mmc_rescan(struct work_struct *work) + mmc_bus_put(host); + + mmc_claim_host(host); ++ host->card_status = MMC_CARD_UNINIT; + if (mmc_card_is_removable(host) && host->ops->get_cd && + host->ops->get_cd(host) == 0) { + mmc_power_off(host); ++ if (host->ops->card_info_save) ++ host->ops->card_info_save(host); + mmc_release_host(host); + goto out; + } +@@ -2311,8 +2332,16 @@ void mmc_rescan(struct work_struct *work) + continue; + freq = host->f_max; + } +- if (!mmc_rescan_try_freq(host, max(freq, host->f_min))) ++ if (!mmc_rescan_try_freq(host, max(freq, host->f_min))) { ++ host->card_status = MMC_CARD_INIT; ++ if (host->ops->card_info_save) ++ host->ops->card_info_save(host); + break; ++ } else if ((i == (ARRAY_SIZE(freqs) - 1)) || ++ (freqs[i] <= host->f_min)) { ++ host->card_status = MMC_CARD_INIT_FAIL; ++ } ++ + if (freqs[i] <= host->f_min) + break; + } +diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c +index 87807ef010a9..bca036b15064 100644 +--- a/drivers/mmc/core/mmc.c ++++ b/drivers/mmc/core/mmc.c +@@ -1418,6 +1418,9 @@ static int mmc_select_hs400es(struct mmc_card *card) + + /* Set host controller to HS400 timing and frequency */ + mmc_set_timing(host, MMC_TIMING_MMC_HS400); ++#if defined(CONFIG_MMC_SDHCI_BSP) || (defined(MODULE) && defined(CONFIG_MMC_SDHCI_BSP_MODULE)) ++ mmc_set_bus_speed(card); ++#endif + + /* Controller enable enhanced strobe function */ + host->ios.enhanced_strobe = true; +@@ -1527,7 +1530,8 @@ static int mmc_select_timing(struct mmc_card *card) + if (!mmc_can_ext_csd(card)) + goto bus_speed; + +- if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES) ++ if ((card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS400ES) && ++ (card->host->caps & MMC_CAP_8_BIT_DATA)) + err = mmc_select_hs400es(card); + else if (card->mmc_avail_type & EXT_CSD_CARD_TYPE_HS200) + err = mmc_select_hs200(card); +@@ -2254,6 +2258,7 @@ int mmc_attach_mmc(struct mmc_host *host) + if (err) + return err; + ++ host->type = MMC_HOST_TYPE_MMC; + mmc_attach_bus(host, &mmc_ops); + if (host->ocr_avail_mmc) + host->ocr_avail = host->ocr_avail_mmc; +diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c +index 868b121ce4f3..0b2e4208c92f 100644 +--- a/drivers/mmc/core/sd.c ++++ b/drivers/mmc/core/sd.c +@@ -1340,6 +1340,7 @@ int mmc_attach_sd(struct mmc_host *host) + if (err) + return err; + ++ host->type = MMC_HOST_TYPE_SD; + mmc_attach_bus(host, &mmc_sd_ops); + if (host->ocr_avail_sd) + host->ocr_avail = host->ocr_avail_sd; +diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c +index 99a4ce68d82f..438a12197b1d 100644 +--- a/drivers/mmc/core/sdio.c ++++ b/drivers/mmc/core/sdio.c +@@ -27,6 +27,10 @@ + #include "sdio_ops.h" + #include "sdio_cis.h" + ++#ifdef CONFIG_ARCH_BSP ++#include "host.h" ++#endif ++ + MMC_DEV_ATTR(vendor, "0x%04x\n", card->cis.vendor); + MMC_DEV_ATTR(device, "0x%04x\n", card->cis.device); + MMC_DEV_ATTR(revision, "%u.%u\n", card->major_rev, card->minor_rev); +@@ -893,7 +897,7 @@ static int mmc_sdio_init_card(struct mmc_host *host, u32 ocr, + return err; + } + +-static int mmc_sdio_reinit_card(struct mmc_host *host) ++int mmc_sdio_reinit_card(struct mmc_host *host) + { + int ret; + +@@ -903,7 +907,7 @@ static int mmc_sdio_reinit_card(struct mmc_host *host) + + return mmc_sdio_init_card(host, host->card->ocr, host->card); + } +- ++EXPORT_SYMBOL(mmc_sdio_reinit_card); + /* + * Host is being removed. Free up the current card. + */ +@@ -1195,6 +1199,7 @@ int mmc_attach_sdio(struct mmc_host *host) + if (err) + return err; + ++ host->type = MMC_HOST_TYPE_SDIO; + mmc_attach_bus(host, &mmc_sdio_ops); + if (host->ocr_avail_sdio) + host->ocr_avail = host->ocr_avail_sdio; +@@ -1308,3 +1313,40 @@ int mmc_attach_sdio(struct mmc_host *host) + return err; + } + ++#ifdef CONFIG_ARCH_BSP ++/* sdio_reset_comm has been fixed in latest kernel/msm.git for Linux ++ * 2.6.27. The implementation prior to that buggy, and needs broadcom's ++ * patch for it*/ ++int sdio_reset_comm(struct mmc_card *card) ++{ ++ struct mmc_host *host = card->host; ++ u32 ocr; ++ u32 rocr; ++ int err; ++ ++ mmc_claim_host(host); ++ mmc_retune_disable(host); ++ mmc_go_idle(host); ++ mmc_set_clock(host, host->f_min); ++ err = mmc_send_io_op_cond(host, 0, &ocr); ++ if (err) ++ goto err; ++ rocr = mmc_select_voltage(host, ocr); ++ if (!rocr) { ++ err = -EINVAL; ++ goto err; ++ } ++ err = mmc_sdio_init_card(host, rocr, card); ++ if (err) ++ goto err; ++ mmc_release_host(host); ++ return 0; ++err: ++ printk("%s: Error resetting SDIO communications: %d\n", ++ mmc_hostname(host), err); ++ mmc_release_host(host); ++ return err; ++} ++EXPORT_SYMBOL(sdio_reset_comm); ++#endif ++ +diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig +index 82e1fbd6b2ff..9a0e6045326d 100644 +--- a/drivers/mmc/host/Kconfig ++++ b/drivers/mmc/host/Kconfig +@@ -1102,3 +1102,10 @@ config MMC_OWL + + config MMC_SDHCI_EXTERNAL_DMA + bool ++ ++config MMC_SDHCI_SS928V100 ++ tristate "SDHCI MMC Driver For SS928V100" ++ default y ++ help ++ Only for ss928v100 board ++ +diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile +index 451c25fc2c69..444a57ddac64 100644 +--- a/drivers/mmc/host/Makefile ++++ b/drivers/mmc/host/Makefile +@@ -106,6 +106,8 @@ obj-$(CONFIG_MMC_SDHCI_SPRD) += sdhci-sprd.o + obj-$(CONFIG_MMC_CQHCI) += cqhci.o + obj-$(CONFIG_MMC_HSQ) += mmc_hsq.o + ++obj-$(CONFIG_MMC_SDHCI_SS928V100) += sdhci-bsp.o mci_proc.o sdhci-ss928v100.o ++ + ifeq ($(CONFIG_CB710_DEBUG),y) + CFLAGS-cb710-mmc += -DDEBUG + endif +diff --git a/drivers/mmc/host/bsp_quirk_ids.h b/drivers/mmc/host/bsp_quirk_ids.h +new file mode 100644 +index 000000000000..5846dee0891d +--- /dev/null ++++ b/drivers/mmc/host/bsp_quirk_ids.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (c) Shenshu Technologies Co., Ltd. 2022. All rights reserved. ++ * Description: bsp cmdq quirk header ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _DRIVERS_MMC_BSP_QUIRK_IDS_H ++#define _DRIVERS_MMC_BSP_QUIRK_IDS_H ++ ++#define MMC_CMDQ_FORCE_OFF 0x1 ++#define MMC_CMDQ_DIS_WHITELIST 0x2 ++ ++#ifdef CONFIG_MMC_CQHCI ++#include "../core/quirks.h" ++#include "../core/card.h" ++ ++#define CID_MANFID_SANDISK_F 0x45 ++/* ++ * Quirk cmdq for MMC products. ++ */ ++static inline void __maybe_unused bsp_cmdq_quirk_mmc(struct mmc_card *card, int data) ++{ ++ struct mmc_host *host = card->host; ++ ++ if (host != NULL) { ++ host->caps2 |= (MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); ++ pr_debug("Whitelist: match device %s\n", card->cid.prod_name); ++ } ++} ++ ++static const struct mmc_fixup mmc_cmdq_whitelist[] = { ++ /* Toshiba */ ++ MMC_FIXUP("008GB0", CID_MANFID_TOSHIBA, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("016G30", CID_MANFID_TOSHIBA, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("016GB0", CID_MANFID_TOSHIBA, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("008G30", CID_MANFID_TOSHIBA, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ /* Samsung */ ++ MMC_FIXUP("BJTD4R", CID_MANFID_SAMSUNG, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("CKTA42", CID_MANFID_SAMSUNG, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("8GTF4R", CID_MANFID_SAMSUNG, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("AJTD4R", CID_MANFID_SAMSUNG, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ /* Sandisk */ ++ MMC_FIXUP("DF4032", CID_MANFID_SANDISK_F, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("DG4016", CID_MANFID_SANDISK_F, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("DF4128", CID_MANFID_SANDISK_F, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ MMC_FIXUP("DG4008", CID_MANFID_SANDISK_F, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ /* Kingston */ ++ MMC_FIXUP("TB2816", CID_MANFID_KINGSTON, CID_OEMID_ANY, bsp_cmdq_quirk_mmc, 0), ++ /* null, no remove */ ++ END_FIXUP ++}; ++ ++#endif /* CONFIG_MMC_CQHCI*/ ++ ++#endif /* _DRIVERS_MMC_BSP_QUIRK_IDS_H */ +diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c +index 7ba4f714106f..edb66c70cf94 100644 +--- a/drivers/mmc/host/cqhci.c ++++ b/drivers/mmc/host/cqhci.c +@@ -46,6 +46,11 @@ static inline u8 *get_link_desc(struct cqhci_host *cq_host, u8 tag) + + static inline dma_addr_t get_trans_desc_dma(struct cqhci_host *cq_host, u8 tag) + { ++ if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT) ++ return cq_host->trans_desc_dma_base + ++ (cq_host->mmc->max_segs * tag * 2 * /* 2 is double segs size */ ++ cq_host->trans_desc_len); ++ + return cq_host->trans_desc_dma_base + + (cq_host->mmc->max_segs * tag * + cq_host->trans_desc_len); +@@ -53,6 +58,11 @@ static inline dma_addr_t get_trans_desc_dma(struct cqhci_host *cq_host, u8 tag) + + static inline u8 *get_trans_desc(struct cqhci_host *cq_host, u8 tag) + { ++ if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT) ++ return cq_host->trans_desc_base + ++ (cq_host->trans_desc_len * ++ cq_host->mmc->max_segs * 2 * tag); /* 2 is double trans desc size */ ++ + return cq_host->trans_desc_base + + (cq_host->trans_desc_len * cq_host->mmc->max_segs * tag); + } +@@ -193,8 +203,12 @@ static int cqhci_host_alloc_tdl(struct cqhci_host *cq_host) + + cq_host->desc_size = cq_host->slot_sz * cq_host->num_slots; + +- cq_host->data_size = cq_host->trans_desc_len * cq_host->mmc->max_segs * +- cq_host->mmc->cqe_qdepth; ++ if (cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT) ++ cq_host->data_size = cq_host->trans_desc_len * ++ cq_host->mmc->max_segs * 2 * cq_host->mmc->cqe_qdepth; /* 2 is double seg size */ ++ else ++ cq_host->data_size = cq_host->trans_desc_len * ++ cq_host->mmc->max_segs * cq_host->mmc->cqe_qdepth; + + pr_debug("%s: cqhci: desc_size: %zu data_sz: %zu slot-sz: %d\n", + mmc_hostname(cq_host->mmc), cq_host->desc_size, cq_host->data_size, +@@ -267,17 +281,14 @@ static void __cqhci_enable(struct cqhci_host *cq_host) + + cqhci_writel(cq_host, cq_host->rca, CQHCI_SSC2); + ++ cqhci_writel(cq_host, SEND_QSR_INTERVAL, CQHCI_SSC1); ++ + cqhci_set_irqs(cq_host, 0); + + cqcfg |= CQHCI_ENABLE; + + cqhci_writel(cq_host, cqcfg, CQHCI_CFG); + +- if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) +- cqhci_writel(cq_host, 0, CQHCI_CTL); +- +- mmc->cqe_on = true; +- + if (cq_host->ops->enable) + cq_host->ops->enable(mmc); + +@@ -297,8 +308,6 @@ static void __cqhci_disable(struct cqhci_host *cq_host) + cqcfg &= ~CQHCI_ENABLE; + cqhci_writel(cq_host, cqcfg, CQHCI_CFG); + +- cq_host->mmc->cqe_on = false; +- + cq_host->activated = false; + } + +@@ -383,6 +392,8 @@ static void cqhci_off(struct mmc_host *mmc) + cq_host->ops->post_disable(mmc); + + mmc->cqe_on = false; ++ ++ cqhci_deactivate(mmc); + } + + static void cqhci_disable(struct mmc_host *mmc) +@@ -452,7 +463,7 @@ static int cqhci_dma_map(struct mmc_host *host, struct mmc_request *mrq) + return sg_count; + } + +-static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, ++static void _cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, + bool dma64) + { + __le32 *attr = (__le32 __force *)desc; +@@ -474,6 +485,27 @@ static void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end, + } + } + ++static void cqhci_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, ++ dma_addr_t addr, int len, bool end, bool dma64, unsigned int blksz) ++{ ++ int desc_len; ++ ++ if ((cq_host->quirks & CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT) && ++ ((addr % SYNOPSYS_DMA_LIMIT + len) > SYNOPSYS_DMA_LIMIT)) { ++ if ((addr + (unsigned int)len) % SYNOPSYS_DMA_LIMIT < blksz) ++ BUG_ON(1); ++ ++ desc_len = (SYNOPSYS_DMA_LIMIT - addr % SYNOPSYS_DMA_LIMIT); ++ _cqhci_set_tran_desc(*desc, addr, desc_len, false, dma64); ++ ++ *desc = *desc + cq_host->trans_desc_len; ++ len -= desc_len; ++ addr += desc_len; ++ } ++ ++ _cqhci_set_tran_desc(*desc, addr, len, end, dma64); ++} ++ + static int cqhci_prep_tran_desc(struct mmc_request *mrq, + struct cqhci_host *cq_host, int tag) + { +@@ -500,7 +532,7 @@ static int cqhci_prep_tran_desc(struct mmc_request *mrq, + + if ((i+1) == sg_count) + end = true; +- cqhci_set_tran_desc(desc, addr, len, end, dma64); ++ cqhci_set_tran_desc(cq_host, &desc, addr, len, end, dma64, data->blksz); + desc += cq_host->trans_desc_len; + } + +@@ -888,7 +920,6 @@ static bool cqhci_clear_all_tasks(struct mmc_host *mmc, unsigned int timeout) + cqhci_set_irqs(cq_host, 0); + + ret = cqhci_tasks_cleared(cq_host); +- + if (!ret) + pr_debug("%s: cqhci: Failed to clear tasks\n", + mmc_hostname(mmc)); +@@ -951,6 +982,9 @@ static void cqhci_recovery_start(struct mmc_host *mmc) + cq_host->ops->disable(mmc, true); + + mmc->cqe_on = false; ++ ++ cqhci_deactivate(mmc); ++ + } + + static int cqhci_error_from_flags(unsigned int flags) +diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h +index 89bf6adbce8c..05571faf079a 100644 +--- a/drivers/mmc/host/cqhci.h ++++ b/drivers/mmc/host/cqhci.h +@@ -80,6 +80,12 @@ + + /* send status config 1 */ + #define CQHCI_SSC1 0x40 ++/* ++ * Value n means CQE would send CMD13 during the transfer of data block ++ * BLOCK_CNT-n ++ */ ++#define SEND_QSR_INTERVAL 0x70001 ++ + #define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) + + /* send status config 2 */ +@@ -138,6 +144,7 @@ + #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32) + #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0) + ++#define SYNOPSYS_DMA_LIMIT 0x8000000 + struct cqhci_host_ops; + struct mmc_host; + struct mmc_request; +@@ -164,6 +171,7 @@ struct cqhci_host { + + u32 quirks; + #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1 ++#define CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT 0x2 + + bool enabled; + bool halted; +diff --git a/drivers/mmc/host/mci_proc.c b/drivers/mmc/host/mci_proc.c +new file mode 100644 +index 000000000000..1ce672c9817f +--- /dev/null ++++ b/drivers/mmc/host/mci_proc.c +@@ -0,0 +1,338 @@ ++/* ++ * Copyright (c) 2016 Shenshu Technologies Co., Ltd. ++ * Description: mci driver ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include "mci_proc.h" ++#include "sdhci.h" ++#include "../core/card.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MCI_PARENT "mci" ++#define MCI_STATS_PROC "mci_info" ++#define MAX_CLOCK_SCALE 4 ++ ++static struct proc_dir_entry *proc_mci_dir; ++static struct mmc_host *mci_host[MCI_SLOT_NUM] = {NULL}; ++ ++struct mmc_host *mci_get_proc_host(unsigned int index) ++{ ++ if (index < MCI_SLOT_NUM) ++ return mci_host[index]; ++ else ++ return NULL; ++} ++ ++void mci_insert_proc_host(struct mmc_host *host) ++{ ++ static unsigned int slot_index; ++ if (slot_index >= MCI_SLOT_NUM) { ++ return; ++ } ++ ++ mci_host[slot_index] = host; ++ slot_index++; ++} ++ ++#define BIT_WIDTH 32 ++static unsigned int unstuff_bits(const u32 *resp, u32 start, u32 size) ++{ ++ const u32 mask = ((size < BIT_WIDTH) ? 1 << size : 0) - 1; ++ const int off = 0x3 - ((start) / BIT_WIDTH); ++ const int shft = (start) & 31; /* max shift value 31 */ ++ u32 res; ++ ++ res = resp[off] >> shft; ++ if (size + shft > BIT_WIDTH) ++ res |= resp[off - 1] << ((BIT_WIDTH - shft) % BIT_WIDTH); ++ res = res & mask; ++ ++ return res; ++} ++ ++static const char *mci_get_card_type(unsigned int sd_type) ++{ ++ const char *card_type[MAX_CARD_TYPE + 1] = { ++ "MMC card", ++ "SD card", ++ "SDIO card", ++ "SD combo (IO+mem) card", ++ "unknown" ++ }; ++ ++ if (sd_type >= MAX_CARD_TYPE) ++ return card_type[MAX_CARD_TYPE]; ++ else ++ return card_type[sd_type]; ++} ++ ++static const char *mci_get_uhs_speeds(unsigned int sd_bus_speed) ++{ ++ const char *uhs_speeds[] = { ++ [UHS_SDR12_BUS_SPEED] = "SDR12 ", ++ [UHS_SDR25_BUS_SPEED] = "SDR25 ", ++ [UHS_SDR50_BUS_SPEED] = "SDR50 ", ++ [UHS_SDR104_BUS_SPEED] = "SDR104 ", ++ [UHS_DDR50_BUS_SPEED] = "DDR50 ", ++ }; ++ ++ if (sd_bus_speed >= ARRAY_SIZE(uhs_speeds)) ++ return NULL; ++ else ++ return uhs_speeds[sd_bus_speed]; ++} ++ ++static unsigned int mci_get_uhs_speeds_size(void) ++{ ++ const char *uhs_speeds[] = { ++ [UHS_SDR12_BUS_SPEED] = "SDR12 ", ++ [UHS_SDR25_BUS_SPEED] = "SDR25 ", ++ [UHS_SDR50_BUS_SPEED] = "SDR50 ", ++ [UHS_SDR104_BUS_SPEED] = "SDR104 ", ++ [UHS_DDR50_BUS_SPEED] = "DDR50 ", ++ }; ++ ++ return (unsigned int)ARRAY_SIZE(uhs_speeds); ++} ++ ++static const char *mci_get_clock_unit(unsigned int clock_scale) ++{ ++ const char *clock_unit[MAX_CLOCK_SCALE] = { ++ "Hz", ++ "KHz", ++ "MHz", ++ "GHz" ++ }; ++ ++ if (clock_scale >= MAX_CLOCK_SCALE) ++ return NULL; ++ else ++ return clock_unit[clock_scale]; ++} ++ ++static unsigned int analyze_clock_scale(unsigned int clock, ++ unsigned int *clock_val) ++{ ++ unsigned int scale = 0; ++ unsigned int tmp = clock; ++ ++ while (1) { ++ tmp = tmp / 1000; /* Cal freq by dividing 1000 */ ++ if (tmp > 0) { ++ *clock_val = tmp; ++ scale++; ++ } else { ++ break; ++ } ++ } ++ return scale; ++} ++ ++static inline int is_card_uhs(unsigned char timing) ++{ ++ return timing >= MMC_TIMING_UHS_SDR12 && ++ timing <= MMC_TIMING_UHS_DDR50; ++}; ++ ++static inline int is_card_hs(unsigned char timing) ++{ ++ return timing == MMC_TIMING_SD_HS || timing == MMC_TIMING_MMC_HS; ++}; ++ ++static void mci_stats_printout(struct seq_file *s, unsigned int index_mci) ++{ ++ unsigned int clock_scale, clock_value = 0; ++ unsigned int speed_class, grade_speed_uhs; ++ struct mmc_host *mmc = mci_get_proc_host(index_mci); ++ struct sdhci_host *host = (struct sdhci_host *)mmc_priv(mmc); ++ struct card_info *info = &(host->c_info); ++ ++ seq_printf(s, "\tType: %s", mci_get_card_type(info->card_type)); ++ ++ if (info->card_state & MMC_STATE_BLOCKADDR) ++ seq_printf(s, "(%s)\n", (info->card_state & MMC_CARD_SDXC) ? ++ "SDXC" : "SDHC"); ++ ++ seq_printf(s, "\tMode: %s", ++ is_card_uhs(info->timing) ? "UHS" : ++ is_card_hs(info->timing) ? "HS" : ++ (info->enhanced_strobe == true) ? "HS400ES" : ++ (info->timing == MMC_TIMING_MMC_HS400) ? "HS400" : ++ (info->timing == MMC_TIMING_MMC_HS200) ? "HS200" : ++ (info->timing == MMC_TIMING_MMC_DDR52) ? "DDR" : "DS"); ++ if (is_card_uhs(info->timing) && ++ info->sd_bus_speed < mci_get_uhs_speeds_size()) ++ seq_printf(s, " %s\n", mci_get_uhs_speeds(info->sd_bus_speed)); ++ else ++ seq_printf(s, "\n"); ++ ++ speed_class = unstuff_bits(info->ssr, 56, 8); /* 56 = 440 - 384 */ ++ grade_speed_uhs = unstuff_bits(info->ssr, 12, 4); /* 12 = 396 - 384 */ ++ seq_printf(s, "\tSpeed Class: Class %s\n", ++ (speed_class == 0x00) ? "0" : ++ (speed_class == 0x01) ? "2" : ++ (speed_class == 0x02) ? "4" : ++ (speed_class == 0x03) ? "6" : ++ (speed_class == 0x04) ? "10" : "Reserved"); ++ ++ seq_printf(s, "\tUhs Speed Grade: %s\n", ++ (grade_speed_uhs == 0x00) ? ++ "Less than 10MB/sec(0h)" : ++ (grade_speed_uhs == 0x01) ? ++ "10MB/sec and above(1h)" : "Reserved"); ++ ++ clock_scale = analyze_clock_scale(info->card_support_clock, &clock_value); ++ seq_printf(s, "\tHost work clock: %d%s\n", ++ clock_value, mci_get_clock_unit(clock_scale)); ++ ++ clock_scale = analyze_clock_scale(info->card_support_clock, &clock_value); ++ seq_printf(s, "\tCard support clock: %d%s\n", ++ clock_value, mci_get_clock_unit(clock_scale)); ++ ++ clock_scale = analyze_clock_scale(mmc->actual_clock, &clock_value); ++ seq_printf(s, "\tCard work clock: %d%s\n", ++ clock_value, mci_get_clock_unit(clock_scale)); ++ /* add card read/write error count */ ++ seq_printf(s, "\tCard error count: %d\n", host->error_count); ++} ++ ++static void mci_stats_seq_printout(struct seq_file *s) ++{ ++ unsigned int index_mci; ++ struct mmc_host *mmc = NULL; ++ ++ struct sdhci_host *host = NULL; ++ ++ for (index_mci = 0; index_mci < MCI_SLOT_NUM; index_mci++) { ++ mmc = mci_get_proc_host(index_mci); ++ if (mmc == NULL) { ++ seq_printf(s, "MCI%d: invalid\n", index_mci); ++ continue; ++ } else { ++ seq_printf(s, "MCI%d", index_mci); ++ } ++ ++ host = mmc_priv(mmc); ++ if (host->mmc->ops->get_cd(host->mmc)) ++ seq_puts(s, ": pluged"); ++ else ++ seq_puts(s, ": unplugged"); ++ ++ if (host->c_info.card_connect != CARD_CONNECT) { ++ if (mmc->card_status == MMC_CARD_INIT_FAIL) ++ seq_puts(s, "_init_failed\n"); ++ else ++ seq_puts(s, "_disconnected\n"); ++ } else { ++ seq_puts(s, "_connected\n"); ++ mci_stats_printout(s, index_mci); ++ } ++ } ++} ++ ++/* proc interface setup */ ++static void *mci_seq_start(struct seq_file *s, loff_t *pos) ++{ ++ /* counter is used to tracking multi proc interfaces ++ * We have only one interface so return zero ++ * pointer to start the sequence. ++ */ ++ static unsigned long counter; ++ ++ if (*pos == 0) ++ return &counter; ++ ++ return NULL; ++} ++ ++/* proc interface next */ ++static void *mci_seq_next(struct seq_file *s, void *v, loff_t *pos) ++{ ++ (*pos)++; ++ ++ return mci_seq_start(s, pos); ++} ++ ++/* define parameters where showed in proc file */ ++static int mci_stats_seq_show(struct seq_file *s, void *v) ++{ ++ mci_stats_seq_printout(s); ++ return 0; ++} ++ ++/* proc interface stop */ ++static void mci_seq_stop(struct seq_file *s, void *v) ++{ ++} ++ ++/* proc interface operation */ ++static const struct seq_operations mci_stats_seq_ops = { ++ .start = mci_seq_start, ++ .next = mci_seq_next, ++ .stop = mci_seq_stop, ++ .show = mci_stats_seq_show ++}; ++ ++/* proc file open */ ++static int mci_stats_proc_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &mci_stats_seq_ops); ++}; ++ ++static const struct proc_ops mci_stats_proc_ops = { ++ .proc_open = mci_stats_proc_open, ++ .proc_read = seq_read, ++ .proc_release = seq_release ++}; ++ ++int mci_proc_init(void) ++{ ++ struct proc_dir_entry *proc_stats_entry = NULL; ++ ++ proc_mci_dir = proc_mkdir(MCI_PARENT, NULL); ++ if (proc_mci_dir == NULL) { ++ pr_err("%s: failed to create proc file %s\n", ++ __func__, MCI_PARENT); ++ return 1; ++ } ++ ++ proc_stats_entry = proc_create(MCI_STATS_PROC, ++ 0, proc_mci_dir, &mci_stats_proc_ops); ++ if (proc_stats_entry == NULL) { ++ pr_err("%s: failed to create proc file %s\n", ++ __func__, MCI_STATS_PROC); ++ return 1; ++ } ++ ++ return 0; ++} ++ ++int mci_proc_shutdown(void) ++{ ++ if (proc_mci_dir != NULL) { ++ remove_proc_entry(MCI_STATS_PROC, proc_mci_dir); ++ remove_proc_entry(MCI_PARENT, NULL); ++ proc_mci_dir = NULL; ++ } ++ ++ return 0; ++} +diff --git a/drivers/mmc/host/mci_proc.h b/drivers/mmc/host/mci_proc.h +new file mode 100644 +index 000000000000..637be3c39b45 +--- /dev/null ++++ b/drivers/mmc/host/mci_proc.h +@@ -0,0 +1,41 @@ ++/* ++ * Copyright (c) 2016 Shenshu Technologies Co., Ltd. ++ * Description: mci header ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++/* ++ * MCI connection table manager ++ */ ++#ifndef __MCI_PROC_H__ ++#define __MCI_PROC_H__ ++ ++#include ++ ++#define MAX_CARD_TYPE 4 ++#define MAX_SPEED_MODE 5 ++ ++#if defined(CONFIG_ARCH_SS928V100) ++#define MCI_SLOT_NUM 3 ++#else ++#error MCI_SLOT_NUM should not be zero! ++#endif ++ ++struct mmc_host *mci_get_proc_host(unsigned int index); ++void mci_insert_proc_host(struct mmc_host *host); ++int mci_proc_init(void); ++int mci_proc_shutdown(void); ++ ++#endif /* __MCI_PROC_H__ */ +diff --git a/drivers/mmc/host/sdhci-bsp.c b/drivers/mmc/host/sdhci-bsp.c +new file mode 100644 +index 000000000000..f86c915ca272 +--- /dev/null ++++ b/drivers/mmc/host/sdhci-bsp.c +@@ -0,0 +1,950 @@ ++/* ++ * Copyright (c) Shenshu Technologies Co., Ltd. 2017-2020. All rights reserved. ++ * Description: sdhci driver ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include "sdhci-bsp.h" ++#include ++#include "cqhci.h" ++#include "mci_proc.h" ++#include "bsp_quirk_ids.h" ++ ++static u32 __read_mostly g_cmdq_flag = 0; ++ ++static int __init bsp_cmdq_setup(char *str) ++{ ++ /* off */ ++ if (!strcasecmp(str, "off") ) { ++ g_cmdq_flag |= MMC_CMDQ_FORCE_OFF; ++ } ++ ++ /* no whitelist */ ++ if (!strcasecmp(str, "nowhitelist") ) { ++ g_cmdq_flag |= MMC_CMDQ_DIS_WHITELIST; ++ } ++ ++ return 1; ++} ++__setup("cmdq=", bsp_cmdq_setup); ++ ++int sdhci_bsp_parse_dt(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ struct device_node *np = host->mmc->parent->of_node; ++ u32 bus_width; ++ int ret; ++ ++ ret = mmc_of_parse(host->mmc); ++ if (ret) ++ return ret; ++ ++#ifdef CONFIG_MMC_CQHCI ++ if (of_get_property(np, "mmc-cmd-queue", NULL)) ++ host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; ++#endif ++ if (of_get_property(np, "mmc-broken-cmd23", NULL)) ++ host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; ++ ++ if (of_property_read_u32(np, "bus-width", &bus_width) == 0) { ++ priv->bus_width = bus_width; ++ } else { ++ pr_err("%s: \"bus-width\" property is missing, assuming 1 bit.\n", ++ mmc_hostname(host->mmc)); ++ priv->bus_width = 1; ++ } ++ ++ if (of_get_property(np, "sdhci,1-bit-only", NULL) || ++ (priv->bus_width == 1)) { ++ priv->bus_width = 1; ++ host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; ++ } ++ ++ return 0; ++} ++ ++void bsp_enable_sample(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ ++ reg = sdhci_readl(host, SDHCI_AT_CTRL); ++ reg |= SDHCI_SAMPLE_EN; ++ sdhci_writel(host, reg, SDHCI_AT_CTRL); ++} ++ ++void bsp_set_sample_phase(struct sdhci_host *host, u32 phase) ++{ ++ unsigned int reg; ++ ++ reg = sdhci_readl(host, SDHCI_AT_STAT); ++ reg &= ~SDHCI_PHASE_SEL_MASK; ++ reg |= phase; ++ sdhci_writel(host, reg, SDHCI_AT_STAT); ++} ++ ++void bsp_disable_card_clk(struct sdhci_host *host) ++{ ++ u16 clk; ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk &= ~SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++} ++ ++void bsp_enable_card_clk(struct sdhci_host *host) ++{ ++ u16 clk; ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk |= SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++} ++ ++void bsp_disable_internal_clk(struct sdhci_host *host) ++{ ++ u16 clk; ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk &= ~SDHCI_CLOCK_INT_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++} ++ ++void bsp_enable_internal_clk(struct sdhci_host *host) ++{ ++ unsigned int timeout = 20; ++ u16 clk; ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_PLL_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ while (!(clk & SDHCI_CLOCK_INT_STABLE)) { ++ if (timeout == 0) { ++ pr_err("%s: Internal clock never stabilised.\n", ++ __func__); ++ return; ++ } ++ timeout--; ++ udelay(1000); /* delay 1000us */ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ } ++} ++ ++static void bsp_select_sample_phase(struct sdhci_host *host, ++ unsigned int phase) ++{ ++ bsp_disable_card_clk(host); ++ bsp_set_sample_phase(host, phase); ++ bsp_wait_sample_dll_ready(host); ++ bsp_enable_card_clk(host); ++ udelay(1); ++} ++ ++static int sd_abort_tuning(struct mmc_host *host, u32 opcode) ++{ ++ struct mmc_command cmd = {}; ++ ++ if (opcode != MMC_SEND_TUNING_BLOCK) ++ return 0; ++ ++ cmd.opcode = MMC_STOP_TRANSMISSION; ++ cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC; ++ ++ cmd.busy_timeout = 150; /* 150 ms */ ++ return mmc_wait_for_cmd(host, &cmd, 0); ++} ++ ++static int bsp_send_status(struct mmc_host *host) ++{ ++ struct mmc_command cmd = {0}; ++ ++ BUG_ON(!host); ++ ++ cmd.opcode = MMC_SEND_STATUS; ++ cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC; ++ ++ return mmc_wait_for_cmd(host, &cmd, 1); ++} ++ ++static int bsp_send_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ int count, err; ++ ++ count = 0; ++ do { ++ err = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (err) { ++ if (opcode == MMC_SEND_TUNING_BLOCK) ++ sd_abort_tuning(host->mmc, opcode); ++ else ++ mmc_abort_tuning(host->mmc, opcode); ++ bsp_send_status(host->mmc); ++ break; ++ } ++ count++; ++ } while (count < MAX_TUNING_NUM); ++ ++ return err; ++} ++ ++static void bsp_pre_tuning(struct sdhci_host *host) ++{ ++ sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); ++ sdhci_writel(host, host->ier | SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); ++ ++ bsp_enable_sample(host); ++ host->is_tuning = 1; ++} ++ ++static void bsp_post_tuning(struct sdhci_host *host) ++{ ++ unsigned short ctrl; ++ ++ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl |= SDHCI_CTRL_TUNED_CLK; ++ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); ++ ++ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); ++ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); ++ host->is_tuning = 0; ++} ++ ++#ifndef SDHCI_BSP_EDGE_TUNING ++static int bsp_get_best_sample(u32 candidates) ++{ ++ int rise = NOT_FOUND; ++ int fall, i, win; ++ int win_max_r = NOT_FOUND; ++ int win_max_f = NOT_FOUND; ++ int end_fall = NOT_FOUND; ++ int found = NOT_FOUND; ++ int win_max = 0; ++ ++ for (i = 0; i < PHASE_SCALE; i++) { ++ if ((candidates & 0x3) == 0x2) ++ rise = (i + 1) % PHASE_SCALE; ++ ++ if ((candidates & 0x3) == 0x1) { ++ fall = i; ++ if (rise != NOT_FOUND) { ++ win = fall - rise + 1; ++ if (win > win_max) { ++ win_max = win; ++ found = (fall + rise) / 2; /* Get window center by devide 2 */ ++ win_max_r = rise; ++ win_max_f = fall; ++ rise = NOT_FOUND; ++ fall = NOT_FOUND; ++ } ++ } else { ++ end_fall = fall; ++ } ++ } ++ candidates = ror32(candidates, 1); ++ } ++ ++ if (end_fall != NOT_FOUND && rise != NOT_FOUND) { ++ fall = end_fall; ++ if (end_fall < rise) ++ end_fall += PHASE_SCALE; ++ ++ win = end_fall - rise + 1; ++ if (win > win_max) { ++ found = (rise + (win / 2)) % PHASE_SCALE; /* Get window center by devide 2 */ ++ win_max_r = rise; ++ win_max_f = fall; ++ } ++ } ++ ++ if (found != NOT_FOUND) ++ pr_err("valid phase shift [%d, %d] Final Phase:%d\n", ++ win_max_r, win_max_f, found); ++ ++ return found; ++} ++ ++static int sdhci_bsp_exec_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int sample; ++ unsigned int candidates = 0; ++ int phase, err; ++ ++ bsp_pre_tuning(host); ++ ++ for (sample = 0; sample < PHASE_SCALE; sample++) { ++ bsp_select_sample_phase(host, sample); ++ ++ err = bsp_send_tuning(host, opcode); ++ if (err) ++ pr_debug("send tuning CMD%u fail! phase:%d err:%d\n", ++ opcode, sample, err); ++ else ++ candidates |= (0x1 << sample); ++ } ++ ++ pr_info("%s: tuning done! candidates 0x%X: ", ++ mmc_hostname(host->mmc), candidates); ++ ++ phase = bsp_get_best_sample(candidates); ++ if (phase == NOT_FOUND) { ++ phase = priv->sample_phase; ++ pr_err("no valid phase shift! use default %d\n", phase); ++ } ++ ++ priv->tuning_phase = phase; ++ bsp_select_sample_phase(host, phase); ++ bsp_post_tuning(host); ++ ++ return 0; ++} ++#else ++static void bsp_enable_edge_tuning(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ ++ reg = sdhci_readl(host, SDHCI_MULTI_CYCLE); ++ reg |= SDHCI_EDGE_DETECT_EN; ++ sdhci_writel(host, reg, SDHCI_MULTI_CYCLE); ++} ++ ++static void bsp_disable_edge_tuning(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ ++ reg = sdhci_readl(host, SDHCI_MULTI_CYCLE); ++ reg &= ~SDHCI_EDGE_DETECT_EN; ++ sdhci_writel(host, reg, SDHCI_MULTI_CYCLE); ++} ++ ++static int sdhci_bsp_exec_edge_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int index, val; ++ unsigned int found; ++ unsigned int prev_found = 0; ++ unsigned int edge_p2f, edge_f2p, start, end; ++ unsigned int phase, fall, rise; ++ unsigned int fall_updat_flag = 0; ++ int err; ++ int prev_err = 0; ++ ++ bsp_pre_tuning(host); ++ bsp_enable_edge_tuning(host); ++ ++ start = 0; ++ end = PHASE_SCALE / EDGE_TUNING_PHASE_STEP; ++ ++ edge_p2f = start; ++ edge_f2p = end; ++ for (index = 0; index <= end; index++) { ++ bsp_select_sample_phase(host, index * EDGE_TUNING_PHASE_STEP); ++#if defined(CONFIG_ARCH_SS919V100) ++ bsp_find_edge_clear(host); ++#endif ++ err = bsp_send_tuning(host, opcode); ++ if (!err) { ++ val = sdhci_readl(host, SDHCI_MULTI_CYCLE); ++ found = val & SDHCI_FOUND_EDGE; ++ } else { ++ found = 1; ++ } ++ ++ if (prev_found && !found) ++ edge_f2p = index; ++ else if (!prev_found && found) ++ edge_p2f = index; ++ ++ if ((edge_p2f != start) && (edge_f2p != end)) ++ break; ++ ++ prev_found = found; ++ } ++ ++ if ((edge_p2f == start) && (edge_f2p == end)) { ++ pr_err("%s: tuning failed! can not found edge!\n", ++ mmc_hostname(host->mmc)); ++ return -1; ++ } ++ ++ bsp_disable_edge_tuning(host); ++ ++#ifdef OLD419TEST ++ start = edge_p2f * EDGE_TUNING_PHASE_STEP; ++ end = edge_f2p * EDGE_TUNING_PHASE_STEP; ++ if (end <= start) ++ end += PHASE_SCALE; ++#else ++ if ((edge_p2f < edge_p2f * EDGE_TUNING_PHASE_STEP) && ++ (EDGE_TUNING_PHASE_STEP < edge_p2f * EDGE_TUNING_PHASE_STEP)) ++ start = edge_p2f * EDGE_TUNING_PHASE_STEP; ++ ++ if ((edge_f2p < edge_f2p * EDGE_TUNING_PHASE_STEP) && ++ (EDGE_TUNING_PHASE_STEP < edge_f2p * EDGE_TUNING_PHASE_STEP)) ++ end = edge_f2p * EDGE_TUNING_PHASE_STEP; ++ ++ if (end <= start) { ++ if (end < end + PHASE_SCALE) ++ end += PHASE_SCALE; ++ } ++#endif ++ ++ fall = start; ++ rise = end; ++ for (index = start; index <= end; index++) { ++ bsp_select_sample_phase(host, index % PHASE_SCALE); ++ err = bsp_send_tuning(host, opcode); ++ if (err) ++ pr_debug("send tuning CMD%u fail! phase:%d err:%d\n", ++ opcode, index, err); ++ ++ if (err && index == start) { ++ if (!fall_updat_flag) { ++ fall_updat_flag = 1; ++ fall = start; ++ } ++ } else if (!prev_err && err) { ++ if (!fall_updat_flag) { ++ fall_updat_flag = 1; ++ fall = index; ++ } ++ } ++ ++ if (prev_err && !err) ++ rise = index; ++ ++ if (err && index == end) ++ rise = end; ++ ++ prev_err = err; ++ } ++ ++#ifdef OLD419TEST ++ phase = ((fall + rise) / 2 + PHASE_SCALE / 2) % /* 2 for cal average */ ++ PHASE_SCALE; ++#else ++ /* EBG-Number-Reverse-Add */ ++ if ((fall > fall + rise) || (rise > fall + rise)) ++ phase = ((fall + rise) / 2 + PHASE_SCALE / 2) % /* 2 for cal average */ ++ PHASE_SCALE; ++ else ++ phase = ((fall + rise) / 2 + PHASE_SCALE / 2) % /* 2 for cal average */ ++ PHASE_SCALE; ++#endif ++ ++ pr_info("%s: tuning done! valid phase shift [%d, %d] Final Phase:%d\n", ++ mmc_hostname(host->mmc), rise % PHASE_SCALE, ++ fall % PHASE_SCALE, phase); ++ ++ priv->tuning_phase = phase; ++ bsp_select_sample_phase(host, phase); ++ bsp_post_tuning(host); ++ ++ return 0; ++} ++#endif ++ ++static int sdhci_bsp_execute_tuning(struct sdhci_host *host, u32 opcode) ++{ ++#ifdef SDHCI_BSP_EDGE_TUNING ++ return sdhci_bsp_exec_edge_tuning(host, opcode); ++#else ++ return sdhci_bsp_exec_tuning(host, opcode); ++#endif ++} ++ ++static void bsp_set_emmc_card(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ ++ if (host->timing == MMC_TIMING_MMC_HS || ++ host->timing == MMC_TIMING_MMC_DDR52 || ++ host->timing == MMC_TIMING_MMC_HS200 || ++ host->timing == MMC_TIMING_MMC_HS400) { ++ reg = sdhci_readl(host, SDHCI_EMMC_CTRL); ++ reg |= SDHCI_CARD_IS_EMMC; ++ sdhci_writel(host, reg, SDHCI_EMMC_CTRL); ++ } ++} ++ ++static void sdhci_bsp_set_uhs_signaling(struct sdhci_host *host, ++ unsigned int timing) ++{ ++ sdhci_set_uhs_signaling(host, timing); ++ host->timing = timing; ++ bsp_set_emmc_card(host); ++ bsp_set_drv_cap(host); ++} ++ ++static void sdhci_bsp_hw_reset(struct sdhci_host *host) ++{ ++ sdhci_writel(host, 0x0, SDHCI_EMMC_HW_RESET); ++ udelay(10); /* delay 10us */ ++ sdhci_writel(host, 0x1, SDHCI_EMMC_HW_RESET); ++ udelay(200); /* delay 200us */ ++} ++ ++static void sdhci_bsp_adma_write_desc(struct sdhci_host *host, void **desc, ++ dma_addr_t addr, int len, unsigned int cmd) ++{ ++ int offset; ++ ++ /* work around for buffer across 128M boundary, split the buffer */ ++ if (((addr & (SDHCI_DMA_BOUNDARY_SIZE - 1)) + len) > ++ SDHCI_DMA_BOUNDARY_SIZE) { ++ offset = SDHCI_DMA_BOUNDARY_SIZE - ++ (addr & (SDHCI_DMA_BOUNDARY_SIZE - 1)); ++ sdhci_adma_write_desc(host, desc, addr, offset, ++ ADMA2_TRAN_VALID); ++ addr += offset; ++ len -= offset; ++ } ++ sdhci_adma_write_desc(host, desc, addr, len, ++ ADMA2_TRAN_VALID); ++} ++ ++/* ++ * This api is for wifi driver rescan the sdio device ++ */ ++int bsp_sdio_rescan(int slot) ++{ ++ struct mmc_host *mmc = NULL; ++ ++ if ((slot >= MCI_SLOT_NUM) || (slot <= 0)) { ++ pr_err("invalid mmc slot, please check the argument\n"); ++ return -EINVAL; ++ } ++ ++#ifdef OLD419TEST ++ mmc = mci_host[slot]; ++#else ++ mmc = mci_get_proc_host(slot); ++#endif ++ if (mmc == NULL) { ++ pr_err("invalid mmc, please check the argument\n"); ++ return -EINVAL; ++ } ++ ++ mmc_detect_change(mmc, 0); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(bsp_sdio_rescan); ++ ++static const struct of_device_id sdhci_bsp_match[] = { ++ { .compatible = "vendor,sdhci" }, ++ {}, ++}; ++ ++MODULE_DEVICE_TABLE(of, sdhci_bsp_match); ++ ++static struct sdhci_ops sdhci_bsp_ops = { ++ .platform_execute_tuning = sdhci_bsp_execute_tuning, ++ .reset = sdhci_reset, ++ .set_clock = sdhci_bsp_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = sdhci_bsp_set_uhs_signaling, ++ .hw_reset = sdhci_bsp_hw_reset, ++#if defined(CONFIG_ARCH_SS318V100) || defined(CONFIG_ARCH_SS919V100) || \ ++ defined(CONFIG_ARCH_SS918V100) || defined(CONFIG_ARCH_SS015V100) || \ ++ defined(CONFIG_ARCH_SS013V100) || defined(CONFIG_ARCH_SS928V100) || \ ++ defined(CONFIG_ARCH_SS927V100) ++#ifdef OLD419TEST ++ .signal_voltage_switch = sdhci_bsp_start_signal_voltage_switch, ++#else ++ .start_signal_voltage_switch = sdhci_bsp_start_signal_voltage_switch, ++#endif ++#endif ++#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS ++#if defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100) ++ .write_l = sdhci_bsp_writel, ++ .write_w = sdhci_bsp_writew, ++ .write_b = sdhci_bsp_writeb, ++ .read_l = sdhci_bsp_readl, ++ .read_w = sdhci_bsp_readw, ++ .read_b = sdhci_bsp_readb, ++#endif ++#endif ++ .init = sdhci_bsp_extra_init, ++}; ++ ++static const struct sdhci_pltfm_data sdhci_bsp_pdata = { ++ .ops = &sdhci_bsp_ops, ++ .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++}; ++ ++#ifdef CONFIG_MMC_CQHCI ++static u32 sdhci_bsp_cqhci_irq(struct sdhci_host *host, u32 intmask) ++{ ++ int cmd_error = 0; ++ int data_error = 0; ++ ++ if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) ++ return intmask; ++ ++ cqhci_irq(host->mmc, intmask, cmd_error, data_error); ++ ++ return 0; ++} ++ ++static void sdhci_bsp_controller_v4_enable(struct sdhci_host *host, int enable) ++{ ++ u16 ctrl; ++ ++ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); ++ if (enable) ++ ctrl |= SDHCI_CTRL_HOST_VER4_ENABLE; ++ else ++ ctrl &= ~SDHCI_CTRL_HOST_VER4_ENABLE; ++ ++ if (host->flags & SDHCI_USE_64_BIT_DMA) ++ ctrl |= SDHCI_CTRL_64BIT_ADDR; ++ ++ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); ++} ++ ++static void sdhci_bsp_cqe_enable(struct mmc_host *mmc) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ unsigned int timeout = 10000; ++ u16 reg, clk; ++ u8 ctrl; ++ ++ /* SW_RST_DAT */ ++ sdhci_reset(host, SDHCI_RESET_DATA); ++ ++ sdhci_bsp_controller_v4_enable(host, 1); ++ ++ /* Set the DMA boundary value and block size */ ++ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, ++ MMC_BLOCK_SIZE), SDHCI_BLOCK_SIZE); ++ ++ /* need to set multitransfer for cmdq */ ++ reg = sdhci_readw(host, SDHCI_TRANSFER_MODE); ++ reg |= SDHCI_TRNS_MULTI; ++ reg |= SDHCI_TRNS_BLK_CNT_EN; ++ sdhci_writew(host, reg, SDHCI_TRANSFER_MODE); ++ ++ /* ADMA2 only */ ++ ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); ++ ctrl &= ~SDHCI_CTRL_DMA_MASK; ++ ctrl |= SDHCI_CTRL_ADMA32; ++ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++ ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk |= SDHCI_CLOCK_PLL_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ while (mmc->ops->card_busy(mmc)) { ++ timeout--; ++ if (!timeout) { ++ pr_err("%s: wait busy timeout\n", __func__); ++ break; ++ } ++ udelay(1); ++ } ++ ++ sdhci_cqe_enable(mmc); ++} ++ ++static void sdhci_bsp_cqe_disable(struct mmc_host *mmc, bool recovery) ++{ ++ int timeout = 10000; ++ ++ while (mmc->ops->card_busy(mmc)) { ++ timeout--; ++ if (!timeout) { ++ pr_err("%s: wait busy timeout\n", __func__); ++ break; ++ } ++ udelay(1); ++ } ++ ++ sdhci_bsp_controller_v4_enable(mmc_priv(mmc), 0); ++ ++ sdhci_cqe_disable(mmc, recovery); ++} ++ ++static void sdhci_bsp_dumpregs(struct mmc_host *mmc) ++{ ++ sdhci_dumpregs(mmc_priv(mmc)); ++} ++ ++static const struct cqhci_host_ops sdhci_bsp_cqhci_ops = { ++ .enable = sdhci_bsp_cqe_enable, ++ .disable = sdhci_bsp_cqe_disable, ++ .dumpregs = sdhci_bsp_dumpregs, ++}; ++ ++static const struct sdhci_ops sdhci_bsp_cqe_ops = { ++ .platform_execute_tuning = sdhci_bsp_execute_tuning, ++ .reset = sdhci_reset, ++ .set_clock = sdhci_bsp_set_clock, ++ .set_bus_width = sdhci_set_bus_width, ++ .set_uhs_signaling = sdhci_bsp_set_uhs_signaling, ++#if defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100) ++#ifdef OLD419TEST ++ .signal_voltage_switch = ++ sdhci_bsp_start_signal_voltage_switch, ++#else ++ .start_signal_voltage_switch = ++ sdhci_bsp_start_signal_voltage_switch, ++#endif ++#endif ++ .hw_reset = sdhci_bsp_hw_reset, ++ .irq = sdhci_bsp_cqhci_irq, ++ .init = sdhci_bsp_extra_init, ++}; ++ ++static const struct sdhci_pltfm_data sdhci_bsp_cqe_pdata = { ++ .ops = &sdhci_bsp_cqe_ops, ++ .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, ++ .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, ++}; ++ ++static int sdhci_bsp_add_host(struct sdhci_host *host) ++{ ++ struct cqhci_host *cq_host = NULL; ++ bool dma64 = false; ++ int ret; ++ ++ if (g_cmdq_flag & MMC_CMDQ_FORCE_OFF) { ++ /* force cmdq off by bootarges */ ++ host->mmc->caps2 &= ~MMC_CAP2_CQE; ++ } ++ ++ if (!(host->mmc->caps2 & MMC_CAP2_CQE)) ++ return sdhci_add_host(host); ++ ++ ret = sdhci_setup_host(host); ++ if (ret) ++ return ret; ++ ++ cq_host = devm_kzalloc(host->mmc->parent, sizeof(*cq_host), GFP_KERNEL); ++ if (cq_host == NULL) { ++ pr_err("%s: allocate memory for CQE fail\n", __func__); ++ ret = -ENOMEM; ++ goto cleanup; ++ } ++ ++ cq_host->mmio = host->ioaddr + 0x180; ++ cq_host->ops = &sdhci_bsp_cqhci_ops; ++ ++ /* ++ * synopsys controller has dma 128M algin limit, ++ * may split the trans descriptors ++ */ ++ cq_host->quirks |= CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT; ++ ++ dma64 = host->flags & SDHCI_USE_64_BIT_DMA; ++ if (dma64) ++ cq_host->caps |= CQHCI_TASK_DESC_SZ_128; ++ ++ ret = cqhci_init(cq_host, host->mmc, dma64); ++ if (ret) { ++ pr_err("%s: CQE init fail\n", __func__); ++ return ret; ++ } ++ ++ ret = __sdhci_add_host(host); ++ if (ret) ++ return ret; ++ ++ return 0; ++ ++cleanup: ++ sdhci_cleanup_host(host); ++ return ret; ++} ++#else ++static int sdhci_bsp_add_host(struct sdhci_host *host) ++{ ++ return sdhci_add_host(host); ++} ++#endif ++ ++static void sdhci_bsp_init_card(struct mmc_host *host, struct mmc_card *card) ++{ ++#ifdef CONFIG_MMC_CQHCI ++ u32 idx; ++ /* eMMC spec: cid product name offset: 0, 7, 6, 5, 4, 11 */ ++ const u8 cid_pnm_offset[] = {0, 7, 6, 5, 4, 11}; ++ ++ if (host == NULL || card == NULL) { ++ pr_err("null card or host\n"); ++ return; ++ } ++ ++ if ((card->type == MMC_TYPE_MMC) && (host->caps2 & MMC_CAP2_CQE)) { ++ u8 *raw_cid = (u8 *)card->raw_cid; ++ ++ /* Skip whitelist */ ++ if (g_cmdq_flag & MMC_CMDQ_DIS_WHITELIST) { ++ return; ++ } ++ ++ /* Clear MMC CQE capblility */ ++ host->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); ++ ++ /* Manufacturer ID: b[127:120](eMMC v2.0 and upper), 0/24: idx/bit offset */ ++ card->cid.manfid = card->raw_cid[0] >> 24 & 0xFF; ++ ++ /* Decode CID with eMMC v2.0 and upper */ ++ for (idx = 0; idx < sizeof(cid_pnm_offset); idx++) { ++ card->cid.prod_name[idx] = raw_cid[cid_pnm_offset[idx]]; ++ } ++ card->cid.prod_name[++idx] = 0; ++ mmc_fixup_device(card, mmc_cmdq_whitelist); ++ } ++#endif ++} ++ ++static int sdhci_bsp_probe(struct platform_device *pdev) ++{ ++ struct sdhci_host *host = NULL; ++ const struct sdhci_pltfm_data *pdata = NULL; ++ int ret; ++ ++#ifdef CONFIG_MMC_CQHCI ++ if (of_get_property(pdev->dev.of_node, "mmc-cmd-queue", NULL)) ++ pdata = &sdhci_bsp_cqe_pdata; ++ else ++ pdata = &sdhci_bsp_pdata; ++#else ++ pdata = &sdhci_bsp_pdata; ++#endif ++ host = sdhci_pltfm_init(pdev, pdata, sizeof(struct sdhci_bsp_priv)); ++ if (IS_ERR(host)) ++ return PTR_ERR(host); ++ ++ host->mmc_host_ops.init_card = sdhci_bsp_init_card; ++ ++ ret = sdhci_bsp_pltfm_init(pdev, host); ++ if (ret) ++ goto pltfm_free; ++ ++ if (bsp_support_runtime_pm(host)) { ++ pm_runtime_get_noresume(&pdev->dev); ++ pm_runtime_set_autosuspend_delay(&pdev->dev, BSP_MMC_AUTOSUSPEND_DELAY_MS); ++ pm_runtime_use_autosuspend(&pdev->dev); ++ pm_runtime_set_active(&pdev->dev); ++ pm_runtime_enable(&pdev->dev); ++ } ++ ++ ret = sdhci_bsp_add_host(host); ++ if (ret) ++ goto pm_runtime_disable; ++ ++ if (bsp_support_runtime_pm(host)) { ++ pm_runtime_mark_last_busy(&pdev->dev); ++ pm_runtime_put_autosuspend(&pdev->dev); ++ } ++ ++ return 0; ++ ++pm_runtime_disable: ++ if (bsp_support_runtime_pm(host)) { ++ pm_runtime_disable(&pdev->dev); ++ pm_runtime_set_suspended(&pdev->dev); ++ pm_runtime_put_noidle(&pdev->dev); ++ } ++ ++pltfm_free: ++ sdhci_pltfm_free(pdev); ++ return ret; ++} ++ ++static int sdhci_bsp_remove(struct platform_device *pdev) ++{ ++ struct sdhci_host *host = platform_get_drvdata(pdev); ++ int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) == ++ 0xffffffff); ++ ++ if (bsp_support_runtime_pm(host)) { ++ pm_runtime_get_sync(&pdev->dev); ++ pm_runtime_disable(&pdev->dev); ++ pm_runtime_put_noidle(&pdev->dev); ++ } ++ ++ sdhci_remove_host(host, dead); ++ sdhci_pltfm_free(pdev); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int sdhci_bsp_runtime_suspend(struct device *dev) ++{ ++ struct sdhci_host *host = dev_get_drvdata(dev); ++ ++ bsp_disable_card_clk(host); ++ return 0; ++} ++ ++static int sdhci_bsp_runtime_resume(struct device *dev) ++{ ++ struct sdhci_host *host = dev_get_drvdata(dev); ++ ++ bsp_enable_card_clk(host); ++ return 0; ++} ++#endif ++ ++static const struct dev_pm_ops sdhci_bsp_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, ++ sdhci_pltfm_resume) ++ ++ SET_RUNTIME_PM_OPS(sdhci_bsp_runtime_suspend, ++ sdhci_bsp_runtime_resume, ++ NULL) ++}; ++ ++static struct platform_driver sdhci_bsp_driver = { ++ .probe = sdhci_bsp_probe, ++ .remove = sdhci_bsp_remove, ++ .driver = { ++ .name = "sdhci_bsp", ++ .of_match_table = sdhci_bsp_match, ++ .pm = &sdhci_bsp_pm_ops, ++ }, ++}; ++ ++static int __init sdhci_bsp_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sdhci_bsp_driver); ++ if (ret) ++ return ret; ++ ++ ret = mci_proc_init(); ++ if (ret) ++ platform_driver_unregister(&sdhci_bsp_driver); ++ ++ return ret; ++} ++ ++static void __exit sdhci_bsp_exit(void) ++{ ++ mci_proc_shutdown(); ++ ++ platform_driver_unregister(&sdhci_bsp_driver); ++} ++ ++module_init(sdhci_bsp_init); ++module_exit(sdhci_bsp_exit); ++MODULE_DESCRIPTION("SDHCI driver for Vendor"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/mmc/host/sdhci-bsp.h b/drivers/mmc/host/sdhci-bsp.h +new file mode 100644 +index 000000000000..f8ee2e26cebc +--- /dev/null ++++ b/drivers/mmc/host/sdhci-bsp.h +@@ -0,0 +1,135 @@ ++/* ++ * Copyright (c) Shenshu Technologies Co., Ltd. 2017-2020. All rights reserved. ++ * Description: sdhci header ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef _DRIVERS_MMC_SDHCI_BSP_H ++#define _DRIVERS_MMC_SDHCI_BSP_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "sdhci-pltfm.h" ++ ++#define SDHCI_BSP_EDGE_TUNING /* enable edge tuning */ ++ ++#define PHASE_SCALE 32 ++#define NOT_FOUND (-1) ++#define MAX_TUNING_NUM 1 ++#define MAX_FREQ 200000000 ++#define EDGE_TUNING_PHASE_STEP 4 ++#define MMC_BLOCK_SIZE 512 ++ ++/* Software auto suspend delay */ ++#define BSP_MMC_AUTOSUSPEND_DELAY_MS 50 ++ ++static inline void *sdhci_get_pltfm_priv(struct sdhci_host *host) ++{ ++ return sdhci_pltfm_priv(sdhci_priv(host)); ++} ++ ++struct sdhci_bsp_priv { ++ struct reset_control *crg_rst; ++ struct reset_control *dll_rst; ++ struct reset_control *sampl_rst; ++ struct regmap *crg_regmap; ++ struct regmap *misc_regmap; ++ struct regmap *iocfg_regmap; ++ void __iomem *phy_addr; ++ unsigned int devid; ++ unsigned int drv_phase; ++ unsigned int sample_phase; ++ unsigned int tuning_phase; ++ unsigned int bus_width; ++}; ++ ++/* extended host controller registers. */ ++#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000 ++#define SDHCI_CLOCK_PLL_EN 0x0008 ++#define SDHCI_CTRL_64BIT_ADDR 0x2000 ++#define SDHCI_CAN_DO_ADMA3 0x08000000 ++ ++/* extended registers */ ++#define SDHCI_MSHC_CTRL 0x508 ++#define SDHCI_CMD_CONFLIT_CHECK 0x01 ++ ++#define SDHCI_AXI_MBIIU_CTRL 0x510 ++#define SDHCI_GM_WR_OSRC_LMT_MASK (0x7 << 24) ++#define sdhci_gm_wr_osrc_lmt_sel(x) ((x) << 24) ++#define SDHCI_GM_RD_OSRC_LMT_MASK (0x7 << 16) ++#define sdhci_gm_rd_osrc_lmt_sel(x) ((x) << 16) ++#define SDHCI_UNDEFL_INCR_EN 0x1 ++ ++#define SDHCI_EMMC_CTRL 0x52C ++#define SDHCI_CARD_IS_EMMC 0x0001 ++#define SDHCI_ENH_STROBE_EN 0x0100 ++ ++#define SDHCI_EMMC_HW_RESET 0x534 ++ ++#define SDHCI_AT_CTRL 0x540 ++#define SDHCI_SAMPLE_EN 0x00000010 ++ ++#define SDHCI_AT_STAT 0x544 ++#define SDHCI_PHASE_SEL_MASK 0x000000FF ++ ++#define SDHCI_MULTI_CYCLE 0x54C ++#define SDHCI_FIND_EDGE_CLR (0x1 << 14) ++#define SDHCI_FOUND_EDGE (0x1 << 11) ++#define SDHCI_EDGE_DETECT_EN (0x1 << 8) ++#define SDHCI_DOUT_EN_F_EDGE (0x1 << 6) ++#define SDHCI_DATA_DLY_EN (0x1 << 3) ++#define SDHCI_CMD_DLY_EN (0x1 << 2) ++ ++void bsp_set_drv_cap(struct sdhci_host *host); ++void bsp_get_phase(struct sdhci_host *host); ++void bsp_set_drv_phase(struct sdhci_host *host, unsigned int phase); ++void bsp_enable_sample(struct sdhci_host *host); ++void bsp_set_sample_phase(struct sdhci_host *host, u32 phase); ++void bsp_disable_card_clk(struct sdhci_host *host); ++void bsp_enable_card_clk(struct sdhci_host *host); ++void bsp_disable_internal_clk(struct sdhci_host *host); ++void bsp_enable_internal_clk(struct sdhci_host *host); ++void bsp_enable_sample_dll_slave(struct sdhci_host *host); ++void bsp_wait_sample_dll_ready(struct sdhci_host *host); ++void bsp_wait_p4_dll_lock(struct sdhci_host *host); ++void bsp_wait_ds_dll_ready(struct sdhci_host *host); ++void bsp_wait_ds_180_dll_ready(struct sdhci_host *host); ++void bsp_wait_ds_dll_lock(struct sdhci_host *host); ++void bsp_set_ds_dll_delay(struct sdhci_host *host); ++void sdhci_bsp_set_clock(struct sdhci_host *host, unsigned int clk); ++void sdhci_bsp_writel(struct sdhci_host *host, u32 val, int reg); ++void sdhci_bsp_writew(struct sdhci_host *host, u16 val, int reg); ++void sdhci_bsp_writeb(struct sdhci_host *host, u8 val, int reg); ++u32 sdhci_bsp_readl(struct sdhci_host *host, int reg); ++u16 sdhci_bsp_readw(struct sdhci_host *host, int reg); ++u8 sdhci_bsp_readb(struct sdhci_host *host, int reg); ++int bsp_support_runtime_pm(struct sdhci_host *host); ++int sdhci_bsp_pltfm_init(struct platform_device *pdev, ++ struct sdhci_host *host); ++void sdhci_bsp_extra_init(struct sdhci_host *host); ++int sdhci_bsp_parse_dt(struct sdhci_host *host); ++int sdhci_bsp_start_signal_voltage_switch(struct sdhci_host *host, ++ struct mmc_ios *ios); ++#if defined(CONFIG_ARCH_SS919V100) ++void bsp_find_edge_clear(struct sdhci_host *host); ++#endif ++#endif /* _DRIVERS_MMC_SDHCI_BSP_H */ +diff --git a/drivers/mmc/host/sdhci-ss928v100.c b/drivers/mmc/host/sdhci-ss928v100.c +new file mode 100644 +index 000000000000..1f81cb0ba5ca +--- /dev/null ++++ b/drivers/mmc/host/sdhci-ss928v100.c +@@ -0,0 +1,931 @@ ++/* ++ * ++ * Copyright (c) 2020-2021 Shenshu Technologies Co., Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include "sdhci-bsp.h" ++#include "mci_proc.h" ++ ++#define GET_EMMC_BUS_WIDTH_FORM_DTS ++ ++#define REG_BASE_EMMC_PHY 0x10010000 ++#define EMMC_PHY_INITCTRL (REG_BASE_EMMC_PHY + 0x4) ++#define EMMC_INIT_EN 0x1 ++#define EMMC_DLYMEAS_EN (0x1 << 2) ++#define EMMC_ZCAL_EN (0x1 << 3) ++#define INITCTRL_CHECK_TIMES 100 ++ ++#define PERI_CRG_MMC_DRV_DLL 0x34c8 ++#define PERI_CRG_SDIO0_DRV_DLL 0x35c8 ++#define PERI_CRG_SDIO1_DRV_DLL 0x36c8 ++#define CRG_DRV_PHASE_SEL_SHIFT 15 ++#define CRG_DRV_PHASE_SEL_MASK (0x1F << 15) ++ ++#define PERI_CRG_MMC_STAT 0x34d8 ++#define CRG_SAM_DLL_READY BIT(12) ++#define CRG_DS_DLL_READY BIT(10) ++#define CRG_P4_DLL_LOCKED BIT(9) ++ ++/* MMC IO */ ++#define REG_MMC_CLK_IO 0x00 ++#define REG_MMC_CMD_IO 0x04 ++#define REG_MMC_D0_IO 0x08 ++#define REG_MMC_D1_IO 0x0c ++#define REG_MMC_D2_IO 0x10 ++#define REG_MMC_D3_IO 0x14 ++#define REG_MMC_D4_IO 0x18 ++#define REG_MMC_D5_IO 0x1c ++#define REG_MMC_D6_IO 0x20 ++#define REG_MMC_D7_IO 0x24 ++#define REG_MMC_DQS_IO 0x28 ++#define REG_MMC_RST_IO 0x2c ++ ++/* SDIO0 IO */ ++ ++#define REG_SDIO0_DETECT_IO 0x80 ++#define REG_SDIO0_PWEN_N 0x84 ++#define REG_SDIO0_CMD_IO 0x88 ++#define REG_SDIO0_D0_IO 0x8c ++#define REG_SDIO0_D1_IO 0x90 ++#define REG_SDIO0_D2_IO 0x94 ++#define REG_SDIO0_D3_IO 0x98 ++#define REG_SDIO0_CLK_IO 0x9c ++ ++/* SDIO1 IO */ ++#define REG_SDIO1_D0_IO 0x40 ++#define REG_SDIO1_D1_IO 0x44 ++#define REG_SDIO1_D2_IO 0x48 ++#define REG_SDIO1_D3_IO 0x4c ++#define REG_SDIO1_CLK_IO 0x50 ++#define REG_SDIO1_CMD_IO 0x54 ++ ++/* IO CFG */ ++#define IO_CFG_DRV_STR_MASK (0xf << 4) /* eMMC or SDIO */ ++#define io_cfg_drv_str_sel(str) ((str) << 4) ++ ++#define IO_CFG_PULL_UPDW_MASK (0x03 << 8) /* eMMC or SDIO */ ++#define IO_CFG_EMMC_PULL_UP BIT(9) /* eMMC */ ++#define IO_CFG_EMMC_PULL_UPDW_EN BIT(8) /* eMMC */ ++#define IO_CFG_PULL_DOWN BIT(9) /* SDIO */ ++#define IO_CFG_PULL_UP BIT(8) /* SDIO */ ++#define IO_CFG_SDIO_MASK (IO_CFG_DRV_STR_MASK | IO_CFG_PULL_UPDW_MASK) ++ ++#define IO_CFG_SDIO_MUX 0x1 ++#define IO_CFG_EMMC_MUX 0x2 ++#define IO_CFG_MUX_MASK 0xF ++#define MMC_BUS_WIDTH_8_BIT 8 ++#define MMC_BUS_WIDTH_4_BIT 4 ++ ++#define REG_SYSSTAT 0x11020018 ++#define BOOT_MEDIA_EMMC 0xc ++#define EMMC_BOOT_8BIT BIT(11) ++#define BOOT_FLAG_MASK (0x3 << 2) ++ ++#define REG_MISC_PWR_SWITCH 0x102E0010 ++#define SDIO0_PWRSW_SEL_1V8 BIT(5) ++#define SDIO0_PWR_EN BIT(4) ++#define SDIO0_IO_MODE_SEL_1V8 BIT(1) ++#define SDIO0_PWR_CTRL_BY_MISC BIT(0) ++ ++#define IO_CLK 0 ++#define IO_CMD 1 ++#define IO_DATA 2 ++#define IO_RST 3 ++#define IO_DS 4 ++#define EMMC_IO_TYPE_NUM 5 ++#define SDIO_IO_TYPE_NUM 3 ++ ++/* sample drive phase */ ++#define DRIVE 0 ++#define SAMPLE 1 ++#define PHASE_TYPE_NUM 2 ++ ++static unsigned int reg_mmc_data_io[] = { ++ REG_MMC_D0_IO, REG_MMC_D1_IO, ++ REG_MMC_D2_IO, REG_MMC_D3_IO, ++ REG_MMC_D4_IO, REG_MMC_D5_IO, ++ REG_MMC_D6_IO, REG_MMC_D7_IO ++}; ++ ++static unsigned int reg_sdio0_data_io[] = { ++ REG_SDIO0_D0_IO, REG_SDIO0_D1_IO, ++ REG_SDIO0_D2_IO, REG_SDIO0_D3_IO, ++}; ++ ++static unsigned int reg_sdio1_data_io[] = { ++ REG_SDIO1_D0_IO, REG_SDIO1_D1_IO, ++ REG_SDIO1_D2_IO, REG_SDIO1_D3_IO, ++}; ++ ++/* drive capabilities */ ++static u32 mmc_io_cfg[][EMMC_IO_TYPE_NUM] = { /* CLK CMD DATA RST DQS */ ++ [MMC_TIMING_LEGACY] = { ++ io_cfg_drv_str_sel(0x4) | IO_CFG_EMMC_PULL_UPDW_EN, /* 0x4 is 0b100 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x2 is 0b010 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x2) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x2 is 0b010 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_UP ++ }, ++ [MMC_TIMING_MMC_HS] = { ++ io_cfg_drv_str_sel(0x4) | IO_CFG_EMMC_PULL_UPDW_EN, /* 0x4 is 0b100 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x2 is 0b010 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x2) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x2 is 0b010 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_UP ++ }, ++ [MMC_TIMING_MMC_HS200] = { ++ io_cfg_drv_str_sel(0x4) | IO_CFG_EMMC_PULL_UPDW_EN, /* 0x4 is 0b100 */ ++ io_cfg_drv_str_sel(0x5) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x5 is 0b101 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x5) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x5 is 0b101 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_UP ++ }, ++ [MMC_TIMING_MMC_HS400] = { ++ io_cfg_drv_str_sel(0x4) | IO_CFG_EMMC_PULL_UPDW_EN, /* 0x4 is 0b100 */ ++ io_cfg_drv_str_sel(0x5) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x5 is 0b101 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x5) | IO_CFG_EMMC_PULL_UPDW_EN | /* 0x5 is 0b101 */ ++ IO_CFG_EMMC_PULL_UP, ++ io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_UP, ++ io_cfg_drv_str_sel(0x4) | IO_CFG_EMMC_PULL_UPDW_EN /* 0x4 is 0b100 */ ++ } ++}; ++ ++static u32 sdio0_io_cfg[][SDIO_IO_TYPE_NUM] = { /* CLK CMD DATA */ ++ [MMC_TIMING_LEGACY] = { ++ io_cfg_drv_str_sel(0x9) | IO_CFG_PULL_DOWN, /* 0x9 is 0b1001 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP, /* 0x3 is 0b0011 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP /* 0x3 is 0b0011 */ ++ }, ++ [MMC_TIMING_SD_HS] = { ++ io_cfg_drv_str_sel(0xa) | IO_CFG_PULL_DOWN, /* 0xa is 0b1010 */ ++ io_cfg_drv_str_sel(0x4) | IO_CFG_PULL_UP, /* 0x4 is 0b0100 */ ++ io_cfg_drv_str_sel(0x4) | IO_CFG_PULL_UP /* 0x4 is 0b0100 */ ++ }, ++ [MMC_TIMING_UHS_SDR12] = { ++ io_cfg_drv_str_sel(0x5) | IO_CFG_PULL_DOWN, /* 0x5 is 0b0101 */ ++ io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_UP, ++ io_cfg_drv_str_sel(0x0) | IO_CFG_PULL_UP ++ }, ++ [MMC_TIMING_UHS_SDR25] = { ++ io_cfg_drv_str_sel(0x7) | IO_CFG_PULL_DOWN, /* 0x7 is 0b0111 */ ++ io_cfg_drv_str_sel(0x1) | IO_CFG_PULL_UP, /* 0x1 is 0b0001 */ ++ io_cfg_drv_str_sel(0x1) | IO_CFG_PULL_UP /* 0x1 is 0b0001 */ ++ }, ++ [MMC_TIMING_UHS_SDR50] = { ++ io_cfg_drv_str_sel(0x7) | IO_CFG_PULL_DOWN, /* 0x7 is 0b0111 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP, /* 0x3 is 0b0011 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP /* 0x3 is 0b0011 */ ++ }, ++ [MMC_TIMING_UHS_SDR104] = { ++ io_cfg_drv_str_sel(0xd) | IO_CFG_PULL_DOWN, /* 0xd is 0b1101 */ ++ io_cfg_drv_str_sel(0x7) | IO_CFG_PULL_UP, /* 0x7 is 0b0111 */ ++ io_cfg_drv_str_sel(0x7) | IO_CFG_PULL_UP /* 0x7 is 0b0111 */ ++ } ++}; ++ ++static u32 sdio1_io_cfg[][SDIO_IO_TYPE_NUM] = { /* CLK CMD DATA */ ++ [MMC_TIMING_LEGACY] = { ++ io_cfg_drv_str_sel(0x8) | IO_CFG_PULL_DOWN, /* 0x8 is 0b1000 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_PULL_UP, /* 0x2 is 0b0010 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_PULL_UP /* 0x2 is 0b0010 */ ++ }, ++ [MMC_TIMING_MMC_HS] = { ++ io_cfg_drv_str_sel(0x9) | IO_CFG_PULL_DOWN, /* 0x9 is 0b1001 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP, /* 0x3 is 0b0011 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP /* 0x3 is 0b0011 */ ++ }, ++ [MMC_TIMING_SD_HS] = { ++ io_cfg_drv_str_sel(0x4) | IO_CFG_PULL_DOWN, /* 0x4 is 0b0100 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP, /* 0x3 is 0b0011 */ ++ io_cfg_drv_str_sel(0x3) | IO_CFG_PULL_UP /* 0x3 is 0b0011 */ ++ }, ++ [MMC_TIMING_UHS_SDR12] = { ++ io_cfg_drv_str_sel(0x4) | IO_CFG_PULL_DOWN, /* 0x4 is 0b0100 */ ++ io_cfg_drv_str_sel(0x1) | IO_CFG_PULL_UP, /* 0x4 is 0b0001 */ ++ io_cfg_drv_str_sel(0x1) | IO_CFG_PULL_UP /* 0x4 is 0b0001 */ ++ }, ++ [MMC_TIMING_UHS_SDR25] = { ++ io_cfg_drv_str_sel(0x6) | IO_CFG_PULL_DOWN, /* 0x6 is 0b0110 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_PULL_UP, /* 0x2 is 0b0010 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_PULL_UP /* 0x2 is 0b0010 */ ++ }, ++ [MMC_TIMING_UHS_SDR50] = { ++ io_cfg_drv_str_sel(0x6) | IO_CFG_PULL_DOWN, /* 0x6 is 0b0110 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_PULL_UP, /* 0x2 is 0b0010 */ ++ io_cfg_drv_str_sel(0x2) | IO_CFG_PULL_UP /* 0x2 is 0b0010 */ ++ }, ++ [MMC_TIMING_UHS_SDR104] = { ++ io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_DOWN, /* 0xb is 0b1011 */ ++ io_cfg_drv_str_sel(0x6) | IO_CFG_PULL_UP, /* 0x6 is 0b0110 */ ++ io_cfg_drv_str_sel(0x6) | IO_CFG_PULL_UP /* 0x6 is 0b0110 */ ++ }, ++ [MMC_TIMING_MMC_HS200] = { ++ io_cfg_drv_str_sel(0xb) | IO_CFG_PULL_DOWN, /* 0xb is 0b1011 */ ++ io_cfg_drv_str_sel(0x6) | IO_CFG_PULL_UP, /* 0x6 is 0b0110 */ ++ io_cfg_drv_str_sel(0x6) | IO_CFG_PULL_UP, /* 0x6 is 0b0110 */ ++ } ++}; ++ ++static u32 mmc_phase_cfg[][PHASE_TYPE_NUM] = { /* drive,sample phase */ ++ [MMC_TIMING_LEGACY] = { 16, 0 }, /* 16 for 180 degree */ ++ [MMC_TIMING_MMC_HS] = { 16, 4 }, /* 16 for 180 degree,4 for 45 degree */ ++ [MMC_TIMING_MMC_HS200] = { 18, 0 }, /* 18 for 202.5 degree */ ++ [MMC_TIMING_MMC_HS400] = { 7, 0 } /* 7 for 78.75 degree */ ++}; ++ ++static u32 sdio0_phase_cfg[][PHASE_TYPE_NUM] = { /* drive , sample phase */ ++ [MMC_TIMING_LEGACY] = { 16, 0 }, /* 16 for 180 degree */ ++ [MMC_TIMING_SD_HS] = { 18, 4 }, /* 18 for 202.5 degree */ ++ [MMC_TIMING_UHS_SDR12] = { 16, 0 }, /* 16 for 180 degree */ ++ [MMC_TIMING_UHS_SDR25] = { 16, 4 }, /* 16 for 180 degree,4 for 45 degree */ ++ [MMC_TIMING_UHS_SDR50] = { 20, 0 }, /* 20 for 225 degree */ ++ [MMC_TIMING_UHS_SDR104] = { 20, 0 }, /* 20 for 225 degree */ ++}; ++ ++static u32 sdio1_phase_cfg[][PHASE_TYPE_NUM] = { /* drive , sample phase */ ++ [MMC_TIMING_LEGACY] = { 16, 0 }, /* 16 for 180 degree */ ++ [MMC_TIMING_MMC_HS] = { 16, 4 }, /* 16 for 180 degree,4 for 45 degree */ ++ [MMC_TIMING_SD_HS] = { 16, 4 }, /* 16 for 180 degree,4 for 45 degree */ ++ [MMC_TIMING_UHS_SDR12] = { 16, 0 }, /* 16 for 180 degree */ ++ [MMC_TIMING_UHS_SDR25] = { 16, 4 }, /* 16 for 180 degree,4 for 45 degree */ ++ [MMC_TIMING_UHS_SDR50] = { 20, 0 }, /* 20 for 225 degree */ ++ [MMC_TIMING_UHS_SDR104] = { 20, 0 }, /* 20 for 225 degree */ ++ [MMC_TIMING_MMC_HS200] = { 20, 0 }, /* 20 for 225 degree */ ++}; ++ ++/* Do ZQ resistance calibration for eMMC PHY IO */ ++static int resistance_calibration(void) ++{ ++ int i; ++ u32 reg_val; ++ void __iomem *viraddr; ++ ++ viraddr = ioremap(EMMC_PHY_INITCTRL, sizeof(u32)); ++ //viraddr = ioremap_nocache(EMMC_PHY_INITCTRL, sizeof(u32)); ++ if (!viraddr) { ++ pr_err("resistance_calibration ioremap error.\n"); ++ return -ENOMEM; ++ } ++ reg_val = readl(viraddr); ++ reg_val |= EMMC_INIT_EN | EMMC_ZCAL_EN; ++ writel(reg_val, viraddr); ++ ++ for (i = 0; i < INITCTRL_CHECK_TIMES; i++) { ++ reg_val = readl(viraddr); ++ if ((reg_val & (EMMC_INIT_EN | EMMC_ZCAL_EN)) == 0) { ++ iounmap(viraddr); ++ return 0; ++ } ++ udelay(10); /* delay 10 us */ ++ } ++ ++ iounmap(viraddr); ++ return -ETIMEDOUT; ++} ++ ++void sdhci_bsp_extra_init(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ u32 ctrl; ++ ++ ctrl = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL); ++ ctrl &= ~SDHCI_UNDEFL_INCR_EN; ++ sdhci_writel(host, ctrl, SDHCI_AXI_MBIIU_CTRL); ++ ++ /* eMMC device */ ++ if (priv->devid == 0) { ++ ctrl = sdhci_readl(host, SDHCI_EMMC_CTRL); ++ ctrl |= SDHCI_CARD_IS_EMMC; ++ sdhci_writel(host, ctrl, SDHCI_EMMC_CTRL); ++ } ++ ++ host->error_count = 0; ++} ++ ++static void set_drv_str(struct sdhci_host *host, ++ unsigned int offset, unsigned int drv_str) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ regmap_write_bits(priv->iocfg_regmap, offset, IO_CFG_SDIO_MASK, drv_str); ++} ++ ++void bsp_set_drv_cap(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int i; ++ ++ if (priv->devid == 0) { /* emmc devices */ ++ set_drv_str(host, REG_MMC_CLK_IO, ++ mmc_io_cfg[host->timing][IO_CLK]); ++ set_drv_str(host, REG_MMC_CMD_IO, ++ mmc_io_cfg[host->timing][IO_CMD]); ++ ++ for (i = 0; i < priv->bus_width; i++) ++ set_drv_str(host, reg_mmc_data_io[i], ++ mmc_io_cfg[host->timing][IO_DATA]); ++ ++ set_drv_str(host, REG_MMC_RST_IO, ++ mmc_io_cfg[host->timing][IO_RST]); ++ ++ if (host->timing == MMC_TIMING_MMC_HS400) ++ set_drv_str(host, REG_MMC_DQS_IO, ++ mmc_io_cfg[host->timing][IO_DS]); ++ } else if (priv->devid == 1) { /* sdio0 devices */ ++ set_drv_str(host, REG_SDIO0_CLK_IO, ++ sdio0_io_cfg[host->timing][IO_CLK]); ++ set_drv_str(host, REG_SDIO0_CMD_IO, ++ sdio0_io_cfg[host->timing][IO_CMD]); ++ for (i = 0; i < priv->bus_width; i++) ++ set_drv_str(host, reg_sdio0_data_io[i], ++ sdio0_io_cfg[host->timing][IO_DATA]); ++ } else { /* sdio1 devices */ ++ set_drv_str(host, REG_SDIO1_CLK_IO, ++ sdio1_io_cfg[host->timing][IO_CLK]); ++ set_drv_str(host, REG_SDIO1_CMD_IO, ++ sdio1_io_cfg[host->timing][IO_CMD]); ++ for (i = 0; i < priv->bus_width; i++) ++ set_drv_str(host, reg_sdio1_data_io[i], ++ sdio1_io_cfg[host->timing][IO_DATA]); ++ } ++} ++ ++void bsp_wait_sample_dll_ready(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ unsigned int timeout = 20; ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ do { ++ regmap_read(priv->crg_regmap, PERI_CRG_MMC_STAT, ®); ++ if (reg & CRG_SAM_DLL_READY) ++ return; ++ ++ udelay(1000); /* delay 1000us */ ++ timeout--; ++ } while (timeout > 0); ++ ++ pr_err("%s: SAMPL DLL slave not ready.\n", mmc_hostname(host->mmc)); ++} ++ ++void bsp_wait_p4_dll_lock(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ unsigned int timeout = 20; ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ do { ++ regmap_read(priv->crg_regmap, PERI_CRG_MMC_STAT, ®); ++ if (reg & CRG_P4_DLL_LOCKED) ++ return; ++ ++ udelay(1000); /* delay 1000us */ ++ timeout--; ++ } while (timeout > 0); ++ ++ pr_err("%s: P4 DLL master not locked.\n", mmc_hostname(host->mmc)); ++} ++ ++void bsp_wait_ds_dll_ready(struct sdhci_host *host) ++{ ++ unsigned int reg; ++ unsigned int timeout = 20; ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ do { ++ regmap_read(priv->crg_regmap, PERI_CRG_MMC_STAT, ®); ++ if (reg & CRG_DS_DLL_READY) ++ return; ++ ++ udelay(1000); /* delay 1000us */ ++ timeout--; ++ } while (timeout > 0); ++ ++ pr_err("%s: DS DLL slave not ready.\n", mmc_hostname(host->mmc)); ++} ++ ++static int set_signal_voltage_1v8(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int ctrl; ++ void __iomem *pw_reg; ++ ++ pr_debug("%s: set voltage to 180\n", mmc_hostname(host->mmc)); ++ ++ if (priv->devid == 0 || priv->devid == 2) /* device id 2 for sdio1 */ ++ return 0; ++ ++ if (priv->devid == 1) { ++ pw_reg = ioremap(REG_MISC_PWR_SWITCH, 4); /* 4 bytes */ ++ //pw_reg = ioremap_nocache(REG_MISC_PWR_SWITCH, 4); /* 4 bytes */ ++ if (pw_reg == NULL) ++ return -ENOMEM; ++ ctrl = readl(pw_reg); ++ ctrl |= SDIO0_PWRSW_SEL_1V8; ++ writel(ctrl, pw_reg); ++ ++ usleep_range(1000, 2000); /* Sleep between 1000 and 2000us */ ++ ++ ctrl |= SDIO0_IO_MODE_SEL_1V8; ++ writel(ctrl, pw_reg); ++ ++ ctrl = readl(pw_reg); ++ iounmap(pw_reg); ++ ++ if ((ctrl & SDIO0_PWRSW_SEL_1V8) && (ctrl & SDIO0_IO_MODE_SEL_1V8)) ++ return 0; ++ } ++ ++ pr_warn("%s: 1.8V output did not became stable\n", ++ mmc_hostname(host->mmc)); ++ ++ return -EAGAIN; ++} ++ ++static int set_signal_voltage_3v3(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int ctrl; ++ void __iomem *pw_reg; ++ ++ /* sdio1: it is fixed to 1v8, so we fake that 3v3 is ok */ ++ if (priv->devid == 2) /* device id 2 for sdio1 */ ++ return 0; ++ ++ pr_debug("%s: set voltage to 330\n", mmc_hostname(host->mmc)); ++ ++ if (priv->devid == 1) { ++ pw_reg = ioremap(REG_MISC_PWR_SWITCH, 4); /* 4 bytes */ ++ //pw_reg = ioremap_nocache(REG_MISC_PWR_SWITCH, 4); /* 4 bytes */ ++ if (pw_reg == NULL) ++ return -ENOMEM; ++ ctrl = readl(pw_reg); ++ ctrl |= SDIO0_PWR_CTRL_BY_MISC | SDIO0_PWR_EN; ++ ctrl &= ~SDIO0_IO_MODE_SEL_1V8; ++ writel(ctrl, pw_reg); ++ ++ usleep_range(1000, 2000); /* Sleep between 1000 and 2000us */ ++ ++ ctrl &= ~SDIO0_PWRSW_SEL_1V8; ++ writel(ctrl, pw_reg); ++ ++ ctrl = readl(pw_reg); ++ iounmap(pw_reg); ++ ++ if ((ctrl & SDIO0_PWR_CTRL_BY_MISC) ++ && (ctrl & SDIO0_PWR_EN) ++ && !(ctrl & SDIO0_IO_MODE_SEL_1V8) && ++ !(ctrl & SDIO0_PWRSW_SEL_1V8)) ++ return 0; ++ } ++ ++ pr_warn("%s: 3.3V output did not became stable\n", ++ mmc_hostname(host->mmc)); ++ ++ return -EAGAIN; ++} ++ ++int sdhci_bsp_start_signal_voltage_switch(struct sdhci_host *host, ++ struct mmc_ios *ios) ++{ ++ switch (ios->signal_voltage) { ++ case MMC_SIGNAL_VOLTAGE_330: ++ if (!(host->flags & SDHCI_SIGNALING_330)) ++ return -EINVAL; ++ return set_signal_voltage_3v3(host); ++ case MMC_SIGNAL_VOLTAGE_180: ++ if (!(host->flags & SDHCI_SIGNALING_180)) ++ return -EINVAL; ++ return set_signal_voltage_1v8(host); ++ default: ++ /* No signal voltage switch required */ ++ return 0; ++ } ++} ++ ++void bsp_get_phase(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int timing = host->mmc->ios.timing; ++ ++ if (priv->devid == 0) { ++ if (timing == MMC_TIMING_MMC_HS400 || ++ timing == MMC_TIMING_MMC_HS200) ++ priv->sample_phase = priv->tuning_phase; ++ else ++ priv->sample_phase = mmc_phase_cfg[timing][SAMPLE]; ++ ++ priv->drv_phase = mmc_phase_cfg[timing][DRIVE]; ++ } else if (priv->devid == 1) { ++ if (timing == MMC_TIMING_UHS_SDR104 || ++ timing == MMC_TIMING_UHS_SDR50) ++ priv->sample_phase = priv->tuning_phase; ++ else ++ priv->sample_phase = sdio0_phase_cfg[timing][SAMPLE]; ++ ++ priv->drv_phase = sdio0_phase_cfg[timing][DRIVE]; ++ } else if (priv->devid == 2) { /* device id 2 for sdio1 */ ++ if (timing == MMC_TIMING_MMC_HS200 || ++ timing == MMC_TIMING_UHS_SDR104 || ++ timing == MMC_TIMING_UHS_SDR50) ++ priv->sample_phase = priv->tuning_phase; ++ else ++ priv->sample_phase = sdio1_phase_cfg[timing][SAMPLE]; ++ ++ priv->drv_phase = sdio1_phase_cfg[timing][DRIVE]; ++ } ++} ++ ++void bsp_set_drv_phase(struct sdhci_host *host, unsigned int phase) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ if (priv->devid == 0) ++ regmap_write_bits(priv->crg_regmap, PERI_CRG_MMC_DRV_DLL, ++ CRG_DRV_PHASE_SEL_MASK, (phase << CRG_DRV_PHASE_SEL_SHIFT)); ++ else if (priv->devid == 1) ++ regmap_write_bits(priv->crg_regmap, PERI_CRG_SDIO0_DRV_DLL, ++ CRG_DRV_PHASE_SEL_MASK, (phase << CRG_DRV_PHASE_SEL_SHIFT)); ++ else if (priv->devid == 2) /* device id 2 for sdio1 */ ++ regmap_write_bits(priv->crg_regmap, PERI_CRG_SDIO1_DRV_DLL, ++ CRG_DRV_PHASE_SEL_MASK, (phase << CRG_DRV_PHASE_SEL_SHIFT)); ++} ++ ++#ifndef GET_EMMC_BUS_WIDTH_FORM_DTS ++unsigned int get_mmc_bus_width(void) ++{ ++ void __iomem *sys_stat_reg; ++ unsigned int sys_stat; ++ unsigned int bus_width; ++ ++ sys_stat_reg = ioremap_nocache(REG_SYSSTAT, sizeof(sys_stat)); ++ sys_stat = readl(sys_stat_reg); ++ iounmap(sys_stat_reg); ++ ++ if ((sys_stat & BOOT_FLAG_MASK) == BOOT_MEDIA_EMMC) { ++ bus_width = (sys_stat & EMMC_BOOT_8BIT) ? ++ MMC_BUS_WIDTH_8_BIT : MMC_BUS_WIDTH_4_BIT; ++ } else { ++ /* up to 4 bit mode support when spi nand start up */ ++ bus_width = MMC_BUS_WIDTH_4_BIT; ++ } ++ ++ return bus_width; ++} ++ ++void set_mmc_bus_width(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ /* for eMMC devices only */ ++ if (priv->devid == 0) { ++ priv->bus_width = get_mmc_bus_width(); ++ if (priv->bus_width == MMC_BUS_WIDTH_8_BIT) { ++ host->mmc->caps |= MMC_CAP_8_BIT_DATA; ++ host->mmc->caps &= ~MMC_CAP_4_BIT_DATA; ++ } else { ++ host->mmc->caps |= MMC_CAP_4_BIT_DATA; ++ host->mmc->caps &= ~MMC_CAP_8_BIT_DATA; ++ } ++ } ++} ++#endif ++ ++static void sdhci_enhanced_strobe( ++ struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ u16 ctrl; ++ struct sdhci_host *host = mmc_priv(mmc); ++ ++ ctrl = sdhci_readw(host, SDHCI_EMMC_CTRL); ++ if (ios->enhanced_strobe) ++ ctrl |= SDHCI_ENH_STROBE_EN; ++ else ++ ctrl &= ~SDHCI_ENH_STROBE_EN; ++ ++ sdhci_writew(host, ctrl, SDHCI_EMMC_CTRL); ++} ++ ++static void mmc_crg_init(struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct sdhci_bsp_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ ++ reset_control_assert(priv->crg_rst); ++ udelay(25); /* delay 25us */ ++ reset_control_deassert(priv->crg_rst); ++ udelay(10); /* delay 10us */ ++} ++ ++static inline void set_io_mux(struct sdhci_host *host, ++ unsigned int offset, unsigned int pin_mux) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ ++ regmap_write_bits(priv->iocfg_regmap, offset, ++ IO_CFG_MUX_MASK, pin_mux); ++} ++ ++static void mmc_io_mux_config(struct sdhci_host *host) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ unsigned int devid = priv->devid; ++ unsigned int bus_width = priv->bus_width; ++ unsigned int i, pin_mux; ++ ++ pin_mux = devid == 0 ? IO_CFG_EMMC_MUX : IO_CFG_SDIO_MUX; ++ ++ if (devid == 0) { /* eMMC device */ ++ set_io_mux(host, REG_MMC_CLK_IO, IO_CFG_EMMC_MUX); ++ set_io_mux(host, REG_MMC_CMD_IO, IO_CFG_EMMC_MUX); ++ for (i = 0; i < bus_width; i++) ++ set_io_mux(host, reg_mmc_data_io[i], IO_CFG_EMMC_MUX); ++ ++ set_io_mux(host, REG_MMC_RST_IO, IO_CFG_EMMC_MUX); ++ if (bus_width == MMC_BUS_WIDTH_8_BIT) ++ set_io_mux(host, REG_MMC_DQS_IO, IO_CFG_EMMC_MUX); ++ } else if (devid == 1) { ++ set_io_mux(host, REG_SDIO0_DETECT_IO, IO_CFG_SDIO_MUX); ++ set_io_mux(host, REG_SDIO0_PWEN_N, IO_CFG_SDIO_MUX); ++ set_io_mux(host, REG_SDIO0_CLK_IO, IO_CFG_SDIO_MUX); ++ set_io_mux(host, REG_SDIO0_CMD_IO, IO_CFG_SDIO_MUX); ++ for (i = 0; i < bus_width; i++) ++ set_io_mux(host, reg_sdio0_data_io[i], IO_CFG_SDIO_MUX); ++ } ++} ++ ++static int priv_init(struct platform_device *pdev, struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct sdhci_bsp_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ struct device_node *np = pdev->dev.of_node; ++ int rc; ++ ++ priv->crg_rst = devm_reset_control_get(&pdev->dev, "crg_reset"); ++ if (IS_ERR_OR_NULL(priv->crg_rst)) { ++ rc = PTR_ERR(priv->crg_rst); ++ dev_err(&pdev->dev, "get crg_rst failed. %d\n", rc); ++ return PTR_ERR(priv->crg_rst); ++ } ++ ++ priv->dll_rst = devm_reset_control_get(&pdev->dev, "dll_reset"); ++ if (IS_ERR_OR_NULL(priv->dll_rst)) { ++ rc = PTR_ERR(priv->dll_rst); ++ dev_err(&pdev->dev, "get dll_reset failed. %d\n", rc); ++ return PTR_ERR(priv->dll_rst); ++ } ++ ++ priv->sampl_rst = NULL; ++ ++ priv->crg_regmap = syscon_regmap_lookup_by_phandle(np, "crg_regmap"); ++ if (IS_ERR(priv->crg_regmap)) { ++ rc = PTR_ERR(priv->crg_regmap); ++ dev_err(&pdev->dev, "get crg regmap failed. %d\n", rc); ++ return PTR_ERR(priv->crg_regmap); ++ } ++ ++ priv->iocfg_regmap = syscon_regmap_lookup_by_phandle(np, ++ "iocfg_regmap"); ++ if (IS_ERR(priv->iocfg_regmap)) { ++ rc = PTR_ERR(priv->iocfg_regmap); ++ dev_err(&pdev->dev, "get iocfg regmap failed. %d\n", rc); ++ return PTR_ERR(priv->iocfg_regmap); ++ } ++ ++ if (of_property_read_u32(np, "devid", &priv->devid)) { ++ dev_err(mmc_dev(host->mmc), "get devid failed.\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static void sdhci_caps_quirks_init(struct sdhci_host *host) ++{ ++ /* ++ * only eMMC has a hw reset, and now eMMC signaling ++ * is fixed to 180 ++ */ ++ if (host->mmc->caps & MMC_CAP_HW_RESET) { ++ host->flags &= ~SDHCI_SIGNALING_330; ++ host->flags |= SDHCI_SIGNALING_180; ++ } ++ ++ /* ++ * we parse the support timings from dts, so we read the ++ * host capabilities early and clear the timing capabilities, ++ * SDHCI_QUIRK_MISSING_CAPS is set so that sdhci driver would ++ * not read it again ++ */ ++ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); ++ host->caps &= ~(SDHCI_CAN_DO_HISPD | SDHCI_CAN_VDD_300); ++ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); ++ host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | ++ SDHCI_SUPPORT_DDR50 | SDHCI_CAN_DO_ADMA3); ++ host->quirks |= SDHCI_QUIRK_MISSING_CAPS | ++ SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | ++ SDHCI_QUIRK_SINGLE_POWER_WRITE; ++ host->quirks2 &= ~SDHCI_QUIRK2_ACMD23_BROKEN; ++} ++ ++int sdhci_bsp_pltfm_init(struct platform_device *pdev, ++ struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct clk *clk = NULL; ++ int ret; ++ ++ ret = priv_init(pdev, host); ++ if (ret) ++ return ret; ++ ++ ret = resistance_calibration(); ++ if (ret) ++ return ret; ++ ++ clk = devm_clk_get(mmc_dev(host->mmc), "mmc_clk"); ++ if (IS_ERR_OR_NULL(clk)) { ++ dev_err(mmc_dev(host->mmc), "get clk failed.\n"); ++ return -EINVAL; ++ } ++ pltfm_host->clk = clk; ++ ret = clk_prepare_enable(pltfm_host->clk); ++ if (ret) ++ return ret; ++ ++ mmc_crg_init(host); ++ ret = sdhci_bsp_parse_dt(host); ++ if (ret) ++ return ret; ++ ++#ifndef GET_EMMC_BUS_WIDTH_FORM_DTS ++ set_mmc_bus_width(host); ++#endif ++ ++ sdhci_caps_quirks_init(host); ++ host->mmc_host_ops.hs400_enhanced_strobe = sdhci_enhanced_strobe; ++#ifdef OLD419TEST ++ mci_host[slot_index++] = host->mmc; ++#else ++ mci_insert_proc_host(host->mmc); ++#endif ++ /* Initialization pin multiplexing first */ ++ mmc_io_mux_config(host); ++ ++ return 0; ++} ++ ++void sdhci_bsp_set_clock(struct sdhci_host *host, unsigned int clk) ++{ ++ struct sdhci_bsp_priv *priv = sdhci_get_pltfm_priv(host); ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ unsigned int timing = host->mmc->ios.timing; ++ ++ bsp_disable_card_clk(host); ++ udelay(25); /* delay 25us */ ++ bsp_disable_internal_clk(host); ++ ++ if (clk == 0) { ++ host->mmc->actual_clock = 0; ++ return; ++ } ++ ++ clk_set_rate(pltfm_host->clk, clk); ++ host->mmc->actual_clock = clk_get_rate(pltfm_host->clk); ++ ++ bsp_get_phase(host); ++ bsp_set_drv_phase(host, priv->drv_phase); ++ bsp_enable_sample(host); ++ bsp_set_sample_phase(host, priv->sample_phase); ++ ++ udelay(5); /* delay 5us */ ++ ++ bsp_enable_internal_clk(host); ++ ++ if ((timing == MMC_TIMING_MMC_HS400) || ++ (timing == MMC_TIMING_MMC_HS200) || ++ (timing == MMC_TIMING_UHS_SDR104) || ++ (timing == MMC_TIMING_UHS_SDR50)) { ++ reset_control_assert(priv->dll_rst); ++ reset_control_deassert(priv->dll_rst); ++ bsp_wait_p4_dll_lock(host); ++ bsp_wait_sample_dll_ready(host); ++ } ++ ++ if (timing == MMC_TIMING_MMC_HS400) ++ bsp_wait_ds_dll_ready(host); ++ ++ bsp_enable_card_clk(host); ++ udelay(75); /* delay 75us */ ++} ++ ++inline unsigned long sdhci_bsp_get_peri_lock(struct sdhci_host *host) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct sdhci_bsp_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ ++ if (priv->devid != 0) { ++ return bsp_peri_lock(BSP_PERI_SDIO); ++ } ++ ++ return 0; ++} ++ ++inline void sdhci_bsp_put_peri_lock(struct sdhci_host *host, unsigned long flags) ++{ ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct sdhci_bsp_priv *priv = sdhci_pltfm_priv(pltfm_host); ++ ++ if (priv->devid != 0) { ++ bsp_peri_unlock(flags, BSP_PERI_SDIO); ++ } ++} ++ ++void sdhci_bsp_writel(struct sdhci_host *host, u32 val, int reg) ++{ ++ unsigned long flags; ++ ++ flags = sdhci_bsp_get_peri_lock(host); ++ writel(val, host->ioaddr + reg); ++ sdhci_bsp_put_peri_lock(host, flags); ++} ++ ++void sdhci_bsp_writew(struct sdhci_host *host, u16 val, int reg) ++{ ++ unsigned long flags; ++ ++ flags = sdhci_bsp_get_peri_lock(host); ++ writew(val, host->ioaddr + reg); ++ sdhci_bsp_put_peri_lock(host, flags); ++} ++ ++void sdhci_bsp_writeb(struct sdhci_host *host, u8 val, int reg) ++{ ++ unsigned long flags; ++ ++ flags = sdhci_bsp_get_peri_lock(host); ++ writeb(val, host->ioaddr + reg); ++ sdhci_bsp_put_peri_lock(host, flags); ++} ++ ++u32 sdhci_bsp_readl(struct sdhci_host *host, int reg) ++{ ++ u32 val; ++ unsigned long flags; ++ ++ flags = sdhci_bsp_get_peri_lock(host); ++ val = readl(host->ioaddr + reg); ++ sdhci_bsp_put_peri_lock(host, flags); ++ ++ return val; ++} ++ ++u16 sdhci_bsp_readw(struct sdhci_host *host, int reg) ++{ ++ u16 val; ++ unsigned long flags; ++ ++ flags = sdhci_bsp_get_peri_lock(host); ++ val = readw(host->ioaddr + reg); ++ sdhci_bsp_put_peri_lock(host, flags); ++ ++ return val; ++} ++ ++u8 sdhci_bsp_readb(struct sdhci_host *host, int reg) ++{ ++ u8 val; ++ unsigned long flags; ++ ++ flags = sdhci_bsp_get_peri_lock(host); ++ val = readb(host->ioaddr + reg); ++ sdhci_bsp_put_peri_lock(host, flags); ++ ++ return val; ++} ++ ++int bsp_support_runtime_pm(struct sdhci_host *host) ++{ ++ struct mmc_host *mmc = host->mmc; ++ ++ /* only eMMC/SD Card device support runtime_pm */ ++ if (mmc->caps2 & MMC_CAP2_NO_SDIO) ++ return 1; ++ else ++ return 0; ++} +diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c +index 133f0d376480..62015c39cea4 100644 +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -342,6 +342,9 @@ static void sdhci_init(struct sdhci_host *host, int soft) + host->reinit_uhs = true; + mmc->ops->set_ios(mmc, &mmc->ios); + } ++ ++ if (host->ops->init) ++ host->ops->init(host); + } + + static void sdhci_reinit(struct sdhci_host *host) +@@ -2080,6 +2083,12 @@ void sdhci_set_power_noreg(struct sdhci_host *host, unsigned char mode, + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); + if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) + sdhci_runtime_pm_bus_off(host); ++ /* ++ * Controllers need an extra 100ms delay to ensure power off ++ * completely ++ */ ++ msleep(100); ++ + } else { + /* + * Spec says that we should clear the power reg before setting +@@ -2445,7 +2454,9 @@ void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) + } + + /* Re-enable SD Clock */ +- host->ops->set_clock(host, host->clock); ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ clk |= SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + } else + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + +@@ -2586,6 +2597,9 @@ int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, + u16 ctrl; + int ret; + ++ if (host->ops->start_signal_voltage_switch) ++ return host->ops->start_signal_voltage_switch(host, ios); ++ + /* + * Signal Voltage Switching is only applicable for Host Controllers + * v3.00 and above. +@@ -3263,9 +3277,11 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *intmask_p) + */ + if (host->pending_reset) + return; ++#ifndef CONFIG_MMC_SDHCI_NEBULA + pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + sdhci_dumpregs(host); ++#endif + return; + } + +@@ -3393,10 +3409,11 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) + if (host->pending_reset) + return; + ++#ifndef CONFIG_MMC_SDHCI_NEBULA + pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", + mmc_hostname(host->mmc), (unsigned)intmask); + sdhci_dumpregs(host); +- ++#endif + return; + } + +@@ -3860,10 +3877,15 @@ void sdhci_cqe_enable(struct mmc_host *mmc) + { + struct sdhci_host *host = mmc_priv(mmc); + unsigned long flags; ++#ifndef CONFIG_MMC_SDHCI_NEBULA ++#ifndef CONFIG_MMC_SDHCI_BSP + u8 ctrl; +- ++#endif ++#endif + spin_lock_irqsave(&host->lock, flags); + ++#ifndef CONFIG_MMC_SDHCI_NEBULA ++#ifndef CONFIG_MMC_SDHCI_BSP + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_DMA_MASK; + /* +@@ -3881,7 +3903,8 @@ void sdhci_cqe_enable(struct mmc_host *mmc) + + sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, 512), + SDHCI_BLOCK_SIZE); +- ++#endif ++#endif + /* Set maximum timeout */ + sdhci_set_timeout(host, NULL); + +@@ -4856,6 +4879,8 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) + + sdhci_disable_card_detection(host); + ++ free_irq(host->irq, host); ++ + mmc_remove_host(mmc); + + sdhci_led_unregister(host); +@@ -4865,7 +4890,6 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) + + sdhci_writel(host, 0, SDHCI_INT_ENABLE); + sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); +- free_irq(host->irq, host); + + del_timer_sync(&host->timer); + del_timer_sync(&host->data_timer); +diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h +index 4db57c3a8cd4..5b68369378de 100644 +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -185,7 +185,7 @@ + #define SDHCI_CTRL_UHS_SDR50 0x0002 + #define SDHCI_CTRL_UHS_SDR104 0x0003 + #define SDHCI_CTRL_UHS_DDR50 0x0004 +-#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ ++#define SDHCI_CTRL_HS400 0x0007 + #define SDHCI_CTRL_VDD_180 0x0008 + #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 + #define SDHCI_CTRL_DRV_TYPE_B 0x0000 +@@ -284,6 +284,7 @@ + + #define SDHCI_MAX_DIV_SPEC_200 256 + #define SDHCI_MAX_DIV_SPEC_300 2046 ++#define SDHCI_DMA_BOUNDARY_SIZE (0x1 << 27) + + /* + * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2. +@@ -360,12 +361,27 @@ enum sdhci_cookie { + COOKIE_MAPPED, /* mapped by sdhci_prepare_data() */ + }; + ++struct card_info { ++ unsigned int card_type; ++ unsigned char timing; ++ bool enhanced_strobe; ++ unsigned char card_connect; ++#define CARD_CONNECT 1 ++#define CARD_DISCONNECT 0 ++ unsigned int card_support_clock; /* clock rate */ ++ unsigned int card_state; /* (our) card state */ ++ unsigned int sd_bus_speed; ++ unsigned int ssr[16]; ++}; ++ + struct sdhci_host { + /* Data set by hardware interface driver */ + const char *hw_name; /* Hardware bus name */ + + unsigned int quirks; /* Deviations from spec. */ +- ++ ++ struct card_info c_info; ++ u32 is_tuning; + /* Controller doesn't honor resets unless we touch the clock register */ + #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0) + /* Controller has bad caps bits, but really supports DMA */ +@@ -609,6 +625,8 @@ struct sdhci_host { + u32 adma_table_cnt; + + u64 data_timeout; ++ ++ unsigned int error_count; + + unsigned long private[] ____cacheline_aligned; + }; +@@ -657,6 +675,14 @@ struct sdhci_ops { + void (*request_done)(struct sdhci_host *host, + struct mmc_request *mrq); + void (*dump_vendor_regs)(struct sdhci_host *host); ++ void (*init)(struct sdhci_host *host); ++#ifdef OLD419TEST ++ int (*signal_voltage_switch)(struct sdhci_host *host, ++ struct mmc_ios *ios); ++#else ++ int (*start_signal_voltage_switch)(struct sdhci_host *host, ++ struct mmc_ios *ios); ++#endif + }; + + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS +diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig +index 48c9601adf2e..33257f23f861 100644 +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -44,6 +44,7 @@ source "drivers/net/ethernet/chelsio/Kconfig" + source "drivers/net/ethernet/cirrus/Kconfig" + source "drivers/net/ethernet/cisco/Kconfig" + source "drivers/net/ethernet/cortina/Kconfig" ++source "drivers/net/ethernet/vendor/Kconfig" + + config CX_ECAT + tristate "Beckhoff CX5020 EtherCAT master support" +diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile +index d637fd528a14..47c6df4f19ef 100644 +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -98,3 +98,4 @@ obj-$(CONFIG_NET_VENDOR_SYNOPSYS) += synopsys/ + obj-$(CONFIG_NET_VENDOR_PENSANDO) += pensando/ + obj-$(CONFIG_NET_VENDOR_NETSWIFT) += netswift/ + obj-$(CONFIG_NET_VENDOR_NEBULA_MATRIX) += nebula-matrix/ ++obj-$(CONFIG_NET_VENDOR_VENDOR) += vendor/ +diff --git a/drivers/net/ethernet/vendor/Kconfig b/drivers/net/ethernet/vendor/Kconfig +new file mode 100644 +index 000000000000..c0e4e42161e2 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/Kconfig +@@ -0,0 +1,20 @@ ++# ++# VENDOR device configuration ++# ++ ++config NET_VENDOR_VENDOR ++ bool "Vendor devices" ++ default y ++ depends on OF || ACPI ++ depends on ARM || ARM64 || COMPILE_TEST ++ help ++ If you have a network (Ethernet) card belonging to this class, say Y. ++ ++ Note that the answer to this question doesn't directly affect the ++ kernel: saying N will just cause the configurator to skip all ++ the questions about Vendor devices. If you say Y, you will be asked ++ for your specific card in the following questions. ++ ++if NET_VENDOR_VENDOR ++source "drivers/net/ethernet/vendor/gmac/Kconfig" ++endif # NET_VENDOR_VENDOR +diff --git a/drivers/net/ethernet/vendor/Makefile b/drivers/net/ethernet/vendor/Makefile +new file mode 100644 +index 000000000000..59540a62a016 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/Makefile +@@ -0,0 +1,6 @@ ++# SPDX-License-Identifier: GPL-2.0 ++# ++# Makefile for the VENDOR network device drivers. ++# ++ ++obj-$(CONFIG_ETH_GMAC) += gmac/ +diff --git a/drivers/net/ethernet/vendor/gmac/Kconfig b/drivers/net/ethernet/vendor/gmac/Kconfig +new file mode 100644 +index 000000000000..4e2bb132dc48 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/Kconfig +@@ -0,0 +1,106 @@ ++# ++# gmac family network device configuration ++# ++ ++menuconfig ETH_GMAC ++ tristate "eth gmac family network device support" ++ select PHYLIB ++ select RESET_CONTROLLER ++ help ++ This selects the eth gmac family network device. ++ The gigabit switch fabric (GSF) receives and transmits data over Ethernet ++ ports at 10/100/1000 Mbit/s in full-duplex or half-duplex mode. ++ The Ethernet port exchanges data with the CPU port, and supports ++ the energy efficient Ethernet (EEE) and wake on LAN (WoL) functions. ++ ++if ETH_GMAC ++ ++config GMAC_DDR_64BIT ++ bool "gmac ddr width 64 bit" ++ depends on ARM64 ++ default n ++ help ++ This define the gmac supports DDR width 64 bit. ++ In the newest version, the DDR size may be 8G. ++ But in old version, the gmac only supports DDR width 32 bit. ++ The default value is false. ++ ++config GMAC_DESC_4WORD ++ bool "gmac descriptor size is 4 words" ++ default y ++ help ++ This define the size of gmac descriptor structure. ++ In the newest version, descriptor size is 4 words. ++ But in some old version, the size is 8 words. ++ The default value is true. ++ ++config GMAC_RXCSUM ++ bool "gmac Receive checksumming offload supported" ++ default y ++ help ++ This indicate MAC support Receive checksumming offload. ++ Support IPv4 and IPv6, tcp and udp. ++ The default value is enabled. ++ If old version MAC does not support, disable this option please. ++ ++config RX_FLOW_CTRL_SUPPORT ++ bool "rx flow ctrl supported" ++ default y ++ help ++ Rx flow ctrl supported, default is enabled. ++ When we received pause frame, ++ we will stop transmiting data frame for some time. ++ The stopping time is the time filled in pause frame. ++ ++config TX_FLOW_CTRL_SUPPORT ++ bool "tx flow ctrl supported" ++ default y ++ help ++ Tx flow ctrl supported, default is enabled. ++ When we has no buffer to receive packet, ++ we will send pause frame. ++ When buffer is available, we will send zero-quanta pause frame. ++ ++config TX_FLOW_CTRL_PAUSE_TIME ++ hex "tx flow ctrl pause time" ++ default "0xFFFF" ++ help ++ The pause time filled in the sending pause frame. ++ The unit is the time for transmiting 512 bit data. ++ This value is 16 bit, so its value is 0x0000~0xFFFF. ++ The default value is 0xFFFF. ++ ++config TX_FLOW_CTRL_PAUSE_INTERVAL ++ hex "tx flow ctrl pause interval" ++ default "0xFFFF" ++ help ++ The interval time for sending pause frame. ++ When the remainint amount of receive queue is below tx flow ctrl active threshold, ++ we will wait this time to transmiting pause frame. ++ The unit is the time for transmiting 512 bit data. ++ This value is 16 bit, so its value is 0x0000~0xFFFF. ++ The default value is 0xFFFF. ++ ++config TX_FLOW_CTRL_ACTIVE_THRESHOLD ++ int "tx flow ctrl active threshold" ++ default "16" ++ range 1 127 ++ help ++ The threshold for activing tx flow ctrl. ++ When the left amount of receive queue descriptors is below this threshold, ++ hardware will send pause frame immediately. ++ We advise this value is set smaller than 64. Too bigger is not a good choice. ++ This value must be smaller than tx flow ctrl deactive threshold. ++ ++config TX_FLOW_CTRL_DEACTIVE_THRESHOLD ++ int "tx flow ctrl deactive threshold" ++ default "32" ++ range 1 127 ++ help ++ The threshold for deactiving tx flow ctrl. ++ When the left amount of receive queue descriptors is above or equal with this threshold, ++ hardware will exit flow control state. ++ We advise this value is set smaller than 64. Too bigger is not a good choice. ++ This value must be larger than tx flow ctrl active threshold. ++ ++endif # ETH_GMAC +diff --git a/drivers/net/ethernet/vendor/gmac/Makefile b/drivers/net/ethernet/vendor/gmac/Makefile +new file mode 100644 +index 000000000000..90d5a73b792e +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_ETH_GMAC) += eth_gmac.o ++eth_gmac-objs := gmac.o gmac_ethtool_ops.o gmac_phy_fixup.o gmac_pm.o gmac_proc.o gmac_netdev_ops.o autoeee/autoeee.o autoeee/phy_id_table.o +diff --git a/drivers/net/ethernet/vendor/gmac/autoeee/autoeee.c b/drivers/net/ethernet/vendor/gmac/autoeee/autoeee.c +new file mode 100644 +index 000000000000..33bd74fff65a +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/autoeee/autoeee.c +@@ -0,0 +1,137 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include "autoeee.h" ++#include "../gmac.h" ++#include ++#include ++ ++static u32 set_link_stat(struct gmac_netdev_local const *ld) ++{ ++ u32 link_stat = 0; ++ ++ switch (ld->phy->speed) { ++ case SPEED_10: ++ link_stat |= GMAC_SPD_10M; ++ break; ++ case SPEED_100: ++ link_stat |= GMAC_SPD_100M; ++ break; ++ case SPEED_1000: ++ link_stat |= GMAC_SPD_1000M; ++ break; ++ default: ++ break; ++ } ++ return link_stat; ++} ++ ++static void set_eee_clk(struct gmac_netdev_local const *ld, u32 phy_id) ++{ ++ u32 v; ++ ++ if ((phy_id & REALTEK_PHY_MASK) == REALTEK_PHY_ID_8211E) { ++ v = readl(ld->gmac_iobase + EEE_CLK); ++ v &= ~MASK_EEE_CLK; ++ v |= BIT_DISABLE_TX_CLK; ++ writel(v, ld->gmac_iobase + EEE_CLK); ++ } else if ((phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9031) { ++ v = readl(ld->gmac_iobase + EEE_CLK); ++ v &= ~MASK_EEE_CLK; ++ v |= (BIT_DISABLE_TX_CLK | BIT_PHY_KSZ9031); ++ writel(v, ld->gmac_iobase + EEE_CLK); ++ } ++} ++ ++static void enable_eee(struct gmac_netdev_local const *ld) ++{ ++ u32 v; ++ ++ /* EEE_1us: 0x7c for 125M */ ++ writel(0x7c, ld->gmac_iobase + ++ EEE_TIME_CLK_CNT); ++ writel(0x1e0400, ld->gmac_iobase + EEE_TIMER); ++ ++ v = readl(ld->gmac_iobase + EEE_LINK_STATUS); ++ v |= 0x3 << 1; /* auto EEE and ... */ ++ v |= BIT_PHY_LINK_STATUS; /* phy linkup */ ++ writel(v, ld->gmac_iobase + EEE_LINK_STATUS); ++ ++ v = readl(ld->gmac_iobase + EEE_ENABLE); ++ v |= BIT_EEE_ENABLE; /* enable EEE */ ++ writel(v, ld->gmac_iobase + EEE_ENABLE); ++} ++ ++static void set_phy_eee_mode(struct gmac_netdev_local const *ld) ++{ ++ u32 v; ++ if (netif_msg_wol(ld)) ++ pr_info("enter phy-EEE mode\n"); ++ ++ v = readl(ld->gmac_iobase + EEE_ENABLE); ++ v &= ~BIT_EEE_ENABLE; /* disable auto-EEE */ ++ writel(v, ld->gmac_iobase + EEE_ENABLE); ++} ++ ++void init_autoeee(struct gmac_netdev_local *ld) ++{ ++ int phy_id; ++ int eee_available, lp_eee_capable; ++ u32 v, link_stat; ++ struct phy_info *phy_info = NULL; ++ if (ld == NULL || ld->eee_init == NULL || ld->phy == NULL) ++ return; ++ phy_id = ld->phy->phy_id; ++ if (ld->eee_init != NULL) ++ goto eee_init; ++ ++ phy_info = phy_search_ids(phy_id); ++ if (phy_info == NULL) ++ goto not_support; ++ ++ eee_available = phy_info->eee_available; ++ if (netif_msg_wol(ld) && phy_info->name != NULL) ++ pr_info("fit phy_id:0x%x, phy_name:%s, eee:%d\n", ++ phy_info->phy_id, phy_info->name, eee_available); ++ ++ if (!eee_available) ++ goto not_support; ++ ++ if (eee_available == PHY_EEE) { ++ set_phy_eee_mode(ld); ++ return; ++ } ++ ++ ld->eee_init = phy_info->eee_init; ++eee_init: ++ link_stat = set_link_stat(ld); ++ ++ lp_eee_capable = ld->eee_init(ld->phy); ++ if (lp_eee_capable < 0) ++ return; ++ ++ if (ld->phy->link) { ++ if (((u32)lp_eee_capable) & link_stat) { ++ set_eee_clk(ld, phy_id); ++ enable_eee(ld); ++ ++ if (netif_msg_wol(ld)) ++ pr_info("enter auto-EEE mode\n"); ++ } else { ++ if (netif_msg_wol(ld)) ++ pr_info("link partner not support EEE\n"); ++ } ++ } else { ++ v = readl(ld->gmac_iobase + EEE_LINK_STATUS); ++ v &= ~(BIT_PHY_LINK_STATUS); /* phy linkdown */ ++ writel(v, ld->gmac_iobase + EEE_LINK_STATUS); ++ } ++ ++ return; ++ ++not_support: ++ ld->eee_init = NULL; ++ if (netif_msg_wol(ld)) ++ pr_info("non-EEE mode\n"); ++} +diff --git a/drivers/net/ethernet/vendor/gmac/autoeee/autoeee.h b/drivers/net/ethernet/vendor/gmac/autoeee/autoeee.h +new file mode 100644 +index 000000000000..924cc604b3f4 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/autoeee/autoeee.h +@@ -0,0 +1,49 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef _AUTO_EEE_H ++#define _AUTO_EEE_H ++ ++#include "../gmac.h" ++ ++#define NO_EEE 0 ++#define MAC_EEE 1 ++#define PHY_EEE 2 ++#define PARTNER_EEE 2 ++ ++struct phy_info { ++ char *name; ++ int phy_id; ++ char eee_available; /* eee support by this phy */ ++ int (*eee_init)(struct phy_device *phy_dev); ++}; ++ ++/* GMAC register definition */ ++#define EEE_CLK 0x800 ++#define MASK_EEE_CLK (0x3 << 20) ++#define BIT_DISABLE_TX_CLK BIT(21) ++#define BIT_PHY_KSZ9031 BIT(20) ++#define EEE_ENABLE 0x808 ++#define BIT_EEE_ENABLE BIT(0) ++#define EEE_TIMER 0x80C ++#define EEE_LINK_STATUS 0x810 ++#define BIT_PHY_LINK_STATUS BIT(0) ++#define EEE_TIME_CLK_CNT 0x814 ++ ++/* ----------------------------phy register-------------------------------*/ ++/* MMD: MDIO Manageable Device */ ++#define MACR 0x0D ++#define MAADR 0x0E ++#define EEE_DEV 0x3 ++#define EEE_CAPABILITY 0x14 ++#define EEELPAR_DEV 0x7 ++#define EEELPAR 0x3D /* EEE link partner ability register */ ++#define EEE_ADVERTISE 0x3c ++#define LP_1000BASE_EEE BIT(2) ++#define LP_100BASE_EEE BIT(1) ++ ++struct phy_info *phy_search_ids(int phy_id); ++void init_autoeee(struct gmac_netdev_local *ld); ++ ++#endif +diff --git a/drivers/net/ethernet/vendor/gmac/autoeee/phy_id_table.c b/drivers/net/ethernet/vendor/gmac/autoeee/phy_id_table.c +new file mode 100644 +index 000000000000..848f0112ede5 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/autoeee/phy_id_table.c +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include "../gmac.h" ++#include "autoeee.h" ++ ++struct phy_info phy_info_table[]; ++ ++struct phy_info *phy_search_ids(int phy_id) ++{ ++ int i; ++ struct phy_info *fit_info = NULL; ++ ++ for (i = 0; phy_info_table[i].name; i++) { ++ if (phy_id == phy_info_table[i].phy_id) { ++ fit_info = &phy_info_table[i]; ++ break; ++ } ++ } ++ ++ return fit_info; ++} ++ ++static inline int phy_mmd_read(struct phy_device *phy_dev, ++ u32 mmd_device, u32 regnum) ++{ ++ phy_write(phy_dev, MACR, mmd_device); /* function = 00 address */ ++ phy_write(phy_dev, MAADR, regnum); ++ phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */ ++ ++ return phy_read(phy_dev, MAADR); ++} ++ ++static inline int phy_mmd_write(struct phy_device *phy_dev, u32 mmd_device, ++ u32 regnum, u16 val) ++{ ++ phy_write(phy_dev, MACR, mmd_device); /* function = 00 address */ ++ phy_write(phy_dev, MAADR, regnum); ++ phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */ ++ ++ return phy_write(phy_dev, MAADR, val); ++} ++ ++static int smsc_lan8740_init(struct phy_device *phy_dev) ++{ ++ static int first_time = 0; ++ int v; ++ u32 eee_type = 0; ++ ++ if (!first_time) { ++ /* Realtek LAN 8740 start to enable eee */ ++ int eee_lan; ++ ++ eee_lan = phy_read(phy_dev, 0x10); ++ if (eee_lan < 0) ++ return eee_lan; ++ eee_lan = (u32)eee_lan | 0x4; ++ phy_write(phy_dev, 0x10, eee_lan); ++ eee_lan = phy_read(phy_dev, 0x10); ++ if (eee_lan < 0) ++ return eee_lan; ++ /* auto negotiate after enable eee */ ++ eee_lan = phy_read(phy_dev, 0x0); ++ if (eee_lan < 0) ++ return eee_lan; ++ eee_lan = (u32)eee_lan | 0x200; ++ phy_write(phy_dev, 0x0, eee_lan); ++ first_time = 1; ++ } ++ ++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR); ++ if ((u32)v & LP_1000BASE_EEE) ++ eee_type |= GMAC_SPD_1000M; ++ if ((u32)v & LP_100BASE_EEE) ++ eee_type |= GMAC_SPD_100M; ++ ++ return (int)eee_type; ++} ++ ++#define RTL8211EG_MAC 0 ++#if RTL8211EG_MAC ++static int rtl8211eg_mac_init(struct phy_device *phy_dev) ++{ ++ static int first_time = 0; ++ /* Realtek 8211EG start reset to change eee to mac */ ++ int v; ++ u32 eee_type = 0; ++ ++ if (!first_time) { ++ int tmp; ++ ++ phy_write(phy_dev, 0x1f, 0x0); ++ phy_write(phy_dev, MII_BMCR, BMCR_RESET); /* reset phy */ ++ do { /* wait phy restart over */ ++ udelay(1); ++ tmp = phy_read(phy_dev, MII_BMSR); ++ /* no need to wait AN finished */ ++ tmp &= (BMSR_ANEGCOMPLETE | BMSR_ANEGCAPABLE); ++ } while (!tmp); ++ ++ phy_write(phy_dev, 0x1f, 0x7); ++ phy_write(phy_dev, 0x1e, 0x20); ++ phy_write(phy_dev, 0x1b, 0xa03a); ++ phy_write(phy_dev, 0x1f, 0x0); ++ ++ first_time = 1; ++ } ++ ++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR); ++ if ((u32)v & LP_1000BASE_EEE) ++ eee_type |= GMAC_SPD_1000M; ++ if ((u32)v & LP_100BASE_EEE) ++ eee_type |= GMAC_SPD_100M; ++ ++ return (int)eee_type; ++} ++#else ++static int rtl8211eg_init(struct phy_device *phy_dev) ++{ ++ u32 eee_type = 0; ++ u32 v; ++ ++ v = (u32)phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR); ++ if (v & LP_1000BASE_EEE) ++ eee_type |= GMAC_SPD_1000M; ++ if (v & LP_100BASE_EEE) ++ eee_type |= GMAC_SPD_100M; ++ ++ return (int)eee_type; ++} ++#endif ++ ++static int festa_v200_init(struct phy_device *phy_dev) ++{ ++ static int first_time_init = 0; ++ int v; ++ u32 eee_type = 0; ++ ++ if (!first_time_init) { ++ /* EEE_CAPABILITY register: support 100M-BaseT */ ++ v = phy_mmd_read(phy_dev, EEE_DEV, EEE_CAPABILITY); ++ phy_mmd_write(phy_dev, EEE_DEV, EEE_CAPABILITY, ++ ((u32)v) | BIT(1)); ++ ++ /* EEE_ADVERTISEMENT register: advertising 100M-BaseT */ ++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEE_ADVERTISE); ++ phy_mmd_write(phy_dev, EEELPAR_DEV, EEE_ADVERTISE, ++ ((u32)v) | BIT(1)); ++ ++ v = phy_read(phy_dev, MII_BMCR); ++ if (v < 0) ++ return v; ++ v = (u32)v | (BMCR_ANENABLE | BMCR_ANRESTART); ++ phy_write(phy_dev, MII_BMCR, v); /* auto-neg restart */ ++ ++ first_time_init = 1; ++ } ++ ++ v = phy_mmd_read(phy_dev, EEELPAR_DEV, EEELPAR); ++ if ((u32)v & LP_1000BASE_EEE) ++ eee_type |= GMAC_SPD_1000M; ++ if ((u32)v & LP_100BASE_EEE) ++ eee_type |= GMAC_SPD_100M; ++ ++ return (int)eee_type; ++} ++ ++struct phy_info phy_info_table[] = { ++ /* phy_name phy_id eee_available phy_driver */ ++ {"SMSC LAN8740", 0x0007c110, MAC_EEE, &smsc_lan8740_init}, ++#if RTL8211EG_MAC ++ {"Realtek 8211EG", 0x001cc915, MAC_EEE, &rtl8211eg_mac_init}, ++#else ++ {"Realtek 8211EG", 0x001cc915, PHY_EEE, &rtl8211eg_init}, ++#endif ++ {"Festa V200", VENDOR_PHY_ID_FESTAV200, MAC_EEE, &festa_v200_init}, ++}; +diff --git a/drivers/net/ethernet/vendor/gmac/gmac.c b/drivers/net/ethernet/vendor/gmac/gmac.c +new file mode 100644 +index 000000000000..bf476144c2af +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac.c +@@ -0,0 +1,2289 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "autoeee/autoeee.h" ++#include "gmac_ethtool_ops.h" ++#include "gmac_netdev_ops.h" ++#include "gmac_phy_fixup.h" ++#include "gmac_pm.h" ++#include "gmac_proc.h" ++#include "gmac.h" ++ ++#define has_tso_cap(hw_cap) ((((hw_cap) >> 28) & 0x3) == VER_TSO) ++#define has_rxhash_cap(hw_cap) ((hw_cap) & BIT(30)) ++#define has_rss_cap(hw_cap) ((hw_cap) & BIT(31)) ++ ++#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) ++static int debug = -1; ++module_param(debug, int, 0000); ++MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); ++ ++static void gmac_set_desc_depth(struct gmac_netdev_local const *priv, ++ u32 rx, u32 tx) ++{ ++ u32 reg, val; ++ int i; ++ ++ writel(BITS_RX_FQ_DEPTH_EN, priv->gmac_iobase + RX_FQ_REG_EN); ++ val = readl(priv->gmac_iobase + RX_FQ_DEPTH); ++ val &= ~Q_ADDR_HI8_MASK; ++ val |= rx << DESC_WORD_SHIFT; ++ writel(val, priv->gmac_iobase + RX_FQ_DEPTH); ++ writel(0, priv->gmac_iobase + RX_FQ_REG_EN); ++ ++ writel(BITS_RX_BQ_DEPTH_EN, priv->gmac_iobase + RX_BQ_REG_EN); ++ val = readl(priv->gmac_iobase + RX_BQ_DEPTH); ++ val &= ~Q_ADDR_HI8_MASK; ++ val |= rx << DESC_WORD_SHIFT; ++ writel(val, priv->gmac_iobase + RX_BQ_DEPTH); ++ for (i = 1; i < priv->num_rxqs; i++) { ++ reg = rx_bq_depth_queue(i); ++ val = readl(priv->gmac_iobase + reg); ++ val &= ~Q_ADDR_HI8_MASK; ++ val |= rx << DESC_WORD_SHIFT; ++ writel(val, priv->gmac_iobase + reg); ++ } ++ writel(0, priv->gmac_iobase + RX_BQ_REG_EN); ++ ++ writel(BITS_TX_BQ_DEPTH_EN, priv->gmac_iobase + TX_BQ_REG_EN); ++ val = readl(priv->gmac_iobase + TX_BQ_DEPTH); ++ val &= ~Q_ADDR_HI8_MASK; ++ val |= tx << DESC_WORD_SHIFT; ++ writel(val, priv->gmac_iobase + TX_BQ_DEPTH); ++ writel(0, priv->gmac_iobase + TX_BQ_REG_EN); ++ ++ writel(BITS_TX_RQ_DEPTH_EN, priv->gmac_iobase + TX_RQ_REG_EN); ++ val = readl(priv->gmac_iobase + TX_RQ_DEPTH); ++ val &= ~Q_ADDR_HI8_MASK; ++ val |= tx << DESC_WORD_SHIFT; ++ writel(val, priv->gmac_iobase + TX_RQ_DEPTH); ++ writel(0, priv->gmac_iobase + TX_RQ_REG_EN); ++} ++ ++static void gmac_set_rx_fq(struct gmac_netdev_local const *priv, ++ dma_addr_t phy_addr) ++{ ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ u32 val; ++#endif ++ writel(BITS_RX_FQ_START_ADDR_EN, priv->gmac_iobase + RX_FQ_REG_EN); ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ val = readl(priv->gmac_iobase + RX_FQ_DEPTH); ++ val &= Q_ADDR_HI8_MASK; ++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET; ++ writel(val, priv->gmac_iobase + RX_FQ_DEPTH); ++#endif ++ writel((u32)phy_addr, priv->gmac_iobase + RX_FQ_START_ADDR); ++ writel(0, priv->gmac_iobase + RX_FQ_REG_EN); ++} ++ ++static void gmac_set_rx_bq(struct gmac_netdev_local const *priv, ++ dma_addr_t phy_addr) ++{ ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ u32 val; ++#endif ++ ++ /* ++ * Logical limitation: We must enable BITS_RX_BQ_DEPTH_EN ++ * to write rx_bq_start_addr_39to32 successfully. ++ */ ++ writel(BITS_RX_BQ_START_ADDR_EN | BITS_RX_BQ_DEPTH_EN, priv->gmac_iobase + RX_BQ_REG_EN); ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ val = readl(priv->gmac_iobase + RX_BQ_DEPTH); ++ val &= Q_ADDR_HI8_MASK; ++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET; ++ writel(val, priv->gmac_iobase + RX_BQ_DEPTH); ++#endif ++ writel((u32)phy_addr, priv->gmac_iobase + RX_BQ_START_ADDR); ++ writel(0, priv->gmac_iobase + RX_BQ_REG_EN); ++} ++ ++static void gmac_set_tx_bq(struct gmac_netdev_local const *priv, ++ dma_addr_t phy_addr) ++{ ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ u32 val; ++#endif ++ writel(BITS_TX_BQ_START_ADDR_EN, priv->gmac_iobase + TX_BQ_REG_EN); ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ val = readl(priv->gmac_iobase + TX_BQ_DEPTH); ++ val &= Q_ADDR_HI8_MASK; ++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET; ++ writel(val, priv->gmac_iobase + TX_BQ_DEPTH); ++#endif ++ writel((u32)phy_addr, priv->gmac_iobase + TX_BQ_START_ADDR); ++ writel(0, priv->gmac_iobase + TX_BQ_REG_EN); ++} ++ ++static void gmac_set_tx_rq(struct gmac_netdev_local const *priv, ++ dma_addr_t phy_addr) ++{ ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ u32 val; ++#endif ++ writel(BITS_TX_RQ_START_ADDR_EN, priv->gmac_iobase + TX_RQ_REG_EN); ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ val = readl(priv->gmac_iobase + TX_RQ_DEPTH); ++ val &= Q_ADDR_HI8_MASK; ++ val |= (phy_addr >> REG_BIT_WIDTH) << Q_ADDR_HI8_OFFSET; ++ writel(val, priv->gmac_iobase + TX_RQ_DEPTH); ++#endif ++ writel((u32)phy_addr, priv->gmac_iobase + TX_RQ_START_ADDR); ++ writel(0, priv->gmac_iobase + TX_RQ_REG_EN); ++} ++ ++static void gmac_hw_set_desc_addr(struct gmac_netdev_local const *priv) ++{ ++ u32 reg; ++ int i; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ u32 val; ++#endif ++ ++ gmac_set_rx_fq(priv, priv->RX_FQ.phys_addr); ++ gmac_set_rx_bq(priv, priv->RX_BQ.phys_addr); ++ gmac_set_tx_rq(priv, priv->TX_RQ.phys_addr); ++ gmac_set_tx_bq(priv, priv->TX_BQ.phys_addr); ++ ++ for (i = 1; i < priv->num_rxqs; i++) { ++ reg = rx_bq_depth_queue(i); ++ writel(BITS_RX_BQ_START_ADDR_EN, ++ priv->gmac_iobase + RX_BQ_REG_EN); ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ val = readl(priv->gmac_iobase + reg); ++ val &= Q_ADDR_HI8_MASK; ++ val |= ((priv->pool[BASE_QUEUE_NUMS + i].phys_addr) >> REG_BIT_WIDTH) << ++ Q_ADDR_HI8_OFFSET; ++ writel(val, priv->gmac_iobase + reg); ++#endif ++ reg = (u32)rx_bq_start_addr_queue(i); ++ /* pool 3 add i */ ++ writel((u32)(priv->pool[BASE_QUEUE_NUMS + i].phys_addr), ++ priv->gmac_iobase + reg); ++ writel(0, priv->gmac_iobase + RX_BQ_REG_EN); ++ } ++} ++ ++static void gmac_set_rss_cap(struct gmac_netdev_local const *priv) ++{ ++ u32 val = 0; ++ ++ if (priv->has_rxhash_cap) ++ val |= BIT_RXHASH_CAP; ++ if (priv->has_rss_cap) ++ val |= BIT_RSS_CAP; ++ writel(val, priv->gmac_iobase + HW_CAP_EN); ++} ++ ++static void gmac_hw_init(struct gmac_netdev_local *priv) ++{ ++ u32 val; ++ u32 reg; ++ int i; ++ ++ /* disable and clear all interrupts */ ++ writel(0, priv->gmac_iobase + ENA_PMU_INT); ++ writel(~0, priv->gmac_iobase + RAW_PMU_INT); ++ ++ for (i = 1; i < priv->num_rxqs; i++) { ++ reg = (u32)rss_ena_int_queue(i); ++ writel(0, priv->gmac_iobase + reg); ++ } ++ writel(~0, priv->gmac_iobase + RSS_RAW_PMU_INT); ++ ++ /* enable CRC erro packets filter */ ++ val = readl(priv->gmac_iobase + REC_FILT_CONTROL); ++ val |= BIT_CRC_ERR_PASS; ++ writel(val, priv->gmac_iobase + REC_FILT_CONTROL); ++ ++ /* set tx min packet length */ ++ val = readl(priv->gmac_iobase + CRF_MIN_PACKET); ++ val &= ~BIT_MASK_TX_MIN_LEN; ++ val |= ETH_HLEN << BIT_OFFSET_TX_MIN_LEN; ++ writel(val, priv->gmac_iobase + CRF_MIN_PACKET); ++ ++ /* fix bug for udp and ip error check */ ++ writel(CONTROL_WORD_CONFIG, priv->gmac_iobase + CONTROL_WORD); ++ ++ writel(0, priv->gmac_iobase + COL_SLOT_TIME); ++ ++ writel(DUPLEX_HALF, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL); ++ ++ /* interrupt when rcv packets >= RX_BQ_INT_THRESHOLD */ ++ val = RX_BQ_INT_THRESHOLD | ++ (TX_RQ_INT_THRESHOLD << BITS_OFFSET_TX_RQ_IN_TH); ++ writel(val, priv->gmac_iobase + IN_QUEUE_TH); ++ ++ /* RX_BQ/TX_RQ in timeout threshold */ ++ writel(0x10000, priv->gmac_iobase + RX_BQ_IN_TIMEOUT_TH); ++ ++ writel(0x18000, priv->gmac_iobase + TX_RQ_IN_TIMEOUT_TH); ++ ++ gmac_set_desc_depth(priv, RX_DESC_NUM, TX_DESC_NUM); ++} ++ ++/* ++ * the func stop the hw desc and relaim the software skb resource ++ * before reusing the gmac, you'd better reset the gmac ++ */ ++static void gmac_reclaim_rx_tx_resource(struct gmac_netdev_local *ld) ++{ ++ unsigned long rxflags, txflags; ++ int rd_offset, wr_offset; ++ int i; ++ ++ if (ld == NULL) ++ return; ++ ++ gmac_irq_disable_all_queue(ld); ++ gmac_hw_desc_disable(ld); ++ writel(STOP_RX_TX, ld->gmac_iobase + STOP_CMD); ++ ++ spin_lock_irqsave(&ld->rxlock, rxflags); ++ /* RX_BQ: logic write pointer */ ++ wr_offset = readl(ld->gmac_iobase + RX_BQ_WR_ADDR); ++ /* prevent to reclaim skb in rx bottom half */ ++ writel(wr_offset, ld->gmac_iobase + RX_BQ_RD_ADDR); ++ ++ for (i = 1; i < ld->num_rxqs; i++) { ++ u32 rx_bq_wr_reg, rx_bq_rd_reg; ++ ++ rx_bq_wr_reg = rx_bq_wr_addr_queue(i); ++ rx_bq_rd_reg = rx_bq_rd_addr_queue(i); ++ ++ wr_offset = readl(ld->gmac_iobase + rx_bq_wr_reg); ++ writel(wr_offset, ld->gmac_iobase + rx_bq_rd_reg); ++ } ++ ++ /* RX_FQ: logic read pointer */ ++ rd_offset = readl(ld->gmac_iobase + RX_FQ_RD_ADDR); ++ if (rd_offset == 0) ++ rd_offset = (RX_DESC_NUM - 1) << DESC_BYTE_SHIFT; ++ else ++ rd_offset -= DESC_SIZE; ++ /* stop to feed hw desc */ ++ writel(rd_offset, ld->gmac_iobase + RX_FQ_WR_ADDR); ++ ++ for (i = 0; i < ld->RX_FQ.count; i++) { ++ if (!ld->RX_FQ.skb[i]) ++ ld->RX_FQ.skb[i] = SKB_MAGIC; ++ } ++ spin_unlock_irqrestore(&ld->rxlock, rxflags); ++ ++ /* ++ * no need to wait pkts in TX_RQ finish to free all skb, ++ * because gmac_xmit_reclaim is in the tx_lock, ++ */ ++ spin_lock_irqsave(&ld->txlock, txflags); ++ /* TX_RQ: logic write */ ++ wr_offset = readl(ld->gmac_iobase + TX_RQ_WR_ADDR); ++ /* stop to reclaim tx skb */ ++ writel(wr_offset, ld->gmac_iobase + TX_RQ_RD_ADDR); ++ ++ /* TX_BQ: logic read */ ++ rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR); ++ if (rd_offset == 0) ++ rd_offset = (TX_DESC_NUM - 1) << DESC_BYTE_SHIFT; ++ else ++ rd_offset -= DESC_SIZE; ++ /* stop software tx skb */ ++ writel(rd_offset, ld->gmac_iobase + TX_BQ_WR_ADDR); ++ ++ for (i = 0; i < ld->TX_BQ.count; i++) { ++ if (!ld->TX_BQ.skb[i]) ++ ld->TX_BQ.skb[i] = SKB_MAGIC; ++ } ++ spin_unlock_irqrestore(&ld->txlock, txflags); ++} ++ ++void gmac_hw_set_mac_addr(struct net_device *dev) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(dev); ++ unsigned char *mac = dev->dev_addr; ++ u32 val; ++ ++ val = mac[1] | (mac[0] << 8); /* mac[1]->(7, 0) mac[0]->(15, 8) */ ++ writel(val, priv->gmac_iobase + STATION_ADDR_HIGH); ++ val = mac[5] | (mac[4] << 8) | /* mac[5]->(7, 0) mac[4]->(8, 15) */ ++ (mac[3] << 16) | (mac[2] << 24); /* mac[3]->(23, 16) mac[2]->(31, 24) */ ++ writel(val, priv->gmac_iobase + STATION_ADDR_LOW); ++} ++ ++static void gmac_free_rx_skb(struct gmac_netdev_local const *ld) ++{ ++ struct sk_buff *skb = NULL; ++ int i; ++ ++ for (i = 0; i < ld->RX_FQ.count; i++) { ++ skb = ld->RX_FQ.skb[i]; ++ if (skb != NULL) { ++ ld->rx_skb[i] = NULL; ++ ld->RX_FQ.skb[i] = NULL; ++ if (skb == SKB_MAGIC) ++ continue; ++ dev_kfree_skb_any(skb); ++ /* ++ * need to unmap the skb here ++ * but there is no way to get the dma_addr here, ++ * and unmap(TO_DEVICE) ops do nothing in fact, ++ * so we ignore to call ++ * dma_unmap_single(dev, dma_addr, skb->len, ++ * DMA_TO_DEVICE) ++ */ ++ } ++ } ++} ++ ++static void gmac_free_tx_skb(struct gmac_netdev_local const *ld) ++{ ++ struct sk_buff *skb = NULL; ++ int i; ++ ++ for (i = 0; i < ld->TX_BQ.count; i++) { ++ skb = ld->TX_BQ.skb[i]; ++ if (skb != NULL) { ++ ld->tx_skb[i] = NULL; ++ ld->TX_BQ.skb[i] = NULL; ++ if (skb == SKB_MAGIC) ++ continue; ++ netdev_completed_queue(ld->netdev, 1, skb->len); ++ dev_kfree_skb_any(skb); ++ } ++ } ++} ++ ++/* board related func */ ++static void gmac_mac_core_reset(struct gmac_netdev_local const *priv) ++{ ++ /* undo reset */ ++ if (priv == NULL || priv->port_rst == NULL) ++ return; ++ reset_control_deassert(priv->port_rst); ++ usleep_range(50, 60); /* wait 50~60us */ ++ ++ /* soft reset mac port */ ++ reset_control_assert(priv->port_rst); ++ usleep_range(50, 60); /* wait 50~60us */ ++ /* undo reset */ ++ reset_control_deassert(priv->port_rst); ++} ++ ++/* reset and re-config gmac */ ++static void gmac_restart(struct gmac_netdev_local *ld) ++{ ++ unsigned long rxflags, txflags; ++ ++ if (ld == NULL || ld->netdev == NULL) ++ return; ++ /* restart hw engine now */ ++ gmac_mac_core_reset(ld); ++ ++ spin_lock_irqsave(&ld->rxlock, rxflags); ++ spin_lock_irqsave(&ld->txlock, txflags); ++ ++ gmac_free_rx_skb(ld); ++ gmac_free_tx_skb(ld); ++ ++ pmt_reg_restore(ld); ++ gmac_hw_init(ld); ++ gmac_hw_set_mac_addr(ld->netdev); ++ gmac_hw_set_desc_addr(ld); ++ ++ /* we don't set macif here, it will be set in adjust_link */ ++ if (netif_running(ld->netdev)) { ++ /* ++ * when resume, only do the following operations ++ * when dev is up before suspend. ++ */ ++ gmac_rx_refill(ld); ++ gmac_set_multicast_list(ld->netdev); ++ ++ gmac_hw_desc_enable(ld); ++ gmac_port_enable(ld); ++ gmac_irq_enable_all_queue(ld); ++ } ++ spin_unlock_irqrestore(&ld->txlock, txflags); ++ spin_unlock_irqrestore(&ld->rxlock, rxflags); ++} ++ ++#define GMAC_LINK_CHANGE_PROTECT ++#define GMAC_MAC_TX_RESET_IN_LINKUP ++ ++#ifdef GMAC_LINK_CHANGE_PROTECT ++#define GMAC_MS_TO_NS (1000000ULL) ++#define GMAC_FLUSH_WAIT_TIME (100*GMAC_MS_TO_NS) ++/* protect code */ ++static void gmac_linkup_flush(struct gmac_netdev_local const *ld) ++{ ++ int tx_bq_wr_offset, tx_bq_rd_offset; ++ unsigned long long time_limit, time_now; ++ ++ time_now = sched_clock(); ++ time_limit = time_now + GMAC_FLUSH_WAIT_TIME; ++ ++ do { ++ tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR); ++ tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR); ++ ++ time_now = sched_clock(); ++ if (unlikely(((long long)time_now - (long long)time_limit) >= 0)) ++ break; ++ } while (tx_bq_rd_offset != tx_bq_wr_offset); ++ ++ mdelay(1); ++} ++#endif ++ ++#ifdef GMAC_MAC_TX_RESET_IN_LINKUP ++static void gmac_mac_tx_state_engine_reset(struct gmac_netdev_local const *priv) ++{ ++ u32 val; ++ val = readl(priv->gmac_iobase + MAC_CLEAR); ++ val |= BIT_TX_SOFT_RESET; ++ writel(val, priv->gmac_iobase + MAC_CLEAR); ++ ++ mdelay(5); /* wait 5ms */ ++ ++ val = readl(priv->gmac_iobase + MAC_CLEAR); ++ val &= ~BIT_TX_SOFT_RESET; ++ writel(val, priv->gmac_iobase + MAC_CLEAR); ++} ++#endif ++ ++static void gmac_config_port(struct net_device const *dev, u32 speed, u32 duplex) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(dev); ++ u32 val; ++ ++ switch (priv->phy_mode) { ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ if (speed == SPEED_1000) ++ val = RGMII_SPEED_1000; ++ else if (speed == SPEED_100) ++ val = RGMII_SPEED_100; ++ else ++ val = RGMII_SPEED_10; ++ break; ++ case PHY_INTERFACE_MODE_MII: ++ if (speed == SPEED_100) ++ val = MII_SPEED_100; ++ else ++ val = MII_SPEED_10; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ if (speed == SPEED_100) ++ val = RMII_SPEED_100; ++ else ++ val = RMII_SPEED_10; ++ break; ++ default: ++ netdev_warn(dev, "not supported mode\n"); ++ val = MII_SPEED_10; ++ break; ++ } ++ ++ if (duplex) ++ val |= GMAC_FULL_DUPLEX; ++ ++ reset_control_assert(priv->macif_rst); ++ writel_relaxed(val, priv->macif_base); ++ reset_control_deassert(priv->macif_rst); ++ ++ writel_relaxed(BIT_MODE_CHANGE_EN, priv->gmac_iobase + MODE_CHANGE_EN); ++ if (speed == SPEED_1000) ++ val = GMAC_SPEED_1000; ++ else if (speed == SPEED_100) ++ val = GMAC_SPEED_100; ++ else ++ val = GMAC_SPEED_10; ++ writel_relaxed(val, priv->gmac_iobase + PORT_MODE); ++ writel_relaxed(0, priv->gmac_iobase + MODE_CHANGE_EN); ++ writel_relaxed(duplex, priv->gmac_iobase + MAC_DUPLEX_HALF_CTRL); ++} ++ ++static unsigned int flow_ctrl_en = FLOW_OFF; ++static int tx_flow_ctrl_pause_time = CONFIG_TX_FLOW_CTRL_PAUSE_TIME; ++static int tx_flow_ctrl_pause_interval = CONFIG_TX_FLOW_CTRL_PAUSE_INTERVAL; ++static int tx_flow_ctrl_active_threshold = CONFIG_TX_FLOW_CTRL_ACTIVE_THRESHOLD; ++static int tx_flow_ctrl_deactive_threshold = ++ CONFIG_TX_FLOW_CTRL_DEACTIVE_THRESHOLD; ++ ++static void gmac_set_flow_ctrl_args(struct gmac_netdev_local *ld) ++{ ++ if (ld == NULL) ++ return; ++ ld->flow_ctrl = flow_ctrl_en; ++ ld->pause = tx_flow_ctrl_pause_time; ++ ld->pause_interval = tx_flow_ctrl_pause_interval; ++ ld->flow_ctrl_active_threshold = tx_flow_ctrl_active_threshold; ++ ld->flow_ctrl_deactive_threshold = tx_flow_ctrl_deactive_threshold; ++} ++ ++static void gmac_set_flow_ctrl_params(struct gmac_netdev_local const *ld) ++{ ++ unsigned int rx_fq_empty_th; ++ unsigned int rx_fq_full_th; ++ unsigned int rx_bq_empty_th; ++ unsigned int rx_bq_full_th; ++ unsigned int rec_filter; ++ if (ld == NULL) ++ return; ++ writel(ld->pause, ld->gmac_iobase + FC_TX_TIMER); ++ writel(ld->pause_interval, ld->gmac_iobase + PAUSE_THR); ++ ++ rx_fq_empty_th = readl(ld->gmac_iobase + RX_FQ_ALEMPTY_TH); ++ rx_fq_empty_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET); ++ rx_fq_empty_th |= (ld->flow_ctrl_active_threshold << ++ BITS_Q_PAUSE_TH_OFFSET); ++ writel(rx_fq_empty_th, ld->gmac_iobase + RX_FQ_ALEMPTY_TH); ++ ++ rx_fq_full_th = readl(ld->gmac_iobase + RX_FQ_ALFULL_TH); ++ rx_fq_full_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET); ++ rx_fq_full_th |= (ld->flow_ctrl_deactive_threshold << ++ BITS_Q_PAUSE_TH_OFFSET); ++ writel(rx_fq_full_th, ld->gmac_iobase + RX_FQ_ALFULL_TH); ++ ++ rx_bq_empty_th = readl(ld->gmac_iobase + RX_BQ_ALEMPTY_TH); ++ rx_bq_empty_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET); ++ rx_bq_empty_th |= (ld->flow_ctrl_active_threshold << ++ BITS_Q_PAUSE_TH_OFFSET); ++ writel(rx_bq_empty_th, ld->gmac_iobase + RX_BQ_ALEMPTY_TH); ++ ++ rx_bq_full_th = readl(ld->gmac_iobase + RX_BQ_ALFULL_TH); ++ rx_bq_full_th &= ~(BITS_Q_PAUSE_TH_MASK << BITS_Q_PAUSE_TH_OFFSET); ++ rx_bq_full_th |= (ld->flow_ctrl_deactive_threshold << ++ BITS_Q_PAUSE_TH_OFFSET); ++ writel(rx_bq_full_th, ld->gmac_iobase + RX_BQ_ALFULL_TH); ++ ++ writel(0, ld->gmac_iobase + CRF_TX_PAUSE); ++ ++ rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL); ++ rec_filter |= BIT_PAUSE_FRM_PASS; ++ writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL); ++} ++ ++void gmac_set_flow_ctrl_state(struct gmac_netdev_local const *ld, int pause) ++{ ++ unsigned int flow_rx_q_en; ++ unsigned int flow; ++ if (ld == NULL) ++ return; ++ flow_rx_q_en = readl(ld->gmac_iobase + RX_PAUSE_EN); ++ flow_rx_q_en &= ~(BIT_RX_FQ_PAUSE_EN | BIT_RX_BQ_PAUSE_EN); ++ if (pause && (ld->flow_ctrl & FLOW_TX)) ++ flow_rx_q_en |= (BIT_RX_FQ_PAUSE_EN | BIT_RX_BQ_PAUSE_EN); ++ writel(flow_rx_q_en, ld->gmac_iobase + RX_PAUSE_EN); ++ ++ flow = readl(ld->gmac_iobase + PAUSE_EN); ++ flow &= ~(BIT_RX_FDFC | BIT_TX_FDFC); ++ if (pause) { ++ if (ld->flow_ctrl & FLOW_RX) ++ flow |= BIT_RX_FDFC; ++ if (ld->flow_ctrl & FLOW_TX) ++ flow |= BIT_TX_FDFC; ++ } ++ writel(flow, ld->gmac_iobase + PAUSE_EN); ++} ++ ++static void gmac_adjust_link(struct net_device *dev) ++{ ++ struct gmac_netdev_local *priv = NULL; ++ struct phy_device *phy = NULL; ++ bool link_status_changed = false; ++ if (dev == NULL) ++ return; ++ priv = netdev_priv(dev); ++ if (priv == NULL || priv->phy == NULL) ++ return; ++ phy = priv->phy; ++ if (phy->link) { ++ if ((priv->old_speed != phy->speed) || ++ (priv->old_duplex != phy->duplex)) { ++#ifdef GMAC_LINK_CHANGE_PROTECT ++ unsigned long txflags; ++ ++ spin_lock_irqsave(&priv->txlock, txflags); ++ ++ gmac_linkup_flush(priv); ++#endif ++ gmac_config_port(dev, phy->speed, phy->duplex); ++#ifdef GMAC_MAC_TX_RESET_IN_LINKUP ++ gmac_mac_tx_state_engine_reset(priv); ++#endif ++#ifdef GMAC_LINK_CHANGE_PROTECT ++ spin_unlock_irqrestore(&priv->txlock, txflags); ++#endif ++ gmac_set_flow_ctrl_state(priv, phy->pause); ++ ++ if (priv->autoeee) ++ init_autoeee(priv); ++ ++ link_status_changed = true; ++ priv->old_link = 1; ++ priv->old_speed = phy->speed; ++ priv->old_duplex = phy->duplex; ++ } ++ } else if (priv->old_link) { ++ link_status_changed = true; ++ priv->old_link = 0; ++ netif_carrier_off(dev); ++ priv->old_speed = SPEED_UNKNOWN; ++ priv->old_duplex = DUPLEX_UNKNOWN; ++ } ++ ++ if (link_status_changed && netif_msg_link(priv)) ++ phy_print_status(phy); ++} ++ ++static int gmac_init_sg_desc_queue(struct gmac_netdev_local *ld) ++{ ++ ld->sg_count = ld->TX_BQ.count + GMAC_SG_DESC_ADD; ++ ld->dma_sg_desc = (struct sg_desc *)dma_alloc_coherent(ld->dev, ++ ld->sg_count * sizeof(struct sg_desc), ++ &ld->dma_sg_phy, GFP_KERNEL); ++ ++ if (ld->dma_sg_desc == NULL) { ++ pr_err("alloc sg desc dma error!\n"); ++ return -ENOMEM; ++ } ++ ++ ld->sg_head = 0; ++ ld->sg_tail = 0; ++ ++ return 0; ++} ++ ++static void gmac_destroy_sg_desc_queue(struct gmac_netdev_local *ld) ++{ ++ if (ld->dma_sg_desc) { ++ dma_free_coherent(ld->dev, ++ ld->sg_count * sizeof(struct sg_desc), ++ ld->dma_sg_desc, ld->dma_sg_phy); ++ ld->dma_sg_desc = NULL; ++ } ++} ++ ++static bool gmac_rx_fq_empty(struct gmac_netdev_local const *priv) ++{ ++ u32 start, end; ++ ++ start = readl(priv->gmac_iobase + RX_FQ_WR_ADDR); ++ end = readl(priv->gmac_iobase + RX_FQ_RD_ADDR); ++ if (start == end) ++ return true; ++ else ++ return false; ++} ++ ++static bool gmac_rxq_has_packets(struct gmac_netdev_local const *priv, int rxq_id) ++{ ++ u32 rx_bq_rd_reg, rx_bq_wr_reg; ++ u32 start, end; ++ ++ rx_bq_rd_reg = rx_bq_rd_addr_queue(rxq_id); ++ rx_bq_wr_reg = rx_bq_wr_addr_queue(rxq_id); ++ ++ start = readl(priv->gmac_iobase + rx_bq_rd_reg); ++ end = readl(priv->gmac_iobase + rx_bq_wr_reg); ++ if (start == end) ++ return false; ++ else ++ return true; ++} ++ ++static void gmac_trace(int level, const char *fmt, ...) ++{ ++ if (level >= GMAC_TRACE_LEVEL) { ++ va_list args; ++ va_start(args, fmt); ++ printk("gmac_trace:"); ++ printk(fmt, args); ++ printk("\n"); ++ va_end(args); ++ } ++} ++ ++static void gmac_monitor_func(struct timer_list *t) ++{ ++ struct gmac_netdev_local *ld = from_timer(ld, t, monitor); ++ struct net_device *dev = NULL; ++ u32 refill_cnt; ++ ++ if (ld == NULL) { ++ gmac_trace(GMAC_NORMAL_LEVEL, "ld is null"); ++ return; ++ } ++ ++ if (ld->netdev == NULL) { ++ gmac_trace(GMAC_NORMAL_LEVEL, "ld->netdev is null"); ++ return; ++ } ++ dev_hold(ld->netdev); ++ dev = ld->netdev; ++ if (!netif_running(dev)) { ++ dev_put(dev); ++ gmac_trace(GMAC_NORMAL_LEVEL, "network driver is stopped"); ++ return; ++ } ++ dev_put(dev); ++ ++ spin_lock(&ld->rxlock); ++ refill_cnt = gmac_rx_refill(ld); ++ if (!refill_cnt && gmac_rx_fq_empty(ld)) { ++ int rxq_id; ++ ++ for (rxq_id = 0; rxq_id < ld->num_rxqs; rxq_id++) { ++ if (gmac_rxq_has_packets(ld, rxq_id)) ++ napi_schedule(&ld->q_napi[rxq_id].napi); ++ } ++ } ++ spin_unlock(&ld->rxlock); ++ ++ ld->monitor.expires = jiffies + GMAC_MONITOR_TIMER; ++ mod_timer(&ld->monitor, ld->monitor.expires); ++} ++ ++u32 gmac_rx_refill(struct gmac_netdev_local *priv) ++{ ++ struct gmac_desc *desc = NULL; ++ struct sk_buff *skb = NULL; ++ struct cyclic_queue_info dma_info; ++ u32 len = ETH_MAX_FRAME_SIZE; ++ dma_addr_t addr; ++ u32 refill_cnt = 0; ++ u32 i; ++ /* software write pointer */ ++ dma_info.start = dma_cnt(readl(priv->gmac_iobase + RX_FQ_WR_ADDR)); ++ /* logic read pointer */ ++ dma_info.end = dma_cnt(readl(priv->gmac_iobase + RX_FQ_RD_ADDR)); ++ dma_info.num = CIRC_SPACE(dma_info.start, dma_info.end, RX_DESC_NUM); ++ ++ for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) { ++ if (priv->RX_FQ.skb[dma_info.pos] || priv->rx_skb[dma_info.pos]) ++ break; ++ ++ skb = netdev_alloc_skb_ip_align(priv->netdev, len); ++ if (unlikely(skb == NULL)) ++ break; ++ ++ addr = dma_map_single(priv->dev, skb->data, len, ++ DMA_FROM_DEVICE); ++ if (dma_mapping_error(priv->dev, addr)) { ++ dev_kfree_skb_any(skb); ++ break; ++ } ++ ++ desc = priv->RX_FQ.desc + dma_info.pos; ++ desc->data_buff_addr = (u32)addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ desc->reserve31 = addr >> REG_BIT_WIDTH; ++#endif ++ priv->RX_FQ.skb[dma_info.pos] = skb; ++ priv->rx_skb[dma_info.pos] = skb; ++ ++ desc->buffer_len = len - 1; ++ desc->data_len = 0; ++ desc->fl = 0; ++ desc->descvid = DESC_VLD_FREE; ++ desc->skb_id = dma_info.pos; ++ ++ refill_cnt++; ++ dma_info.pos = dma_ring_incr(dma_info.pos, RX_DESC_NUM); ++ } ++ ++ /* ++ * This barrier is important here. It is required to ensure ++ * the ARM CPU flushes it's DMA write buffers before proceeding ++ * to the next instruction, to ensure that GMAC will see ++ * our descriptor changes in memory ++ */ ++ gmac_sync_barrier(); ++ ++ if (dma_info.pos != dma_info.start) ++ writel(dma_byte(dma_info.pos), priv->gmac_iobase + RX_FQ_WR_ADDR); ++ ++ return refill_cnt; ++} ++ ++static int gmac_rx_checksum(struct net_device *dev, struct sk_buff *skb, ++ struct gmac_desc const *desc) ++{ ++ int hdr_csum_done, payload_csum_done; ++ int hdr_csum_err, payload_csum_err; ++ if (skb == NULL || desc == NULL || dev == NULL) ++ return -EINVAL; ++ if (dev->features & NETIF_F_RXCSUM) { ++ hdr_csum_done = desc->header_csum_done; ++ payload_csum_done = desc->payload_csum_done; ++ hdr_csum_err = desc->header_csum_err; ++ payload_csum_err = desc->payload_csum_err; ++ ++ if (hdr_csum_done && payload_csum_done) { ++ if (unlikely(hdr_csum_err || payload_csum_err)) { ++ dev->stats.rx_errors++; ++ dev->stats.rx_crc_errors++; ++ dev_kfree_skb_any(skb); ++ return -1; ++ } else { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ } ++ } ++ return 0; ++} ++ ++static void gmac_rx_skbput(struct net_device *dev, struct sk_buff *skb, ++ struct gmac_desc const *desc, int rxq_id) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ dma_addr_t addr; ++ u32 len; ++ int ret; ++ ++ len = desc->data_len; ++ ++ addr = desc->data_buff_addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ addr |= (dma_addr_t)(desc->reserve31) << REG_BIT_WIDTH; ++#endif ++ dma_unmap_single(ld->dev, addr, ETH_MAX_FRAME_SIZE, DMA_FROM_DEVICE); ++ ++ if ((addr & NET_IP_ALIGN) == 0) ++ skb_reserve(skb, 2); /* 2:NET_IP_ALIGN */ ++ ++ skb_put(skb, len); ++ if (skb->len > ETH_MAX_FRAME_SIZE) { ++ netdev_err(dev, "rcv len err, len = %d\n", skb->len); ++ dev->stats.rx_errors++; ++ dev->stats.rx_length_errors++; ++ dev_kfree_skb_any(skb); ++ return; ++ } ++ ++ skb->protocol = eth_type_trans(skb, dev); ++ skb->ip_summed = CHECKSUM_NONE; ++ ++#if defined(CONFIG_GMAC_RXCSUM) ++ ret = gmac_rx_checksum(dev, skb, desc); ++ if (unlikely(ret)) ++ return; ++#endif ++ if ((dev->features & NETIF_F_RXHASH) && desc->has_hash) ++ skb_set_hash(skb, desc->rxhash, desc->l3_hash ? ++ PKT_HASH_TYPE_L3 : PKT_HASH_TYPE_L4); ++ ++ skb_record_rx_queue(skb, rxq_id); ++ ++ napi_gro_receive(&ld->q_napi[rxq_id].napi, skb); ++ dev->stats.rx_packets++; ++ dev->stats.rx_bytes += len; ++} ++ ++static int gmac_rx_skb(struct net_device *dev, struct gmac_desc *desc, ++ u16 skb_id, int rxq_id) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ struct sk_buff *skb = NULL; ++ ++ spin_lock(&ld->rxlock); ++ skb = ld->rx_skb[skb_id]; ++ if (unlikely(skb == NULL)) { ++ spin_unlock(&ld->rxlock); ++ netdev_err(dev, "inconsistent rx_skb\n"); ++ return -1; ++ } ++ ++ /* data consistent check */ ++ if (unlikely(skb != ld->RX_FQ.skb[skb_id])) { ++ netdev_err(dev, "desc->skb(0x%p),RX_FQ.skb[%d](0x%p)\n", ++ skb, skb_id, ld->RX_FQ.skb[skb_id]); ++ if (ld->RX_FQ.skb[skb_id] == SKB_MAGIC) { ++ spin_unlock(&ld->rxlock); ++ return 0; ++ } ++ WARN_ON(1); ++ } else { ++ ld->RX_FQ.skb[skb_id] = NULL; ++ } ++ spin_unlock(&ld->rxlock); ++ ++ gmac_rx_skbput(dev, skb, desc, rxq_id); ++ return 0; ++} ++ ++static int gmac_rx(struct net_device *dev, int limit, int rxq_id) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ struct gmac_desc *desc = NULL; ++ struct cyclic_queue_info dma_info; ++ u32 rx_bq_rd_reg, rx_bq_wr_reg; ++ u16 skb_id; ++ u32 i; ++ ++ rx_bq_rd_reg = rx_bq_rd_addr_queue(rxq_id); ++ rx_bq_wr_reg = rx_bq_wr_addr_queue(rxq_id); ++ ++ /* software read pointer */ ++ dma_info.start = dma_cnt(readl(ld->gmac_iobase + rx_bq_rd_reg)); ++ /* logic write pointer */ ++ dma_info.end = dma_cnt(readl(ld->gmac_iobase + rx_bq_wr_reg)); ++ dma_info.num = CIRC_CNT(dma_info.end, dma_info.start, RX_DESC_NUM); ++ if (dma_info.num > limit) ++ dma_info.num = limit; ++ ++ /* ensure get updated desc */ ++ rmb(); ++ for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) { ++ if (rxq_id) ++ desc = ld->pool[BASE_QUEUE_NUMS + rxq_id].desc + dma_info.pos; ++ else ++ desc = ld->RX_BQ.desc + dma_info.pos; ++ skb_id = desc->skb_id; ++ ++ if (unlikely(gmac_rx_skb(dev, desc, skb_id, rxq_id))) ++ break; ++ ++ spin_lock(&ld->rxlock); ++ ld->rx_skb[skb_id] = NULL; ++ spin_unlock(&ld->rxlock); ++ dma_info.pos = dma_ring_incr(dma_info.pos, RX_DESC_NUM); ++ } ++ ++ if (dma_info.pos != dma_info.start) ++ writel(dma_byte(dma_info.pos), ld->gmac_iobase + rx_bq_rd_reg); ++ ++ spin_lock(&ld->rxlock); ++ gmac_rx_refill(ld); ++ spin_unlock(&ld->rxlock); ++ ++ return dma_info.num; ++} ++ ++static int gmac_check_tx_err(struct gmac_netdev_local const *ld, ++ struct gmac_tso_desc const *tx_bq_desc, unsigned int desc_pos) ++{ ++ unsigned int tx_err = tx_bq_desc->tx_err; ++ ++ if (unlikely(tx_err & ERR_ALL)) { ++ struct sg_desc *desc_cur = NULL; ++ int *sg_word = NULL; ++ int i; ++ ++ WARN((tx_err & ERR_ALL), ++ "TX ERR: desc1=0x%x, desc2=0x%x, desc5=0x%x\n", ++ tx_bq_desc->data_buff_addr, ++ tx_bq_desc->desc1.val, tx_bq_desc->tx_err); ++ ++ desc_cur = ld->dma_sg_desc + ld->TX_BQ.sg_desc_offset[desc_pos]; ++ sg_word = (int *)desc_cur; ++ for (i = 0; i < sizeof(struct sg_desc) / sizeof(int); i++) ++ pr_err("%s,%d: sg_desc word[%d]=0x%x\n", ++ __func__, __LINE__, i, sg_word[i]); ++ ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static void gmac_xmit_release_gso_sg(struct gmac_netdev_local *ld, ++ struct gmac_tso_desc const *tx_rq_desc, unsigned int desc_pos) ++{ ++ struct sg_desc *desc_cur = NULL; ++ int nfrags = tx_rq_desc->desc1.tx.nfrags_num; ++ unsigned int desc_offset; ++ dma_addr_t addr; ++ size_t len; ++ int i; ++ ++ desc_offset = ld->TX_BQ.sg_desc_offset[desc_pos]; ++ WARN_ON(desc_offset != ld->sg_tail); ++ desc_cur = ld->dma_sg_desc + desc_offset; ++ ++ addr = desc_cur->linear_addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ addr |= (dma_addr_t)(desc_cur->reserv3 >> SG_DESC_HI8_OFFSET) << REG_BIT_WIDTH; ++#endif ++ len = desc_cur->linear_len; ++ dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE); ++ for (i = 0; i < nfrags; i++) { ++ addr = desc_cur->frags[i].addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ addr |= (dma_addr_t) (desc_cur->frags[i].reserved >> SG_DESC_HI8_OFFSET) << REG_BIT_WIDTH; ++#endif ++ len = desc_cur->frags[i].size; ++ dma_unmap_page(ld->dev, addr, len, DMA_TO_DEVICE); ++ } ++} ++ ++static int gmac_xmit_release_gso(struct gmac_netdev_local *ld, ++ struct gmac_tso_desc *tx_rq_desc, unsigned int desc_pos) ++{ ++ int pkt_type; ++ unsigned int nfrags = tx_rq_desc->desc1.tx.nfrags_num; ++ dma_addr_t addr; ++ size_t len; ++ ++ if (unlikely(gmac_check_tx_err(ld, tx_rq_desc, desc_pos) < 0)) { ++ /* dev_close */ ++ gmac_irq_disable_all_queue(ld); ++ gmac_hw_desc_disable(ld); ++ ++ netif_carrier_off(ld->netdev); ++ netif_stop_queue(ld->netdev); ++ ++ phy_stop(ld->phy); ++ del_timer_sync(&ld->monitor); ++ return -1; ++ } ++ ++ if (tx_rq_desc->desc1.tx.tso_flag || (nfrags != 0)) ++ pkt_type = PKT_SG; ++ else ++ pkt_type = PKT_NORMAL; ++ ++ if (pkt_type == PKT_NORMAL) { ++ addr = tx_rq_desc->data_buff_addr; ++#if defined(CONFIG_GMAC_DDR_64BIT) ++ addr |= (dma_addr_t)(tx_rq_desc->reserve_desc2 & TX_DESC_HI8_MASK) << REG_BIT_WIDTH; ++#endif ++ len = tx_rq_desc->desc1.tx.data_len; ++ dma_unmap_single(ld->dev, addr, len, DMA_TO_DEVICE); ++ } else { ++ gmac_xmit_release_gso_sg(ld, tx_rq_desc, desc_pos); ++ ++ ld->sg_tail = (ld->sg_tail + 1) % ld->sg_count; ++ } ++ ++ return 0; ++} ++ ++static int gmac_xmit_reclaim_release(struct net_device const *dev, ++ struct sk_buff *skb, struct gmac_desc *desc, u32 pos) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(dev); ++ struct gmac_tso_desc *tso_desc = NULL; ++ dma_addr_t addr; ++ ++ if (priv->tso_supported) { ++ tso_desc = (struct gmac_tso_desc *)desc; ++ return gmac_xmit_release_gso(priv, tso_desc, pos); ++ } else { ++ addr = desc->data_buff_addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ addr |= (dma_addr_t)(desc->rxhash & TX_DESC_HI8_MASK) << REG_BIT_WIDTH; ++#endif ++ dma_unmap_single(priv->dev, addr, skb->len, DMA_TO_DEVICE); ++ } ++ return 0; ++} ++ ++static void gmac_xmit_reclaim(struct net_device *dev) ++{ ++ struct sk_buff *skb = NULL; ++ struct gmac_desc *desc = NULL; ++ struct gmac_netdev_local *priv = netdev_priv(dev); ++ unsigned int bytes_compl = 0; ++ unsigned int pkts_compl = 0; ++ struct cyclic_queue_info dma_info; ++ u32 i; ++ ++ spin_lock(&priv->txlock); ++ ++ /* software read */ ++ dma_info.start = dma_cnt(readl(priv->gmac_iobase + TX_RQ_RD_ADDR)); ++ /* logic write */ ++ dma_info.end = dma_cnt(readl(priv->gmac_iobase + TX_RQ_WR_ADDR)); ++ dma_info.num = CIRC_CNT(dma_info.end, dma_info.start, TX_DESC_NUM); ++ ++ for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) { ++ skb = priv->tx_skb[dma_info.pos]; ++ if (unlikely(skb == NULL)) { ++ netdev_err(dev, "inconsistent tx_skb\n"); ++ break; ++ } ++ ++ if (skb != priv->TX_BQ.skb[dma_info.pos]) { ++ netdev_err(dev, "wired, tx skb[%d](%p) != skb(%p)\n", ++ dma_info.pos, priv->TX_BQ.skb[dma_info.pos], skb); ++ if (priv->TX_BQ.skb[dma_info.pos] == SKB_MAGIC) ++ goto next; ++ } ++ ++ pkts_compl++; ++ bytes_compl += skb->len; ++ desc = priv->TX_RQ.desc + dma_info.pos; ++ if (gmac_xmit_reclaim_release(dev, skb, desc, dma_info.pos) < 0) ++ break; ++ ++ priv->TX_BQ.skb[dma_info.pos] = NULL; ++next: ++ priv->tx_skb[dma_info.pos] = NULL; ++ dev_consume_skb_any(skb); ++ dma_info.pos = dma_ring_incr(dma_info.pos, TX_DESC_NUM); ++ } ++ ++ if (dma_info.pos != dma_info.start) ++ writel(dma_byte(dma_info.pos), priv->gmac_iobase + TX_RQ_RD_ADDR); ++ ++ if ((pkts_compl != 0) || (bytes_compl != 0)) ++ netdev_completed_queue(dev, pkts_compl, bytes_compl); ++ ++ if (unlikely(netif_queue_stopped(priv->netdev)) && (pkts_compl != 0)) ++ netif_wake_queue(priv->netdev); ++ ++ spin_unlock(&priv->txlock); ++} ++ ++static int gmac_poll(struct napi_struct *napi, int budget) ++{ ++ struct gmac_napi *q_napi = container_of(napi, ++ struct gmac_napi, napi); ++ struct gmac_netdev_local *priv = q_napi->ndev_priv; ++ struct net_device *dev = priv->netdev; ++ int work_done = 0; ++ int task = budget; ++ u32 ints, num; ++ u32 raw_int_reg, raw_int_mask; ++ ++ dev_hold(dev); ++ if (q_napi->rxq_id) { ++ raw_int_reg = RSS_RAW_PMU_INT; ++ raw_int_mask = def_int_mask_queue((u32)q_napi->rxq_id); ++ } else { ++ raw_int_reg = RAW_PMU_INT; ++ raw_int_mask = DEF_INT_MASK; ++ } ++ ++ do { ++ if (!q_napi->rxq_id) ++ gmac_xmit_reclaim(dev); ++ num = gmac_rx(dev, task, q_napi->rxq_id); ++ work_done += num; ++ task -= num; ++ if (work_done >= budget) ++ break; ++ ++ ints = readl(priv->gmac_iobase + raw_int_reg); ++ ints &= raw_int_mask; ++ writel(ints, priv->gmac_iobase + raw_int_reg); ++ } while (ints || gmac_rxq_has_packets(priv, q_napi->rxq_id)); ++ ++ if (work_done < budget) { ++ napi_complete(napi); ++ gmac_irq_enable_queue(priv, q_napi->rxq_id); ++ } ++ ++ dev_put(dev); ++ return work_done; ++} ++ ++static irqreturn_t gmac_interrupt(int irq, void *dev_id) ++{ ++ struct gmac_napi *q_napi = (struct gmac_napi *)dev_id; ++ struct gmac_netdev_local *ld = q_napi->ndev_priv; ++ u32 ints; ++ u32 raw_int_reg, raw_int_mask; ++ ++ if (gmac_queue_irq_disabled(ld, q_napi->rxq_id)) ++ return IRQ_NONE; ++ ++ if (q_napi->rxq_id) { ++ raw_int_reg = RSS_RAW_PMU_INT; ++ raw_int_mask = def_int_mask_queue((u32)q_napi->rxq_id); ++ } else { ++ raw_int_reg = RAW_PMU_INT; ++ raw_int_mask = DEF_INT_MASK; ++ } ++ ++ ints = readl(ld->gmac_iobase + raw_int_reg); ++ ints &= raw_int_mask; ++ writel(ints, ld->gmac_iobase + raw_int_reg); ++ ++ if (likely(ints || gmac_rxq_has_packets(ld, q_napi->rxq_id))) { ++ gmac_irq_disable_queue(ld, q_napi->rxq_id); ++ napi_schedule(&q_napi->napi); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++void gmac_enable_napi(struct gmac_netdev_local *priv) ++{ ++ struct gmac_napi *q_napi = NULL; ++ int i; ++ ++ if (priv == NULL) ++ return; ++ ++ for (i = 0; i < priv->num_rxqs; i++) { ++ q_napi = &priv->q_napi[i]; ++ napi_enable(&q_napi->napi); ++ } ++} ++ ++void gmac_disable_napi(struct gmac_netdev_local *priv) ++{ ++ struct gmac_napi *q_napi = NULL; ++ int i; ++ ++ if (priv == NULL) ++ return; ++ ++ for (i = 0; i < priv->num_rxqs; i++) { ++ q_napi = &priv->q_napi[i]; ++ napi_disable(&q_napi->napi); ++ } ++} ++ ++void gmac_enable_rxcsum_drop(struct gmac_netdev_local const *ld, bool drop) ++{ ++ unsigned int v; ++ ++ v = readl(ld->gmac_iobase + TSO_COE_CTRL); ++ if (drop) ++ v |= COE_ERR_DROP; ++ else ++ v &= ~COE_ERR_DROP; ++ writel(v, ld->gmac_iobase + TSO_COE_CTRL); ++} ++ ++static const struct ethtool_ops eth_ethtools_ops = { ++ .get_drvinfo = gmac_get_drvinfo, ++ .get_link = gmac_get_link, ++ .get_pauseparam = gmac_get_pauseparam, ++ .set_pauseparam = gmac_set_pauseparam, ++ .get_msglevel = gmac_ethtool_getmsglevel, ++ .set_msglevel = gmac_ethtool_setmsglevel, ++ .get_rxfh_key_size = gmac_get_rxfh_key_size, ++ .get_rxfh_indir_size = gmac_get_rxfh_indir_size, ++ .get_rxfh = gmac_get_rxfh, ++ .set_rxfh = gmac_set_rxfh, ++ .get_rxnfc = gmac_get_rxnfc, ++ .set_rxnfc = gmac_set_rxnfc, ++ .get_link_ksettings = phy_ethtool_get_link_ksettings, ++ .set_link_ksettings = phy_ethtool_set_link_ksettings, ++}; ++ ++static const struct net_device_ops eth_netdev_ops = { ++ .ndo_open = gmac_net_open, ++ .ndo_stop = gmac_net_close, ++ .ndo_start_xmit = gmac_net_xmit, ++ .ndo_set_rx_mode = gmac_set_multicast_list, ++ .ndo_set_features = gmac_set_features, ++ .ndo_do_ioctl = gmac_ioctl, ++ .ndo_set_mac_address = gmac_net_set_mac_address, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_get_stats = gmac_net_get_stats, ++}; ++ ++static int gmac_of_get_param(struct gmac_netdev_local *ld, ++ struct device_node const *node) ++{ ++ /* get auto eee */ ++ ld->autoeee = of_property_read_bool(node, "autoeee"); ++ /* get internal flag */ ++ ld->internal_phy = ++ of_property_read_bool(node, "internal-phy"); ++ ++ return 0; ++} ++ ++static void gmac_destroy_hw_desc_queue(struct gmac_netdev_local *priv) ++{ ++ int i; ++ ++ for (i = 0; i < QUEUE_NUMS + RSS_NUM_RXQS - 1; i++) { ++ if (priv->pool[i].desc) { ++ dma_free_coherent(priv->dev, priv->pool[i].size, ++ priv->pool[i].desc, ++ priv->pool[i].phys_addr); ++ priv->pool[i].desc = NULL; ++ } ++ } ++ ++ kfree(priv->RX_FQ.skb); ++ kfree(priv->TX_BQ.skb); ++ priv->RX_FQ.skb = NULL; ++ priv->TX_BQ.skb = NULL; ++ ++ if (priv->tso_supported) { ++ kfree(priv->TX_BQ.sg_desc_offset); ++ priv->TX_BQ.sg_desc_offset = NULL; ++ } ++ ++ kfree(priv->tx_skb); ++ priv->tx_skb = NULL; ++ ++ kfree(priv->rx_skb); ++ priv->rx_skb = NULL; ++} ++ ++static int gmac_init_desc_queue_mem(struct gmac_netdev_local *priv) ++{ ++ priv->RX_FQ.skb = kzalloc(priv->RX_FQ.count ++ * sizeof(struct sk_buff *), GFP_KERNEL); ++ if (!priv->RX_FQ.skb) ++ return -ENOMEM; ++ ++ priv->rx_skb = kzalloc(priv->RX_FQ.count ++ * sizeof(struct sk_buff *), GFP_KERNEL); ++ if (priv->rx_skb == NULL) ++ return -ENOMEM; ++ ++ priv->TX_BQ.skb = kzalloc(priv->TX_BQ.count ++ * sizeof(struct sk_buff *), GFP_KERNEL); ++ if (!priv->TX_BQ.skb) ++ return -ENOMEM; ++ ++ priv->tx_skb = kzalloc(priv->TX_BQ.count ++ * sizeof(struct sk_buff *), GFP_KERNEL); ++ if (priv->tx_skb == NULL) ++ return -ENOMEM; ++ ++ if (priv->tso_supported) { ++ priv->TX_BQ.sg_desc_offset = kzalloc(priv->TX_BQ.count ++ * sizeof(int), GFP_KERNEL); ++ if (!priv->TX_BQ.sg_desc_offset) ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int gmac_init_hw_desc_queue(struct gmac_netdev_local *priv) ++{ ++ struct device *dev = NULL; ++ struct gmac_desc *virt_addr = NULL; ++ dma_addr_t phys_addr = 0; ++ int size, i; ++ if (priv == NULL || priv->dev == NULL) ++ return -EINVAL; ++ dev = priv->dev; ++ if (dev == NULL) ++ return -EINVAL; ++ priv->RX_FQ.count = RX_DESC_NUM; ++ priv->RX_BQ.count = RX_DESC_NUM; ++ priv->TX_BQ.count = TX_DESC_NUM; ++ priv->TX_RQ.count = TX_DESC_NUM; ++ ++ for (i = 1; i < RSS_NUM_RXQS; i++) ++ priv->pool[BASE_QUEUE_NUMS + i].count = RX_DESC_NUM; ++ ++ for (i = 0; i < (QUEUE_NUMS + RSS_NUM_RXQS - 1); i++) { ++ size = priv->pool[i].count * sizeof(struct gmac_desc); ++ virt_addr = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); ++ if (virt_addr == NULL) ++ goto error_free_pool; ++ ++ if (memset_s(virt_addr, size, 0, size) != EOK) { ++ pr_info("gmac init hw desc queue: memset_s failed\n"); ++ goto error_free_pool; ++ } ++ priv->pool[i].size = (unsigned int)size; ++ priv->pool[i].desc = virt_addr; ++ priv->pool[i].phys_addr = phys_addr; ++ } ++ ++ if (gmac_init_desc_queue_mem(priv) == -ENOMEM) ++ goto error_free_pool; ++ ++ gmac_hw_set_desc_addr(priv); ++ ++ return 0; ++ ++error_free_pool: ++ gmac_destroy_hw_desc_queue(priv); ++ ++ return -ENOMEM; ++} ++ ++static void gmac_init_napi(struct gmac_netdev_local *priv) ++{ ++ struct gmac_napi *q_napi = NULL; ++ int i; ++ ++ if (priv == NULL || priv->netdev == NULL) ++ return; ++ ++ for (i = 0; i < priv->num_rxqs; i++) { ++ q_napi = &priv->q_napi[i]; ++ q_napi->rxq_id = (unsigned int)i; ++ q_napi->ndev_priv = priv; ++ netif_napi_add(priv->netdev, &q_napi->napi, gmac_poll, ++ NAPI_POLL_WEIGHT); ++ } ++} ++ ++static void gmac_destroy_napi(struct gmac_netdev_local *priv) ++{ ++ struct gmac_napi *q_napi = NULL; ++ int i; ++ ++ if (priv == NULL) ++ return; ++ ++ for (i = 0; i < priv->num_rxqs; i++) { ++ q_napi = &priv->q_napi[i]; ++ netif_napi_del(&q_napi->napi); ++ } ++} ++ ++static int gmac_request_irqs(struct platform_device *pdev, ++ struct gmac_netdev_local *priv) ++{ ++ struct device *dev = NULL; ++ int ret; ++ int i; ++ ++ if (priv == NULL || pdev == NULL || pdev->name == NULL) ++ return -1; ++ ++ dev = priv->dev; ++ if (dev == NULL) ++ return -1; ++ ++ for (i = 0; i < priv->num_rxqs; i++) { ++ ret = platform_get_irq(pdev, i); ++ if (ret < 0) { ++ dev_err(dev, "No irq[%d] resource, ret=%d\n", i, ret); ++ return ret; ++ } ++ priv->irq[i] = (unsigned int)ret; ++ ++ ret = devm_request_irq(dev, priv->irq[i], gmac_interrupt, ++ IRQF_SHARED, pdev->name, &priv->q_napi[i]); ++ if (ret) { ++ dev_err(dev, "devm_request_irq failed, ret=%d\n", ret); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static int gmac_dev_probe_res(struct platform_device *pdev, ++ struct gmac_netdev_local *priv) ++{ ++ struct device *dev = &pdev->dev; ++ struct net_device *ndev = priv->netdev; ++ struct resource *res = NULL; ++ int ret; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, MEM_GMAC_IOBASE); ++ priv->gmac_iobase = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->gmac_iobase)) { ++ ret = PTR_ERR(priv->gmac_iobase); ++ return ret; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, MEM_MACIF_IOBASE); ++ priv->macif_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->macif_base)) { ++ ret = PTR_ERR(priv->macif_base); ++ return ret; ++ } ++ ++ /* only for some chip to fix AXI bus burst and outstanding config */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, MEM_AXI_BUS_CFG_IOBASE); ++ priv->axi_bus_cfg_base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(priv->axi_bus_cfg_base)) ++ priv->axi_bus_cfg_base = NULL; ++ ++ priv->port_rst = devm_reset_control_get(dev, GMAC_PORT_RST_NAME); ++ if (IS_ERR(priv->port_rst)) { ++ ret = PTR_ERR(priv->port_rst); ++ return ret; ++ } ++ ++ priv->macif_rst = devm_reset_control_get(dev, GMAC_MACIF_RST_NAME); ++ if (IS_ERR(priv->macif_rst)) { ++ ret = PTR_ERR(priv->macif_rst); ++ return ret; ++ } ++ ++ priv->phy_rst = devm_reset_control_get(dev, GMAC_PHY_RST_NAME); ++ if (IS_ERR(priv->phy_rst)) ++ priv->phy_rst = NULL; ++ ++ priv->clk = devm_clk_get(&pdev->dev, GMAC_MAC_CLK_NAME); ++ if (IS_ERR(priv->clk)) { ++ netdev_err(ndev, "failed to get clk\n"); ++ ret = -ENODEV; ++ return ret; ++ } ++ ++ ret = clk_prepare_enable(priv->clk); ++ if (ret < 0) { ++ netdev_err(ndev, "failed to enable clk %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++static int gmac_dev_macif_clk(struct platform_device *pdev, ++ struct gmac_netdev_local *priv, struct net_device *ndev) ++{ ++ int ret; ++ ++ priv->macif_clk = devm_clk_get(&pdev->dev, GMAC_MACIF_CLK_NAME); ++ if (IS_ERR(priv->macif_clk)) ++ priv->macif_clk = NULL; ++ ++ if (priv->macif_clk != NULL) { ++ ret = clk_prepare_enable(priv->macif_clk); ++ if (ret < 0) { ++ netdev_err(ndev, "failed enable macif_clk %d\n", ret); ++ return ret; ++ } ++ } ++ return 0; ++} ++ ++static int gmac_dev_probe_init(struct platform_device *pdev, ++ struct gmac_netdev_local *priv, struct net_device *ndev) ++{ ++ int ret; ++#if defined(CONFIG_GMAC_DDR_64BIT) ++ struct device *dev = &pdev->dev; ++#endif ++ ++ gmac_init_napi(priv); ++ spin_lock_init(&priv->rxlock); ++ spin_lock_init(&priv->txlock); ++ spin_lock_init(&priv->pmtlock); ++ ++ /* init netdevice */ ++ ndev->irq = priv->irq[0]; ++ ndev->watchdog_timeo = 3 * HZ; /* 3HZ */ ++ ndev->netdev_ops = ð_netdev_ops; ++ ndev->ethtool_ops = ð_ethtools_ops; ++ ++ if (priv->has_rxhash_cap) ++ ndev->hw_features |= NETIF_F_RXHASH; ++ if (priv->has_rss_cap) ++ ndev->hw_features |= NETIF_F_NTUPLE; ++ if (priv->tso_supported) ++ ndev->hw_features |= NETIF_F_SG | ++ NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | ++ NETIF_F_TSO | NETIF_F_TSO6; ++ ++#if defined(CONFIG_GMAC_RXCSUM) ++ ndev->hw_features |= NETIF_F_RXCSUM; ++ gmac_enable_rxcsum_drop(priv, true); ++#endif ++ ++ ndev->features |= ndev->hw_features; ++ ndev->features |= NETIF_F_HIGHDMA | NETIF_F_GSO; ++ ndev->vlan_features |= ndev->features; ++ ++ timer_setup(&priv->monitor, gmac_monitor_func, 0); ++ ++ device_set_wakeup_capable(priv->dev, 1); ++ /* ++ * when we can let phy powerdown? ++ * In some mode, we don't want phy powerdown, ++ * so I set wakeup enable all the time ++ */ ++ device_set_wakeup_enable(priv->dev, 1); ++ ++ priv->wol_enable = false; ++ ++ priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); ++ ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); /* 64bit */ ++ if (ret) { ++ pr_err("dma set mask 64 failed! ret=%d", ret); ++ return ret; ++ } ++#endif ++ ++ /* init hw desc queue */ ++ ret = gmac_init_hw_desc_queue(priv); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int gmac_dev_probe_phy(struct platform_device *pdev, ++ struct gmac_netdev_local *priv, struct net_device *ndev, ++ bool fixed_link) ++{ ++ int ret; ++ ++ /* phy fix here?? other way ??? */ ++ gmac_phy_register_fixups(); ++ /* Unable to handle kernel paging request at virtual address 08ffffff80052fc0 */ ++ priv->phy = of_phy_connect(ndev, priv->phy_node, ++ &gmac_adjust_link, 0, priv->phy_mode); ++ if (priv->phy == NULL || priv->phy->drv == NULL) { ++ ret = -ENODEV; ++ return ret; ++ } ++ ++ /* If the phy_id is all zero and not fixed link, there is no device there */ ++ if ((priv->phy->phy_id == 0) && !fixed_link) { ++ pr_info("phy %d not found\n", priv->phy->mdio.addr); ++ ret = -ENODEV; ++ return ret; ++ } ++ ++ pr_info("attached PHY %d to driver %s, PHY_ID=0x%x\n", ++ priv->phy->mdio.addr, priv->phy->drv->name, priv->phy->phy_id); ++ ++ /* Stop Advertising 1000BASE Capability if interface is not RGMII */ ++ if ((priv->phy_mode == PHY_INTERFACE_MODE_MII) || ++ (priv->phy_mode == PHY_INTERFACE_MODE_RMII)) { ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT | ETHTOOL_LINK_MODE_1000baseT_Half_BIT, ++ priv->phy->advertising); ++ /* ++ * Internal FE phy's reg BMSR bit8 is wrong, make the kernel ++ * believe it has the 1000base Capability, so fix it here ++ */ ++ if (priv->phy->phy_id == VENDOR_PHY_ID_FESTAV200) ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT | ETHTOOL_LINK_MODE_1000baseT_Half_BIT, ++ priv->phy->supported); ++ } ++ ++ gmac_set_flow_ctrl_args(priv); ++ gmac_set_flow_ctrl_params(priv); ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, priv->phy->supported); ++ if (priv->flow_ctrl) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, priv->phy->advertising); ++ if (priv->autoeee) ++ init_autoeee(priv); ++ ++ ret = gmac_request_irqs(pdev, priv); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static void gmac_set_hw_cap(struct platform_device *pdev, ++ struct gmac_netdev_local *priv) ++{ ++ unsigned int hw_cap; ++ ++ hw_cap = readl(priv->gmac_iobase + CRF_MIN_PACKET); ++ priv->tso_supported = has_tso_cap(hw_cap); ++ priv->has_rxhash_cap = has_rxhash_cap(hw_cap); ++ priv->has_rss_cap = has_rss_cap(hw_cap); ++ ++ gmac_set_rss_cap(priv); ++ gmac_get_rss_key(priv); ++ if (priv->has_rss_cap) { ++ priv->rss_info.ind_tbl_size = RSS_INDIRECTION_TABLE_SIZE; ++ gmac_get_rss(priv); ++ } ++ ++ if (priv->has_rxhash_cap) { ++ priv->rss_info.hash_cfg = DEF_HASH_CFG; ++ gmac_config_hash_policy(priv); ++ } ++} ++ ++static void gmac_set_mac_addr(struct net_device *ndev, ++ struct device_node *node) ++{ ++ const char *mac_addr = NULL; ++ ++ mac_addr = of_get_mac_address(node); ++ if (!IS_ERR_OR_NULL(mac_addr)) ++ ether_addr_copy(ndev->dev_addr, mac_addr); ++ else ++ eth_hw_addr_random(ndev); ++ ++ gmac_hw_set_mac_addr(ndev); ++} ++ ++/* board independent func */ ++static void gmac_hw_internal_phy_reset(struct gmac_netdev_local const *priv) ++{ ++} ++ ++/* board independent func */ ++static void gmac_hw_external_phy_reset(struct gmac_netdev_local const *priv) ++{ ++ if (priv == NULL) ++ return; ++ if (priv->phy_rst != NULL) { ++ /* write 0 to cancel reset */ ++ reset_control_deassert(priv->phy_rst); ++ msleep(50); /* wait 50ms */ ++ ++ /* XX use CRG register to reset phy */ ++ /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */ ++ reset_control_assert(priv->phy_rst); ++ ++ /* ++ * delay some time to ensure reset ok, ++ * this depends on PHY hardware feature ++ */ ++ msleep(50); /* wait 50ms */ ++ ++ /* write 0 to cancel reset */ ++ reset_control_deassert(priv->phy_rst); ++ /* delay some time to ensure later MDIO access */ ++ msleep(50); /* wait 50ms */ ++ } ++} ++ ++/* board independent func */ ++static void gmac_hw_phy_reset(struct gmac_netdev_local *priv) ++{ ++ if (priv == NULL) ++ return; ++ if (priv->internal_phy) ++ gmac_hw_internal_phy_reset(priv); ++ else ++ gmac_hw_external_phy_reset(priv); ++} ++ ++static int gmac_phy_init(struct device *dev, struct net_device *ndev, ++ struct gmac_netdev_local *priv, struct device_node *node, bool *fixed_link) ++{ ++ int ret; ++ ++ /* ++ * phy reset, should be early than "of_mdiobus_register". ++ * becausue "of_mdiobus_register" will read PHY register by MDIO. ++ */ ++ gmac_hw_phy_reset(priv); ++ ++ gmac_of_get_param(priv, node); ++ ++ ret = of_get_phy_mode(node, &priv->phy_mode); ++ if (ret < 0) { ++ netdev_err(ndev, "not find phy-mode\n"); ++ return ret; ++ } ++ ++ priv->phy_node = of_parse_phandle(node, "phy-handle", 0); ++ if (priv->phy_node == NULL) { ++ /* check if a fixed-link is defined in device-tree */ ++ if (of_phy_is_fixed_link(node)) { ++ ret = of_phy_register_fixed_link(node); ++ if (ret < 0) { ++ dev_err(dev, "cannot register fixed PHY %d\n", ret); ++ return ret; ++ } ++ ++ /* ++ * In the case of a fixed PHY, the DT node associated ++ * to the PHY is the Ethernet MAC DT node. ++ */ ++ priv->phy_node = of_node_get(node); ++ *fixed_link = true; ++ } else { ++ netdev_err(ndev, "not find phy-handle\n"); ++ ret = -EINVAL; ++ return ret; ++ } ++ } ++ return 0; ++} ++ ++static void gmac_verify_flow_ctrl_args(void) ++{ ++#if defined(CONFIG_TX_FLOW_CTRL_SUPPORT) ++ flow_ctrl_en |= FLOW_TX; ++#endif ++#if defined(CONFIG_RX_FLOW_CTRL_SUPPORT) ++ flow_ctrl_en |= FLOW_RX; ++#endif ++ if (tx_flow_ctrl_active_threshold < FC_ACTIVE_MIN || ++ tx_flow_ctrl_active_threshold > FC_ACTIVE_MAX) ++ tx_flow_ctrl_active_threshold = FC_ACTIVE_DEFAULT; ++ ++ if (tx_flow_ctrl_deactive_threshold < FC_DEACTIVE_MIN || ++ tx_flow_ctrl_deactive_threshold > FC_DEACTIVE_MAX) ++ tx_flow_ctrl_deactive_threshold = FC_DEACTIVE_DEFAULT; ++ ++ if (tx_flow_ctrl_active_threshold >= tx_flow_ctrl_deactive_threshold) { ++ tx_flow_ctrl_active_threshold = FC_ACTIVE_DEFAULT; ++ tx_flow_ctrl_deactive_threshold = FC_DEACTIVE_DEFAULT; ++ } ++ ++ if (tx_flow_ctrl_pause_time < 0 || ++ tx_flow_ctrl_pause_time > FC_PAUSE_TIME_MAX) ++ tx_flow_ctrl_pause_time = FC_PAUSE_TIME_DEFAULT; ++ ++ if (tx_flow_ctrl_pause_interval < 0 || ++ tx_flow_ctrl_pause_interval > FC_PAUSE_TIME_MAX) ++ tx_flow_ctrl_pause_interval = FC_PAUSE_INTERVAL_DEFAULT; ++ ++ /* ++ * pause interval should not bigger than pause time, ++ * but should not too smaller to avoid sending too many pause frame. ++ */ ++ if ((tx_flow_ctrl_pause_interval > tx_flow_ctrl_pause_time) || ++ (tx_flow_ctrl_pause_interval < ((unsigned int)tx_flow_ctrl_pause_time >> 1))) ++ tx_flow_ctrl_pause_interval = tx_flow_ctrl_pause_time; ++} ++ ++static int gmac_dev_probe_device(struct platform_device *pdev, ++ struct net_device **p_ndev, struct gmac_netdev_local **p_priv) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct net_device *ndev = NULL; ++ struct gmac_netdev_local *priv = NULL; ++ int num_rxqs; ++ ++ gmac_verify_flow_ctrl_args(); ++ ++ if (of_device_is_compatible(node, "vendor,gmac-v5")) ++ num_rxqs = RSS_NUM_RXQS; ++ else ++ num_rxqs = 1; ++ ++ ndev = alloc_etherdev_mqs(sizeof(struct gmac_netdev_local), 1, ++ num_rxqs); ++ if (ndev == NULL) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, ndev); ++ SET_NETDEV_DEV(ndev, dev); ++ ++ priv = netdev_priv(ndev); ++ priv->dev = dev; ++ priv->netdev = ndev; ++ priv->num_rxqs = num_rxqs; ++ ++ *p_ndev = ndev; ++ *p_priv = priv; ++ return 0; ++} ++ ++static int gmac_dev_probe_queue(struct platform_device *pdev, ++ struct gmac_netdev_local *priv, struct net_device *ndev, bool fixed_link) ++{ ++ int ret; ++ ++ ret = gmac_dev_probe_init(pdev, priv, ndev); ++ if (ret) ++ goto _error_hw_desc_queue; ++ ++ if (priv->tso_supported) { ++ ret = gmac_init_sg_desc_queue(priv); ++ if (ret) ++ goto _error_sg_desc_queue; ++ } ++ ++ /* register netdevice */ ++ ret = register_netdev(priv->netdev); ++ if (ret) { ++ pr_err("register_ndev failed!"); ++ goto _error_sg_desc_queue; ++ } ++ ++ /* ++ * reset queue here to make BQL only reset once. ++ * if we put netdev_reset_queue() in gmac_net_open(), ++ * the BQL will be reset when ifconfig eth0 down and up, ++ * but the tx ring is not cleared before. ++ * As a result, the NAPI poll will call netdev_completed_queue() ++ * and BQL throw a bug. ++ */ ++ netdev_reset_queue(ndev); ++ ++ /* config PHY power down to save power */ ++ phy_suspend(priv->phy); ++ ++ clk_disable_unprepare(priv->clk); ++ if (priv->macif_clk != NULL) ++ clk_disable_unprepare(priv->macif_clk); ++ ++ pr_info("ETH: %s, phy_addr=%d\n", ++ phy_modes(priv->phy_mode), priv->phy->mdio.addr); ++ ++ return ret; ++ ++_error_sg_desc_queue: ++ if (priv->tso_supported) ++ gmac_destroy_sg_desc_queue(priv); ++_error_hw_desc_queue: ++ gmac_destroy_hw_desc_queue(priv); ++ gmac_destroy_napi(priv); ++ ++ return ret; ++} ++ ++static int gmac_dev_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct net_device *ndev = NULL; ++ struct gmac_netdev_local *priv = NULL; ++ int ret; ++ bool fixed_link = false; ++ ++ ret = gmac_dev_probe_device(pdev, &ndev, &priv); ++ if (ret) ++ return ret; ++ ++ ret = gmac_dev_probe_res(pdev, priv); ++ if (ret) ++ goto out_free_netdev; ++ ++ ret = gmac_dev_macif_clk(pdev, priv, ndev); ++ if (ret) ++ goto out_clk_disable; ++ ++ gmac_mac_core_reset(priv); ++ ++ ret = gmac_phy_init(dev, ndev, priv, node, &fixed_link); ++ if (ret) ++ goto out_macif_clk_disable; ++ ++ gmac_set_mac_addr(ndev, node); ++ gmac_set_hw_cap(pdev, priv); ++ ++ /* init hw controller */ ++ gmac_hw_init(priv); ++ ++ ret = gmac_dev_probe_phy(pdev, priv, ndev, fixed_link); ++ if (ret) { ++ if (priv->phy == NULL) ++ goto out_phy_node; ++ else ++ goto out_phy_disconnect; ++ } ++ ++ ret = gmac_dev_probe_queue(pdev, priv, ndev, fixed_link); ++ if (ret) ++ goto out_phy_disconnect; ++ ++ return ret; ++ ++out_phy_disconnect: ++ phy_disconnect(priv->phy); ++out_phy_node: ++ of_node_put(priv->phy_node); ++out_macif_clk_disable: ++ if (priv->macif_clk != NULL) ++ clk_disable_unprepare(priv->macif_clk); ++out_clk_disable: ++ clk_disable_unprepare(priv->clk); ++out_free_netdev: ++ free_netdev(ndev); ++ ++ return ret; ++} ++ ++static int gmac_dev_remove(struct platform_device *pdev) ++{ ++ struct net_device *ndev = platform_get_drvdata(pdev); ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ ++ /* stop the gmac and free all resource */ ++ del_timer_sync(&priv->monitor); ++ gmac_destroy_napi(priv); ++ ++ unregister_netdev(ndev); ++ ++ gmac_reclaim_rx_tx_resource(priv); ++ gmac_free_rx_skb(priv); ++ gmac_free_tx_skb(priv); ++ ++ if (priv->tso_supported) ++ gmac_destroy_sg_desc_queue(priv); ++ gmac_destroy_hw_desc_queue(priv); ++ ++ phy_disconnect(priv->phy); ++ of_node_put(priv->phy_node); ++ ++ free_netdev(ndev); ++ ++ gmac_phy_unregister_fixups(); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static void gmac_disable_irq(struct gmac_netdev_local *priv) ++{ ++ int i; ++ ++ for (i = 0; i < priv->num_rxqs; i++) ++ disable_irq(priv->irq[i]); ++} ++ ++static void gmac_enable_irq(struct gmac_netdev_local *priv) ++{ ++ int i; ++ ++ for (i = 0; i < priv->num_rxqs; i++) ++ enable_irq(priv->irq[i]); ++} ++ ++/* board related func */ ++static void gmac_internal_phy_clk_disable(struct gmac_netdev_local const *priv) ++{ ++} ++ ++/* board related func */ ++static void gmac_hw_all_clk_disable(struct gmac_netdev_local *priv) ++{ ++ /* ++ * If macif clock is enabled when suspend, we should ++ * disable it here. ++ * Because when resume, PHY will link up again and ++ * macif clock will be enabled too. If we don't disable ++ * macif clock in suspend, macif clock will be enabled twice. ++ */ ++ if (priv == NULL || priv->clk == NULL || priv->netdev == NULL || priv->macif_clk == NULL) ++ return; ++ ++ if (priv->netdev->flags & IFF_UP) ++ clk_disable_unprepare(priv->macif_clk); ++ ++ /* ++ * This is called in suspend, when net device is down, ++ * MAC clk is disabled. ++ * So we need to judge whether MAC clk is enabled, ++ * otherwise kernel will WARNING if clk disable twice. ++ */ ++ if (priv->netdev->flags & IFF_UP) ++ clk_disable_unprepare(priv->clk); ++ ++ if (priv->internal_phy) ++ gmac_internal_phy_clk_disable(priv); ++} ++ ++int gmac_dev_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct net_device *ndev = platform_get_drvdata(pdev); ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ ++ gmac_disable_irq(priv); ++ /* ++ * If support Wake on LAN, we should not disconnect phy ++ * because it will call phy_suspend to power down phy. ++ */ ++ if (!priv->wol_enable) ++ phy_disconnect(priv->phy); ++ del_timer_sync(&priv->monitor); ++ /* ++ * If suspend when netif is not up, the napi_disable will run into ++ * dead loop and dpm_drv_timeout will give warning. ++ */ ++ if (netif_running(ndev)) ++ gmac_disable_napi(priv); ++ netif_device_detach(ndev); ++ ++ netif_carrier_off(ndev); ++ ++ /* ++ * If netdev is down, MAC clock is disabled. ++ * So if we want to reclaim MAC rx and tx resource, ++ * we must first enable MAC clock and then disable it. ++ */ ++ if (!(ndev->flags & IFF_UP)) ++ clk_prepare_enable(priv->clk); ++ ++ gmac_reclaim_rx_tx_resource(priv); ++ ++ if (!(ndev->flags & IFF_UP)) ++ clk_disable_unprepare(priv->clk); ++ ++ pmt_enter(priv); ++ ++ if (!priv->wol_enable) { ++ /* ++ * if no WOL, then poweroff ++ * no need to call genphy_resume() in resume, ++ * because we reset everything ++ */ ++ genphy_suspend(priv->phy); /* power down phy */ ++ msleep(20); /* wait 20ms */ ++ gmac_hw_all_clk_disable(priv); ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(gmac_dev_suspend); ++ ++/* board related func */ ++static void gmac_internal_phy_clk_enable(struct gmac_netdev_local const *priv) ++{ ++} ++ ++/* board related func */ ++static void gmac_hw_all_clk_enable(struct gmac_netdev_local *priv) ++{ ++ if (priv == NULL || priv->netdev == NULL || priv->clk == NULL) ++ return; ++ ++ if (priv->internal_phy) ++ gmac_internal_phy_clk_enable(priv); ++ ++ if (priv->netdev->flags & IFF_UP) ++ clk_prepare_enable(priv->macif_clk); ++ ++ /* If net device is down when suspend, we should not enable MAC clk. */ ++ if (priv->netdev->flags & IFF_UP) ++ clk_prepare_enable(priv->clk); ++} ++ ++int gmac_dev_resume(struct platform_device *pdev) ++{ ++ struct net_device *ndev = platform_get_drvdata(pdev); ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ int ret; ++ ++ /* ++ * If we support Wake on LAN, we doesn't call clk_disable. ++ * But when we resume, the uboot may off mac clock and reset phy ++ * by re-write the mac CRG register. ++ * So we first call clk_disable, and then clk_enable. ++ */ ++ if (priv->wol_enable) ++ gmac_hw_all_clk_disable(priv); ++ ++ gmac_hw_all_clk_enable(priv); ++ /* internal FE_PHY: enable clk and reset */ ++ gmac_hw_phy_reset(priv); ++ ++ /* ++ * If netdev is down, MAC clock is disabled. ++ * So if we want to restart MAC and re-initialize it, ++ * we must first enable MAC clock and then disable it. ++ */ ++ if (!(ndev->flags & IFF_UP)) ++ clk_prepare_enable(priv->clk); ++ ++ /* power on gmac */ ++ gmac_restart(priv); ++ ++ /* ++ * If support WoL, we didn't disconnect phy. ++ * But when we resume, we reset PHY, so we want to ++ * call phy_connect to make phy_fixup excuted. ++ * This is important for internal PHY fix. ++ */ ++ if (priv->wol_enable) ++ phy_disconnect(priv->phy); ++ ++ ret = phy_connect_direct(ndev, priv->phy, gmac_adjust_link, ++ priv->phy_mode); ++ if (ret) ++ return ret; ++ ++ /* ++ * If we suspend and resume when net device is down, ++ * some operations are unnecessary. ++ */ ++ if (ndev->flags & IFF_UP) { ++ priv->monitor.expires = jiffies + GMAC_MONITOR_TIMER; ++ mod_timer(&priv->monitor, priv->monitor.expires); ++ priv->old_link = 0; ++ priv->old_speed = SPEED_UNKNOWN; ++ priv->old_duplex = DUPLEX_UNKNOWN; ++ } ++ if (netif_running(ndev)) ++ gmac_enable_napi(priv); ++ netif_device_attach(ndev); ++ if (ndev->flags & IFF_UP) ++ phy_start(priv->phy); ++ gmac_enable_irq(priv); ++ ++ pmt_exit(priv); ++ ++ if (!(ndev->flags & IFF_UP)) ++ clk_disable_unprepare(priv->clk); ++ ++ return 0; ++} ++EXPORT_SYMBOL(gmac_dev_resume); ++#endif ++ ++static const struct of_device_id gmac_of_match[] = { ++ { .compatible = "vendor,gmac", }, ++ { .compatible = "vendor,gmac-v1", }, ++ { .compatible = "vendor,gmac-v2", }, ++ { .compatible = "vendor,gmac-v3", }, ++ { .compatible = "vendor,gmac-v4", }, ++ { .compatible = "vendor,gmac-v5", }, ++ { }, ++}; ++ ++MODULE_DEVICE_TABLE(of, gmac_of_match); ++ ++static struct platform_driver gmac_dev_driver = { ++ .probe = gmac_dev_probe, ++ .remove = gmac_dev_remove, ++#ifdef CONFIG_PM ++ .suspend = gmac_dev_suspend, ++ .resume = gmac_dev_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = GMAC_DRIVER_NAME, ++ .of_match_table = gmac_of_match, ++ }, ++}; ++ ++static int __init gmac_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&gmac_dev_driver); ++ if (ret) ++ return ret; ++ ++ gmac_proc_create(); ++ ++ return 0; ++} ++ ++static void __exit gmac_exit(void) ++{ ++ platform_driver_unregister(&gmac_dev_driver); ++ ++ gmac_proc_destroy(); ++} ++ ++module_init(gmac_init); ++module_exit(gmac_exit); ++ ++MODULE_AUTHOR("Vendor"); ++MODULE_DESCRIPTION("Vendor double GMAC driver, base on driver gmacv200"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/net/ethernet/vendor/gmac/gmac.h b/drivers/net/ethernet/vendor/gmac/gmac.h +new file mode 100644 +index 000000000000..d3a3b7842c89 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac.h +@@ -0,0 +1,779 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef GMAC_GMAC_H ++#define GMAC_GMAC_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define STATION_ADDR_LOW 0x0000 ++#define STATION_ADDR_HIGH 0x0004 ++#define MAC_DUPLEX_HALF_CTRL 0x0008 ++ ++#define PORT_MODE 0x0040 ++ ++#define PORT_EN 0x0044 ++#define BITS_TX_EN BIT(2) ++#define BITS_RX_EN BIT(1) ++ ++#define FC_TX_TIMER 0x001C ++ ++#define PAUSE_THR 0x0038 ++ ++#define PAUSE_EN 0x0048 ++#define BIT_RX_FDFC BIT(0) ++#define BIT_TX_FDFC BIT(1) ++ ++#define RX_PAUSE_EN 0x02A4 ++#define BIT_RX_FQ_PAUSE_EN BIT(0) ++#define BIT_RX_BQ_PAUSE_EN BIT(1) ++ ++#define CRF_TX_PAUSE 0x0340 ++ ++#define BITS_Q_PAUSE_TH_OFFSET 16 ++#define BITS_Q_PAUSE_TH_MASK 0xFFFF ++ ++#define REC_FILT_CONTROL 0x0064 ++#define BIT_CRC_ERR_PASS BIT(5) ++#define BIT_PAUSE_FRM_PASS BIT(4) ++#define BIT_VLAN_DROP_EN BIT(3) ++#define BIT_BC_DROP_EN BIT(2) ++#define BIT_MC_MATCH_EN BIT(1) ++#define BIT_UC_MATCH_EN BIT(0) ++ ++#define PORT_MC_ADDR_LOW 0x0068 ++#define PORT_MC_ADDR_HIGH 0x006C ++#define MAC_CLEAR 0x0070 ++#define BIT_TX_SOFT_RESET BIT(0) ++ ++#define MODE_CHANGE_EN 0x01b4 ++#define BIT_MODE_CHANGE_EN BIT(0) ++ ++#define COL_SLOT_TIME 0x01c0 ++ ++#define CRF_MIN_PACKET 0x0210 ++#define BIT_OFFSET_TX_MIN_LEN 8 ++#define BIT_MASK_TX_MIN_LEN GENMASK(13, 8) ++ ++#define CONTROL_WORD 0x0214 ++#define CONTROL_WORD_CONFIG 0x640 ++ ++#define TSO_COE_CTRL 0x02e8 ++#define BIT_COE_IPHDR_DROP BIT(4) ++#define BIT_COE_PAYLOAD_DROP BIT(5) ++#define BIT_COE_IPV6_UDP_ZERO_DROP BIT(6) ++#define COE_ERR_DROP (BIT_COE_IPHDR_DROP | \ ++ BIT_COE_PAYLOAD_DROP | \ ++ BIT_COE_IPV6_UDP_ZERO_DROP) ++ ++#define RX_FQ_START_ADDR 0x0500 ++#define RX_FQ_DEPTH 0x0504 ++#define REG_BIT_WIDTH 32 ++#define Q_ADDR_HI8_OFFSET 24 ++#define Q_ADDR_HI8_MASK (BIT(Q_ADDR_HI8_OFFSET) - 1) ++#define TX_DESC_HI8_MASK 0xff ++#define SG_DESC_HI8_OFFSET 8 ++#define RX_FQ_WR_ADDR 0x0508 ++#define BITS_RX_FQ_WR_ADDR mk_bits(0, 21) ++#define RX_FQ_RD_ADDR 0x050c ++#define BITS_RX_FQ_RD_ADDR mk_bits(0, 21) ++#define RX_FQ_VLDDESC_CNT 0x0510 ++#define BITS_RX_FQ_VLDDESC_CNT mk_bits(0, 16) ++#define RX_FQ_ALEMPTY_TH 0x0514 ++#define BITS_RX_FQ_ALEMPTY_TH mk_bits(0, 16) ++#define RX_FQ_REG_EN 0x0518 ++#define BITS_RX_FQ_START_ADDR_EN BIT(2) ++#define BITS_RX_FQ_DEPTH_EN BIT(1) ++#define BITS_RX_FQ_RD_ADDR_EN mk_bits(0, 1) ++#define RX_FQ_ALFULL_TH 0x051c ++#define BITS_RX_FQ_ALFULL_TH mk_bits(0, 16) ++ ++#define RX_BQ_START_ADDR 0x0520 ++#define RX_BQ_DEPTH 0x0524 ++#define RX_BQ_WR_ADDR 0x0528 ++#define RX_BQ_RD_ADDR 0x052c ++#define RX_BQ_FREE_DESC_CNT 0x0530 ++#define BITS_RX_BQ_FREE_DESC_CNT mk_bits(0, 16) ++#define RX_BQ_ALEMPTY_TH 0x0534 ++#define BITS_RX_BQ_ALEMPTY_TH mk_bits(0, 16) ++#define RX_BQ_REG_EN 0x0538 ++#define BITS_RX_BQ_START_ADDR_EN BIT(2) ++#define BITS_RX_BQ_DEPTH_EN BIT(1) ++#define BITS_RX_BQ_WR_ADDR_EN mk_bits(0, 1) ++#define RX_BQ_ALFULL_TH 0x053c ++#define BITS_RX_BQ_ALFULL_TH mk_bits(0, 16) ++ ++#define TX_BQ_START_ADDR 0x0580 ++#define TX_BQ_DEPTH 0x0584 ++#define TX_BQ_WR_ADDR 0x0588 ++#define BITS_TX_BQ_WR_ADDR mk_bits(0, 21) ++#define TX_BQ_RD_ADDR 0x058c ++#define BITS_TX_BQ_RD_ADDR mk_bits(0, 21) ++#define TX_BQ_VLDDESC_CNT 0x0590 ++#define BITS_TX_BQ_VLDDESC_CNT mk_bits(0, 16) ++#define TX_BQ_ALEMPTY_TH 0x0594 ++#define BITS_TX_BQ_ALEMPTY_TH mk_bits(0, 16) ++#define TX_BQ_REG_EN 0x0598 ++#define BITS_TX_BQ_START_ADDR_EN BIT(2) ++#define BITS_TX_BQ_DEPTH_EN BIT(1) ++#define BITS_TX_BQ_RD_ADDR_EN mk_bits(0, 1) ++#define TX_BQ_ALFULL_TH 0x059c ++#define BITS_TX_BQ_ALFULL_TH mk_bits(0, 16) ++ ++#define TX_RQ_START_ADDR 0x05a0 ++#define TX_RQ_DEPTH 0x05a4 ++#define TX_RQ_WR_ADDR 0x05a8 ++#define BITS_TX_RQ_WR_ADDR mk_bits(0, 21) ++#define TX_RQ_RD_ADDR 0x05ac ++#define BITS_TX_RQ_RD_ADDR mk_bits(0, 21) ++#define TX_RQ_FREE_DESC_CNT 0x05b0 ++#define BITS_TX_RQ_FREE_DESC_CNT mk_bits(0, 16) ++#define TX_RQ_ALEMPTY_TH 0x05b4 ++#define BITS_TX_RQ_ALEMPTY_TH mk_bits(0, 16) ++#define TX_RQ_REG_EN 0x05b8 ++#define BITS_TX_RQ_START_ADDR_EN BIT(2) ++#define BITS_TX_RQ_DEPTH_EN BIT(1) ++#define BITS_TX_RQ_WR_ADDR_EN mk_bits(0, 1) ++#define TX_RQ_ALFULL_TH 0x05bc ++#define BITS_TX_RQ_ALFULL_TH mk_bits(0, 16) ++ ++#define RAW_PMU_INT 0x05c0 ++#define ENA_PMU_INT 0x05c4 ++ ++#define DESC_WR_RD_ENA 0x05CC ++ ++#define IN_QUEUE_TH 0x05d8 ++#define BITS_OFFSET_TX_RQ_IN_TH 16 ++ ++#define RX_BQ_IN_TIMEOUT_TH 0x05E0 ++ ++#define TX_RQ_IN_TIMEOUT_TH 0x05e4 ++ ++#define STOP_CMD 0x05e8 ++#define BITS_TX_STOP_EN BIT(1) ++#define BITS_RX_STOP_EN BIT(0) ++#define STOP_RX_TX (BITS_TX_STOP_EN | BITS_RX_STOP_EN) ++ ++#define RSS_IND_TBL 0x0c0c ++#define BIT_IND_TBL_READY BIT(13) ++#define BIT_IND_TLB_WR BIT(12) ++#define RSS_RAW_PMU_INT 0x0c10 ++#define RSS_QUEUE1_START_ADDR 0x0c20 ++#define rx_bq_start_addr_queue(i) (RSS_QUEUE1_START_ADDR + \ ++ ((i) - 1) * 0x10) ++#define RSS_QUEUE1_DEPTH 0x0c24 ++#define RX_BQ_WR_ADDR_QUEUE1 0x0c28 ++#define RX_BQ_RD_ADDR_QUEUE1 0x0c2c ++#define RSS_QUEUE1_ENA_INT 0x0c90 ++#define rss_ena_int_queue(i) (RSS_QUEUE1_ENA_INT + ((i) - 1) * 0x4) ++#define rx_bq_depth_queue(i) (RSS_QUEUE1_DEPTH + ((i) - 1) * 0x10) ++#define rx_bq_wr_addr_queue(i) ((i) ? (RX_BQ_WR_ADDR_QUEUE1 + \ ++ ((i) - 1) * 0x10) : RX_BQ_WR_ADDR) ++#define rx_bq_rd_addr_queue(i) ((i) ? (RX_BQ_RD_ADDR_QUEUE1 + \ ++ ((i) - 1) * 0x10) : RX_BQ_RD_ADDR) ++ ++#define def_int_mask_queue(i) (0x3 << (2 * ((i) - 1))) ++ ++/* AXI burst and outstanding config */ ++#define BURST_OUTSTANDING_REG 0x3014 ++#define BURST4_OUTSTANDING1 0x81ff ++#define BURST_OUTSTANDING_OFFSET 16 ++ ++#define GMAC_SPEED_1000 0x05 ++#define GMAC_SPEED_100 0x01 ++#define GMAC_SPEED_10 0x00 ++ ++#define IPV4_HEAD_LENGTH 0x5 ++ ++enum gmac_tx_err { ++ ERR_NONE = 0, ++ ERR_DESC_CFG = (1 << 0), ++ ERR_DATA_LEN = (1 << 1), ++ ERR_DESC_NFRAG_NUM = (1 << 2), /* bit2 */ ++ ERR_DESC_IP_HDR_LEN = (1 << 3), /* bit3 */ ++ ERR_DESC_PROT_HDR_LEN = (1 << 4), /* bit4 */ ++ ERR_DESC_MTU = (1 << 5), /* bit5 */ ++ ERR_LINK_SGPKT_LEN = (1 << 8), /* bit8 */ ++ ERR_LINK_TSOPKT_LINEAR = (1 << 9), /* bit9 */ ++ ERR_LINK_NFRAG_LEN = (1 << 10), /* bit10 */ ++ ERR_LINK_TOTAL_LEN = (1 << 11), /* bit11 */ ++ ERR_HDR_TCP_BCMC = (1 << 12), /* bit12 */ ++ ERR_HDR_UDP_BC = (1 << 13), /* bit13 */ ++ ERR_HDR_VLAN_IP_TYPE = (1 << 14), /* bit14 */ ++ ERR_HDR_IP_TYPE = (1 << 15), /* bit15 */ ++ ERR_HDR_IP_VERSION = (1 << 16), /* bit16 */ ++ ERR_HDR_IP_HDR_LEN = (1 << 17), /* bit17 */ ++ ERR_HDR_IP_TOTAL_LEN = (1 << 18), /* bit18 */ ++ ERR_HDR_IPV6_TTL_PROT = (1 << 19), /* bit19 */ ++ ERR_HDR_IPV4_OFFSET = (1 << 20), /* bit20 */ ++ ERR_HDR_IPV4_TTL_PROT = (1 << 21), /* bit21 */ ++ ERR_HDR_UDP_LEN = (1 << 22), /* bit22 */ ++ ERR_HDR_TCP_LEN = (1 << 23), /* bit23 */ ++ ERR_DESC = (ERR_DESC_CFG | ERR_DATA_LEN | ++ ERR_DESC_NFRAG_NUM | ERR_DESC_IP_HDR_LEN | ++ ERR_DESC_PROT_HDR_LEN | ERR_DESC_MTU), ++ ERR_LINK = (ERR_LINK_SGPKT_LEN | ERR_LINK_TSOPKT_LINEAR | ++ ERR_LINK_NFRAG_LEN | ERR_LINK_TOTAL_LEN), ++ ERR_HDR = (ERR_HDR_TCP_BCMC | ERR_HDR_UDP_BC | ++ ERR_HDR_VLAN_IP_TYPE | ERR_HDR_IP_TYPE | ++ ERR_HDR_IP_VERSION | ERR_HDR_IP_HDR_LEN | ++ ERR_HDR_IP_TOTAL_LEN | ERR_HDR_IPV6_TTL_PROT | ++ ERR_HDR_IPV4_OFFSET | ERR_HDR_IPV4_TTL_PROT | ++ ERR_HDR_UDP_LEN | ERR_HDR_TCP_LEN), ++ ERR_ALL = (ERR_DESC | ERR_LINK | ERR_HDR), ++}; ++ ++#define GMAC_DRIVER_NAME "gmac_v200" ++ ++#define GMAC_MAC_CLK_NAME "gmac_clk" ++#define GMAC_MACIF_CLK_NAME "macif_clk" ++ ++#define GMAC_PORT_RST_NAME "port_reset" ++#define GMAC_MACIF_RST_NAME "macif_reset" ++#define GMAC_PHY_RST_NAME "phy_reset" ++ ++#define GMAC_IOSIZE 0x1000 ++#define GMAC_OFFSET (GMAC_IOSIZE) ++ ++#define RX_BQ_IN_INT BIT(17) ++#define TX_RQ_IN_INT BIT(19) ++#define RX_BQ_IN_TIMEOUT_INT BIT(28) ++#define TX_RQ_IN_TIMEOUT_INT BIT(29) ++ ++#define DEF_INT_MASK (RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT | \ ++ TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT) ++ ++/* write or read descriptor need memory barrier */ ++#define gmac_sync_barrier() do { isb(); smp_mb(); } while (0) ++ ++#define VENDOR_PHY_ID_FESTAV200 0x20669823 ++#define PHY_ID_KSZ8051MNL 0x00221550 ++#define PHY_ID_KSZ8081RNB 0x00221560 ++#define PHY_ID_UNKNOWN 0x00221513 ++#define DEFAULT_PHY_MASK 0xfffffff0 ++#define REALTEK_PHY_ID_8211E 0x001cc915 ++#define REALTEK_PHY_ID_8211FS 0x001cc916 ++#define REALTEK_PHY_MASK 0x001fffff ++ ++enum { ++ GMAC_PORT0, ++ GMAC_PORT1, ++ GMAC_MAX_PORT, ++}; ++ ++enum { ++ MEM_GMAC_IOBASE, ++ MEM_MACIF_IOBASE, ++ MEM_AXI_BUS_CFG_IOBASE, ++ MEM_FWD_IOBASE, ++ MEM_CTRL_IOBASE, ++}; ++ ++#define GMAC_LINKED BIT(0) ++#define GMAC_DUP_FULL BIT(1) ++#define GMAC_SPD_10M BIT(2) ++#define GMAC_SPD_100M BIT(3) ++#define GMAC_SPD_1000M BIT(4) ++/* Flow Control defines */ ++#define FLOW_OFF 0 ++#define FLOW_RX 1 ++#define FLOW_TX 2 ++#define FLOW_AUTO (FLOW_TX | FLOW_RX) ++ ++#define RX_BQ_INT_THRESHOLD 0x40 ++#define TX_RQ_INT_THRESHOLD 0x20 ++ ++#define GMAC_MONITOR_TIMER (msecs_to_jiffies(200)) ++ ++#define ETH_MAX_FRAME_SIZE (1600 + 128) ++#define SKB_SIZE (ETH_MAX_FRAME_SIZE) ++ ++#define DESC_VLD_FREE 0 ++#define DESC_VLD_BUSY 1 ++ ++#define DESC_FL_FIRST 2 ++#define DESC_FL_MID 0 ++#define DESC_FL_LAST 1 ++#define DESC_FL_FULL 3 ++ ++#if defined(CONFIG_GMAC_DESC_4WORD) ++#define DESC_WORD_SHIFT 2 ++#else ++#define DESC_WORD_SHIFT 3 ++#endif ++#define DESC_BYTE_SHIFT (DESC_WORD_SHIFT + 2) ++#define DESC_WORD_CNT (1 << DESC_WORD_SHIFT) ++#define DESC_SIZE (1 << DESC_BYTE_SHIFT) ++ ++#define RX_DESC_NUM 1024 ++#define TX_DESC_NUM 1024 ++ ++/* DMA descriptor ring helpers */ ++#define dma_ring_incr(n, s) (((n) + 1) & ((s) - 1)) ++#define dma_cnt(n) ((n) >> DESC_BYTE_SHIFT) ++#define dma_byte(n) ((n) << DESC_BYTE_SHIFT) ++ ++#define RSS_HASH_KEY_SIZE 4 ++#define RSS_INDIRECTION_TABLE_SIZE 128 ++#define RSS_NUM_RXQS 4 ++ ++#define HW_CAP_TSO BIT(0) ++#define HW_CAP_RXCSUM BIT(1) ++#define HW_CAP_CCI BIT(2) ++#define has_cap_tso(hw_cap) ((hw_cap) & HW_CAP_TSO) ++#define has_cap_rxcsum(hw_cap) ((hw_cap) & HW_CAP_RXCSUM) ++ ++#define GMAC_TRACE_LEVEL 10 ++#define GMAC_NORMAL_LEVEL 7 ++ ++#define mk_bits(shift, nbits) ((((shift) & 0x1F) << 16) | ((nbits) & 0x3F)) ++ ++#define FC_ACTIVE_MIN 1 ++#define FC_ACTIVE_DEFAULT 16 ++#define FC_ACTIVE_MAX 127 ++#define FC_DEACTIVE_MIN 1 ++#define FC_DEACTIVE_DEFAULT 32 ++#define FC_DEACTIVE_MAX 127 ++ ++#define FC_PAUSE_TIME_DEFAULT 0xFFFF ++#define FC_PAUSE_INTERVAL_DEFAULT 0xFFFF ++#define FC_PAUSE_TIME_MAX 0xFFFF ++ ++#define HW_CAP_EN 0x0c00 ++#define BIT_RSS_CAP BIT(0) ++#define BIT_RXHASH_CAP BIT(1) ++#define RSS_HASH_KEY 0x0c04 ++#define RSS_HASH_CONFIG 0x0c08 ++#define TCPV4_L3_HASH_EN BIT(0) ++#define TCPV4_L4_HASH_EN BIT(1) ++#define TCPV4_VLAN_HASH_EN BIT(2) ++#define UDPV4_L3_HASH_EN BIT(4) ++#define UDPV4_L4_HASH_EN BIT(5) ++#define UDPV4_VLAN_HASH_EN BIT(6) ++#define IPV4_L3_HASH_EN BIT(8) ++#define IPV4_VLAN_HASH_EN BIT(9) ++#define TCPV6_L3_HASH_EN BIT(12) ++#define TCPV6_L4_HASH_EN BIT(13) ++#define TCPV6_VLAN_HASH_EN BIT(14) ++#define UDPV6_L3_HASH_EN BIT(16) ++#define UDPV6_L4_HASH_EN BIT(17) ++#define UDPV6_VLAN_HASH_EN BIT(18) ++#define IPV6_L3_HASH_EN BIT(20) ++#define IPV6_VLAN_HASH_EN BIT(21) ++#define DEF_HASH_CFG 0x377377 ++ ++#define RGMII_SPEED_1000 0x2c ++#define RGMII_SPEED_100 0x2f ++#define RGMII_SPEED_10 0x2d ++#define MII_SPEED_100 0x0f ++#define MII_SPEED_10 0x0d ++#define RMII_SPEED_100 0x8f ++#define RMII_SPEED_10 0x8d ++#define GMAC_FULL_DUPLEX BIT(4) ++ ++/* tso stuff */ ++#define SG_FLAG BIT(30) ++#define COE_FLAG BIT(29) ++#define TSO_FLAG BIT(28) ++#define VLAN_FLAG BIT(10) ++#define IPV6_FLAG BIT(9) ++#define UDP_FLAG BIT(8) ++ ++#define PKT_IPV6_HDR_LEN 10 ++#define PKT_UDP_HDR_LEN 2 ++#define WORD_TO_BYTE 4 ++enum { ++ PKT_NORMAL, ++ PKT_SG ++}; ++ ++enum { ++ PKT_IPV4, ++ PKT_IPV6 ++}; ++ ++enum { ++ PKT_TCP, ++ PKT_UDP ++}; ++ ++struct frags_info { ++ /* Word(2*i+2) */ ++ u32 addr; ++ /* Word(2*i+3) */ ++ u32 size : 16; ++ u32 reserved : 16; ++}; ++ ++struct sg_desc { ++ /* Word0 */ ++ u32 total_len : 17; ++ u32 reserv : 15; ++ /* Word1 */ ++ u32 ipv6_id; ++ /* Word2 */ ++ u32 linear_addr; ++ /* Word3 */ ++ u32 linear_len : 16; ++ u32 reserv3 : 16; ++ /* MAX_SKB_FRAGS is 18 */ ++ struct frags_info frags[18]; ++}; ++/* tso stuff end */ ++ ++#if defined(CONFIG_GMAC_DESC_4WORD) ++struct gmac_desc { ++ unsigned int data_buff_addr; ++ ++ unsigned int buffer_len : 11; ++#if defined(CONFIG_GMAC_RXCSUM) ++ unsigned int reserve2 : 1; ++ unsigned int payload_csum_err : 1; ++ unsigned int header_csum_err : 1; ++ unsigned int payload_csum_done : 1; ++ unsigned int header_csum_done : 1; ++#else ++ unsigned int reserve2 : 5; ++#endif ++ unsigned int data_len : 11; ++ unsigned int reserve1 : 2; ++ unsigned int fl : 2; ++ unsigned int descvid : 1; ++ ++ unsigned int rxhash; ++ unsigned int reserve3 : 8; ++ unsigned int l3_hash : 1; ++ unsigned int has_hash : 1; ++ unsigned int skb_id : 14; ++ unsigned int reserve31 : 8; ++}; ++ ++struct gmac_tso_desc { ++ unsigned int data_buff_addr; ++ union { ++ struct { ++ unsigned int prot_hdr_len : 4; ++ unsigned int ip_hdr_len : 4; ++ unsigned int prot_type : 1; ++ unsigned int ip_ver : 1; ++ unsigned int vlan_flag : 1; ++ unsigned int nfrags_num : 5; ++ unsigned int data_len : 11; ++ unsigned int reservel : 1; ++ unsigned int tso_flag : 1; ++ unsigned int coe_flag : 1; ++ unsigned int sg_flag : 1; ++ unsigned int hw_own : 1; ++ } tx; ++ unsigned int val; ++ } desc1; ++ unsigned int reserve_desc2; ++ unsigned int tx_err; ++}; ++#else ++struct gmac_desc { ++ unsigned int data_buff_addr; ++ ++ unsigned int buffer_len : 11; ++#if defined(CONFIG_GMAC_RXCSUM) ++ unsigned int reserve2 : 1; ++ unsigned int payload_csum_err : 1; ++ unsigned int header_csum_err : 1; ++ unsigned int payload_csum_done : 1; ++#else ++ unsigned int reserve2 : 5; ++#endif ++ unsigned int data_len : 11; ++ unsigned int reserve1 : 2; ++ unsigned int fl : 2; ++ unsigned int descvid : 1; ++ ++ unsigned int rxhash; ++ unsigned int reserve3 : 8; ++ unsigned int l3_hash : 1; ++ unsigned int has_hash : 1; ++ unsigned int skb_id : 14; ++ unsigned int reserve31 : 8; ++ ++ unsigned int reserve4; ++ unsigned int reserve5; ++ unsigned int reserve6; ++ unsigned int reserve7; ++}; ++ ++struct gmac_tso_desc { ++ unsigned int data_buff_addr; ++ union { ++ struct { ++ unsigned int prot_hdr_len : 4; ++ unsigned int ip_hdr_len : 4; ++ unsigned int prot_type : 1; ++ unsigned int ip_ver : 1; ++ unsigned int vlan_flag : 1; ++ unsigned int nfrags_num : 5; ++ unsigned int data_len : 11; ++ unsigned int reservel : 1; ++ unsigned int tso_flag : 1; ++ unsigned int coe_flag : 1; ++ unsigned int sg_flag : 1; ++ unsigned int hw_own : 1; ++ } tx; ++ unsigned int val; ++ } desc1; ++ unsigned int reserve_desc2; ++ unsigned int reserve3; ++ ++ unsigned int tx_err; ++ unsigned int reserve5; ++ unsigned int reserve6; ++ unsigned int reserve7; ++}; ++#endif ++ ++#define SKB_MAGIC ((struct sk_buff *)0x5a) ++ ++struct gmac_napi { ++ struct napi_struct napi; ++ struct gmac_netdev_local *ndev_priv; ++ int rxq_id; ++}; ++ ++struct gmac_rss_info { ++ u32 hash_cfg; ++ u32 ind_tbl_size; ++ u8 ind_tbl[RSS_INDIRECTION_TABLE_SIZE]; ++ u8 key[RSS_HASH_KEY_SIZE]; ++}; ++ ++#define QUEUE_NUMS 4 ++#define BASE_QUEUE_NUMS 3 ++ ++struct gmac_netdev_local { ++#define GMAC_SG_DESC_ADD 64U ++ struct sg_desc *dma_sg_desc ____cacheline_aligned; ++ dma_addr_t dma_sg_phy; ++ unsigned int sg_head; ++ unsigned int sg_tail; ++ unsigned int sg_count; ++ ++ void __iomem *gmac_iobase; ++ void __iomem *macif_base; ++ void __iomem *axi_bus_cfg_base; ++ int index; /* 0 -- mac0, 1 -- mac1 */ ++ ++ u32 hw_cap; ++ bool tso_supported; ++ bool has_rxhash_cap; ++ bool has_rss_cap; ++ int num_rxqs; ++ struct gmac_napi q_napi[RSS_NUM_RXQS]; ++ int irq[RSS_NUM_RXQS]; ++ struct gmac_rss_info rss_info; ++ ++ struct reset_control *port_rst; ++ struct reset_control *macif_rst; ++ struct reset_control *phy_rst; ++ ++ struct { ++ struct gmac_desc *desc; ++ dma_addr_t phys_addr; ++ int *sg_desc_offset; ++ /* how many desc in the desc pool */ ++ unsigned int count; ++ struct sk_buff **skb; ++ unsigned int size; ++ } pool[QUEUE_NUMS + RSS_NUM_RXQS - 1]; ++#define RX_FQ pool[0] ++#define RX_BQ pool[1] ++#define TX_BQ pool[2] ++#define TX_RQ pool[3] ++ ++ struct sk_buff **tx_skb; ++ struct sk_buff **rx_skb; ++ ++ struct device *dev; ++ struct net_device *netdev; ++ struct clk *clk; ++ struct clk *macif_clk; ++ ++ struct gmac_adapter *adapter; ++ ++ struct timer_list monitor; ++ ++ char phy_name[MII_BUS_ID_SIZE]; ++ struct phy_device *phy; ++ struct device_node *phy_node; ++ phy_interface_t phy_mode; ++ bool autoeee; ++ bool internal_phy; ++ int (*eee_init)(struct phy_device *phy_dev); ++ ++ unsigned int flow_ctrl; ++ unsigned int pause; ++ unsigned int pause_interval; ++ unsigned int flow_ctrl_active_threshold; ++ unsigned int flow_ctrl_deactive_threshold; ++ ++ int old_link; ++ int old_speed; ++ int old_duplex; ++ ++ /* receive packet lock */ ++ spinlock_t rxlock; ++ /* transmit packet lock */ ++ spinlock_t txlock; ++ /* power management lock */ ++ spinlock_t pmtlock; ++ ++ int dev_state; /* INIT/OPEN/CLOSE */ ++ char pm_state; ++ bool wol_enable; ++ u32 msg_enable; ++#define INIT 0 /* init gmac */ ++#define OPEN 1 /* power on gmac */ ++#define CLOSE 2 /* power off gmac */ ++}; ++ ++enum tso_version { ++ VER_NO_TSO = 0x0, ++ VER_BYTE_SPLICE = 0x1, ++ VER_SG_COE = 0x2, ++ VER_TSO = 0x3, ++}; ++ ++struct cyclic_queue_info { ++ u32 start; ++ u32 end; ++ u32 num; ++ u32 pos; ++}; ++ ++/* ethtool ops related func */ ++void gmac_set_flow_ctrl_state(struct gmac_netdev_local const *ld, int pause); ++ ++/* netdev ops related func */ ++void gmac_hw_set_mac_addr(struct net_device *dev); ++void gmac_enable_napi(struct gmac_netdev_local *priv); ++void gmac_disable_napi(struct gmac_netdev_local *priv); ++u32 gmac_rx_refill(struct gmac_netdev_local *priv); ++void gmac_enable_rxcsum_drop(struct gmac_netdev_local const *ld, bool drop); ++ ++static inline void gmac_irq_enable(struct gmac_netdev_local const *ld) ++{ ++ if (ld == NULL) ++ return; ++ ++ writel(RX_BQ_IN_INT | RX_BQ_IN_TIMEOUT_INT ++ | TX_RQ_IN_INT | TX_RQ_IN_TIMEOUT_INT, ++ ld->gmac_iobase + ENA_PMU_INT); ++} ++ ++static inline void gmac_irq_enable_queue(struct gmac_netdev_local *ld, unsigned int rxq_id) ++{ ++ if (ld == NULL) ++ return; ++ ++ if (rxq_id) { ++ const u32 reg = rss_ena_int_queue(rxq_id); ++ writel(~0, ld->gmac_iobase + reg); ++ } else { ++ gmac_irq_enable(ld); ++ } ++} ++ ++static inline void gmac_irq_enable_all_queue(struct gmac_netdev_local *ld) ++{ ++ unsigned int i; ++ ++ if (ld == NULL) ++ return; ++ ++ for (i = 0; i < (unsigned int)ld->num_rxqs; i++) ++ gmac_irq_enable_queue(ld, i); ++} ++ ++static inline void gmac_irq_disable(struct gmac_netdev_local const *ld) ++{ ++ if (ld == NULL) ++ return; ++ ++ writel(0, ld->gmac_iobase + ENA_PMU_INT); ++} ++ ++static inline void gmac_irq_disable_queue(struct gmac_netdev_local const *ld, ++ int rxq_id) ++{ ++ if (ld == NULL) ++ return; ++ ++ if (rxq_id) { ++ u32 reg = (u32)rss_ena_int_queue(rxq_id); ++ writel(0, ld->gmac_iobase + reg); ++ } else { ++ gmac_irq_disable(ld); ++ } ++} ++ ++static inline void gmac_irq_disable_all_queue(struct gmac_netdev_local const *ld) ++{ ++ int i; ++ ++ if (ld == NULL) ++ return; ++ ++ for (i = 0; i < ld->num_rxqs; i++) ++ gmac_irq_disable_queue(ld, i); ++} ++ ++static inline bool gmac_queue_irq_disabled(struct gmac_netdev_local *ld, ++ int rxq_id) ++{ ++ u32 reg, val; ++ ++ if (ld == NULL) ++ return false; ++ ++ if (rxq_id) ++ reg = (u32)rss_ena_int_queue(rxq_id); ++ else ++ reg = ENA_PMU_INT; ++ val = readl(ld->gmac_iobase + reg); ++ ++ return !val; ++} ++ ++static inline void gmac_hw_desc_enable(struct gmac_netdev_local const *ld) ++{ ++ if (ld == NULL) ++ return; ++ writel(0xF, ld->gmac_iobase + DESC_WR_RD_ENA); ++} ++ ++static inline void gmac_hw_desc_disable(struct gmac_netdev_local const *ld) ++{ ++ if (ld == NULL) ++ return; ++ writel(0, ld->gmac_iobase + DESC_WR_RD_ENA); ++} ++ ++static inline void gmac_port_enable(struct gmac_netdev_local const *ld) ++{ ++ if (ld == NULL) ++ return; ++ writel(BITS_TX_EN | BITS_RX_EN, ld->gmac_iobase + PORT_EN); ++} ++ ++static inline void gmac_port_disable(struct gmac_netdev_local const *ld) ++{ ++ if (ld != NULL) ++ writel(0, ld->gmac_iobase + PORT_EN); ++} ++ ++#endif +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.c b/drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.c +new file mode 100644 +index 000000000000..646a93d567d1 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.c +@@ -0,0 +1,401 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++ ++#include "gmac.h" ++#include "gmac_ethtool_ops.h" ++ ++void gmac_get_drvinfo(struct net_device *net_dev, ++ struct ethtool_drvinfo *info) ++{ ++ if (info == NULL) ++ return; ++ if (strncpy_s(info->driver, sizeof(info->driver), "gmac driver", sizeof(info->driver))) ++ printk("strncpy_s err : %s %d.\n", __func__, __LINE__); ++ if (strncpy_s(info->version, sizeof(info->version), "gmac v200", sizeof(info->version))) ++ printk("strncpy_s err : %s %d.\n", __func__, __LINE__); ++ if (strncpy_s(info->bus_info, sizeof(info->bus_info), "platform", sizeof(info->bus_info))) ++ printk("strncpy_s err : %s %d.\n", __func__, __LINE__); ++} ++ ++unsigned int gmac_get_link(struct net_device *net_dev) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(net_dev); ++ ++ return ld->phy->link ? GMAC_LINKED : 0; ++} ++ ++void gmac_get_pauseparam(struct net_device *net_dev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct gmac_netdev_local *ld = NULL; ++ if (net_dev == NULL || pause == NULL) ++ return; ++ ld = netdev_priv(net_dev); ++ ++ pause->rx_pause = 0; ++ pause->tx_pause = 0; ++ pause->autoneg = ld->phy->autoneg; ++ ++ if (ld->phy->pause && (ld->flow_ctrl & FLOW_RX)) ++ pause->rx_pause = 1; ++ if (ld->phy->pause && (ld->flow_ctrl & FLOW_TX)) ++ pause->tx_pause = 1; ++} ++ ++int gmac_set_pauseparam(struct net_device *net_dev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(net_dev); ++ struct phy_device *phy = ld->phy; ++ unsigned int new_pause = FLOW_OFF; ++ ++ if (pause == NULL) ++ return -ENOMEM; ++ ++ if (pause->rx_pause) ++ new_pause |= FLOW_RX; ++ if (pause->tx_pause) ++ new_pause |= FLOW_TX; ++ ++ if (new_pause != ld->flow_ctrl) ++ ld->flow_ctrl = new_pause; ++ ++ gmac_set_flow_ctrl_state(ld, phy->pause); ++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT, phy->advertising); ++ if (ld->flow_ctrl) ++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phy->advertising); ++ ++ if (phy->autoneg) { ++ if (netif_running(net_dev)) ++ return phy_start_aneg(phy); ++ } ++ ++ return 0; ++} ++ ++u32 gmac_ethtool_getmsglevel(struct net_device *ndev) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ ++ return priv->msg_enable; ++} ++ ++void gmac_ethtool_setmsglevel(struct net_device *ndev, u32 level) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ ++ priv->msg_enable = level; ++} ++ ++u32 gmac_get_rxfh_key_size(struct net_device *ndev) ++{ ++ return RSS_HASH_KEY_SIZE; ++} ++ ++u32 gmac_get_rxfh_indir_size(struct net_device *ndev) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ ++ return priv->rss_info.ind_tbl_size; ++} ++ ++int gmac_get_rxfh(struct net_device *ndev, u32 *indir, u8 *hkey, ++ u8 *hfunc) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ struct gmac_rss_info *rss = &priv->rss_info; ++ ++ if (hfunc != NULL) ++ *hfunc = ETH_RSS_HASH_TOP; ++ ++ if (hkey != NULL) ++ if (memcpy_s(hkey, RSS_HASH_KEY_SIZE, rss->key, RSS_HASH_KEY_SIZE) < 0) ++ printk("memcpy_s err : %s %d.\n", __func__, __LINE__); ++ ++ if (indir != NULL) { ++ int i; ++ ++ for (i = 0; i < rss->ind_tbl_size; i++) ++ indir[i] = rss->ind_tbl[i]; ++ } ++ ++ return 0; ++} ++ ++void gmac_get_rss_key(struct gmac_netdev_local *priv) ++{ ++ struct gmac_rss_info *rss = NULL; ++ u32 hkey; ++ if (priv == NULL) ++ return; ++ rss = &priv->rss_info; ++ hkey = readl(priv->gmac_iobase + RSS_HASH_KEY); ++ *((u32 *)rss->key) = hkey; ++} ++ ++static void gmac_set_rss_key(struct gmac_netdev_local *priv) ++{ ++ struct gmac_rss_info *rss = &priv->rss_info; ++ ++ writel(*((u32 *)rss->key), priv->gmac_iobase + RSS_HASH_KEY); ++} ++ ++static int gmac_wait_rss_ready(struct gmac_netdev_local const *priv) ++{ ++ void __iomem *base = priv->gmac_iobase; ++ int i; ++ const int timeout = 10000; ++ ++ for (i = 0; !(readl(base + RSS_IND_TBL) & BIT_IND_TBL_READY); i++) { ++ if (i == timeout) { ++ netdev_err(priv->netdev, "wait rss ready timeout!\n"); ++ return -ETIMEDOUT; ++ } ++ usleep_range(10, 20); /* wait 10~20us */ ++ } ++ ++ return 0; ++} ++ ++ ++static void gmac_config_rss(struct gmac_netdev_local *priv) ++{ ++ struct gmac_rss_info *rss = NULL; ++ u32 rss_val; ++ unsigned int i; ++ if (priv == NULL) ++ return; ++ rss = &priv->rss_info; ++ for (i = 0; i < rss->ind_tbl_size; i++) { ++ if (gmac_wait_rss_ready(priv) != 0) ++ break; ++ rss_val = BIT_IND_TLB_WR | (rss->ind_tbl[i] << 8) | i; /* shift 8 */ ++ writel(rss_val, priv->gmac_iobase + RSS_IND_TBL); ++ } ++} ++ ++void gmac_get_rss(struct gmac_netdev_local *priv) ++{ ++ struct gmac_rss_info *rss = NULL; ++ u32 rss_val; ++ int i; ++ if (priv == NULL) ++ return; ++ rss = &priv->rss_info; ++ for (i = 0; i < rss->ind_tbl_size; i++) { ++ if (gmac_wait_rss_ready(priv) != 0) ++ break; ++ writel(i, priv->gmac_iobase + RSS_IND_TBL); ++ if (gmac_wait_rss_ready(priv) != 0) ++ break; ++ rss_val = readl(priv->gmac_iobase + RSS_IND_TBL); ++ rss->ind_tbl[i] = (rss_val >> 10) & 0x3; /* right shift 10 */ ++ } ++} ++ ++int gmac_set_rxfh(struct net_device *ndev, const u32 *indir, ++ const u8 *hkey, const u8 hfunc) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ struct gmac_rss_info *rss = &priv->rss_info; ++ ++ if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) ++ return -EOPNOTSUPP; ++ ++ if (indir != NULL) { ++ int i; ++ ++ for (i = 0; i < rss->ind_tbl_size; i++) ++ rss->ind_tbl[i] = indir[i]; ++ } ++ ++ if (hkey != NULL) { ++ if (memcpy_s(rss->key, RSS_HASH_KEY_SIZE, hkey, RSS_HASH_KEY_SIZE) < 0) ++ printk("memcpy_s err : %s %d.\n", __func__, __LINE__); ++ gmac_set_rss_key(priv); ++ } ++ ++ gmac_config_rss(priv); ++ ++ return 0; ++} ++ ++static void gmac_get_rss_hash(struct ethtool_rxnfc *info, u32 hash_cfg, ++ u32 l3_hash_en, u32 l4_hash_en, u32 vlan_hash_en) ++{ ++ if (hash_cfg & l3_hash_en) ++ info->data |= RXH_IP_SRC | RXH_IP_DST; ++ if (hash_cfg & l4_hash_en) ++ info->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; ++ if (hash_cfg & vlan_hash_en) ++ info->data |= RXH_VLAN; ++} ++ ++static int gmac_get_rss_hash_opts(struct gmac_netdev_local const *priv, ++ struct ethtool_rxnfc *info) ++{ ++ u32 hash_cfg = priv->rss_info.hash_cfg; ++ ++ info->data = 0; ++ ++ switch (info->flow_type) { ++ case TCP_V4_FLOW: ++ gmac_get_rss_hash(info, hash_cfg, TCPV4_L3_HASH_EN, TCPV4_L4_HASH_EN, ++ TCPV4_VLAN_HASH_EN); ++ break; ++ case TCP_V6_FLOW: ++ gmac_get_rss_hash(info, hash_cfg, TCPV6_L3_HASH_EN, TCPV6_L4_HASH_EN, ++ TCPV6_VLAN_HASH_EN); ++ break; ++ case UDP_V4_FLOW: ++ gmac_get_rss_hash(info, hash_cfg, UDPV4_L3_HASH_EN, UDPV4_L4_HASH_EN, ++ UDPV4_VLAN_HASH_EN); ++ break; ++ case UDP_V6_FLOW: ++ gmac_get_rss_hash(info, hash_cfg, UDPV6_L3_HASH_EN, UDPV6_L4_HASH_EN, ++ UDPV6_VLAN_HASH_EN); ++ break; ++ case IPV4_FLOW: ++ gmac_get_rss_hash(info, hash_cfg, IPV4_L3_HASH_EN, 0, ++ IPV4_VLAN_HASH_EN); ++ break; ++ case IPV6_FLOW: ++ gmac_get_rss_hash(info, hash_cfg, IPV6_L3_HASH_EN, 0, ++ IPV6_VLAN_HASH_EN); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int gmac_get_rxnfc(struct net_device *ndev, ++ struct ethtool_rxnfc *info, u32 *rules) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ int ret = -EOPNOTSUPP; ++ if (info == NULL) ++ return -EINVAL; ++ switch (info->cmd) { ++ case ETHTOOL_GRXRINGS: ++ info->data = priv->num_rxqs; ++ ret = 0; ++ break; ++ case ETHTOOL_GRXFH: ++ return gmac_get_rss_hash_opts(priv, info); ++ default: ++ break; ++ } ++ return ret; ++} ++ ++void gmac_config_hash_policy(struct gmac_netdev_local const *priv) ++{ ++ if (priv == NULL) ++ return; ++ writel(priv->rss_info.hash_cfg, priv->gmac_iobase + RSS_HASH_CONFIG); ++} ++ ++static int gmac_set_tcp_udp_hash_cfg(struct ethtool_rxnfc const *info, ++ u32 *hash_cfg, u32 l4_mask, u32 vlan_mask) ++{ ++ switch (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { ++ case 0: // all bits is 0 ++ *hash_cfg &= ~l4_mask; ++ break; ++ case (RXH_L4_B_0_1 | RXH_L4_B_2_3): ++ *hash_cfg |= l4_mask; ++ break; ++ default: ++ return -EINVAL; ++ } ++ if (info->data & RXH_VLAN) ++ *hash_cfg |= vlan_mask; ++ else ++ *hash_cfg &= ~vlan_mask; ++ return 0; ++} ++ ++static int gmac_ip_hash_cfg(struct ethtool_rxnfc const *info, ++ u32 *hash_cfg, u32 vlan_mask) ++{ ++ if (info->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) ++ return -EINVAL; ++ if (info->data & RXH_VLAN) ++ *hash_cfg |= vlan_mask; ++ else ++ *hash_cfg &= ~vlan_mask; ++ return 0; ++} ++ ++static int gmac_set_rss_hash_opts(struct gmac_netdev_local *priv, ++ struct ethtool_rxnfc const *info) ++{ ++ u32 hash_cfg; ++ if (priv == NULL || priv->netdev == NULL) ++ return -EINVAL; ++ hash_cfg = priv->rss_info.hash_cfg; ++ netdev_info(priv->netdev, "Set RSS flow type = %d, data = %lld\n", ++ info->flow_type, info->data); ++ ++ if (!(info->data & RXH_IP_SRC) || !(info->data & RXH_IP_DST)) ++ return -EINVAL; ++ ++ switch (info->flow_type) { ++ case TCP_V4_FLOW: ++ if (gmac_set_tcp_udp_hash_cfg(info, &hash_cfg, ++ TCPV4_L4_HASH_EN, TCPV4_VLAN_HASH_EN) == -EINVAL) ++ return -EINVAL; ++ break; ++ case TCP_V6_FLOW: ++ if (gmac_set_tcp_udp_hash_cfg(info, &hash_cfg, ++ TCPV6_L4_HASH_EN, TCPV6_VLAN_HASH_EN) == -EINVAL) ++ return -EINVAL; ++ break; ++ case UDP_V4_FLOW: ++ if (gmac_set_tcp_udp_hash_cfg(info, &hash_cfg, ++ UDPV4_L4_HASH_EN, UDPV4_L4_HASH_EN) == -EINVAL) ++ return -EINVAL; ++ break; ++ case UDP_V6_FLOW: ++ if (gmac_set_tcp_udp_hash_cfg(info, &hash_cfg, ++ UDPV6_L4_HASH_EN, UDPV6_L4_HASH_EN) == -EINVAL) ++ return -EINVAL; ++ break; ++ case IPV4_FLOW: ++ if (gmac_ip_hash_cfg(info, &hash_cfg, ++ IPV4_VLAN_HASH_EN) == -EINVAL) ++ return -EINVAL; ++ break; ++ case IPV6_FLOW: ++ if (gmac_ip_hash_cfg(info, &hash_cfg, ++ IPV6_VLAN_HASH_EN) == -EINVAL) ++ return -EINVAL; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ priv->rss_info.hash_cfg = hash_cfg; ++ gmac_config_hash_policy(priv); ++ ++ return 0; ++} ++ ++int gmac_set_rxnfc(struct net_device *ndev, struct ethtool_rxnfc *info) ++{ ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ if (info == NULL) ++ return -EINVAL; ++ switch (info->cmd) { ++ case ETHTOOL_SRXFH: ++ return gmac_set_rss_hash_opts(priv, info); ++ default: ++ break; ++ } ++ return -EOPNOTSUPP; ++} +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.h b/drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.h +new file mode 100644 +index 000000000000..f77681838da6 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_ethtool_ops.h +@@ -0,0 +1,35 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef GMAC_ETHTOOL_OPS_H ++#define GMAC_ETHTOOL_OPS_H ++ ++#include "gmac.h" ++ ++void gmac_get_drvinfo(struct net_device *net_dev, ++ struct ethtool_drvinfo *info); ++unsigned int gmac_get_link(struct net_device *net_dev); ++int gmac_get_settings(struct net_device *net_dev, struct ethtool_cmd *cmd); ++int gmac_set_settings(struct net_device *net_dev, struct ethtool_cmd *cmd); ++void gmac_get_pauseparam(struct net_device *net_dev, ++ struct ethtool_pauseparam *pause); ++int gmac_set_pauseparam(struct net_device *net_dev, ++ struct ethtool_pauseparam *pause); ++u32 gmac_ethtool_getmsglevel(struct net_device *ndev); ++void gmac_ethtool_setmsglevel(struct net_device *ndev, u32 level); ++u32 gmac_get_rxfh_key_size(struct net_device *ndev); ++u32 gmac_get_rxfh_indir_size(struct net_device *ndev); ++int gmac_get_rxfh(struct net_device *ndev, u32 *indir, u8 *hkey, u8 *hfunc); ++int gmac_set_rxfh(struct net_device *ndev, const u32 *indir, ++ const u8 *hkey, const u8 hfunc); ++int gmac_get_rxnfc(struct net_device *ndev, ++ struct ethtool_rxnfc *info, u32 *rules); ++int gmac_set_rxnfc(struct net_device *ndev, struct ethtool_rxnfc *info); ++ ++/* gmac.c related func */ ++void gmac_get_rss_key(struct gmac_netdev_local *priv); ++void gmac_get_rss(struct gmac_netdev_local *priv); ++void gmac_config_hash_policy(struct gmac_netdev_local const *priv); ++ ++#endif +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.c b/drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.c +new file mode 100644 +index 000000000000..027b16c0b698 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.c +@@ -0,0 +1,730 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "gmac_pm.h" ++#include "gmac_proc.h" ++#include "gmac_netdev_ops.h" ++ ++int gmac_net_open(struct net_device *dev) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ unsigned long flags; ++ ++ clk_prepare_enable(ld->macif_clk); ++ clk_prepare_enable(ld->clk); ++ ++ /* ++ * If we configure mac address by ++ * "ifconfig ethX hw ether XX:XX:XX:XX:XX:XX", ++ * the ethX must be down state and mac core clock is disabled ++ * which results the mac address has not been configured ++ * in mac core register. ++ * So we must set mac address again here, ++ * because mac core clock is enabled at this time ++ * and we can configure mac address to mac core register. ++ */ ++ gmac_hw_set_mac_addr(dev); ++ ++ /* ++ * We should use netif_carrier_off() here, ++ * because the default state should be off. ++ * And this call should before phy_start(). ++ */ ++ netif_carrier_off(dev); ++ gmac_enable_napi(ld); ++ phy_start(ld->phy); ++ ++ gmac_hw_desc_enable(ld); ++ gmac_port_enable(ld); ++ gmac_irq_enable_all_queue(ld); ++ ++ spin_lock_irqsave(&ld->rxlock, flags); ++ gmac_rx_refill(ld); ++ spin_unlock_irqrestore(&ld->rxlock, flags); ++ ++ ld->monitor.expires = jiffies + GMAC_MONITOR_TIMER; ++ mod_timer(&ld->monitor, ld->monitor.expires); ++ ++ netif_start_queue(dev); ++ ++ return 0; ++} ++ ++int gmac_net_close(struct net_device *dev) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ ++ gmac_irq_disable_all_queue(ld); ++ gmac_hw_desc_disable(ld); ++ ++ gmac_disable_napi(ld); ++ ++ netif_carrier_off(dev); ++ netif_stop_queue(dev); ++ ++ phy_stop(ld->phy); ++ del_timer_sync(&ld->monitor); ++ ++ clk_disable_unprepare(ld->clk); ++ clk_disable_unprepare(ld->macif_clk); ++ ++ return 0; ++} ++ ++static int gmac_check_skb_len(struct sk_buff *skb, struct net_device *dev) ++{ ++ if (skb->len < ETH_HLEN) { ++ dev_kfree_skb_any(skb); ++ dev->stats.tx_errors++; ++ dev->stats.tx_dropped++; ++ return -1; ++ } ++ return 0; ++} ++ ++static int gmac_net_xmit_normal(struct sk_buff *skb, struct net_device *dev, ++ struct gmac_desc *desc, u32 pos) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ dma_addr_t addr; ++ ++ addr = dma_map_single(ld->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (unlikely(dma_mapping_error(ld->dev, addr))) { ++ dev_kfree_skb_any(skb); ++ dev->stats.tx_dropped++; ++ ld->tx_skb[pos] = NULL; ++ ld->TX_BQ.skb[pos] = NULL; ++ return -1; ++ } ++ desc->data_buff_addr = (u32)addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ desc->rxhash = (addr >> REG_BIT_WIDTH) & TX_DESC_HI8_MASK; ++#endif ++ desc->buffer_len = ETH_MAX_FRAME_SIZE - 1; ++ desc->data_len = skb->len; ++ desc->fl = DESC_FL_FULL; ++ desc->descvid = DESC_VLD_BUSY; ++ ++ return 0; ++} ++ ++static int gmac_tx_avail(struct gmac_netdev_local const *ld) ++{ ++ unsigned int tx_bq_wr_offset, tx_bq_rd_offset; ++ ++ if (ld == NULL) ++ return -1; ++ ++ tx_bq_wr_offset = readl(ld->gmac_iobase + TX_BQ_WR_ADDR); ++ tx_bq_rd_offset = readl(ld->gmac_iobase + TX_BQ_RD_ADDR); ++ ++ return (int)((tx_bq_rd_offset >> DESC_BYTE_SHIFT) + TX_DESC_NUM ++ - (tx_bq_wr_offset >> DESC_BYTE_SHIFT) - 1); ++} ++ ++static netdev_tx_t gmac_sw_gso(struct gmac_netdev_local *ld, ++ struct sk_buff *skb) ++{ ++ struct sk_buff *segs = NULL; ++ struct sk_buff *curr_skb = NULL; ++ int ret; ++ int gso_segs = skb_shinfo(skb)->gso_segs; ++ if (gso_segs == 0 && skb_shinfo(skb)->gso_size != 0) ++ gso_segs = DIV_ROUND_UP(skb->len, skb_shinfo(skb)->gso_size); ++ ++ /* Estimate the number of fragments in the worst case */ ++ if (unlikely(gmac_tx_avail(ld) < gso_segs)) { ++ netif_stop_queue(ld->netdev); ++ if (gmac_tx_avail(ld) < gso_segs) { ++ ld->netdev->stats.tx_dropped++; ++ ld->netdev->stats.tx_fifo_errors++; ++ return NETDEV_TX_BUSY; ++ } ++ netif_wake_queue(ld->netdev); ++ } ++ ++ segs = skb_gso_segment(skb, ld->netdev->features & ~(NETIF_F_CSUM_MASK | ++ NETIF_F_SG | NETIF_F_GSO_SOFTWARE)); ++ if (IS_ERR_OR_NULL(segs)) ++ goto drop; ++ ++ do { ++ curr_skb = segs; ++ segs = segs->next; ++ curr_skb->next = NULL; ++ ret = gmac_net_xmit(curr_skb, ld->netdev); ++ if (unlikely(ret != NETDEV_TX_OK)) ++ pr_err_once("gmac_net_xmit error ret=%d\n", ret); ++ } while (segs != NULL); ++ ++ dev_kfree_skb_any(skb); ++ return NETDEV_TX_OK; ++ ++drop: ++ dev_kfree_skb_any(skb); ++ ld->netdev->stats.tx_dropped++; ++ return NETDEV_TX_OK; ++} ++ ++static int gmac_xmit_gso_sg_frag(struct gmac_netdev_local *ld, ++ struct sk_buff *skb, struct sg_desc *desc_cur, ++ struct gmac_tso_desc *tx_bq_desc, unsigned int desc_pos) ++{ ++ int nfrags = skb_shinfo(skb)->nr_frags; ++ dma_addr_t addr; ++ dma_addr_t dma_addr; ++ int i, ret, len; ++ ++ for (i = 0; i < nfrags; i++) { ++ skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; ++ len = frag->bv_len; ++ ++ dma_addr = skb_frag_dma_map(ld->dev, frag, 0, len, DMA_TO_DEVICE); ++ ret = dma_mapping_error(ld->dev, dma_addr); ++ if (unlikely(ret)) { ++ pr_err("skb frag DMA Mapping fail"); ++ return -EFAULT; ++ } ++ desc_cur->frags[i].addr = (u32)dma_addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ desc_cur->frags[i].reserved = (dma_addr >> REG_BIT_WIDTH) << SG_DESC_HI8_OFFSET; ++#endif ++ desc_cur->frags[i].size = len; ++ } ++ ++ addr = ld->dma_sg_phy + ld->sg_head * sizeof(struct sg_desc); ++ tx_bq_desc->data_buff_addr = (u32)addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) & ++ TX_DESC_HI8_MASK; ++#endif ++ ld->TX_BQ.sg_desc_offset[desc_pos] = ld->sg_head; ++ ++ ld->sg_head = (ld->sg_head + 1) % ld->sg_count; ++ ++ return 0; ++} ++ ++static int gmac_xmit_gso_sg(struct gmac_netdev_local *ld, ++ struct sk_buff *skb, ++ struct gmac_tso_desc *tx_bq_desc, unsigned int desc_pos) ++{ ++ struct sg_desc *desc_cur = NULL; ++ dma_addr_t dma_addr; ++ int ret; ++ ++ if (unlikely(((ld->sg_head + 1) % ld->sg_count) == ld->sg_tail)) { ++ /* SG pkt, but sg desc all used */ ++ pr_err("WARNING: sg desc all used.\n"); ++ return -EBUSY; ++ } ++ ++ desc_cur = ld->dma_sg_desc + ld->sg_head; ++ ++ desc_cur->total_len = skb->len; ++ desc_cur->linear_len = skb_headlen(skb); ++ dma_addr = dma_map_single(ld->dev, skb->data, desc_cur->linear_len, DMA_TO_DEVICE); ++ ret = dma_mapping_error(ld->dev, dma_addr); ++ if (unlikely(ret)) { ++ pr_err("DMA Mapping fail"); ++ return -EFAULT; ++ } ++ desc_cur->linear_addr = (u32)dma_addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ desc_cur->reserv3 = (dma_addr >> REG_BIT_WIDTH) << SG_DESC_HI8_OFFSET; ++#endif ++ ret = gmac_xmit_gso_sg_frag(ld, skb, desc_cur, tx_bq_desc, desc_pos); ++ if (unlikely(ret)) ++ return ret; ++ ++ return 0; ++} ++ ++static int gmac_get_pkt_info(struct gmac_netdev_local *ld, ++ struct sk_buff *skb, struct gmac_tso_desc *tx_bq_desc); ++ ++static int gmac_check_hw_capability(struct sk_buff *skb); ++ ++static int gmac_xmit_gso(struct gmac_netdev_local *ld, struct sk_buff *skb, ++ struct gmac_tso_desc *tx_bq_desc, unsigned int desc_pos) ++{ ++ int pkt_type = PKT_NORMAL; ++ int nfrags = skb_shinfo(skb)->nr_frags; ++ dma_addr_t addr; ++ int ret; ++ ++ if (skb_is_gso(skb) || nfrags) ++ pkt_type = PKT_SG; /* TSO pkt or SG pkt */ ++ ++ ret = gmac_check_hw_capability(skb); ++ if (unlikely(ret)) ++ return ret; ++ ++ ret = gmac_get_pkt_info(ld, skb, tx_bq_desc); ++ if (unlikely(ret)) ++ return ret; ++ ++ if (pkt_type == PKT_NORMAL) { ++ addr = dma_map_single(ld->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ ret = dma_mapping_error(ld->dev, addr); ++ if (unlikely(ret)) { ++ pr_err("Normal Packet DMA Mapping fail.\n"); ++ return -EFAULT; ++ } ++ tx_bq_desc->data_buff_addr = (u32)addr; ++#if defined(CONFIG_GMAC_DDR_64BIT ) ++ tx_bq_desc->reserve_desc2 = (addr >> REG_BIT_WIDTH) & TX_DESC_HI8_MASK; ++#endif ++ } else { ++ ret = gmac_xmit_gso_sg(ld, skb, tx_bq_desc, desc_pos); ++ if (unlikely(ret)) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++netdev_tx_t gmac_net_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ struct gmac_desc *desc = NULL; ++ unsigned long txflags; ++ int ret; ++ u32 pos; ++ ++ if (unlikely(gmac_check_skb_len(skb, dev) < 0)) ++ return NETDEV_TX_OK; ++ ++ /* ++ * if adding gmac_xmit_reclaim here, iperf tcp client ++ * performance will be affected, from 550M(avg) to 513M~300M ++ */ ++ ++ /* software write pointer */ ++ pos = dma_cnt(readl(ld->gmac_iobase + TX_BQ_WR_ADDR)); ++ ++ spin_lock_irqsave(&ld->txlock, txflags); ++ ++ if (unlikely(ld->tx_skb[pos] || ld->TX_BQ.skb[pos])) { ++ dev->stats.tx_dropped++; ++ dev->stats.tx_fifo_errors++; ++ netif_stop_queue(dev); ++ spin_unlock_irqrestore(&ld->txlock, txflags); ++ ++ return NETDEV_TX_BUSY; ++ } ++ ++ ld->TX_BQ.skb[pos] = skb; ++ ld->tx_skb[pos] = skb; ++ ++ desc = ld->TX_BQ.desc + pos; ++ ++ if (ld->tso_supported) { ++ ret = gmac_xmit_gso(ld, skb, (struct gmac_tso_desc *)desc, pos); ++ if (unlikely(ret < 0)) { ++ ld->tx_skb[pos] = NULL; ++ ld->TX_BQ.skb[pos] = NULL; ++ spin_unlock_irqrestore(&ld->txlock, txflags); ++ ++ if (ret == -ENOTSUPP) ++ return gmac_sw_gso(ld, skb); ++ ++ dev_kfree_skb_any(skb); ++ dev->stats.tx_dropped++; ++ return NETDEV_TX_OK; ++ } ++ } else { ++ ret = gmac_net_xmit_normal(skb, dev, desc, pos); ++ if (unlikely(ret < 0)) { ++ spin_unlock_irqrestore(&ld->txlock, txflags); ++ return NETDEV_TX_OK; ++ } ++ } ++ ++ /* ++ * This barrier is important here. It is required to ensure ++ * the ARM CPU flushes it's DMA write buffers before proceeding ++ * to the next instruction, to ensure that GMAC will see ++ * our descriptor changes in memory ++ */ ++ gmac_sync_barrier(); ++ pos = dma_ring_incr(pos, TX_DESC_NUM); ++ writel(dma_byte(pos), ld->gmac_iobase + TX_BQ_WR_ADDR); ++ ++ netif_trans_update(dev); ++ dev->stats.tx_packets++; ++ dev->stats.tx_bytes += skb->len; ++ netdev_sent_queue(dev, skb->len); ++ ++ spin_unlock_irqrestore(&ld->txlock, txflags); ++ ++ return NETDEV_TX_OK; ++} ++ ++/* set gmac's multicast list, here we setup gmac's mc filter */ ++static void gmac_gmac_multicast_list(struct net_device const *dev) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ struct netdev_hw_addr *ha = NULL; ++ unsigned int d; ++ unsigned int rec_filter; ++ ++ rec_filter = readl(ld->gmac_iobase + REC_FILT_CONTROL); ++ /* ++ * when set gmac in promisc mode ++ * a. dev in IFF_PROMISC mode ++ */ ++ if ((dev->flags & IFF_PROMISC)) { ++ /* promisc mode.received all pkgs. */ ++ rec_filter &= ~(BIT_BC_DROP_EN | BIT_MC_MATCH_EN | ++ BIT_UC_MATCH_EN); ++ } else { ++ /* drop uc pkgs with field 'DA' not match our's */ ++ rec_filter |= BIT_UC_MATCH_EN; ++ ++ if (dev->flags & IFF_BROADCAST) /* no broadcast */ ++ rec_filter &= ~BIT_BC_DROP_EN; ++ else ++ rec_filter |= BIT_BC_DROP_EN; ++ ++ if (netdev_mc_empty(dev) || !(dev->flags & IFF_MULTICAST)) { ++ /* haven't join any mc group */ ++ writel(0, ld->gmac_iobase + PORT_MC_ADDR_LOW); ++ writel(0, ld->gmac_iobase + PORT_MC_ADDR_HIGH); ++ rec_filter |= BIT_MC_MATCH_EN; ++ } else if ((netdev_mc_count(dev) == 1) && ++ (dev->flags & IFF_MULTICAST)) { ++ netdev_for_each_mc_addr(ha, dev) { ++ d = (ha->addr[0] << 8) | (ha->addr[1]); /* mac[0]->(15, 8) mac[1]->(7, 0) */ ++ writel(d, ld->gmac_iobase + PORT_MC_ADDR_HIGH); ++ ++ d = (ha->addr[2] << 24) | (ha->addr[3] << 16) | /* mac[2]->(31, 24) mac[3]->(23, 16) */ ++ (ha->addr[4] << 8) | (ha->addr[5]); /* mac[4]->(15, 8) mac[5]->(7, 0) */ ++ writel(d, ld->gmac_iobase + PORT_MC_ADDR_LOW); ++ } ++ rec_filter |= BIT_MC_MATCH_EN; ++ } else { ++ rec_filter &= ~BIT_MC_MATCH_EN; ++ } ++ } ++ writel(rec_filter, ld->gmac_iobase + REC_FILT_CONTROL); ++} ++ ++void gmac_set_multicast_list(struct net_device *dev) ++{ ++ gmac_gmac_multicast_list(dev); ++} ++ ++int gmac_set_features(struct net_device *dev, netdev_features_t features) ++{ ++ struct gmac_netdev_local *ld = netdev_priv(dev); ++ netdev_features_t changed = dev->features ^ features; ++ ++ if (changed & NETIF_F_RXCSUM) { ++ if (features & NETIF_F_RXCSUM) ++ gmac_enable_rxcsum_drop(ld, true); ++ else ++ gmac_enable_rxcsum_drop(ld, false); ++ } ++ ++ return 0; ++} ++ ++int gmac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd) ++{ ++ struct gmac_netdev_local *priv = NULL; ++ struct pm_config config; ++ int val = 0; ++ if (ndev == NULL || rq == NULL) ++ return -EINVAL; ++ priv = netdev_priv(ndev); ++ switch (cmd) { ++ case SIOCSETPM: ++ if (rq->ifr_data == NULL || ++ copy_from_user(&config, rq->ifr_data, sizeof(config))) ++ return -EFAULT; ++ return pmt_config(ndev, &config); ++ ++ case SIOCSETSUSPEND: ++ if (rq->ifr_data == NULL || copy_from_user(&val, rq->ifr_data, sizeof(val))) ++ return -EFAULT; ++ return set_suspend(val); ++ ++ case SIOCSETRESUME: ++ if (rq->ifr_data == NULL || copy_from_user(&val, rq->ifr_data, sizeof(val))) ++ return -EFAULT; ++ return set_resume(val); ++ ++ default: ++ if (!netif_running(ndev)) ++ return -EINVAL; ++ ++ if (priv->phy == NULL) ++ return -EINVAL; ++ ++ return phy_mii_ioctl(priv->phy, rq, cmd); ++ } ++ return 0; ++} ++ ++int gmac_net_set_mac_address(struct net_device *dev, void *p) ++{ ++ int ret; ++ ++ ret = eth_mac_addr(dev, p); ++ if (!ret) ++ gmac_hw_set_mac_addr(dev); ++ ++ return ret; ++} ++ ++int eth_change_mtu(struct net_device *dev, int new_mtu) ++{ ++ netdev_warn(dev, "%s is deprecated\n", __func__); ++ dev->mtu = new_mtu; ++ return 0; ++} ++ ++struct net_device_stats *gmac_net_get_stats(struct net_device *dev) ++{ ++ return &dev->stats; ++} ++ ++static void gmac_do_udp_checksum(struct sk_buff *skb) ++{ ++ int offset; ++ __wsum csum; ++ __sum16 udp_csum; ++ ++ offset = skb_checksum_start_offset(skb); ++ WARN_ON(offset >= skb_headlen(skb)); ++ csum = skb_checksum(skb, offset, skb->len - offset, 0); ++ ++ offset += skb->csum_offset; ++ WARN_ON(offset + sizeof(__sum16) > skb_headlen(skb)); ++ udp_csum = csum_fold(csum); ++ if (udp_csum == 0) ++ udp_csum = CSUM_MANGLED_0; ++ ++ *(__sum16 *)(skb->data + offset) = udp_csum; ++ ++ skb->ip_summed = CHECKSUM_NONE; ++} ++ ++static int gmac_get_pkt_info_l3l4(struct gmac_tso_desc *tx_bq_desc, ++ struct sk_buff *skb, unsigned int *l4_proto, unsigned int *max_mss, ++ unsigned char *coe_enable) ++{ ++ __be16 l3_proto; /* level 3 protocol */ ++ int max_data_len = skb->len - ETH_HLEN; ++ ++ l3_proto = skb->protocol; ++ if (skb->protocol == htons(ETH_P_8021Q)) { ++ l3_proto = vlan_get_protocol(skb); ++ tx_bq_desc->desc1.tx.vlan_flag = 1; ++ max_data_len -= VLAN_HLEN; ++ } ++ ++ if (l3_proto == htons(ETH_P_IP)) { ++ struct iphdr *iph; ++ ++ iph = ip_hdr(skb); ++ tx_bq_desc->desc1.tx.ip_ver = PKT_IPV4; ++ tx_bq_desc->desc1.tx.ip_hdr_len = iph->ihl; ++ ++ if ((max_data_len >= GSO_MAX_SIZE) && ++ (ntohs(iph->tot_len) <= (iph->ihl << 2))) /* shift left 2 */ ++ iph->tot_len = htons(GSO_MAX_SIZE - 1); ++ ++ *max_mss -= iph->ihl * WORD_TO_BYTE; ++ *l4_proto = iph->protocol; ++ } else if (l3_proto == htons(ETH_P_IPV6)) { ++ tx_bq_desc->desc1.tx.ip_ver = PKT_IPV6; ++ tx_bq_desc->desc1.tx.ip_hdr_len = PKT_IPV6_HDR_LEN; ++ *max_mss -= PKT_IPV6_HDR_LEN * WORD_TO_BYTE; ++ *l4_proto = ipv6_hdr(skb)->nexthdr; ++ } else { ++ *coe_enable = 0; ++ } ++ ++ if (*l4_proto == IPPROTO_TCP) { ++ tx_bq_desc->desc1.tx.prot_type = PKT_TCP; ++ if (tcp_hdr(skb)->doff < sizeof(struct tcphdr) / WORD_TO_BYTE) ++ return -EFAULT; ++ tx_bq_desc->desc1.tx.prot_hdr_len = tcp_hdr(skb)->doff; ++ *max_mss -= tcp_hdr(skb)->doff * WORD_TO_BYTE; ++ } else if (*l4_proto == IPPROTO_UDP) { ++ tx_bq_desc->desc1.tx.prot_type = PKT_UDP; ++ tx_bq_desc->desc1.tx.prot_hdr_len = PKT_UDP_HDR_LEN; ++ if (l3_proto == htons(ETH_P_IPV6)) ++ *max_mss -= sizeof(struct frag_hdr); ++ } else { ++ *coe_enable = 0; ++ } ++ ++ return 0; ++} ++ ++static int gmac_get_pkt_info(struct gmac_netdev_local *ld, ++ struct sk_buff *skb, struct gmac_tso_desc *tx_bq_desc) ++{ ++ int nfrags; ++ unsigned int l4_proto = IPPROTO_MAX; ++ unsigned int max_mss = ETH_DATA_LEN; ++ unsigned char coe_enable = 0; ++ int ret; ++ if (skb == NULL || tx_bq_desc == NULL) ++ return -EINVAL; ++ ++ nfrags = skb_shinfo(skb)->nr_frags; ++ if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) ++ coe_enable = 1; ++ ++ tx_bq_desc->desc1.val = 0; ++ ++ if (skb_is_gso(skb)) { ++ tx_bq_desc->desc1.tx.tso_flag = 1; ++ tx_bq_desc->desc1.tx.sg_flag = 1; ++ } else if (nfrags) { ++ tx_bq_desc->desc1.tx.sg_flag = 1; ++ } ++ ++ ret = gmac_get_pkt_info_l3l4(tx_bq_desc, skb, &l4_proto, &max_mss, ++ &coe_enable); ++ if (ret < 0) ++ return ret; ++ ++ if (skb_is_gso(skb)) ++ tx_bq_desc->desc1.tx.data_len = ++ (skb_shinfo(skb)->gso_size > max_mss) ? max_mss : ++ skb_shinfo(skb)->gso_size; ++ else ++ tx_bq_desc->desc1.tx.data_len = skb->len; ++ ++ if (coe_enable && skb_is_gso(skb) && (l4_proto == IPPROTO_UDP)) ++ gmac_do_udp_checksum(skb); ++ ++ if (coe_enable) ++ tx_bq_desc->desc1.tx.coe_flag = 1; ++ ++ tx_bq_desc->desc1.tx.nfrags_num = nfrags; ++ ++ tx_bq_desc->desc1.tx.hw_own = DESC_VLD_BUSY; ++ return 0; ++} ++ ++static int gmac_check_hw_capability_for_udp(struct sk_buff const *skb) ++{ ++ struct ethhdr *eth; ++ ++ /* hardware can't dea with UFO broadcast packet */ ++ eth = (struct ethhdr *)(skb->data); ++ if (skb_is_gso(skb) && is_broadcast_ether_addr(eth->h_dest)) ++ return -ENOTSUPP; ++ ++ return 0; ++} ++ ++static int gmac_check_hw_capability_for_ipv6(struct sk_buff *skb) ++{ ++ unsigned int l4_proto; ++ ++ l4_proto = ipv6_hdr(skb)->nexthdr; ++ if ((l4_proto != IPPROTO_TCP) && (l4_proto != IPPROTO_UDP)) { ++ /* ++ * when IPv6 next header is not tcp or udp, ++ * it means that IPv6 next header is extension header. ++ * Hardware can't deal with this case, ++ * so do checksumming by software or do GSO by software. ++ */ ++ if (skb_is_gso(skb)) ++ return -ENOTSUPP; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL && ++ skb_checksum_help(skb)) ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static __be16 gmac_get_l3_proto(struct sk_buff *skb) ++{ ++ __be16 l3_proto; ++ ++ l3_proto = skb->protocol; ++ if (skb->protocol == htons(ETH_P_8021Q)) ++ l3_proto = vlan_get_protocol(skb); ++ ++ return l3_proto; ++} ++ ++static unsigned int gmac_get_l4_proto(struct sk_buff *skb) ++{ ++ __be16 l3_proto; ++ unsigned int l4_proto = IPPROTO_MAX; ++ ++ l3_proto = gmac_get_l3_proto(skb); ++ if (l3_proto == htons(ETH_P_IP)) ++ l4_proto = ip_hdr(skb)->protocol; ++ else if (l3_proto == htons(ETH_P_IPV6)) ++ l4_proto = ipv6_hdr(skb)->nexthdr; ++ ++ return l4_proto; ++} ++ ++static inline bool gmac_skb_is_ipv6(struct sk_buff *skb) ++{ ++ return (gmac_get_l3_proto(skb) == htons(ETH_P_IPV6)); ++} ++ ++static inline bool gmac_skb_is_udp(struct sk_buff *skb) ++{ ++ return (gmac_get_l4_proto(skb) == IPPROTO_UDP); ++} ++ ++static inline bool gmac_skb_is_ipv4_with_options(struct sk_buff *skb) ++{ ++ return ((gmac_get_l3_proto(skb) == htons(ETH_P_IP)) && ++ (ip_hdr(skb)->ihl > IPV4_HEAD_LENGTH)); ++} ++ ++static int gmac_check_hw_capability(struct sk_buff *skb) ++{ ++ int ret; ++ ++ /* ++ * if tcp_mtu_probe() use (2 * tp->mss_cache) as probe_size, ++ * the linear data length will be larger than 2048, ++ * the MAC can't handle it, so let the software do it. ++ */ ++ if (skb == NULL) ++ return -EINVAL; ++ if (skb_is_gso(skb) && (skb_headlen(skb) > 2048)) /* 2048(2k) */ ++ return -ENOTSUPP; ++ ++ if (gmac_skb_is_ipv6(skb)) { ++ ret = gmac_check_hw_capability_for_ipv6(skb); ++ if (ret) ++ return ret; ++ } ++ ++ if (gmac_skb_is_udp(skb)) { ++ ret = gmac_check_hw_capability_for_udp(skb); ++ if (ret) ++ return ret; ++ } ++ ++ if (((skb->ip_summed == CHECKSUM_PARTIAL) || skb_is_gso(skb)) && ++ gmac_skb_is_ipv4_with_options(skb)) ++ return -ENOTSUPP; ++ ++ return 0; ++} +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.h b/drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.h +new file mode 100644 +index 000000000000..6d4f088ae27d +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_netdev_ops.h +@@ -0,0 +1,22 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef GMAC_NETDEV_OPS_H ++#define GMAC_NETDEV_OPS_H ++ ++#include ++ ++#include "gmac.h" ++ ++int gmac_net_open(struct net_device *dev); ++int gmac_net_close(struct net_device *dev); ++netdev_tx_t gmac_net_xmit(struct sk_buff *skb, struct net_device *dev); ++void gmac_set_multicast_list(struct net_device *dev); ++int gmac_set_features(struct net_device *dev, netdev_features_t features); ++int gmac_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd); ++int gmac_net_set_mac_address(struct net_device *dev, void *p); ++int eth_change_mtu(struct net_device *dev, int new_mtu); ++struct net_device_stats *gmac_net_get_stats(struct net_device *dev); ++ ++#endif +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.c b/drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.c +new file mode 100644 +index 000000000000..19089022d504 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.c +@@ -0,0 +1,154 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include "gmac_phy_fixup.h" ++ ++static int ksz8051mnl_phy_fix(struct phy_device *phy_dev) ++{ ++ u32 v; ++ int ret; ++ ++ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII) ++ return 0; ++ ++ ret = phy_read(phy_dev, 0x1F); ++ if (ret < 0) ++ return ret; ++ v = ret; ++ v |= (1 << 7); /* set bit 7, phy RMII 50MHz clk; */ ++ phy_write(phy_dev, 0x1F, v); ++ ++ ret = phy_read(phy_dev, 0x16); ++ if (ret < 0) ++ return ret; ++ v = ret; ++ v |= (1 << 1); /* set phy RMII override; */ ++ phy_write(phy_dev, 0x16, v); ++ ++ return 0; ++} ++ ++static int ksz8081rnb_phy_fix(struct phy_device *phy_dev) ++{ ++ u32 v; ++ int ret; ++ ++ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII) ++ return 0; ++ ++ ret = phy_read(phy_dev, 0x1F); ++ if (ret < 0) ++ return ret; ++ v = ret; ++ v |= (1 << 7); /* set bit 7, phy RMII 50MHz clk; */ ++ phy_write(phy_dev, 0x1F, v); ++ ++ return 0; ++} ++ ++static int unknown_phy_fix(struct phy_device *phy_dev) ++{ ++ u32 v; ++ int ret; ++ ++ if (phy_dev->interface != PHY_INTERFACE_MODE_RMII) ++ return 0; ++ ++ ret = phy_read(phy_dev, 0x1F); ++ if (ret < 0) ++ return ret; ++ v = ret; ++ v |= (1 << 7); /* set bit 7, phy RMII 50MHz clk; */ ++ phy_write(phy_dev, 0x1F, v); ++ ++ return 0; ++} ++ ++static int rtl8211e_phy_fix(struct phy_device *phy_dev) ++{ ++ u32 v; ++ int ret; ++ ++ /* select Extension page */ ++ phy_write(phy_dev, 0x1f, 0x7); ++ /* switch ExtPage 164 */ ++ phy_write(phy_dev, 0x1e, 0xa4); ++ ++ /* config RGMII rx pin io driver max */ ++ ret = phy_read(phy_dev, 0x1c); ++ if (ret < 0) ++ return ret; ++ v = ret; ++ v = (v & 0xff03) | 0xfc; ++ phy_write(phy_dev, 0x1c, v); ++ ++ /* select to page 0 */ ++ phy_write(phy_dev, 0x1f, 0); ++ ++ return 0; ++} ++ ++static int __read_mostly g_yt8521_flag = 0; ++ ++static int __init yt8521_phy_fix_setup(char *str) ++{ ++ if (!strcasecmp(str, "enable") ) ++ g_yt8521_flag = 1; ++ ++ return 0; ++} ++__setup("yt8521_phy_fix=", yt8521_phy_fix_setup); ++ ++static int yt8521_phy_fix(struct phy_device *phy_dev) ++{ ++ phy_write(phy_dev, 0x1e, 0xa00c); ++ phy_write(phy_dev, 0x1f, 0x3e60); ++ phy_write(phy_dev, 0x1e, 0xa00e); ++ phy_write(phy_dev, 0x1f, 0x0060); ++ phy_write(phy_dev, 0x1e, 0xa003); ++ phy_write(phy_dev, 0x1f, 0x00FD); ++ ++ return 0; ++} ++ ++static int rtl8211fs_phy_fix(struct phy_device *phy_dev) ++{ ++ u32 v; ++ // RX or TX delay ++ phy_write(phy_dev, 0x1F, 0xd08); ++ v = phy_read(phy_dev, 17); ++ v |= (1<<8); ++ phy_write(phy_dev, 17, v); ++ ++ // change back to page0 ++ phy_write(phy_dev, 0x1F, 0); ++ return 0; ++} ++ ++void gmac_phy_register_fixups(void) ++{ ++ phy_register_fixup_for_uid(PHY_ID_UNKNOWN, DEFAULT_PHY_MASK, ++ unknown_phy_fix); ++ phy_register_fixup_for_uid(PHY_ID_KSZ8051MNL, DEFAULT_PHY_MASK, ++ ksz8051mnl_phy_fix); ++ phy_register_fixup_for_uid(PHY_ID_KSZ8081RNB, DEFAULT_PHY_MASK, ++ ksz8081rnb_phy_fix); ++ phy_register_fixup_for_uid(REALTEK_PHY_ID_8211E, REALTEK_PHY_MASK, ++ rtl8211e_phy_fix); ++ phy_register_fixup_for_uid(REALTEK_PHY_ID_8211FS, REALTEK_PHY_MASK, ++ rtl8211fs_phy_fix); ++ if (g_yt8521_flag) ++ phy_register_fixup_for_uid(0x110, DEFAULT_PHY_MASK, yt8521_phy_fix); ++} ++ ++void gmac_phy_unregister_fixups(void) ++{ ++ phy_unregister_fixup_for_uid(PHY_ID_UNKNOWN, DEFAULT_PHY_MASK); ++ phy_unregister_fixup_for_uid(PHY_ID_KSZ8051MNL, DEFAULT_PHY_MASK); ++ phy_unregister_fixup_for_uid(PHY_ID_KSZ8081RNB, DEFAULT_PHY_MASK); ++ phy_unregister_fixup_for_uid(REALTEK_PHY_ID_8211E, REALTEK_PHY_MASK); ++ phy_unregister_fixup_for_uid(REALTEK_PHY_ID_8211FS, REALTEK_PHY_MASK); ++ if (g_yt8521_flag) ++ phy_unregister_fixup_for_uid(0x110, DEFAULT_PHY_MASK); ++} +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.h b/drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.h +new file mode 100644 +index 000000000000..e8fe68f7244e +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_phy_fixup.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef GMAC_PHY_FIXUP_H ++#define GMAC_PHY_FIXUP_H ++ ++#include "gmac.h" ++ ++void gmac_phy_register_fixups(void); ++void gmac_phy_unregister_fixups(void); ++ ++#endif +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_pm.c b/drivers/net/ethernet/vendor/gmac/gmac_pm.c +new file mode 100644 +index 000000000000..cee4f62d6e00 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_pm.c +@@ -0,0 +1,340 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++#include ++#include "gmac_pm.h" ++ ++struct pm_reg_config pm_reg_config_backup; ++ ++static void init_crc_table(void); ++static unsigned short compute_crc(const char *message, int nbytes); ++static unsigned short calculate_crc16(const char *buf, unsigned int mask) ++{ ++ char data[N]; ++ int i; ++ int len = 0; ++ ++ if (memset_s(data, sizeof(data), 0, sizeof(data)) != EOK) ++ printk("memset_s err : %s %d.\n", __func__, __LINE__); ++ ++ for (i = 0; i < N; i++) { ++ if (mask & 0x1) ++ data[len++] = buf[i]; ++ ++ mask >>= 1; ++ } ++ ++ return compute_crc(data, len); ++} ++ ++/* use this func in config pm func */ ++static void _pmt_reg_backup(struct gmac_netdev_local const *ld) ++{ ++ if (ld == NULL) ++ return; ++ pm_reg_config_backup.pmt_ctrl = readl(ld->gmac_iobase + PMT_CTRL); ++ pm_reg_config_backup.pmt_mask0 = readl(ld->gmac_iobase + PMT_MASK0); ++ pm_reg_config_backup.pmt_mask1 = readl(ld->gmac_iobase + PMT_MASK1); ++ pm_reg_config_backup.pmt_mask2 = readl(ld->gmac_iobase + PMT_MASK2); ++ pm_reg_config_backup.pmt_mask3 = readl(ld->gmac_iobase + PMT_MASK3); ++ pm_reg_config_backup.pmt_cmd = readl(ld->gmac_iobase + PMT_CMD); ++ pm_reg_config_backup.pmt_offset = readl(ld->gmac_iobase + PMT_OFFSET); ++ pm_reg_config_backup.pmt_crc1_0 = readl(ld->gmac_iobase + PMT_CRC1_0); ++ pm_reg_config_backup.pmt_crc3_2 = readl(ld->gmac_iobase + PMT_CRC3_2); ++} ++ ++#define PM_SET 1 ++#define PM_CLEAR 0 ++ ++static void pmt_config_filter(struct pm_config const *config, ++ struct gmac_netdev_local const *ld) ++{ ++ unsigned int v; ++ unsigned int cmd = 0; ++ unsigned int offset = 0; ++ unsigned short crc[FILTERS] = { 0 }; ++ int reg_mask; ++ unsigned int i; ++ ++ /* ++ * filter.valid mask.valid mask_bytes effect ++ * 0 * * no use the filter ++ * 1 0 * all pkts can wake-up(non-exist) ++ * 1 1 0 all pkts can wake-up ++ * 1 1 !0 normal filter ++ */ ++ /* setup filter */ ++ for (i = 0; i < FILTERS; i++) { ++ if (config->filter[i].valid) { ++ if (config->filter[i].offset < PM_FILTER_OFFSET_MIN) ++ continue; ++ /* high 8 bits offset and low 8 bits valid bit */ ++ offset |= config->filter[i].offset << (i * 8); ++ cmd |= BIT(i * 8); /* valid bit8 */ ++ /* mask offset 4i */ ++ reg_mask = PMT_MASK0 + (i * 4); ++ ++ /* ++ * for logic, mask valid bit(bit31) must set to 0, ++ * 0 is enable ++ */ ++ v = config->filter[i].mask_bytes; ++ v &= ~BIT(31); /* bit31 */ ++ writel(v, ld->gmac_iobase + reg_mask); ++ ++ /* crc */ ++ crc[i] = calculate_crc16(config->filter[i].value, v); ++ if (i <= 1) { /* for filter0 and filter 1 */ ++ v = readl(ld->gmac_iobase + PMT_CRC1_0); ++ v &= ~(0xFFFF << (16 * i)); /* 16 bits mask */ ++ v |= crc[i] << (16 * i); /* 16 bits mask */ ++ writel(v, ld->gmac_iobase + PMT_CRC1_0); ++ } else { /* filter2 and filter3 */ ++ v = readl(ld->gmac_iobase + PMT_CRC3_2); ++ v &= ~(0xFFFF << (16 * (i - 2))); /* filer 2 3, 16 bits mask */ ++ v |= crc[i] << (16 * (i - 2)); /* filer 2 3, 16 bits mask */ ++ writel(v, ld->gmac_iobase + PMT_CRC3_2); ++ } ++ } ++ } ++ ++ if (cmd) { ++ writel(offset, ld->gmac_iobase + PMT_OFFSET); ++ writel(cmd, ld->gmac_iobase + PMT_CMD); ++ } ++} ++ ++static int pmt_config_gmac(struct pm_config const *config, struct gmac_netdev_local *ld) ++{ ++ unsigned int v; ++ unsigned long flags; ++ ++ if (ld == NULL || config == NULL) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&ld->pmtlock, flags); ++ if (config->wakeup_pkts_enable) { ++ /* disable wakeup_pkts_enable before reconfig? */ ++ v = readl(ld->gmac_iobase + PMT_CTRL); ++ v &= ~BIT(2); /* bit2 */ ++ writel(v, ld->gmac_iobase + PMT_CTRL); /* any side effect? */ ++ } else { ++ goto config_ctrl; ++ } ++ ++ pmt_config_filter(config, ld); ++ ++config_ctrl: ++ v = 0; ++ if (config->uc_pkts_enable) ++ v |= BIT(9); /* bit9 uc pkts wakeup */ ++ if (config->wakeup_pkts_enable) ++ v |= BIT(2); /* bit2 use filter framework */ ++ if (config->magic_pkts_enable) ++ v |= BIT(1); /* magic pkts wakeup */ ++ ++ v |= 0x3 << 5; /* set bit5 bit6, clear irq status */ ++ writel(v, ld->gmac_iobase + PMT_CTRL); ++ ++ _pmt_reg_backup(ld); ++ ++ spin_unlock_irqrestore(&ld->pmtlock, flags); ++ ++ return 0; ++} ++ ++/* pmt_config will overwrite pre-config */ ++int pmt_config(struct net_device const *ndev, struct pm_config const *config) ++{ ++ static int init; ++ int ret; ++ struct gmac_netdev_local *priv = netdev_priv(ndev); ++ ++ if (!init) ++ init_crc_table(); ++ ++ ret = pmt_config_gmac(config, priv); ++ if (ret) ++ return ret; ++ ++ priv->pm_state = PM_SET; ++ priv->wol_enable = true; ++ device_set_wakeup_enable(priv->dev, 1); ++ ++ return 0; ++} ++ ++bool pmt_enter(struct gmac_netdev_local *ld) ++{ ++ int pm = false; ++ unsigned long flags; ++ if (ld == NULL) ++ return -EINVAL; ++ spin_lock_irqsave(&ld->pmtlock, flags); ++ if (ld->pm_state == PM_SET) { ++ unsigned int v; ++ ++ v = readl(ld->gmac_iobase + PMT_CTRL); ++ v |= BIT(0); /* enter power down */ ++ v |= BIT(3); /* bit3, enable wakeup irq */ ++ v |= 0x3 << 5; /* set bit5 bit6, clear irq status */ ++ writel(v, ld->gmac_iobase + PMT_CTRL); ++ ++ ld->pm_state = PM_CLEAR; ++ pm = true; ++ } ++ spin_unlock_irqrestore(&ld->pmtlock, flags); ++ return pm; ++} ++ ++void pmt_exit(struct gmac_netdev_local *ld) ++{ ++ unsigned int v; ++ unsigned long flags; ++ if (ld == NULL) ++ return; ++ /* logic auto exit power down mode */ ++ spin_lock_irqsave(&ld->pmtlock, flags); ++ ++ v = readl(ld->gmac_iobase + PMT_CTRL); ++ v &= ~BIT(0); /* enter power down */ ++ v &= ~BIT(3); /* bit3, enable wakeup irq */ ++ ++ v |= 0x3 << 5; /* set bit5 bit6, clear irq status */ ++ writel(v, ld->gmac_iobase + PMT_CTRL); ++ ++ spin_unlock_irqrestore(&ld->pmtlock, flags); ++ ++ ld->wol_enable = false; ++} ++ ++void pmt_reg_restore(struct gmac_netdev_local *ld) ++{ ++ unsigned int v; ++ unsigned long flags; ++ if (ld == NULL) ++ return; ++ spin_lock_irqsave(&ld->pmtlock, flags); ++ v = pm_reg_config_backup.pmt_mask0; ++ writel(v, ld->gmac_iobase + PMT_MASK0); ++ ++ v = pm_reg_config_backup.pmt_mask1; ++ writel(v, ld->gmac_iobase + PMT_MASK1); ++ ++ v = pm_reg_config_backup.pmt_mask2; ++ writel(v, ld->gmac_iobase + PMT_MASK2); ++ ++ v = pm_reg_config_backup.pmt_mask3; ++ writel(v, ld->gmac_iobase + PMT_MASK3); ++ ++ v = pm_reg_config_backup.pmt_cmd; ++ writel(v, ld->gmac_iobase + PMT_CMD); ++ ++ v = pm_reg_config_backup.pmt_offset; ++ writel(v, ld->gmac_iobase + PMT_OFFSET); ++ ++ v = pm_reg_config_backup.pmt_crc1_0; ++ writel(v, ld->gmac_iobase + PMT_CRC1_0); ++ ++ v = pm_reg_config_backup.pmt_crc3_2; ++ writel(v, ld->gmac_iobase + PMT_CRC3_2); ++ ++ v = pm_reg_config_backup.pmt_ctrl; ++ writel(v, ld->gmac_iobase + PMT_CTRL); ++ spin_unlock_irqrestore(&ld->pmtlock, flags); ++} ++ ++/* ========the following code copy from Synopsys DWC_gmac_crc_example.c====== */ ++#define CRC16 /* Change it to CRC16 for CRC16 Computation */ ++ ++#if defined(CRC16) ++#define CRC_NAME "CRC-16" ++#define POLYNOMIAL 0x8005 ++#define INITIAL_REMAINDER 0xFFFF ++#define FINAL_XOR_VALUE 0x0000 ++#define REVERSE_DATA ++#undef REVERSE_REMAINDER ++#endif ++ ++#define WIDTH (8 * sizeof(unsigned short)) ++#define TOPBIT BIT(WIDTH - 1) ++ ++#ifdef REVERSE_DATA ++#undef REVERSE_DATA ++#define reverse_data(X) ((unsigned char)reverse((X), 8)) ++#else ++#undef REVERSE_DATA ++#define reverse_data(X) (X) ++#endif ++ ++#ifdef REVERSE_REMAINDER ++#undef REVERSE_REMAINDER ++#define reverse_remainder(X) ((unsigned short)reverse((X), WIDTH)) ++#else ++#undef REVERSE_REMAINDER ++#define reverse_remainder(X) (X) ++#endif ++ ++#define CRC_TABLE_LEN 256 ++static unsigned short crc_table[CRC_TABLE_LEN]; ++ ++static unsigned int reverse(unsigned int data, unsigned char nbits) ++{ ++ unsigned int reversed = 0x00000000; ++ unsigned char bit; ++ ++ /* Reverse the data about the center bit. */ ++ for (bit = 0; bit < nbits; ++bit) { ++ /* If the LSB bit is set, set the reflection of it. */ ++ if (data & 0x01) ++ reversed |= BIT((nbits - 1) - bit); ++ ++ data = (data >> 1); ++ } ++ return reversed; ++} ++ ++/* This Initializes the partial CRC look up table */ ++static void init_crc_table(void) ++{ ++ unsigned short remainder; ++ unsigned int dividend; ++ unsigned char bit; ++ ++ /* Compute the remainder of each possible dividend. */ ++ for (dividend = 0; dividend < CRC_TABLE_LEN; ++dividend) { ++ /* Start with the dividend followed by zeros, WIDTH - 8. */ ++ remainder = (unsigned short)(dividend << (WIDTH - 8)); ++ ++ /* Perform modulo-2 division, a bit at a time for 8 times. */ ++ for (bit = 8; bit > 0; --bit) { ++ /* Try to divide the current data bit. */ ++ if (remainder & TOPBIT) ++ remainder = (remainder << 1) ^ POLYNOMIAL; ++ else ++ remainder = (remainder << 1); ++ } ++ ++ /* Store the result into the table. */ ++ crc_table[dividend] = remainder; ++ } ++} ++ ++static unsigned short compute_crc(const char *message, int nbytes) ++{ ++ unsigned short remainder = INITIAL_REMAINDER; ++ int byte; ++ unsigned char data; ++ ++ /* Divide the message by the polynomial, a byte at a time. */ ++ for (byte = 0; byte < nbytes; ++byte) { ++ /* high 8 bits */ ++ data = reverse_data(message[byte]) ^ (remainder >> (WIDTH - 8)); ++ remainder = crc_table[data] ^ (remainder << 8); /* shift left 8 bits */ ++ } ++ ++ /* The final remainder is the CRC. */ ++ return (reverse_remainder(remainder) ^ FINAL_XOR_VALUE); ++} +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_pm.h b/drivers/net/ethernet/vendor/gmac/gmac_pm.h +new file mode 100644 +index 000000000000..92d06ad8d0da +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_pm.h +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef __GMAC_PM_H__ ++#define __GMAC_PM_H__ ++ ++#include "gmac.h" ++ ++#define N 31 ++#define FILTERS 4 ++#define PM_FILTER_OFFSET_MIN 12 ++struct pm_config { ++ unsigned char index; /* bit0--eth0 bit1--eth1 */ ++ unsigned char uc_pkts_enable; ++ unsigned char magic_pkts_enable; ++ unsigned char wakeup_pkts_enable; ++ struct { ++ unsigned int mask_bytes : N; ++ unsigned int reserved : 1; /* userspace ignore this bit */ ++ unsigned char offset; /* >= 12 */ ++ unsigned char value[N]; /* byte string */ ++ unsigned char valid; /* valid filter */ ++ } filter[FILTERS]; ++}; ++ ++struct pm_reg_config { ++ unsigned int pmt_ctrl; ++ unsigned int pmt_mask0; ++ unsigned int pmt_mask1; ++ unsigned int pmt_mask2; ++ unsigned int pmt_mask3; ++ unsigned int pmt_cmd; ++ unsigned int pmt_offset; ++ unsigned int pmt_crc1_0; ++ unsigned int pmt_crc3_2; ++}; ++ ++#define PMT_CTRL 0xa00 ++#define PMT_MASK0 0xa04 ++#define PMT_MASK1 0xa08 ++#define PMT_MASK2 0xa0c ++#define PMT_MASK3 0xa10 ++#define PMT_CMD 0xa14 ++#define PMT_OFFSET 0xa18 ++#define PMT_CRC1_0 0xa1c ++#define PMT_CRC3_2 0xa20 ++#define MASK_INVALID_BIT BIT(31) ++ ++ ++int pmt_config(struct net_device const *ndev, struct pm_config const *config); ++bool pmt_enter(struct gmac_netdev_local *ld); ++void pmt_exit(struct gmac_netdev_local *ld); ++void pmt_reg_restore(struct gmac_netdev_local *ld); ++ ++#endif +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_proc.c b/drivers/net/ethernet/vendor/gmac/gmac_proc.c +new file mode 100644 +index 000000000000..0fa531a115a9 +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_proc.c +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#include ++ ++#include "gmac_pm.h" ++#include "gmac_proc.h" ++ ++/* debug code */ ++int set_suspend(int eth_n) ++{ ++ return 0; ++} ++ ++/* debug code */ ++int set_resume(int eth_n) ++{ ++ return 0; ++} ++ ++static int hw_states_read(struct seq_file *m, void *v) ++{ ++ return 0; ++} ++ ++static struct proc_dir_entry *gmac_proc_root; ++ ++static int proc_open_hw_states_read(struct inode *inode, struct file *file) ++{ ++ return single_open(file, hw_states_read, PDE_DATA(inode)); ++} ++ ++static struct proc_file { ++ char *name; ++ const struct proc_ops ops; ++ ++} proc_file[] = { ++ { ++ .name = "hw_stats", ++ .ops = { ++ .proc_open = proc_open_hw_states_read, ++ .proc_read = seq_read, ++ .proc_lseek = seq_lseek, ++ .proc_release = single_release, ++ }, ++ } ++}; ++ ++/* ++ * /proc/gmac/ ++ * |---hw_stats ++ * |---skb_pools ++ */ ++void gmac_proc_create(void) ++{ ++ struct proc_dir_entry *entry = NULL; ++ int i; ++ ++ gmac_proc_root = proc_mkdir("gmac", NULL); ++ if (gmac_proc_root == NULL) ++ return; ++ ++ for (i = 0; i < ARRAY_SIZE(proc_file); i++) { ++ entry = proc_create(proc_file[i].name, 0, gmac_proc_root, ++ &proc_file[i].ops); ++ if (entry == NULL) ++ pr_err("failed to create %s\n", proc_file[i].name); ++ } ++} ++ ++void gmac_proc_destroy(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(proc_file); i++) ++ remove_proc_entry(proc_file[i].name, gmac_proc_root); ++ ++ remove_proc_entry("gmac", NULL); ++} +diff --git a/drivers/net/ethernet/vendor/gmac/gmac_proc.h b/drivers/net/ethernet/vendor/gmac/gmac_proc.h +new file mode 100644 +index 000000000000..4db48281df8c +--- /dev/null ++++ b/drivers/net/ethernet/vendor/gmac/gmac_proc.h +@@ -0,0 +1,21 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++ ++#ifndef GMAC_PROC_H ++#define GMAC_PROC_H ++ ++#include ++ ++#define SIOCSETPM (SIOCDEVPRIVATE + 4) /* set pmt wake up config */ ++#define SIOCSETSUSPEND (SIOCDEVPRIVATE + 5) /* call dev->suspend, debug */ ++#define SIOCSETRESUME (SIOCDEVPRIVATE + 6) /* call dev->resume, debug */ ++ ++void gmac_proc_create(void); ++void gmac_proc_destroy(void); ++ ++/* netdev ops related func */ ++int set_suspend(int eth_n); ++int set_resume(int eth_n); ++ ++#endif +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 698bea312adc..01eb67c4f9b7 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -319,3 +319,9 @@ endif # PHYLIB + config MICREL_KS8995MA + tristate "Micrel KS8995MA 5-ports 10/100 managed Ethernet switch" + depends on SPI ++ ++config SS928V100_PHY ++ tristate "SS928V100 Phy Driver" ++ default y ++ help ++ This driver support the ss928v100 board +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index a13e402074cf..824f61af3131 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -80,3 +80,5 @@ obj-$(CONFIG_STE10XP) += ste10Xp.o + obj-$(CONFIG_TERANETICS_PHY) += teranetics.o + obj-$(CONFIG_VITESSE_PHY) += vitesse.o + obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o ++ ++obj-$(CONFIG_SS928V100_PHY) += mdio_bsp_gemac.o +diff --git a/drivers/net/phy/mdio_bsp_gemac.c b/drivers/net/phy/mdio_bsp_gemac.c +new file mode 100644 +index 000000000000..b6579fb7a3d2 +--- /dev/null ++++ b/drivers/net/phy/mdio_bsp_gemac.c +@@ -0,0 +1,232 @@ ++/* ++ * ++ * Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdio_bsp_gemac.h" ++ ++#define MDIO_SINGLE_CMD 0x00 ++#define MDIO_SINGLE_DATA 0x04 ++#define MDIO_RDATA_STATUS 0x10 ++#define BIT_PHY_ADDR_OFFSET 8 ++#define MDIO_WRITE BIT(16) ++#define MDIO_READ BIT(17) ++#define MDIO_START BIT(20) ++#define MDIO_START_READ (MDIO_START | MDIO_READ) ++#define MDIO_START_WRITE (MDIO_START | MDIO_WRITE) ++ ++struct bsp_gemac_mdio_data { ++ struct clk *clk; ++ struct reset_control *phy_rst; ++ void __iomem *membase; ++}; ++ ++static int bsp_gemac_mdio_wait_ready(struct bsp_gemac_mdio_data *data) ++{ ++ u32 val; ++#define DELAY_US 20 ++#define TIMEOUT_US 10000 ++ return readl_poll_timeout(data->membase + MDIO_SINGLE_CMD, ++ val, !(val & MDIO_START), DELAY_US, TIMEOUT_US); ++} ++ ++static int bsp_gemac_mdio_read(struct mii_bus *bus, int mii_id, int regnum) ++{ ++ struct bsp_gemac_mdio_data *data = bus->priv; ++ int ret; ++ ++ ret = bsp_gemac_mdio_wait_ready(data); ++ if (ret) ++ return ret; ++ ++ writel(MDIO_START_READ | ((u32)mii_id << BIT_PHY_ADDR_OFFSET) | ++ ((u32)regnum), ++ data->membase + MDIO_SINGLE_CMD); ++ ++ ret = bsp_gemac_mdio_wait_ready(data); ++ if (ret) ++ return ret; ++ ++ /* if read data is invalid, we just return 0 instead of -EAGAIN. ++ * This can make MDIO more robust when reading PHY status. ++ */ ++ if (readl(data->membase + MDIO_RDATA_STATUS)) ++ return 0; ++ ++ return readl(data->membase + MDIO_SINGLE_DATA) >> 16; /* 16:right shift */ ++} ++ ++static int bsp_gemac_mdio_write(struct mii_bus *bus, int mii_id, int regnum, ++ u16 value) ++{ ++ struct bsp_gemac_mdio_data *data = bus->priv; ++ int ret; ++ ++ ret = bsp_gemac_mdio_wait_ready(data); ++ if (ret) ++ return ret; ++ ++ writel(value, data->membase + MDIO_SINGLE_DATA); ++ writel(MDIO_START_WRITE | ((u32)mii_id << BIT_PHY_ADDR_OFFSET) | ++ ((u32)regnum), ++ data->membase + MDIO_SINGLE_CMD); ++ ++ return bsp_gemac_mdio_wait_ready(data); ++} ++ ++static void bsp_gemac_external_phy_reset(struct bsp_gemac_mdio_data const *data) ++{ ++ if (data->phy_rst) { ++ /* write 0 to cancel reset */ ++ reset_control_deassert(data->phy_rst); ++ msleep(50); /* 50:delay */ ++ ++ /* use CRG register to reset phy */ ++ /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */ ++ reset_control_assert(data->phy_rst); ++ ++ /* delay some time to ensure reset ok, ++ * this depends on PHY hardware feature ++ */ ++ msleep(50); /* 50:delay */ ++ ++ /* write 0 to cancel reset */ ++ reset_control_deassert(data->phy_rst); ++ /* delay some time to ensure later MDIO access */ ++ msleep(50); /* 50:delay */ ++ } ++} ++ ++static void bsp_gemac_mdiobus_init(struct mii_bus *const bus, struct platform_device *const pdev) ++{ ++ u32 str_len; ++ ++ //va_list arg_list; ++ //va_start(arg_list, "%s"); ++ ++ str_len = strlen(pdev->name); ++ bus->name = "bsp_gemac_mii_bus"; ++ bus->read = &bsp_gemac_mdio_read; ++ bus->write = &bsp_gemac_mdio_write; ++ if (snprintf_s(bus->id, MII_BUS_ID_SIZE, str_len, "%s", pdev->name) < 0) ++ printk("snprintf_s failed! func:%s, line: %d\n", __func__, __LINE__); ++ //va_end(arg_list); ++ //(void)arg_list; ++ bus->parent = &pdev->dev; ++ ++ //if (vsnprintf_s(bus->id, MII_BUS_ID_SIZE, str_len, "%s", pdev->name) < 0) ++ // printk("vsnprintf_s failed! func:%s, line: %d\n", __func__, __LINE__); ++ return; ++} ++ ++static int bsp_gemac_mdio_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct mii_bus *bus = NULL; ++ struct bsp_gemac_mdio_data *data = NULL; ++ struct resource *res = NULL; ++ ++ int ret = bsp_gemac_pinctrl_config(pdev); ++ if (ret) { ++ pr_err("gmac pinctrl config error=%d.\n", ret); ++ return ret; ++ } ++ ++ bus = mdiobus_alloc_size(sizeof(*data)); ++ if (!bus) ++ return -ENOMEM; ++ ++ bsp_gemac_mdiobus_init(bus, pdev); ++ ++ data = bus->priv; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL || data == NULL) { ++ ret = -ENXIO; ++ goto err_out_free_mdiobus; ++ } ++ data->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); ++ if (!data->membase) { ++ ret = -ENOMEM; ++ goto err_out_free_mdiobus; ++ } ++ ++ data->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(data->clk)) { ++ ret = PTR_ERR(data->clk); ++ goto err_out_free_mdiobus; ++ } ++ ++ ret = clk_prepare_enable(data->clk); ++ if (ret) ++ goto err_out_free_mdiobus; ++ ++ data->phy_rst = devm_reset_control_get(&pdev->dev, "phy_reset"); ++ if (IS_ERR(data->phy_rst)) ++ data->phy_rst = NULL; ++ bsp_gemac_external_phy_reset(data); ++ ++ ret = of_mdiobus_register(bus, np); ++ if (ret) ++ goto err_out_disable_clk; ++ ++ platform_set_drvdata(pdev, bus); ++ ++ return 0; ++ ++err_out_disable_clk: ++ clk_disable_unprepare(data->clk); ++err_out_free_mdiobus: ++ mdiobus_free(bus); ++ return ret; ++} ++ ++static int bsp_gemac_mdio_remove(struct platform_device *pdev) ++{ ++ struct mii_bus *bus = platform_get_drvdata(pdev); ++ struct bsp_gemac_mdio_data *data = bus->priv; ++ ++ mdiobus_unregister(bus); ++ clk_disable_unprepare(data->clk); ++ mdiobus_free(bus); ++ ++ return 0; ++} ++ ++static const struct of_device_id bsp_gemac_mdio_dt_ids[] = { ++ { .compatible = "vendor,gemac-mdio" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, bsp_gemac_mdio_dt_ids); ++ ++static struct platform_driver bsp_gemac_mdio_driver = { ++ .probe = bsp_gemac_mdio_probe, ++ .remove = bsp_gemac_mdio_remove, ++ .driver = { ++ .name = "bsp-gemac-mdio", ++ .of_match_table = bsp_gemac_mdio_dt_ids, ++ }, ++}; ++ ++module_platform_driver(bsp_gemac_mdio_driver); ++ ++MODULE_DESCRIPTION("Gigabit Ethernet MAC MDIO interface driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/net/phy/mdio_bsp_gemac.h b/drivers/net/phy/mdio_bsp_gemac.h +new file mode 100644 +index 000000000000..691b80ab6582 +--- /dev/null ++++ b/drivers/net/phy/mdio_bsp_gemac.h +@@ -0,0 +1,28 @@ ++/* ++ * ++ * Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef __MDIO_BSP_GEMAC_H__ ++#define __MDIO_BSP_GEMAC_H__ ++ ++#if defined(CONFIG_ARCH_SS528V100) || defined(CONFIG_ARCH_SS625V100) ++int bsp_gemac_pinctrl_config(struct platform_device *pdev); ++#else ++static inline int bsp_gemac_pinctrl_config(struct platform_device *pdev) ++{ ++ return 0; ++} ++#endif ++ ++#endif /* __MDIO_BSP_GEMAC_H__ */ +diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig +index 9ed5f167a9f3..9a69386e232e 100644 +--- a/drivers/phy/Kconfig ++++ b/drivers/phy/Kconfig +@@ -83,5 +83,6 @@ source "drivers/phy/tegra/Kconfig" + source "drivers/phy/ti/Kconfig" + source "drivers/phy/intel/Kconfig" + source "drivers/phy/xilinx/Kconfig" ++source "drivers/phy/vendor/Kconfig" + + endmenu +diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile +index 6eb2916773c5..9c4683a3d342 100644 +--- a/drivers/phy/Makefile ++++ b/drivers/phy/Makefile +@@ -9,6 +9,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o + obj-$(CONFIG_PHY_XGENE) += phy-xgene.o + obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o + obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o ++obj-$(CONFIG_ARCH_BSP) += vendor/ + obj-y += allwinner/ \ + amlogic/ \ + broadcom/ \ +diff --git a/drivers/phy/vendor/Kconfig b/drivers/phy/vendor/Kconfig +new file mode 100644 +index 000000000000..38c973de485f +--- /dev/null ++++ b/drivers/phy/vendor/Kconfig +@@ -0,0 +1,23 @@ ++config PHY_BSP_SATA ++ tristate "Vendor sata phy support" ++ depends on (ARCH_SS528V100 || ARCH_SS625V100 || ARCH_SS524V100 || ARCH_SS522V100 || ARCH_SS522V101 || ARCH_SS615V100) && OF && HAS_IOMEM ++ default n ++ select GENERIC_PHY ++ help ++ Enable this to support the sata phy that is part of ++ sata driver for Vendor ++ ++config BSP_SATA_MODE ++ int "Vendor sata interworking speed mode(1.5G:0/3G:1/6G:2)" ++ depends on PHY_BSP_SATA ++ help ++ Vendor sata interworking speed mode ++ ++menuconfig VENDOR_USB_PHY ++ tristate "Vendor USB support" ++ ++if VENDOR_USB_PHY ++ ++source "drivers/phy/vendor/usb/Kconfig" ++ ++endif # VENDOR_USB_PHY +diff --git a/drivers/phy/vendor/Makefile b/drivers/phy/vendor/Makefile +new file mode 100644 +index 000000000000..40ce6d5c2b4c +--- /dev/null ++++ b/drivers/phy/vendor/Makefile +@@ -0,0 +1,5 @@ ++# ++# Makefile for the phy drivers. ++# ++obj-$(CONFIG_PHY_BSP_SATA) += phy-bsp-sata.o ++obj-y += usb/ +diff --git a/drivers/phy/vendor/phy-bsp-sata.c b/drivers/phy/vendor/phy-bsp-sata.c +new file mode 100644 +index 000000000000..997694ff51ca +--- /dev/null ++++ b/drivers/phy/vendor/phy-bsp-sata.c +@@ -0,0 +1,175 @@ ++/* ++ * Copyright (c) 2016-2019 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static unsigned int phy_mode = CONFIG_BSP_SATA_MODE; ++static unsigned int ports_num; ++unsigned int sata_port_map; ++ ++#define SLEEP_TIME 20 ++#ifdef MODULE ++module_param(mode_3g, uint, 0600); ++MODULE_PARM_DESC(phy_mode, "sata phy mode (0:1.5G;1:3G(default);2:6G)"); ++#endif ++ ++#ifdef CONFIG_ARCH_SS528V100 ++#include "phy-ss528v100-sata.c" ++#endif ++ ++#ifdef CONFIG_ARCH_SS625V100 ++#include "phy-ss625v100-sata.c" ++#endif ++ ++#if (defined(CONFIG_ARCH_SS524V100) || defined(CONFIG_ARCH_SS522V100) || defined(CONFIG_ARCH_SS522V101) || defined(CONFIG_ARCH_SS615V100)) ++#include "phy-ss524v100-sata.c" ++#endif ++ ++static int bsp_sata_phy_init(struct phy *phy) ++{ ++ unsigned int sata_port_num; ++ void __iomem *mmio = phy_get_drvdata(phy); ++ ++ sata_port_num = bsp_sata_get_port_info(); ++ if ((sata_port_num < 1)) { ++ pr_err("sata ports number:%d WRONG!!!\n", sata_port_num); ++ return -EINVAL; ++ } ++ ports_num = sata_port_num; ++ ++ bsp_sata_poweron(); ++ bsp_sata_reset(); ++ bsp_sata_phy_reset(); ++ bsp_sata_phy_clk_sel(); ++ bsp_sata_clk_enable(); ++ msleep(SLEEP_TIME); ++ bsp_sata_phy_unreset(); ++ msleep(SLEEP_TIME); ++ bsp_sata_unreset(); ++ msleep(SLEEP_TIME); ++ bsp_sata_phy_config(mmio, phy_mode); ++ ++ return 0; ++} ++ ++static int bsp_sata_phy_exit(struct phy *phy) ++{ ++ bsp_sata_phy_reset(); ++ msleep(SLEEP_TIME); ++ bsp_sata_reset(); ++ msleep(SLEEP_TIME); ++ bsp_sata_clk_reset(); ++ msleep(SLEEP_TIME); ++ bsp_sata_clk_disable(); ++ bsp_sata_poweroff(); ++ msleep(SLEEP_TIME); ++ ++ return 0; ++} ++ ++static struct phy_ops bsp_sata_phy_ops = { ++ .init = bsp_sata_phy_init, ++ .exit = bsp_sata_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int bsp_sata_phy_probe(struct platform_device *pdev) ++{ ++ struct phy_provider *phy_provider = NULL; ++ struct device *dev = &pdev->dev; ++ struct resource *res = NULL; ++ struct phy *phy = NULL; ++ void __iomem *mmio = NULL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(dev, "failed to get reg base\n"); ++ return -ENOENT; ++ } ++ ++ mmio = devm_ioremap(dev, res->start, resource_size(res)); ++ if (!mmio) ++ return -ENOMEM; ++ ++ phy = devm_phy_create(dev, NULL, &bsp_sata_phy_ops); ++ if (IS_ERR(phy)) { ++ dev_err(dev, "failed to create PHY\n"); ++ return PTR_ERR(phy); ++ } ++ ++ of_property_read_u32(dev->of_node, "ports_num_max", &ports_num); ++ ++ phy_set_drvdata(phy, mmio); ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (IS_ERR(phy_provider)) ++ return PTR_ERR(phy_provider); ++ ++ return 0; ++} ++ ++static int bsp_sata_phy_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ struct device *dev = &pdev->dev; ++ struct phy *phy = to_phy(dev); ++ ++ bsp_sata_phy_exit(phy); ++ ++ return 0; ++} ++ ++static int bsp_sata_phy_resume(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct phy *phy = to_phy(dev); ++ int ret = 0; ++ ++ ret = bsp_sata_phy_init(phy); ++ if (ret != 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static const struct of_device_id bsp_sata_phy_of_match[] = { ++ { .compatible = "vendor,sata-phy", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, bsp_sata_phy_of_match); ++ ++static struct platform_driver bsp_sata_phy_driver = { ++ .probe = bsp_sata_phy_probe, ++ .suspend = bsp_sata_phy_suspend, ++ .resume = bsp_sata_phy_resume, ++ .driver = { ++ .name = "bsp-sata-phy", ++ .of_match_table = bsp_sata_phy_of_match, ++ } ++}; ++module_platform_driver(bsp_sata_phy_driver); ++ ++MODULE_AUTHOR("Vendor"); ++MODULE_DESCRIPTION("Vendor SATA PHY driver"); ++MODULE_ALIAS("platform:bsp-sata-phy"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/phy/vendor/phy-bsp-sata.h b/drivers/phy/vendor/phy-bsp-sata.h +new file mode 100644 +index 000000000000..984db03987b4 +--- /dev/null ++++ b/drivers/phy/vendor/phy-bsp-sata.h +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (c) 2016-2017 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++enum { ++ /* extended global controller registers */ ++ PHY_CTL0 = 0xA0, ++ PHY_CTL1 = 0xA4, ++ PHY_RST_BACK_MASK = 0xAC, ++ PHY_CTL2 = 0xB0, ++ ++#define PHY_DATA_INVERT (0x1 << 3) ++#define PHY0_RST_MASK (0x1 << 4) ++#define PHY_RST_MASK_ALL (0xF << 4) ++ ++ /* extended registers for each SATA port */ ++ PORT_FIFOTH = 0x44, ++ PORT_FIFOTH2 = 0x7C, ++ PORT_PHYCTL1 = 0x48, ++ PORT_PHYCTL = 0x74, ++ ++#define PHY_MODE_1_5G 0 ++#define PHY_MODE_3G 1 ++#define PHY_MODE_6G 2 ++}; +diff --git a/drivers/phy/vendor/phy-ss524v100-sata.c b/drivers/phy/vendor/phy-ss524v100-sata.c +new file mode 100644 +index 000000000000..b2605fa95dab +--- /dev/null ++++ b/drivers/phy/vendor/phy-ss524v100-sata.c +@@ -0,0 +1,684 @@ ++/* ++ * Copyright (c) 2016-2019 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++#include ++#include ++ ++#include "phy-bsp-sata.h" ++ ++#define BSP_SATA_PHY0_CTLL 0xA0 ++#define BSP_SATA_PHY0_CTLH 0xA4 ++#define BSP_SATA_PHY1_CTLL 0xAC ++#define BSP_SATA_PHY1_CTLH 0xB0 ++ ++#define BSP_SATA_PORT_FIFOTH 0x44 ++#define BSP_SATA_PORT_PHYCTL1 0x70 ++#define BSP_SATA_PORT_PHYCTL2 0x74 ++#define BSP_SATA_PORT_PHYCTL3 0x78 ++ ++#define BSP_SYS_CTRL_REG_BASE 0x11020000 ++#define BSP_SYS_STAT_REG 0x0018 ++#define BSP_SYS_CTRL_REG_MAP_SIZE 0x1000 ++#define get_ups_mode_val(reg_val) (((reg_val) >> 16) & 0x7) ++ ++#define SATA_PHY_CTRL0 0x140 ++#define SATA_PHY_CTRL1 0x144 ++ ++#define P1_PHY_SERDES_ARCH BIT(21) ++#define P0_PHY_SERDES_ARCH BIT(5) ++ ++#define P3_PHY_SERDES_ARCH BIT(21) ++#define P2_PHY_SERDES_ARCH BIT(5) ++ ++#define BSP_MISC_REG_BASE 0x11024000 ++#define BSP_MISC_REG_MAP_SIZE 0x1000 ++ ++#define BSP_COMB_PHY1_TEST_CTRL 0x1c8 ++ ++#define BSP_CRG_REG_BASE 0x11010000 ++ ++#define SATA_CLK_RST_CTRL_1_REG 0x3B40 ++#define SATA_CLK_RST_CTRL_2_REG 0x3B48 ++ ++#define BSP_SATA_CKO_ALIVE_SRST_REQ BIT(0) ++#define BSP_SATA_CKO_CKEN BIT(4) ++#define BSP_SATA_BUS_SRST_REQ BIT(0) ++#define BSP_SATA_BUS_CKEN BIT(4) ++ ++#define SATA_PHY0_CLK_RST_REG 0x3B60 ++#define SATA_PHY1_CLK_RST_REG 0x3B80 ++ ++#define SATA_CTRL_RX_RST BIT(0) ++#define SATA_CTRL_SATA_RST BIT(1) ++#define SATA_CTRL_RX_CKEN BIT(4) ++#define SATA_CTRL_TX_CKEN BIT(5) ++ ++#define COMB_PHY1_PORT_A_REG 0x3B70 ++#define COMB_PHY1_PORT_B_REG 0x3B90 ++ ++#define COMB_PHY_REST BIT(0) ++#define COMB_PHY_TEST_REST BIT(1) ++#define COMB_PHY_REF_CLKEN BIT(4) ++#define COM_PHY_REF_CLKSEL BIT(12) ++#define com_phy_ref_clksel_100m(reg_val) ((reg_val) & (~COM_PHY_REF_CLKSEL)) ++ ++#define SATA_CRG_MAP_SIZE 0x100 ++ ++#define CASE_NUM0 0 ++#define CASE_NUM1 1 ++#define CASE_NUM2 2 ++ ++enum { ++ FIFOTH_VALUE = 0xdffeffff, ++ FIFOTH_VALUE2 = 0x92000047, ++ PHY_VALUE = 0x4900003d, ++ PHYCTL2_VALUE = 0x60555, ++ ++ PORT_BIGENDINE = 0x82e5cb8, ++ ++ PX_TX_AMPLITUDE = 0x36089, ++ PX_TX_DEEMPH = 0x489186, ++ ++ PHY_SG_1_5G = 0xe000030, ++ PHY_SG_3G = 0xe200030, ++ PHY_SG_6G = 0xe400030, ++}; ++ ++static void bsp_sata_poweron(void) ++{ ++} ++ ++static void bsp_sata_poweroff(void) ++{ ++} ++ ++static void bsp_sata0_rx0_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata0_rx0_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata1_rx1_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata1_rx1_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++void bsp_sata_reset_rxtx_assert(unsigned int port_no) ++{ ++ void *crg_base = NULL; ++ void *comb_phy_crg_base = NULL; ++ unsigned int reg_val; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ iounmap(comb_phy_crg_base); ++ return; ++ } ++ ++ switch (port_no) { ++ case CASE_NUM0: ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++ ++ reg_val = readl(comb_phy_crg_base); ++ reg_val |= COMB_PHY_REST; ++ writel(reg_val, comb_phy_crg_base); ++ break; ++ case CASE_NUM1: ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++ ++ reg_val = readl(comb_phy_crg_base + 0x20); ++ reg_val |= COMB_PHY_REST; ++ writel(reg_val, comb_phy_crg_base + 0x20); ++ break; ++ default: ++ break; ++ } ++ iounmap(crg_base); ++ iounmap(comb_phy_crg_base); ++} ++EXPORT_SYMBOL(bsp_sata_reset_rxtx_assert); ++ ++void bsp_sata_reset_rxtx_deassert(unsigned int port_no) ++{ ++ void *crg_base = NULL; ++ void *comb_phy_crg_base = NULL; ++ unsigned int reg_val; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ iounmap(comb_phy_crg_base); ++ return; ++ } ++ ++ switch (port_no) { ++ case CASE_NUM0: ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++ ++ reg_val = readl(comb_phy_crg_base); ++ reg_val &= ~(COMB_PHY_REST); ++ writel(reg_val, comb_phy_crg_base); ++ break; ++ case CASE_NUM1: ++ reg_val = readl(crg_base + 0x40); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++ ++ reg_val = readl(comb_phy_crg_base + 0x20); ++ reg_val &= ~(COMB_PHY_REST); ++ writel(reg_val, comb_phy_crg_base + 0x20); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(crg_base); ++ iounmap(comb_phy_crg_base); ++ udelay(100); /* delay 100 us */ ++} ++EXPORT_SYMBOL(bsp_sata_reset_rxtx_deassert); ++ ++static void bsp_sata_reset(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val |= BSP_SATA_CKO_ALIVE_SRST_REQ; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val |= BSP_SATA_BUS_SRST_REQ; ++ writel(reg_val, crg_base + 0x8); ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ bsp_sata0_rx0_reset(crg_base); ++ bsp_sata1_rx1_reset(crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_unreset(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ bsp_sata0_rx0_unreset(crg_base); ++ bsp_sata1_rx1_unreset(crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val &= ~BSP_SATA_CKO_ALIVE_SRST_REQ; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val &= ~BSP_SATA_BUS_SRST_REQ; ++ writel(reg_val, crg_base + 0x8); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_port1_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_port1_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_port0_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_port0_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy_reset(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_port1_reset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_port0_reset(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++static void bsp_sata_phy_unreset(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_port1_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_port0_unreset(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++ udelay(60); /* delay 60 us */ ++} ++ ++static void bsp_sata_port0_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_port1_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_clk_enable(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ bsp_sata_port0_clk_enable(crg_base); ++ bsp_sata_port1_clk_enable(crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val |= BSP_SATA_CKO_CKEN; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val |= BSP_SATA_BUS_CKEN; ++ writel(reg_val, crg_base + 0x8); ++ ++ iounmap(crg_base); ++ udelay(300); /* delay 300 us */ ++} ++ ++static void bsp_sata_clk_disable(void) ++{ ++ printk("----------bsp_sata_clk_diable--------\n"); ++} ++ ++static void bsp_sata_clk_reset(void) ++{ ++} ++ ++static void bsp_sata_port1_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_port0_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy_clk_sel(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_port1_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_port0_clk_sel(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++void bsp_sata_set_fifoth(void *mmio) ++{ ++ unsigned int port_idx; ++ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ writel(FIFOTH_VALUE, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH)); ++ writel(FIFOTH_VALUE2, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH2)); ++ } ++} ++EXPORT_SYMBOL(bsp_sata_set_fifoth); ++ ++static void bsp_sata_port1_config(void *misc_base) ++{ ++ /* cfg COMBPHY1 PORT B */ ++ writel(0x88200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x88201, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x88200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x48700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x48701, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x48700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x58300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x58301, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x58300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x19100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x19101, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x19100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xC08C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC08C01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC08C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xd88d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd88d01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd88d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++} ++ ++static void bsp_sata_port0_config(void *misc_base) ++{ ++ writel(0x80200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x80201, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x80200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x40700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x40701, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x40700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x50300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x50301, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x50300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x11100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x11101, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x11100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xC00C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC00C01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC00C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xd80d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd80d01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd80d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++} ++ ++static void bsp_sata_port_cfg(void) ++{ ++ void *misc_base = NULL; ++ ++ misc_base = ioremap(BSP_MISC_REG_BASE, BSP_MISC_REG_MAP_SIZE); ++ if (!misc_base) { ++ pr_err("ioremap misc reg failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_port1_config(misc_base); ++ ++ /* cfg COMBPHY1 PORT A */ ++ bsp_sata_port0_config(misc_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(misc_base); ++} ++ ++#define IOCONFIG1_REG_BASE 0x10ff0000 ++#define IOCONFIG1_REG_MAP_SIZE 0x200 ++static void bsp_sata_set_led(void) ++{ ++ void *reg_addr = NULL; ++ unsigned int port_idx; ++ ++ reg_addr = ioremap(IOCONFIG1_REG_BASE, IOCONFIG1_REG_MAP_SIZE); ++ if (reg_addr == NULL) { ++ pr_err("ioremap ioconfg1 register addr for sata failed! func:%s, line:%d\n", ++ __func__, __LINE__); ++ return; ++ } ++ ++ /* Set SATA_LED_N */ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ if (port_idx == 0) ++ writel(0x1201, reg_addr + 0xFC); ++ else ++ writel(0x1201, reg_addr + 0x100); ++ } ++ ++ iounmap(reg_addr); ++} ++ ++static void bsp_sata_phy_config(void *mmio, int phy_mode) ++{ ++ unsigned int phy_config = PHY_SG_6G; ++ unsigned int port_idx; ++ unsigned int val; ++ void *misc_base = NULL; ++ ++ bsp_sata_set_fifoth(mmio); ++ ++ /* Set SATA_LED_N */ ++ bsp_sata_set_led(); ++ ++ /* set phy PX TX amplitude */ ++ /* set phy PX TX pre-emphasis */ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ writel(PX_TX_DEEMPH, (mmio + 0x100 + port_idx * 0x80 + BSP_SATA_PORT_PHYCTL2)); ++ writel(PX_TX_AMPLITUDE, (mmio + 0x100 + port_idx * 0x80 + ++ BSP_SATA_PORT_PHYCTL1)); ++ writel(phy_config, (mmio + 0x100 + port_idx * 0x80 + BSP_SATA_PORT_PHYCTL3)); ++ } ++ ++ misc_base = ioremap(BSP_MISC_REG_BASE, BSP_MISC_REG_MAP_SIZE); ++ if (!misc_base) { ++ pr_err("ioremap misc reg failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM2: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH | P1_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(misc_base); ++ bsp_sata_port_cfg(); ++} ++ ++unsigned int bsp_sata_get_port_info(void) ++{ ++ unsigned int sata_port_num; ++ ++ sata_port_num = 2; /* 2 sata_port_num */ ++ sata_port_map = 0x3; ++ ++ return sata_port_num; ++} +diff --git a/drivers/phy/vendor/phy-ss528v100-sata.c b/drivers/phy/vendor/phy-ss528v100-sata.c +new file mode 100644 +index 000000000000..edf6ee730440 +--- /dev/null ++++ b/drivers/phy/vendor/phy-ss528v100-sata.c +@@ -0,0 +1,1043 @@ ++/* ++ * Copyright (c) 2016-2019 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++#include ++#include ++ ++#include "phy-bsp-sata.h" ++ ++#define BSP_SATA_PHY0_CTLL 0xA0 ++#define BSP_SATA_PHY0_CTLH 0xA4 ++#define BSP_SATA_PHY1_CTLL 0xAC ++#define BSP_SATA_PHY1_CTLH 0xB0 ++ ++#define BSP_SATA_PORT_FIFOTH 0x44 ++#define BSP_SATA_PORT_PHYCTL1 0x70 ++#define BSP_SATA_PORT_PHYCTL2 0x74 ++#define BSP_SATA_PORT_PHYCTL3 0x78 ++ ++#define BSP_SYS_CTRL_REG_BASE 0x11020000 ++#define BSP_SYS_STAT_REG 0x0018 ++#define BSP_SYS_CTRL_REG_MAP_SIZE 0x1000 ++#define get_ups_mode_val(reg_val) (((reg_val) >> 16) & 0x7) ++ ++#define SATA_PHY_CTRL0 0x140 ++#define SATA_PHY_CTRL1 0x144 ++ ++#define P1_PHY_SERDES_ARCH BIT(21) ++#define P0_PHY_SERDES_ARCH BIT(5) ++ ++#define P3_PHY_SERDES_ARCH BIT(21) ++#define P2_PHY_SERDES_ARCH BIT(5) ++ ++#define BSP_MISC_REG_BASE 0x11024000 ++#define BSP_MISC_REG_MAP_SIZE 0x1000 ++ ++#define BSP_COMB_PHY1_TEST_CTRL 0x1cc ++#define BSP_COMB_PHY2_TEST_CTRL 0x1d0 ++ ++#define BSP_CRG_REG_BASE 0x11010000 ++ ++#define SATA_CLK_RST_CTRL_1_REG 0x3B40 ++#define SATA_CLK_RST_CTRL_2_REG 0x3B48 ++ ++#define BSP_SATA_CKO_ALIVE_SRST_REQ BIT(0) ++#define BSP_SATA_CKO_CKEN BIT(4) ++#define BSP_SATA_BUS_SRST_REQ BIT(0) ++#define BSP_SATA_BUS_CKEN BIT(4) ++ ++#define SATA_PHY0_CLK_RST_REG 0x3B60 ++#define SATA_PHY1_CLK_RST_REG 0x3B80 ++#define SATA_PHY2_CLK_RST_REG 0x3BA0 ++#define SATA_PHY3_CLK_RST_REG 0x3BC0 ++ ++#define SATA_CTRL_RX_RST BIT(0) ++#define SATA_CTRL_SATA_RST BIT(1) ++#define SATA_CTRL_RX_CKEN BIT(4) ++#define SATA_CTRL_TX_CKEN BIT(5) ++ ++#define COMB_PHY1_PORT_A_REG 0x3B70 ++#define COMB_PHY1_PORT_B_REG 0x3B90 ++#define COMB_PHY2_PORT_A_REG 0x3BB0 ++#define COMB_PHY2_PORT_B_REG 0x3BD0 ++ ++#define COMB_PHY_REST BIT(0) ++#define COMB_PHY_TEST_REST BIT(1) ++#define COMB_PHY_REF_CLKEN BIT(4) ++#define COM_PHY_REF_CLKSEL BIT(12) ++#define com_phy_ref_clksel_100m(reg_val) ((reg_val) & (~COM_PHY_REF_CLKSEL)) ++ ++#define SATA_CRG_MAP_SIZE 0x100 ++ ++#define CASE_NUM0 0 ++#define CASE_NUM1 1 ++#define CASE_NUM2 2 ++#define CASE_NUM3 3 ++#define CASE_NUM4 4 ++#define CASE_NUM5 5 ++ ++enum { ++ FIFOTH_VALUE = 0xdffeffff, ++ PHY_VALUE = 0x4900003d, ++ PHYCTL2_VALUE = 0x60555, ++ ++ PORT_BIGENDINE = 0x82e5cb8, ++ ++ PX_TX_AMPLITUDE = 0x36089, ++ PX_TX_PREEMPH = 0x486186, ++ ++ PHY_SG_1_5G = 0xe000030, ++ PHY_SG_3G = 0xe200030, ++ PHY_SG_6G = 0xe400030, ++}; ++ ++static void bsp_sata_poweron(void) ++{ ++} ++ ++static void bsp_sata_poweroff(void) ++{ ++} ++ ++static void bsp_ctrl_sata_rx_reset(void *crg_base, unsigned int crg_base_offset) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + crg_base_offset); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + crg_base_offset); ++} ++ ++static void bsp_ctrl_sata_rx_unreset(void *crg_base, unsigned int crg_base_offset) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + crg_base_offset); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + crg_base_offset); ++} ++ ++static void bsp_comb_phy_reset(void *comb_phy_crg_base, unsigned int comb_phy_crg_base_offset) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(comb_phy_crg_base + comb_phy_crg_base_offset); ++ reg_val |= COMB_PHY_REST; ++ writel(reg_val, comb_phy_crg_base + comb_phy_crg_base_offset); ++} ++ ++static void bsp_comb_phy_unreset(void *comb_phy_crg_base, unsigned int comb_phy_crg_base_offset) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(comb_phy_crg_base + comb_phy_crg_base_offset); ++ reg_val &= ~(COMB_PHY_REST); ++ writel(reg_val, comb_phy_crg_base + comb_phy_crg_base_offset); ++} ++ ++static void bsp_sata_rx_reset(void *crg_base, unsigned int port_no) ++{ ++ switch (port_no) { ++ case CASE_NUM1: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x20); ++ break; ++ case CASE_NUM2: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x20); ++ bsp_ctrl_sata_rx_reset(crg_base, 0x40); ++ break; ++ case CASE_NUM3: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x20); ++ bsp_ctrl_sata_rx_reset(crg_base, 0x40); ++ bsp_ctrl_sata_rx_reset(crg_base, 0x60); ++ break; ++ case CASE_NUM4: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x20); ++ bsp_ctrl_sata_rx_reset(crg_base, 0x40); ++ bsp_ctrl_sata_rx_reset(crg_base, 0x60); ++ bsp_ctrl_sata_rx_reset(crg_base, 0x80); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void bsp_sata_rx_unreset(void *crg_base, unsigned int port_no) ++{ ++ switch (port_no) { ++ case CASE_NUM1: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x20); ++ break; ++ case CASE_NUM2: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x20); ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x40); ++ break; ++ case CASE_NUM3: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x20); ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x40); ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x60); ++ break; ++ case CASE_NUM4: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x20); ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x40); ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x60); ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x80); ++ break; ++ default: ++ break; ++ } ++} ++ ++void bsp_sata_reset_rxtx_assert(unsigned int port_no) ++{ ++ void *crg_base = NULL; ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ iounmap(comb_phy_crg_base); ++ return; ++ } ++ ++ switch (port_no) { ++ case CASE_NUM0: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x20); ++ bsp_comb_phy_reset(comb_phy_crg_base, 0x20); ++ break; ++ case CASE_NUM1: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x40); ++ bsp_comb_phy_reset(comb_phy_crg_base, 0x00); ++ break; ++ case CASE_NUM2: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x60); ++ bsp_comb_phy_reset(comb_phy_crg_base, 0x60); ++ break; ++ case CASE_NUM3: ++ bsp_ctrl_sata_rx_reset(crg_base, 0x80); ++ bsp_comb_phy_reset(comb_phy_crg_base, 0x40); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(crg_base); ++ iounmap(comb_phy_crg_base); ++} ++EXPORT_SYMBOL(bsp_sata_reset_rxtx_assert); ++ ++void bsp_sata_reset_rxtx_deassert(unsigned int port_no) ++{ ++ void *crg_base = NULL; ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ iounmap(comb_phy_crg_base); ++ return; ++ } ++ ++ switch (port_no) { ++ case CASE_NUM0: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x20); ++ bsp_comb_phy_unreset(comb_phy_crg_base, 0x20); ++ break; ++ case CASE_NUM1: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x40); ++ bsp_comb_phy_unreset(comb_phy_crg_base, 0x00); ++ break; ++ case CASE_NUM2: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x60); ++ bsp_comb_phy_unreset(comb_phy_crg_base, 0x60); ++ break; ++ case CASE_NUM3: ++ bsp_ctrl_sata_rx_unreset(crg_base, 0x80); ++ bsp_comb_phy_unreset(comb_phy_crg_base, 0x40); ++ break; ++ default: ++ break; ++ } ++ iounmap(crg_base); ++ iounmap(comb_phy_crg_base); ++ udelay(100); /* delay 100 us */ ++} ++EXPORT_SYMBOL(bsp_sata_reset_rxtx_deassert); ++ ++static void bsp_sata_reset(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val |= BSP_SATA_CKO_ALIVE_SRST_REQ; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val |= BSP_SATA_BUS_SRST_REQ; ++ writel(reg_val, crg_base + 0x8); ++ ++ bsp_sata_rx_reset(crg_base, ports_num); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_unreset(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ bsp_sata_rx_unreset(crg_base, ports_num); ++ ++ reg_val = readl(crg_base); ++ reg_val &= ~BSP_SATA_CKO_ALIVE_SRST_REQ; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val &= ~BSP_SATA_BUS_SRST_REQ; ++ writel(reg_val, crg_base + 0x8); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_phy1_portb_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_phy1_portb_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_phy1_porta_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy1_porta_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy2_portb_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x60); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x60); ++} ++ ++static void bsp_sata_phy2_portb_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x60); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x60); ++} ++ ++static void bsp_sata_phy2_porta_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_phy2_porta_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_phy_reset(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_reset(comb_phy_crg_base); ++ break; ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_reset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_reset(comb_phy_crg_base); ++ break; ++ case CASE_NUM3: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_reset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_reset(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_reset(comb_phy_crg_base); ++ break; ++ case CASE_NUM4: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_reset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_reset(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_reset(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT A */ ++ bsp_sata_phy2_porta_reset(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++static void bsp_sata_phy_unreset(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_unreset(comb_phy_crg_base); ++ break; ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_unreset(comb_phy_crg_base); ++ break; ++ case CASE_NUM3: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_unreset(comb_phy_crg_base); ++ break; ++ case CASE_NUM4: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT A */ ++ bsp_sata_phy2_porta_unreset(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ udelay(60); /* delay 60 us */ ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++static void bsp_sata_tx0_rx0_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_tx1_rx1_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_tx2_rx2_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x60); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x60); ++} ++ ++static void bsp_sata_tx3_rx3_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x80); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x80); ++} ++ ++static void bsp_sata_clk_enable(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ bsp_sata_tx0_rx0_clk_enable(crg_base); ++ break; ++ case CASE_NUM2: ++ bsp_sata_tx0_rx0_clk_enable(crg_base); ++ bsp_sata_tx1_rx1_clk_enable(crg_base); ++ break; ++ case CASE_NUM3: ++ bsp_sata_tx0_rx0_clk_enable(crg_base); ++ bsp_sata_tx1_rx1_clk_enable(crg_base); ++ bsp_sata_tx2_rx2_clk_enable(crg_base); ++ break; ++ case CASE_NUM4: ++ bsp_sata_tx0_rx0_clk_enable(crg_base); ++ bsp_sata_tx1_rx1_clk_enable(crg_base); ++ bsp_sata_tx2_rx2_clk_enable(crg_base); ++ bsp_sata_tx3_rx3_clk_enable(crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val |= BSP_SATA_CKO_CKEN; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val |= BSP_SATA_BUS_CKEN; ++ writel(reg_val, crg_base + 0x8); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_clk_disable(void) ++{ ++} ++ ++static void bsp_sata_clk_reset(void) ++{ ++} ++ ++static void bsp_sata_phy1_portb_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_phy1_porta_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy2_portb_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x60); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base + 0x60); ++} ++ ++static void bsp_sata_phy2_porta_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_phy_clk_sel(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_clk_sel(comb_phy_crg_base); ++ break; ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_clk_sel(comb_phy_crg_base); ++ break; ++ case CASE_NUM3: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_clk_sel(comb_phy_crg_base); ++ break; ++ case CASE_NUM4: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY2 PORT A */ ++ bsp_sata_phy2_porta_clk_sel(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++void bsp_sata_set_fifoth(void *mmio) ++{ ++ unsigned int port_idx; ++ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) ++ writel(FIFOTH_VALUE, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH)); ++} ++EXPORT_SYMBOL(bsp_sata_set_fifoth); ++ ++static void bsp_sata_phy1_portb_config(void *misc_base) ++{ ++ writel(0x88200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x88201, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x88200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x19100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x19101, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x19100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xC08C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC08C01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC08C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xd88d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd88d01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd88d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x48700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x48701, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x48700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x58300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x58301, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x58300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++} ++ ++static void bsp_sata_phy1_porta_config(void *misc_base) ++{ ++ writel(0x80200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x80201, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x80200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x11100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x11101, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x11100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xC00C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC00C01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC00C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xd80d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd80d01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd80d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x40700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x40701, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x40700, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x50300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x50301, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x50300, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++} ++ ++static void bsp_sata_phy2_portb_config(void *misc_base) ++{ ++ writel(0x88200, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x88201, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x88200, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0x19100, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x19101, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x19100, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0xC08C00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xC08C01, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xC08C00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0xd88d00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xd88d01, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xd88d00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0x48700, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x48701, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x48700, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0x58300, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x58301, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x58300, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++} ++ ++static void bsp_sata_phy2_porta_config(void *misc_base) ++{ ++ writel(0x80200, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x80201, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x80200, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0x11100, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x11101, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x11100, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0xC00C00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xC00C01, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xC00C00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0xd80d00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xd80d01, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0xd80d00, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0x40700, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x40701, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x40700, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ ++ writel(0x50300, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x50301, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x50300, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY2_TEST_CTRL); ++} ++ ++static void bsp_sata_port_cfg(void) ++{ ++ void *misc_base = NULL; ++ ++ misc_base = ioremap(BSP_MISC_REG_BASE, BSP_MISC_REG_MAP_SIZE); ++ if (!misc_base) { ++ pr_err("ioremap misc reg failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_config(misc_base); ++ break; ++ case CASE_NUM2: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_config(misc_base); ++ ++ /* cfg COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_config(misc_base); ++ break; ++ case CASE_NUM3: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_config(misc_base); ++ ++ /* cfg COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_config(misc_base); ++ ++ /* cfg COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_config(misc_base); ++ break; ++ case CASE_NUM4: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_config(misc_base); ++ ++ /* cfg COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_config(misc_base); ++ ++ /* cfg COMBPHY2 PORT B */ ++ bsp_sata_phy2_portb_config(misc_base); ++ ++ /* cfg COMBPHY2 PORT A */ ++ bsp_sata_phy2_porta_config(misc_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(misc_base); ++} ++ ++#define IOCONFIG1_REG_BASE 0x10ff0000 ++#define IOCONFIG1_REG_MAP_SIZE 0x80 ++static void bsp_sata_set_led(void) ++{ ++ void *reg_addr = NULL; ++ unsigned int port_idx; ++ ++ reg_addr = ioremap(IOCONFIG1_REG_BASE, IOCONFIG1_REG_MAP_SIZE); ++ if (reg_addr == NULL) { ++ pr_err("ioremap ioconfg1 register addr for sata failed! func:%s, line:%d\n", ++ __func__, __LINE__); ++ return; ++ } ++ ++ /* Set SATA_LED_N */ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ if (port_idx == 0) ++ writel(0x1201, reg_addr + 0x48); ++ else if (port_idx == 1) ++ writel(0x1201, reg_addr + 0x4c); ++ else if (port_idx == 2) /* 2 ports_num */ ++ writel(0x1201, reg_addr + 0x50); ++ else ++ writel(0x1201, reg_addr + 0x54); ++ } ++ ++ iounmap(reg_addr); ++} ++ ++static void bsp_sata_phy_config(void *mmio, int phy_mode) ++{ ++ unsigned int phy_config = PHY_SG_6G; ++ unsigned int port_idx; ++ unsigned int val; ++ void *misc_base = NULL; ++ ++ bsp_sata_set_fifoth(mmio); ++ ++ /* Set SATA_LED_N */ ++ bsp_sata_set_led(); ++ ++ /* set phy PX TX amplitude */ ++ /* set phy PX TX pre-emphasis */ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ writel(PX_TX_PREEMPH, (mmio + 0x100 + port_idx * 0x80 + BSP_SATA_PORT_PHYCTL2)); ++ writel(PX_TX_AMPLITUDE, (mmio + 0x100 + port_idx * 0x80 + BSP_SATA_PORT_PHYCTL1)); ++ writel(phy_config, (mmio + 0x100 + port_idx * 0x80 + BSP_SATA_PORT_PHYCTL3)); ++ } ++ ++ misc_base = ioremap(BSP_MISC_REG_BASE, BSP_MISC_REG_MAP_SIZE); ++ if (!misc_base) { ++ pr_err("ioremap misc reg failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ break; ++ case CASE_NUM2: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH | P1_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ break; ++ case CASE_NUM3: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH | P1_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ ++ val = readl(misc_base + SATA_PHY_CTRL1); ++ val |= P2_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL1); ++ break; ++ case CASE_NUM4: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH | P1_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ ++ val = readl(misc_base + SATA_PHY_CTRL1); ++ val |= P2_PHY_SERDES_ARCH | P3_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL1); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(misc_base); ++ bsp_sata_port_cfg(); ++} ++ ++unsigned int bsp_sata_get_port_info(void) ++{ ++ unsigned int ups_mode; ++ unsigned int reg_val; ++ unsigned int sata_port_num; ++ void *sysctrl_reg_base = NULL; ++ ++ sysctrl_reg_base = ioremap(BSP_SYS_CTRL_REG_BASE, BSP_SYS_CTRL_REG_MAP_SIZE); ++ if (!sysctrl_reg_base) { ++ pr_err("ioremap sysctrl reg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return 0; ++ } ++ ++ reg_val = readl(sysctrl_reg_base + BSP_SYS_STAT_REG); ++ ups_mode = get_ups_mode_val(reg_val); ++ switch (ups_mode) { ++ case CASE_NUM1: ++ sata_port_num = 1; ++ sata_port_map = 0x1; ++ break; ++ case CASE_NUM2: ++ case CASE_NUM3: ++ sata_port_num = 2; /* 2 sata_port_num */ ++ sata_port_map = 0x3; ++ break; ++ case CASE_NUM4: ++ sata_port_num = 3; ++ sata_port_map = 0x7; ++ break; ++ case CASE_NUM5: ++ sata_port_num = 4; ++ sata_port_map = 0xf; ++ break; ++ default: ++ sata_port_num = 0; ++ sata_port_map = 0; ++ break; ++ } ++ ++ return sata_port_num; ++} +diff --git a/drivers/phy/vendor/phy-ss625v100-sata.c b/drivers/phy/vendor/phy-ss625v100-sata.c +new file mode 100644 +index 000000000000..596df51badd2 +--- /dev/null ++++ b/drivers/phy/vendor/phy-ss625v100-sata.c +@@ -0,0 +1,732 @@ ++/* ++ * Copyright (c) 2016-2019 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++#include ++#include ++ ++#include "phy-bsp-sata.h" ++ ++#define BSP_SATA_PHY0_CTLL 0xA0 ++#define BSP_SATA_PHY0_CTLH 0xA4 ++#define BSP_SATA_PHY1_CTLL 0xAC ++#define BSP_SATA_PHY1_CTLH 0xB0 ++ ++#define BSP_SATA_PORT_FIFOTH 0x44 ++#define BSP_SATA_PORT_PHYCTL1 0x70 ++#define BSP_SATA_PORT_PHYCTL2 0x74 ++#define BSP_SATA_PORT_PHYCTL3 0x78 ++ ++#define BSP_SYS_CTRL_REG_BASE 0x11020000 ++#define BSP_SYS_STAT_REG 0x0018 ++#define BSP_SYS_CTRL_REG_MAP_SIZE 0x1000 ++#define get_ups_mode_val(reg_val) (((reg_val) >> 16) & 0x7) ++ ++#define SATA_PHY_CTRL0 0x140 ++#define SATA_PHY_CTRL1 0x144 ++ ++#define P1_PHY_SERDES_ARCH BIT(21) ++#define P0_PHY_SERDES_ARCH BIT(5) ++ ++#define P3_PHY_SERDES_ARCH BIT(21) ++#define P2_PHY_SERDES_ARCH BIT(5) ++ ++#define BSP_MISC_REG_BASE 0x11024000 ++#define BSP_MISC_REG_MAP_SIZE 0x1000 ++ ++#define BSP_COMB_PHY1_TEST_CTRL 0x1cc ++#define BSP_COMB_PHY2_TEST_CTRL 0x1d0 ++ ++#define BSP_CRG_REG_BASE 0x11010000 ++ ++#define SATA_CLK_RST_CTRL_1_REG 0x3B40 ++#define SATA_CLK_RST_CTRL_2_REG 0x3B48 ++ ++#define BSP_SATA_CKO_ALIVE_SRST_REQ BIT(0) ++#define BSP_SATA_CKO_CKEN BIT(4) ++#define BSP_SATA_BUS_SRST_REQ BIT(0) ++#define BSP_SATA_BUS_CKEN BIT(4) ++ ++#define SATA_PHY0_CLK_RST_REG 0x3B60 ++#define SATA_PHY1_CLK_RST_REG 0x3B80 ++#define SATA_PHY2_CLK_RST_REG 0x3BA0 ++#define SATA_PHY3_CLK_RST_REG 0x3BC0 ++ ++#define SATA_CTRL_RX_RST BIT(0) ++#define SATA_CTRL_SATA_RST BIT(1) ++#define SATA_CTRL_RX_CKEN BIT(4) ++#define SATA_CTRL_TX_CKEN BIT(5) ++ ++#define COMB_PHY1_PORT_A_REG 0x3B70 ++#define COMB_PHY1_PORT_B_REG 0x3B90 ++#define COMB_PHY2_PORT_A_REG 0x3BB0 ++#define COMB_PHY2_PORT_B_REG 0x3BD0 ++ ++#define COMB_PHY_REST BIT(0) ++#define COMB_PHY_TEST_REST BIT(1) ++#define COMB_PHY_REF_CLKEN BIT(4) ++#define COM_PHY_REF_CLKSEL BIT(12) ++#define com_phy_ref_clksel_100m(reg_val) ((reg_val) & (~COM_PHY_REF_CLKSEL)) ++ ++#define SATA_CRG_MAP_SIZE 0x100 ++ ++#define CASE_NUM0 0 ++#define CASE_NUM1 1 ++#define CASE_NUM2 2 ++ ++enum { ++ FIFOTH_VALUE = 0xdffeffff, ++ PHY_VALUE = 0x4900003d, ++ PHYCTL2_VALUE = 0x60555, ++ ++ PORT_BIGENDINE = 0x82e5cb8, ++ ++ PX_TX_AMPLITUDE = 0x36089, ++ PX_TX_PREEMPH = 0x486186, ++ ++ PHY_SG_1_5G = 0xe000030, ++ PHY_SG_3G = 0xe200030, ++ PHY_SG_6G = 0xe400030, ++}; ++ ++static void bsp_sata_poweron(void) ++{ ++} ++ ++static void bsp_sata_poweroff(void) ++{ ++} ++ ++static void bsp_sata0_rx0_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata0_rx0_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata1_rx1_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata1_rx1_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_rx_reset(void *crg_base, unsigned int port_no) ++{ ++ switch (port_no) { ++ case CASE_NUM1: ++ bsp_sata0_rx0_reset(crg_base); ++ break; ++ case CASE_NUM2: ++ bsp_sata0_rx0_reset(crg_base); ++ bsp_sata1_rx1_reset(crg_base); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void bsp_sata_rx_unreset(void *crg_base, unsigned int port_no) ++{ ++ switch (port_no) { ++ case CASE_NUM1: ++ bsp_sata0_rx0_unreset(crg_base); ++ break; ++ case CASE_NUM2: ++ bsp_sata0_rx0_unreset(crg_base); ++ bsp_sata1_rx1_unreset(crg_base); ++ break; ++ default: ++ break; ++ } ++} ++ ++void bsp_sata_reset_rxtx_assert(unsigned int port_no) ++{ ++ void *crg_base = NULL; ++ void *comb_phy_crg_base = NULL; ++ unsigned int reg_val; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ iounmap(comb_phy_crg_base); ++ return; ++ } ++ ++ switch (port_no) { ++ case CASE_NUM0: ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++ ++ reg_val = readl(comb_phy_crg_base + 0x20); ++ reg_val |= COMB_PHY_REST; ++ writel(reg_val, comb_phy_crg_base + 0x20); ++ break; ++ case CASE_NUM1: ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++ ++ reg_val = readl(comb_phy_crg_base); ++ reg_val |= COMB_PHY_REST; ++ writel(reg_val, comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(crg_base); ++ iounmap(comb_phy_crg_base); ++} ++EXPORT_SYMBOL(bsp_sata_reset_rxtx_assert); ++ ++void bsp_sata_reset_rxtx_deassert(unsigned int port_no) ++{ ++ void *crg_base = NULL; ++ void *comb_phy_crg_base = NULL; ++ unsigned int reg_val; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ iounmap(comb_phy_crg_base); ++ return; ++ } ++ ++ switch (port_no) { ++ case CASE_NUM0: ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x20); ++ ++ reg_val = readl(comb_phy_crg_base + 0x20); ++ reg_val &= ~(COMB_PHY_REST); ++ writel(reg_val, comb_phy_crg_base + 0x20); ++ break; ++ case CASE_NUM1: ++ reg_val = readl(crg_base + 0x40); ++ reg_val &= ~(SATA_CTRL_RX_RST | SATA_CTRL_SATA_RST); ++ writel(reg_val, crg_base + 0x40); ++ ++ reg_val = readl(comb_phy_crg_base); ++ reg_val &= ~(COMB_PHY_REST); ++ writel(reg_val, comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ iounmap(crg_base); ++ iounmap(comb_phy_crg_base); ++ udelay(100); /* delay 100 us */ ++} ++EXPORT_SYMBOL(bsp_sata_reset_rxtx_deassert); ++ ++static void bsp_sata_reset(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val |= BSP_SATA_CKO_ALIVE_SRST_REQ; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val |= BSP_SATA_BUS_SRST_REQ; ++ writel(reg_val, crg_base + 0x8); ++ ++ bsp_sata_rx_reset(crg_base, ports_num); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_unreset(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ bsp_sata_rx_unreset(crg_base, ports_num); ++ ++ reg_val = readl(crg_base); ++ reg_val &= ~BSP_SATA_CKO_ALIVE_SRST_REQ; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val &= ~BSP_SATA_BUS_SRST_REQ; ++ writel(reg_val, crg_base + 0x8); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_phy1_portb_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_phy1_portb_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_phy1_porta_reset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val |= (COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy1_porta_unreset(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val &= ~(COMB_PHY_REST | COMB_PHY_TEST_REST); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy_reset(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_reset(comb_phy_crg_base); ++ break; ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_reset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_reset(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++static void bsp_sata_phy_unreset(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_unreset(comb_phy_crg_base); ++ break; ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_unreset(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_unreset(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++static void bsp_sata_tx0_rx0_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_tx1_rx1_clk_enable(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x40); ++ reg_val |= (SATA_CTRL_RX_CKEN | SATA_CTRL_TX_CKEN); ++ writel(reg_val, crg_base + 0x40); ++} ++ ++static void bsp_sata_clk_enable(void) ++{ ++ unsigned int reg_val; ++ void *crg_base = NULL; ++ ++ crg_base = ioremap((BSP_CRG_REG_BASE + SATA_CLK_RST_CTRL_1_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!crg_base) { ++ pr_err("ioremap sata reset register base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ bsp_sata_tx0_rx0_clk_enable(crg_base); ++ break; ++ case CASE_NUM2: ++ bsp_sata_tx0_rx0_clk_enable(crg_base); ++ bsp_sata_tx1_rx1_clk_enable(crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ reg_val = readl(crg_base); ++ reg_val |= BSP_SATA_CKO_CKEN; ++ writel(reg_val, crg_base); ++ ++ reg_val = readl(crg_base + 0x8); ++ reg_val |= BSP_SATA_BUS_CKEN; ++ writel(reg_val, crg_base + 0x8); ++ ++ iounmap(crg_base); ++} ++ ++static void bsp_sata_clk_disable(void) ++{ ++} ++ ++static void bsp_sata_clk_reset(void) ++{ ++} ++ ++static void bsp_sata_phy1_portb_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base + 0x20); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base + 0x20); ++} ++ ++static void bsp_sata_phy1_porta_clk_sel(void *crg_base) ++{ ++ unsigned int reg_val; ++ ++ reg_val = readl(crg_base); ++ reg_val |= COMB_PHY_REF_CLKEN; ++ reg_val = com_phy_ref_clksel_100m(reg_val); ++ writel(reg_val, crg_base); ++} ++ ++static void bsp_sata_phy_clk_sel(void) ++{ ++ void *comb_phy_crg_base = NULL; ++ ++ comb_phy_crg_base = ioremap((BSP_CRG_REG_BASE + COMB_PHY1_PORT_A_REG), ++ SATA_CRG_MAP_SIZE); ++ if (!comb_phy_crg_base) { ++ pr_err("ioremap comb phy crg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_clk_sel(comb_phy_crg_base); ++ break; ++ case CASE_NUM2: ++ /* COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_clk_sel(comb_phy_crg_base); ++ ++ /* COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_clk_sel(comb_phy_crg_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(comb_phy_crg_base); ++} ++ ++void bsp_sata_set_fifoth(void *mmio) ++{ ++ unsigned int port_idx; ++ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) ++ writel(FIFOTH_VALUE, (mmio + 0x100 + port_idx * 0x80 + PORT_FIFOTH)); ++} ++EXPORT_SYMBOL(bsp_sata_set_fifoth); ++ ++static void bsp_sata_phy1_portb_config(void *misc_base) ++{ ++ writel(0x88200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x88201, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x88200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x19100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x19101, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x19100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xC08C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC08C01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC08C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xd88d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd88d01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd88d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++} ++ ++static void bsp_sata_phy1_porta_config(void *misc_base) ++{ ++ writel(0x80200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x80201, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x80200, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0x11100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x11101, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x11100, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xC00C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC00C01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xC00C00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ ++ writel(0xd80d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd80d01, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0xd80d00, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++ writel(0x0, misc_base + BSP_COMB_PHY1_TEST_CTRL); ++} ++ ++static void bsp_sata_port_cfg(void) ++{ ++ void *misc_base = NULL; ++ ++ misc_base = ioremap(BSP_MISC_REG_BASE, BSP_MISC_REG_MAP_SIZE); ++ if (!misc_base) { ++ pr_err("ioremap misc reg failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_config(misc_base); ++ break; ++ case CASE_NUM2: ++ /* cfg COMBPHY1 PORT B */ ++ bsp_sata_phy1_portb_config(misc_base); ++ ++ /* cfg COMBPHY1 PORT A */ ++ bsp_sata_phy1_porta_config(misc_base); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(misc_base); ++} ++ ++#define IOCONFIG1_REG_BASE 0x10ff0000 ++#define IOCONFIG1_REG_MAP_SIZE 0x80 ++static void bsp_sata_set_led(void) ++{ ++ void *reg_addr = NULL; ++ unsigned int port_idx; ++ ++ reg_addr = ioremap(IOCONFIG1_REG_BASE, IOCONFIG1_REG_MAP_SIZE); ++ if (reg_addr == NULL) { ++ pr_err("ioremap ioconfg1 register addr for sata failed! func:%s, line:%d\n", ++ __func__, __LINE__); ++ return; ++ } ++ ++ /* Set SATA_LED_N */ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ if (port_idx == 0) ++ writel(0x1201, reg_addr + 0x48); ++ else ++ writel(0x1201, reg_addr + 0x4c); ++ } ++ ++ iounmap(reg_addr); ++} ++ ++static void bsp_sata_phy_config(void *mmio, int phy_mode) ++{ ++ unsigned int phy_config = PHY_SG_6G; ++ unsigned int port_idx; ++ unsigned int val; ++ void *misc_base = NULL; ++ ++ bsp_sata_set_fifoth(mmio); ++ ++ /* Set SATA_LED_N */ ++ bsp_sata_set_led(); ++ ++ /* set phy PX TX amplitude */ ++ /* set phy PX TX pre-emphasis */ ++ for (port_idx = 0; port_idx < ports_num; port_idx++) { ++ writel(PX_TX_PREEMPH, (mmio + 0x100 + port_idx * 0x80 + ++ BSP_SATA_PORT_PHYCTL2)); ++ writel(PX_TX_AMPLITUDE, (mmio + 0x100 + port_idx * 0x80 + ++ BSP_SATA_PORT_PHYCTL1)); ++ writel(phy_config, (mmio + 0x100 + port_idx * 0x80 + BSP_SATA_PORT_PHYCTL3)); ++ } ++ ++ misc_base = ioremap(BSP_MISC_REG_BASE, BSP_MISC_REG_MAP_SIZE); ++ if (!misc_base) { ++ pr_err("ioremap misc reg failed! func:%s, line:%d\n", __func__, __LINE__); ++ return; ++ } ++ ++ switch (ports_num) { ++ case CASE_NUM1: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ break; ++ case CASE_NUM2: ++ val = readl(misc_base + SATA_PHY_CTRL0); ++ val |= P0_PHY_SERDES_ARCH | P1_PHY_SERDES_ARCH; ++ writel(val, misc_base + SATA_PHY_CTRL0); ++ break; ++ default: ++ break; ++ } ++ ++ iounmap(misc_base); ++ bsp_sata_port_cfg(); ++} ++ ++unsigned int bsp_sata_get_port_info(void) ++{ ++ unsigned int ups_mode; ++ unsigned int reg_val; ++ unsigned int sata_port_num; ++ void *sysctrl_reg_base = NULL; ++ ++ sysctrl_reg_base = ioremap(BSP_SYS_CTRL_REG_BASE, BSP_SYS_CTRL_REG_MAP_SIZE); ++ if (!sysctrl_reg_base) { ++ pr_err("ioremap sysctrl reg base failed! func:%s, line:%d\n", __func__, ++ __LINE__); ++ return 0; ++ } ++ ++ reg_val = readl(sysctrl_reg_base + BSP_SYS_STAT_REG); ++ ups_mode = get_ups_mode_val(reg_val); ++ switch (ups_mode) { ++ case CASE_NUM1: ++ sata_port_num = 1; ++ sata_port_map = 0x1; ++ break; ++ case CASE_NUM2: ++ sata_port_num = 2; /* 2 sata_port_num */ ++ sata_port_map = 0x3; ++ break; ++ default: ++ sata_port_num = 0; ++ sata_port_map = 0; ++ break; ++ } ++ ++ return sata_port_num; ++} +diff --git a/drivers/phy/vendor/usb/Kconfig b/drivers/phy/vendor/usb/Kconfig +new file mode 100644 +index 000000000000..ab924dabc42f +--- /dev/null ++++ b/drivers/phy/vendor/usb/Kconfig +@@ -0,0 +1,88 @@ ++# ++# Phy drivers for Vendor platforms ++# ++config PHY_BSP_USB2 ++ bool ++ depends on (!ARCH_SS919V100 && !ARCH_SS015V100 && !ARCH_SS101V200 && \ ++ !ARCH_SS101V500 && !ARCH_SS101V300 && !ARCH_SS101V600 && \ ++ !ARCH_SS928V100 && !ARCH_SS927V100) ++ default y ++ help ++ Support for PHY on Vendor Socs. This Phy supports ++ USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It suppots one ++ USB host port to accept one USB device. Support init the phy ++ and adjust phy Eye Diagram. ++ ++config PHY_BSP_USB3 ++ bool ++ depends on (ARCH_SS918V100 || ARCH_SS318V100 || ARCH_SS919V100 || \ ++ ARCH_SS015V100 || ARCH_SS013V100 || ARCH_SS528V100 || \ ++ ARCH_SS625V100 || ARCH_SS928V100 || ARCH_SS927V100) ++ default y ++ help ++ Support for PHY on Vendor Socs. This Phy supports ++ USB3.0 and Compatible with USB2.0. It suppots one ++ USB host port to accept one USB device. Support init the phy ++ and adjust phy Eye Diagram. ++ ++config BSP_USB_PHY ++ bool "Vendor USB PHY driver" ++ depends on (!ARCH_SS101V200 && !ARCH_SS101V500 && !ARCH_SS101V300 && \ ++ !ARCH_SS101V600) ++ default y ++ help ++ Support for PHY on Vendor Socs. This Phy supports ++ USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It suppots one ++ USB host port to accept one USB device. Support init the phy ++ and adjust phy Eye Diagram. ++ ++config PHY_BSP_XVP_USB2 ++ tristate "Vendor XVP USB2 PHY Driver" ++ depends on (ARCH_SS101V200 || ARCH_SS101V500 || ARCH_SS101V300 || \ ++ ARCH_SS101V600) ++ select GENERIC_PHY ++ default y ++ help ++ Support for PHY on Vendor Socs. This Phy supports ++ USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It suppots one ++ USB host port to accept one USB device. Support init the phy ++ and adjust phy Eye Diagram. ++ ++menuconfig USB_MODE_OPTION ++ bool "Vendor USB related configuration" ++ depends on (!ARCH_SS101V200 && !ARCH_SS101V500 && !ARCH_SS101V300 && \ ++ !ARCH_SS101V600 && !ARCH_SS528V100 && !ARCH_SS625V100 && \ ++ !ARCH_SS524V100 && !ARCH_SS522V100 && !ARCH_SS615V100 && \ ++ !ARCH_SS522V101) ++ ++if USB_MODE_OPTION ++ ++config USB_DRD0_IN_HOST ++ bool "USB DRD0 Mode Select HOST" ++ help ++ Select whether the USB drd0 is working in host mode. ++ ++config USB_DRD0_IN_DEVICE ++ bool "USB DRD0 Mode Select DEVICE" ++ depends on !USB_DRD0_IN_HOST ++ depends on (!ARCH_SS528V100 && !ARCH_SS625V100 && !ARCH_SS524V100 && \ ++ !ARCH_SS522V100 && !ARCH_SS615V100 && !ARCH_SS522V101) ++ help ++ Select whether the USB drd0 is working in device mode. ++ ++config USB_DRD1_IN_HOST ++ bool "USB DRD1 Mode Select HOST" ++ depends on (ARCH_SS918V100 || ARCH_SS318V100 || ARCH_SS919V100 || \ ++ ARCH_SS015V100 || ARCH_SS013V100) ++ help ++ Select whether the USB drd1 is working in host mode. ++ ++config USB_DRD1_IN_DEVICE ++ bool "USB DRD1 Mode Select DEVICE" ++ depends on (!USB_DRD1_IN_HOST && !USB_DRD0_IN_DEVICE) ++ depends on (ARCH_SS918V100 || ARCH_SS318V100 || ARCH_SS919V100 || \ ++ ARCH_SS015V100 || ARCH_SS013V100) ++ help ++ Select whether the USB drd1 is working in device mode. ++ ++endif # USB_MODE_OPTION +diff --git a/drivers/phy/vendor/usb/Makefile b/drivers/phy/vendor/usb/Makefile +new file mode 100644 +index 000000000000..f0526a281da6 +--- /dev/null ++++ b/drivers/phy/vendor/usb/Makefile +@@ -0,0 +1,21 @@ ++obj-$(CONFIG_BSP_USB_PHY) += phy-bsp-usb.o ++obj-$(CONFIG_ARCH_SS528V100) += phy-ss528v100-usb.o ++obj-$(CONFIG_ARCH_SS625V100) += phy-ss528v100-usb.o ++obj-$(CONFIG_ARCH_SS524V100) += phy-ss524v100-usb.o ++obj-$(CONFIG_ARCH_SS522V100) += phy-ss524v100-usb.o ++obj-$(CONFIG_ARCH_SS522V101) += phy-ss524v100-usb.o ++obj-$(CONFIG_ARCH_SS615V100) += phy-ss524v100-usb.o ++obj-$(CONFIG_ARCH_SS919V100) += phy-ss919v100-usb.o ++obj-$(CONFIG_ARCH_SS015V100) += phy-ss919v100-usb.o ++obj-$(CONFIG_ARCH_SS318V100) += phy-ss318v100-usb.o ++obj-$(CONFIG_ARCH_SS918V100) += phy-ss918v100-usb.o ++obj-$(CONFIG_ARCH_SS013V100) += phy-ss918v100-usb.o ++obj-$(CONFIG_ARCH_SS812V100) += phy-ss812v100-usb.o ++obj-$(CONFIG_ARCH_SS813V100) += phy-ss813v100-usb.o ++obj-$(CONFIG_ARCH_SS313V100) += phy-ss313v100-usb.o ++obj-$(CONFIG_ARCH_SS011V100) += phy-ss313v100-usb.o ++obj-$(CONFIG_ARCH_SS012V100) += phy-ss313v100-usb.o ++obj-$(CONFIG_ARCH_SS312V100) += phy-ss312v100-usb.o ++obj-$(CONFIG_ARCH_SS928V100) += phy-ss928v100-usb.o ++obj-$(CONFIG_ARCH_SS927V100) += phy-ss928v100-usb.o ++obj-$(CONFIG_PHY_BSP_XVP_USB2) += phy-xvp-bsp-usb.o +diff --git a/drivers/phy/vendor/usb/phy-bsp-usb.c b/drivers/phy/vendor/usb/phy-bsp-usb.c +new file mode 100644 +index 000000000000..d421251ba35d +--- /dev/null ++++ b/drivers/phy/vendor/usb/phy-bsp-usb.c +@@ -0,0 +1,142 @@ ++/* ++* ++* Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include "phy-bsp-usb.h" ++#include ++#include ++#include ++ ++static int bsp_usb_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct phy *phy = NULL; ++ struct bsp_priv *priv = NULL; ++ struct device_node *np = pdev->dev.of_node; ++ if (np == NULL) ++ return -EINVAL; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (priv == NULL) ++ return -ENOMEM; ++ ++ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); ++ if (phy == NULL) { ++ devm_kfree(dev, priv); ++ return -ENOMEM; ++ } ++ ++ priv->peri_crg = of_iomap(np, CRG_NODE_IDX); ++ if (IS_ERR(priv->peri_crg)) ++ priv->peri_crg = NULL; ++ ++ priv->misc_ctrl = of_iomap(np, MISC_NODE_IDX); ++ if (IS_ERR(priv->misc_ctrl)) ++ priv->misc_ctrl = NULL; ++ ++ priv->sys_ctrl = of_iomap(np, SYS_NODE_IDX); ++ if (IS_ERR(priv->sys_ctrl)) ++ priv->sys_ctrl = NULL; ++ ++ priv->ctrl_base = of_iomap(np, CTRL_NODE_IDX); ++ if (IS_ERR(priv->ctrl_base)) ++ priv->ctrl_base = NULL; ++#if defined(CONFIG_ARCH_SS919V100) || defined(CONFIG_ARCH_SS015V100) ++ if (of_property_read_u32(np, "phyid", &priv->phyid)) ++ return -EINVAL; ++#endif ++ platform_set_drvdata(pdev, phy); ++ phy_set_drvdata(phy, priv); ++ ++#ifdef CONFIG_PHY_BSP_USB2 ++ bsp_usb_phy_on(phy); ++#endif ++#ifdef CONFIG_PHY_BSP_USB3 ++ bsp_usb3_phy_on(phy); ++#endif ++ iounmap(priv->peri_crg); ++ iounmap(priv->misc_ctrl); ++ iounmap(priv->sys_ctrl); ++#if defined(CONFIG_ARCH_SS919V100) || defined(CONFIG_ARCH_SS015V100) ++ iounmap(priv->ctrl_base); ++#endif ++ ++ return 0; ++} ++ ++static int bsp_usb_phy_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct phy *phy = dev_get_drvdata(&pdev->dev); ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++#ifdef CONFIG_PHY_BSP_USB2 ++ bsp_usb_phy_off(phy); ++#endif ++#ifdef CONFIG_PHY_BSP_USB3 ++ bsp_usb3_phy_off(phy); ++#endif ++ devm_kfree(dev, priv); ++ devm_kfree(dev, phy); ++ ++ return 0; ++} ++ ++static const struct of_device_id bsp_usb_phy_of_match[] = { ++ { .compatible = "vendor,usb-phy", }, ++ { .compatible = "vendor,usb3-phy_0", }, ++ { .compatible = "vendor,usb3-phy_1", }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, bsp_usb_phy_of_match); ++ ++#ifdef CONFIG_PM_SLEEP ++static int bsp_usb_phy_suspend(struct device *dev) ++{ ++ struct phy *phy = dev_get_drvdata(dev); ++#ifdef CONFIG_PHY_BSP_USB2 ++ bsp_usb_phy_off(phy); ++#endif ++#ifdef CONFIG_PHY_BSP_USB3 ++ bsp_usb3_phy_off(phy); ++#endif ++ return 0; ++} ++ ++static int bsp_usb_phy_resume(struct device *dev) ++{ ++ struct phy *phy = dev_get_drvdata(dev); ++#ifdef CONFIG_PHY_BSP_USB2 ++ bsp_usb_phy_on(phy); ++#endif ++#ifdef CONFIG_PHY_BSP_USB3 ++ bsp_usb3_phy_on(phy); ++#endif ++ return 0; ++} ++#endif /* CONFIG_PM_SLEEP */ ++ ++static SIMPLE_DEV_PM_OPS(bsp_usb_pm_ops, bsp_usb_phy_suspend, ++ bsp_usb_phy_resume); ++ ++static struct platform_driver bsp_usb_phy_driver = { ++ .probe = bsp_usb_phy_probe, ++ .remove = bsp_usb_phy_remove, ++ .driver = { ++ .name = "bsp-usb-phy", ++ .pm = &bsp_usb_pm_ops, ++ .of_match_table = bsp_usb_phy_of_match, ++ } ++}; ++module_platform_driver(bsp_usb_phy_driver); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/phy/vendor/usb/phy-bsp-usb.h b/drivers/phy/vendor/usb/phy-bsp-usb.h +new file mode 100644 +index 000000000000..a5075771c76e +--- /dev/null ++++ b/drivers/phy/vendor/usb/phy-bsp-usb.h +@@ -0,0 +1,66 @@ ++/* ++* ++* Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef USB2_INCLUDE_PHY_H ++#define USB2_INCLUDE_PHY_H ++ ++#include ++extern void bsp_usb_phy_on(struct phy *phy); ++extern void bsp_usb_phy_off(struct phy *phy); ++extern void bsp_usb3_phy_on(struct phy *phy); ++extern void bsp_usb3_phy_off(struct phy *phy); ++ ++struct bsp_priv { ++ void __iomem *peri_crg; ++ void __iomem *misc_ctrl; ++ void __iomem *sys_ctrl; ++ void __iomem *ctrl_base; ++ unsigned int phyid; ++}; ++ ++typedef enum mode { ++ PCIE_X2 = 0, ++ PCIE_X1, ++ USB3 ++} combphy_mode; ++ ++#define U_LEVEL1 10 ++#define U_LEVEL2 20 ++#define U_LEVEL3 30 ++#define U_LEVEL4 50 ++#define U_LEVEL5 100 ++#define U_LEVEL6 200 ++#define U_LEVEL7 300 ++#define U_LEVEL8 500 ++ ++#define M_LEVEL1 2 ++#define M_LEVEL2 5 ++#define M_LEVEL3 10 ++#define M_LEVEL4 20 ++#define M_LEVEL5 50 ++#define M_LEVEL6 100 ++#define M_LEVEL7 200 ++ ++#define __1K__ 0x400 ++#define __2K__ 0x800 ++#define __4K__ 0x1000 ++#define __8K__ 0x2000 ++#define __64K__ 0x10000 ++ ++#define CRG_NODE_IDX 0 ++#define MISC_NODE_IDX 1 ++#define SYS_NODE_IDX 2 ++#define CTRL_NODE_IDX 3 ++ ++#endif /* USB2_INCLUDE_PHY_H */ +diff --git a/drivers/phy/vendor/usb/phy-ss524v100-usb.c b/drivers/phy/vendor/usb/phy-ss524v100-usb.c +new file mode 100644 +index 000000000000..57524691eca4 +--- /dev/null ++++ b/drivers/phy/vendor/usb/phy-ss524v100-usb.c +@@ -0,0 +1,449 @@ ++/* ++* ++* Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include "phy-bsp-usb.h" ++ ++#define PERI_CRG3632 0x0 ++#define DEF_VAL_3632 0x10331 ++#define USB2_0_SRST_REQ (0x1 << 0) ++#define USB2_0_BUS_CKEN (0x1 << 4) ++#define USB2_0_REF_CKEN (0x1 << 5) ++#define USB2_0_UTMI_CKEN (0x1 << 8) ++#define USB2_2_UTMI_CKEN (0x1 << 9) ++#define USB2_0_FREECLK_CKSEL (0x1 << 16) ++ ++#define PERI_CRG3636 0x10 ++#define DEF_VAL_3636 0x153 ++#define USB2_PHY0_REQ (0x1 << 0) ++#define USB2_PHY0_TREQ (0x1 << 1) ++#define USB2_PHY0_APB_SRST_REQ (0x1 << 2) ++#define USB2_PHY0_XTAL_CKEN (0x1 << 4) ++ ++#define PERI_CRG3640 0x20 ++#define DEF_VAL_3640 0x10131 ++#define USB2_1_SRST_REQ (0x1 << 0) ++#define USB2_1_BUS_CKEN (0x1 << 4) ++#define USB2_1_REF_CKEN (0x1 << 5) ++#define USB2_1_UTMI_CKEN (0x1 << 8) ++ ++#define PERI_CRG3644 0x30 ++#define DEF_VAL_3644 0x153 ++#define USB2_PHY1_REQ (0x1 << 0) ++#define USB2_PHY1_TREQ (0x1 << 1) ++#define USB2_PHY1_APB_SRST_REQ (0x1 << 2) ++#define USB2_PHY1_XTAL_CKEN (0x1 << 4) ++ ++#define PERI_CRG3672 0xa0 ++#define DEF_VAL_3672 0x153 ++#define USB2_PHY2_REQ (0x1 << 0) ++#define USB2_PHY2_TREQ (0x1 << 1) ++#define USB2_PHY2_APB_SRST_REQ (0x1 << 2) ++#define USB2_PHY2_XTAL_CKEN (0x1 << 4) ++ ++#define USB_CTRL_BASE 0x10300000 ++#define USB2_PHY2_BASE 0x10310000 ++#define USB2_PHY1_BASE 0x10350000 ++#define USB2_PHY0_BASE 0x10330000 ++ ++#define GUSB2PHYCFG 0xc204 ++#define U2_FREECLK_EXISTS (0x1 << 30) ++ ++#define PHY_PLL_ENABLE (0x3 << 0) ++#define PHY_PLL_OFFSET 0x14 ++ ++#define RG_HSTX_MBIAS 0x0 ++#define RG_HSTX_MBIAS_MASK (0xf << 0) ++#define RG_HSTX_MBIAS_VAL (0xb << 0) ++#define RG_HSTX_DEEN (0x1 << 5) ++#define RG_HSTX_DE (0x4 << 8) ++ ++#define TX_TEST_BIT 0x8 ++#define TX_TEST_BIT_VAL (0x3 << 20) ++ ++#define DISC_REF_VOL_SEL 0x8 ++#define DISC_REF_VOL_SEL_MASK (0x7 << 16) ++#define DISC_REF_VOL_SEL_VAL (0x5 << 16) ++ ++#define SLEW_RATE_OPTION 0xc ++#define SLEW_RATE_OPTION_MASK (0x3 << 20) ++#define SLEW_RATE_OPTION_VAL (0x1 << 20) ++ ++#define TX_REF_VOL_SEL 0x10 ++#define TX_REF_VOL_SEL_MASK (0x7 << 4) ++#define TX_REF_VOL_SEL_VAL (0x6 << 4) ++ ++#define RG_FL_EDGE_MODE 0x10 ++#define RG_FL_EDGE_MODE_VAL (0x1 << 13) ++ ++#define U2_TRIM_VAL_MIN 0x09 ++#define U2_TRIM_VAL_MAX 0x1d ++#define RT_TRIM_VAL_MASK 0x1f ++#define usb2_2_trim_val(p) (((p) >> 10) & RT_TRIM_VAL_MASK) ++#define usb2_1_trim_val(p) (((p) >> 5) & RT_TRIM_VAL_MASK) ++#define usb2_0_trim_val(p) (((p) >> 0) & RT_TRIM_VAL_MASK) ++ ++#define U2_ANA_CFG2 0x8 ++#define usb2_rt_trim_clr(p) ((p) & (~(RT_TRIM_VAL_MASK << 8))) ++#define usb2_rt_trim_set(p) ((p) << 8) ++ ++void bsp_usb_def_config(struct phy *phy) ++{ ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* default value rewrite */ ++ writel(DEF_VAL_3632, priv->peri_crg + PERI_CRG3632); ++ writel(DEF_VAL_3636, priv->peri_crg + PERI_CRG3636); ++ writel(DEF_VAL_3640, priv->peri_crg + PERI_CRG3640); ++ writel(DEF_VAL_3644, priv->peri_crg + PERI_CRG3644); ++ writel(DEF_VAL_3672, priv->peri_crg + PERI_CRG3672); ++ udelay(U_LEVEL6); ++} ++ ++void bsp_usb2_phy0_config(struct phy *phy) ++{ ++ unsigned int reg; ++ unsigned int trim_val; ++ void __iomem *usb2_phy0 = NULL; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ usb2_phy0 = ioremap(USB2_PHY0_BASE, __64K__); ++ if (usb2_phy0 == NULL) ++ return; ++ ++ /* OTP usb2 phy0 */ ++ trim_val = readl(priv->sys_ctrl); ++ trim_val = usb2_0_trim_val(trim_val); ++ if ((trim_val >= U2_TRIM_VAL_MIN) && (trim_val <= U2_TRIM_VAL_MAX)) { ++ reg = readl(usb2_phy0 + U2_ANA_CFG2); ++ reg = usb2_rt_trim_clr(reg); ++ reg |= usb2_rt_trim_set(trim_val); ++ writel(reg, usb2_phy0 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ } ++ ++ /* usb2 phy0 pll enable */ ++ reg = readl(usb2_phy0 + PHY_PLL_OFFSET); ++ reg |= PHY_PLL_ENABLE; ++ writel(reg, usb2_phy0 + PHY_PLL_OFFSET); ++ udelay(U_LEVEL5); ++ ++ /* rg_hstx_mbias: 4'b0011==>4'b1011 */ ++ reg = readl(usb2_phy0 + RG_HSTX_MBIAS); ++ reg &= ~RG_HSTX_MBIAS_MASK; ++ reg |= (RG_HSTX_MBIAS_VAL | RG_HSTX_DEEN | RG_HSTX_DE); ++ writel(reg, usb2_phy0 + RG_HSTX_MBIAS); ++ udelay(U_LEVEL5); ++ ++ /* TX TEST bit Chirp KJ: 1'b0==>1'b1 */ ++ reg = readl(usb2_phy0 + TX_TEST_BIT); ++ reg |= TX_TEST_BIT_VAL; ++ writel(reg, usb2_phy0 + TX_TEST_BIT); ++ udelay(U_LEVEL5); ++ ++ /* disconnect reference voltage sel: 3'b001==>3'b011 */ ++ reg = readl(usb2_phy0 + DISC_REF_VOL_SEL); ++ reg &= ~DISC_REF_VOL_SEL_MASK; ++ reg |= DISC_REF_VOL_SEL_VAL; ++ writel(reg, usb2_phy0 + DISC_REF_VOL_SEL); ++ udelay(U_LEVEL5); ++ ++ /* slew rate option: 2b'00==>2b'01 */ ++ reg = readl(usb2_phy0 + SLEW_RATE_OPTION); ++ reg &= ~SLEW_RATE_OPTION_MASK; ++ reg |= SLEW_RATE_OPTION_VAL; ++ writel(reg, usb2_phy0 + SLEW_RATE_OPTION); ++ udelay(U_LEVEL5); ++ ++ /* TX reference voltage sel: 4'100==>4'110 */ ++ reg = readl(usb2_phy0 + TX_REF_VOL_SEL); ++ reg &= ~TX_REF_VOL_SEL_MASK; ++ reg |= TX_REF_VOL_SEL_VAL; ++ writel(reg, usb2_phy0 + TX_REF_VOL_SEL); ++ udelay(U_LEVEL5); ++ ++ /* rg_fls_edge_mode: 1'b0==>1'b1 */ ++ reg = readl(usb2_phy0 + RG_FL_EDGE_MODE); ++ reg |= RG_FL_EDGE_MODE_VAL; ++ writel(reg, usb2_phy0 + RG_FL_EDGE_MODE); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy0); ++} ++ ++void bsp_usb2_phy1_config(struct phy *phy) ++{ ++ unsigned int reg; ++ unsigned int trim_val; ++ void __iomem *usb2_phy1 = NULL; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ usb2_phy1 = ioremap(USB2_PHY1_BASE, __64K__); ++ if (usb2_phy1 == NULL) ++ return; ++ ++ /* OTP usb2 phy1 */ ++ trim_val = readl(priv->sys_ctrl); ++ trim_val = usb2_1_trim_val(trim_val); ++ if ((trim_val >= U2_TRIM_VAL_MIN) && (trim_val <= U2_TRIM_VAL_MAX)) { ++ reg = readl(usb2_phy1 + U2_ANA_CFG2); ++ reg = usb2_rt_trim_clr(reg); ++ reg |= usb2_rt_trim_set(trim_val); ++ writel(reg, usb2_phy1 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ } ++ ++ /* usb2 phy1 pll enable */ ++ reg = readl(usb2_phy1 + PHY_PLL_OFFSET); ++ reg |= PHY_PLL_ENABLE; ++ writel(reg, usb2_phy1 + PHY_PLL_OFFSET); ++ udelay(U_LEVEL5); ++ ++ /* rg_hstx_mbias: 4'b0011==>4'b1011 */ ++ reg = readl(usb2_phy1 + RG_HSTX_MBIAS); ++ reg &= ~RG_HSTX_MBIAS_MASK; ++ reg |= (RG_HSTX_MBIAS_VAL | RG_HSTX_DEEN | RG_HSTX_DE); ++ writel(reg, usb2_phy1 + RG_HSTX_MBIAS); ++ udelay(U_LEVEL5); ++ ++ /* TX TEST bit Chirp KJ: 1'b0==>1'b1 */ ++ reg = readl(usb2_phy1 + TX_TEST_BIT); ++ reg |= TX_TEST_BIT_VAL; ++ writel(reg, usb2_phy1 + TX_TEST_BIT); ++ udelay(U_LEVEL5); ++ ++ /* disconnect reference voltage sel: 3'b001==>3'b011 */ ++ reg = readl(usb2_phy1 + DISC_REF_VOL_SEL); ++ reg &= ~DISC_REF_VOL_SEL_MASK; ++ reg |= DISC_REF_VOL_SEL_VAL; ++ writel(reg, usb2_phy1 + DISC_REF_VOL_SEL); ++ udelay(U_LEVEL5); ++ ++ /* slew rate option: 2b'00==>2b'01 */ ++ reg = readl(usb2_phy1 + SLEW_RATE_OPTION); ++ reg &= ~SLEW_RATE_OPTION_MASK; ++ reg |= SLEW_RATE_OPTION_VAL; ++ writel(reg, usb2_phy1 + SLEW_RATE_OPTION); ++ udelay(U_LEVEL5); ++ ++ /* TX reference voltage sel: 4'100==>4'110 */ ++ reg = readl(usb2_phy1 + TX_REF_VOL_SEL); ++ reg &= ~TX_REF_VOL_SEL_MASK; ++ reg |= TX_REF_VOL_SEL_VAL; ++ writel(reg, usb2_phy1 + TX_REF_VOL_SEL); ++ udelay(U_LEVEL5); ++ ++ /* rg_fls_edge_mode: 1'b0==>1'b1 */ ++ reg = readl(usb2_phy1 + RG_FL_EDGE_MODE); ++ reg |= RG_FL_EDGE_MODE_VAL; ++ writel(reg, usb2_phy1 + RG_FL_EDGE_MODE); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy1); ++} ++ ++void bsp_usb2_phy2_config(struct phy *phy) ++{ ++ unsigned int reg; ++ unsigned int trim_val; ++ void __iomem *usb2_phy2 = NULL; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ if (priv == NULL) ++ return; ++ ++ if (priv->sys_ctrl == NULL) ++ return; ++ ++ usb2_phy2 = ioremap(USB2_PHY2_BASE, __64K__); ++ if (usb2_phy2 == NULL) ++ return; ++ ++ /* OTP usb2 phy2 */ ++ trim_val = readl(priv->sys_ctrl); ++ trim_val = usb2_2_trim_val(trim_val); ++ if ((trim_val >= U2_TRIM_VAL_MIN) && (trim_val <= U2_TRIM_VAL_MAX)) { ++ reg = readl(usb2_phy2 + U2_ANA_CFG2); ++ reg = usb2_rt_trim_clr(reg); ++ reg |= usb2_rt_trim_set(trim_val); ++ writel(reg, usb2_phy2 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ } ++ ++ /* rg_hstx_mbias: 4'b0011==>4'b1011 */ ++ reg = readl(usb2_phy2 + RG_HSTX_MBIAS); ++ reg &= ~RG_HSTX_MBIAS_MASK; ++ reg |= (RG_HSTX_MBIAS_VAL | RG_HSTX_DEEN | RG_HSTX_DE); ++ writel(reg, usb2_phy2 + RG_HSTX_MBIAS); ++ udelay(U_LEVEL5); ++ ++ /* TX TEST bit Chirp KJ: 1'b0==>1'b1 */ ++ reg = readl(usb2_phy2 + TX_TEST_BIT); ++ reg |= TX_TEST_BIT_VAL; ++ writel(reg, usb2_phy2 + TX_TEST_BIT); ++ udelay(U_LEVEL5); ++ ++ /* disconnect reference voltage sel: 3'b001==>3'b011 */ ++ reg = readl(usb2_phy2 + DISC_REF_VOL_SEL); ++ reg &= ~DISC_REF_VOL_SEL_MASK; ++ reg |= DISC_REF_VOL_SEL_VAL; ++ writel(reg, usb2_phy2 + DISC_REF_VOL_SEL); ++ udelay(U_LEVEL5); ++ ++ /* slew rate option: 2b'00==>2b'01 */ ++ reg = readl(usb2_phy2 + SLEW_RATE_OPTION); ++ reg &= ~SLEW_RATE_OPTION_MASK; ++ reg |= SLEW_RATE_OPTION_VAL; ++ writel(reg, usb2_phy2 + SLEW_RATE_OPTION); ++ udelay(U_LEVEL5); ++ ++ /* TX reference voltage sel: 4'100==>4'110 */ ++ reg = readl(usb2_phy2 + TX_REF_VOL_SEL); ++ reg &= ~TX_REF_VOL_SEL_MASK; ++ reg |= TX_REF_VOL_SEL_VAL; ++ writel(reg, usb2_phy2 + TX_REF_VOL_SEL); ++ udelay(U_LEVEL5); ++ ++ /* rg_fls_edge_mode: 1'b0==>1'b1 */ ++ reg = readl(usb2_phy2 + RG_FL_EDGE_MODE); ++ reg |= RG_FL_EDGE_MODE_VAL; ++ writel(reg, usb2_phy2 + RG_FL_EDGE_MODE); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy2); ++ usb2_phy2 = NULL; ++} ++ ++void bsp_usb_ctrl_config(void) ++{ ++ unsigned int reg; ++ void __iomem *ctrl_base = NULL; ++ ++ ctrl_base = ioremap(USB_CTRL_BASE, __64K__); ++ if (ctrl_base == NULL) ++ return; ++ ++ reg = readl(ctrl_base + GUSB2PHYCFG); ++ reg &= ~U2_FREECLK_EXISTS; ++ writel(reg, ctrl_base + GUSB2PHYCFG); ++ udelay(U_LEVEL6); ++ ++ iounmap(ctrl_base); ++} ++ ++void bsp_usb2_0_config(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* open usb2 phy0 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3636); ++ reg |= USB2_PHY0_XTAL_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3636); ++ udelay(U_LEVEL6); ++ ++ /* open usb2 phy2 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3672); ++ reg |= USB2_PHY2_XTAL_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3672); ++ udelay(U_LEVEL6); ++ ++ /* cancel usb2 phy0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3636); ++ reg &= ~(USB2_PHY0_REQ | USB2_PHY0_TREQ | USB2_PHY0_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3636); ++ mdelay(M_LEVEL1); ++ ++ /* cancel usb2 phy2 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3672); ++ reg &= ~(USB2_PHY2_REQ | USB2_PHY2_TREQ | USB2_PHY2_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3672); ++ mdelay(M_LEVEL1); ++ ++ bsp_usb2_phy0_config(phy); ++ ++ bsp_usb2_phy2_config(phy); ++ ++ /* open pipe/suspend/ref/bus clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3632); ++ reg |= USB2_0_REF_CKEN; ++ reg |= USB2_0_BUS_CKEN; ++ reg |= USB2_0_UTMI_CKEN; ++ reg |= USB2_2_UTMI_CKEN; ++ reg |= USB2_0_FREECLK_CKSEL; ++ writel(reg, priv->peri_crg + PERI_CRG3632); ++ udelay(U_LEVEL6); ++ ++ /* cancel ctrl0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3632); ++ reg &= ~USB2_0_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3632); ++ udelay(U_LEVEL6); ++ ++ bsp_usb_ctrl_config(); ++} ++ ++void bsp_usb2_1_config(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ if (priv == NULL) ++ return; ++ ++ /* open usb2 phy1 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3644); ++ reg |= USB2_PHY1_XTAL_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3644); ++ udelay(U_LEVEL6); ++ ++ /* cancel usb2 phy1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3644); ++ reg &= ~(USB2_PHY1_REQ | USB2_PHY1_TREQ | USB2_PHY1_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3644); ++ mdelay(M_LEVEL1); ++ ++ bsp_usb2_phy1_config(phy); ++ ++ /* open utmi/ref/bus clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3640); ++ reg |= USB2_1_BUS_CKEN; ++ reg |= USB2_1_REF_CKEN; ++ reg |= USB2_1_UTMI_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3640); ++ udelay(U_LEVEL6); ++ ++ /* cancel ctrl1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3640); ++ reg &= ~USB2_1_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3640); ++ udelay(U_LEVEL6); ++} ++ ++void bsp_usb_phy_on(struct phy *phy) ++{ ++ bsp_usb_def_config(phy); ++ ++ bsp_usb2_0_config(phy); ++ ++ bsp_usb2_1_config(phy); ++} ++EXPORT_SYMBOL(bsp_usb_phy_on); ++ ++void bsp_usb_phy_off(struct phy *phy) ++{ ++ bsp_usb_def_config(phy); ++} ++EXPORT_SYMBOL(bsp_usb_phy_off); +diff --git a/drivers/phy/vendor/usb/phy-ss528v100-usb.c b/drivers/phy/vendor/usb/phy-ss528v100-usb.c +new file mode 100644 +index 000000000000..a55bbc774055 +--- /dev/null ++++ b/drivers/phy/vendor/usb/phy-ss528v100-usb.c +@@ -0,0 +1,584 @@ ++/* ++* ++* Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include "phy-bsp-usb.h" ++ ++#define PERI_CRG3632 0x0 ++#define USB2_0_UTMI_CKEN (0x1 << 8) ++ ++#define PERI_CRG3636 0x10 ++#define USB2_PHY0_REQ (0x1 << 0) ++#define USB2_PHY0_TREQ (0x1 << 1) ++#define USB2_PHY0_APB_SRST_REQ (0x1 << 2) ++#define USB2_PHY0_XTAL_CKEN (0x1 << 4) ++ ++#define PERI_CRG3640 0x20 ++#define USB2_1_SRST_REQ (0x1 << 0) ++#define USB2_1_BUS_CKEN (0x1 << 4) ++#define USB2_1_REF_CKEN (0x1 << 5) ++#define USB2_1_UTMI_CKEN (0x1 << 8) ++ ++#define PERI_CRG3644 0x30 ++#define USB2_PHY1_REQ (0x1 << 0) ++#define USB2_PHY1_TREQ (0x1 << 1) ++#define USB2_PHY1_APB_SRST_REQ (0x1 << 2) ++#define USB2_PHY1_XTAL_CKEN (0x1 << 4) ++ ++#define PERI_CRG3664 0x80 ++#define USB3_SRST_REQ (0x1 << 0) ++#define USB3_BUS_CKEN (0x1 << 4) ++#define USB3_REF_CKEN (0x1 << 5) ++#define USB3_SUSPEND_CKEN (0x1 << 6) ++#define USB3_UTMI_CKEN (0x1 << 8) ++#define USB3_PIPE_CKEN (0x1 << 12) ++ ++#define PERI_CRG3672 0xa0 ++#define USB2_PHY2_REQ (0x1 << 0) ++#define USB2_PHY2_TREQ (0x1 << 1) ++#define USB2_PHY2_APB_SRST_REQ (0x1 << 2) ++#define USB2_PHY2_XTAL_CKEN (0x1 << 4) ++ ++#define PERI_CRG3676 0xb0 ++#define COMBPHY0_SRST_REQ (0x1 << 0) ++#define COMBPHY0_TEST_SRST_REQ (0x1 << 1) ++#define COMBPHY0_REF_CKEN (0x1 << 4) ++ ++#define USB_CTRL6 0xc ++#define U3_PORT_DISABLE (0x1 << 12) ++ ++#define USB2_PHY2_BASE 0x10310000 ++#define USB2_PHY1_BASE 0x10350000 ++#define USB2_PHY0_BASE 0x10330000 ++ ++#define U2_ANA_CFG0 0x0 ++#define HSTX_MBIAS_MASK (0xf << 0) ++#define ana_cfg0_val(p) ((p) & (~HSTX_MBIAS_MASK)) ++#define U2_2_HSTX_MBIAS (0x3 << 0) ++#define U2_1_HSTX_MBIAS (0x3 << 0) ++#define U2_0_HSTX_MBIAS (0x3 << 0) ++ ++#define U2_2_HSTX_DEEN (0x1 << 5) ++#define U2_1_HSTX_DEEN (0x1 << 5) ++#define U2_0_HSTX_DEEN (0x1 << 5) ++ ++#define HSTX_DE_MASK (0xf << 8) ++#define U2_2_HSTX_DE (0x8 << 8) ++#define U2_1_HSTX_DE (0x8 << 8) ++#define U2_0_HSTX_DE (0x8 << 8) ++ ++#define U2_ANA_CFG2 0x8 ++#define VDISCREF_SEL_MASK (0x7 << 16) ++#define ana_cfg2_val(p) ((p) & (~VDISCREF_SEL_MASK)) ++#define U2_2_VDISCREF_SEL (0x6 << 16) ++#define U2_1_VDISCREF_SEL (0x6 << 16) ++#define U2_0_VDISCREF_SEL (0x6 << 16) ++#define U2_TEST_TX (0x1 << 20) ++#define U2_TEST_TX_HALT_DEEN (0x1 << 21) ++ ++#define U2_TRIM_VAL_MIN 0x09 ++#define U2_TRIM_VAL_MAX 0x1d ++#define RT_TRIM_VAL_MASK 0x1f ++#define usb2_2_trim_val(p) (((p) >> 10) & RT_TRIM_VAL_MASK) ++#define usb2_1_trim_val(p) (((p) >> 5) & RT_TRIM_VAL_MASK) ++#define usb2_0_trim_val(p) (((p) >> 0) & RT_TRIM_VAL_MASK) ++ ++#define usb2_rt_trim_clr(p) ((p) & (~(RT_TRIM_VAL_MASK << 8))) ++#define usb2_rt_trim_set(p) ((p) << 8) ++ ++#define U2_ANA_CFG3 0xc ++#define SLEW_RATE_OPT_MASK (0x3 << 20) ++#define ana_cfg3_val(p) ((p) & (~SLEW_RATE_OPT_MASK)) ++#define U2_2_SLEW_RATE_OPT (0x1 << 20) ++#define U2_1_SLEW_RATE_OPT (0x1 << 20) ++#define U2_0_SLEW_RATE_OPT (0x1 << 20) ++ ++#define U2_ANA_CFG4 0x10 ++#define VTXREF_SEL_MASK (0x7 << 4) ++#define ana_cfg4_val(p) ((p) & (~VTXREF_SEL_MASK)) ++#define U2_VTXREF_SEL (0x5 << 4) ++#define U2_FLS_EDGE_MODE (0x1 << 13) ++#define U2_VTXREF_SEL_U3P (0x6 << 4) ++ ++#define COMBPHY_CTRL0 0x40 ++#define PI_CURRENT_TRIM_ENABLE 0x11100 ++#define PI_CURRENT_TRIM_VAL 0x11101 ++#define TX_SWING_COMP_ENABLE 0xc1200 ++#define TX_SWING_COMP_VAL 0xc1201 ++ ++#define PHY_PLL_ENABLE (0x3 << 0) ++#define PHY_PLL_OFFSET 0x14 ++ ++static void bsp_usb2_phy1_eye_config(struct phy *phy) ++{ ++ unsigned int reg; ++ unsigned int trim_val; ++ void __iomem *usb2_phy1 = NULL; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ usb2_phy1 = ioremap(USB2_PHY1_BASE, __64K__); ++ if (usb2_phy1 == NULL) ++ return; ++ ++ /* adjust the hstx mbias deen de */ ++ reg = readl(usb2_phy1 + U2_ANA_CFG0); ++ reg = ana_cfg0_val(reg); ++ reg |= U2_1_HSTX_MBIAS; ++ reg |= U2_1_HSTX_DEEN; ++ reg &= ~HSTX_DE_MASK; ++ reg |= U2_1_HSTX_DE; ++ writel(reg, usb2_phy1 + U2_ANA_CFG0); ++ udelay(U_LEVEL5); ++ ++ /* vdiscref sel and test tx set */ ++ reg = readl(usb2_phy1 + U2_ANA_CFG2); ++ reg = ana_cfg2_val(reg); ++ reg |= U2_1_VDISCREF_SEL; ++ reg |= U2_TEST_TX; ++ reg |= U2_TEST_TX_HALT_DEEN; ++ writel(reg, usb2_phy1 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ ++ /* OTP usb2 phy1 */ ++ trim_val = readl(priv->sys_ctrl); ++ trim_val = usb2_1_trim_val(trim_val); ++ if ((trim_val >= U2_TRIM_VAL_MIN) && (trim_val <= U2_TRIM_VAL_MAX)) { ++ reg = readl(usb2_phy1 + U2_ANA_CFG2); ++ reg = usb2_rt_trim_clr(reg); ++ reg |= usb2_rt_trim_set(trim_val); ++ writel(reg, usb2_phy1 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ } ++ ++ /* ATOP TEST bit */ ++ reg = readl(usb2_phy1 + U2_ANA_CFG3); ++ reg = ana_cfg3_val(reg); ++ reg |= U2_1_SLEW_RATE_OPT; ++ writel(reg, usb2_phy1 + U2_ANA_CFG3); ++ udelay(U_LEVEL5); ++ ++ /* vtxref sel==>430mV, enable fls edge mode */ ++ reg = readl(usb2_phy1 + U2_ANA_CFG4); ++ reg = ana_cfg4_val(reg); ++ reg |= U2_VTXREF_SEL; ++ reg |= U2_FLS_EDGE_MODE; ++ writel(reg, usb2_phy1 + U2_ANA_CFG4); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy1); ++} ++ ++void bsp_usb2_phy1_config(struct phy *phy) ++{ ++ unsigned int reg; ++ void __iomem *usb2_phy1 = NULL; ++ ++ usb2_phy1 = ioremap(USB2_PHY1_BASE, __64K__); ++ if (usb2_phy1 == NULL) ++ return; ++ ++ /* usb2 phy1 pll enable */ ++ reg = readl(usb2_phy1 + PHY_PLL_OFFSET); ++ reg |= PHY_PLL_ENABLE; ++ writel(reg, usb2_phy1 + PHY_PLL_OFFSET); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy1); ++} ++ ++void bsp_usb_crg_config(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* ctrl1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3640); ++ reg |= USB2_1_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3640); ++ udelay(U_LEVEL6); ++ ++ /* usb2 phy1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3644); ++ reg |= (USB2_PHY1_REQ | USB2_PHY1_TREQ | USB2_PHY1_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3644); ++ udelay(U_LEVEL6); ++ ++ /* open usb2 phy1 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3644); ++ reg |= USB2_PHY1_XTAL_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3644); ++ udelay(U_LEVEL6); ++ ++ /* cancel usb2 phy1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3644); ++ reg &= ~(USB2_PHY1_REQ | USB2_PHY1_TREQ | USB2_PHY1_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3644); ++ mdelay(M_LEVEL1); ++ ++ /* open utmi/ref/bus clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3640); ++ reg |= USB2_1_BUS_CKEN; ++ reg |= USB2_1_REF_CKEN; ++ reg |= USB2_1_UTMI_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3640); ++ udelay(U_LEVEL6); ++ ++ /* cancel ctrl1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3640); ++ reg &= ~USB2_1_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3640); ++ udelay(U_LEVEL6); ++} ++ ++void bsp_usb_phy_on(struct phy *phy) ++{ ++ bsp_usb_crg_config(phy); ++ ++ bsp_usb2_phy1_config(phy); ++ ++ bsp_usb2_phy1_eye_config(phy); ++} ++EXPORT_SYMBOL(bsp_usb_phy_on); ++ ++void bsp_usb_phy_off(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* ctrl1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3640); ++ reg |= USB2_1_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3640); ++ udelay(U_LEVEL6); ++ ++ /* usb2 phy1 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3644); ++ reg |= (USB2_PHY1_REQ | USB2_PHY1_TREQ | USB2_PHY1_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3644); ++ udelay(U_LEVEL6); ++} ++EXPORT_SYMBOL(bsp_usb_phy_off); ++ ++static void bsp_usb2_phy0_eye_config(struct phy *phy) ++{ ++ unsigned int reg; ++ unsigned int trim_val; ++ void __iomem *usb2_phy0 = NULL; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ usb2_phy0 = ioremap(USB2_PHY0_BASE, __64K__); ++ if (usb2_phy0 == NULL) ++ return; ++ ++ /* adjust the hstx mbias deen DE */ ++ reg = readl(usb2_phy0 + U2_ANA_CFG0); ++ reg = ana_cfg0_val(reg); ++ reg |= U2_0_HSTX_MBIAS; ++ reg |= U2_0_HSTX_DEEN; ++ reg &= ~HSTX_DE_MASK; ++ reg |= U2_0_HSTX_DE; ++ writel(reg, usb2_phy0 + U2_ANA_CFG0); ++ udelay(U_LEVEL5); ++ ++ /* vdiscref sel and test tx set */ ++ reg = readl(usb2_phy0 + U2_ANA_CFG2); ++ reg = ana_cfg2_val(reg); ++ reg |= U2_0_VDISCREF_SEL; ++ reg |= U2_TEST_TX; ++ reg |= U2_TEST_TX_HALT_DEEN; ++ writel(reg, usb2_phy0 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ ++ /* OTP usb2 phy0 */ ++ trim_val = readl(priv->sys_ctrl); ++ trim_val = usb2_0_trim_val(trim_val); ++ if ((trim_val >= U2_TRIM_VAL_MIN) && (trim_val <= U2_TRIM_VAL_MAX)) { ++ reg = readl(usb2_phy0 + U2_ANA_CFG2); ++ reg = usb2_rt_trim_clr(reg); ++ reg |= usb2_rt_trim_set(trim_val); ++ writel(reg, usb2_phy0 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ } ++ ++ /* ATOP TEST bit */ ++ reg = readl(usb2_phy0 + U2_ANA_CFG3); ++ reg = ana_cfg3_val(reg); ++ reg |= U2_0_SLEW_RATE_OPT; ++ writel(reg, usb2_phy0 + U2_ANA_CFG3); ++ udelay(U_LEVEL5); ++ ++ /* vtxref sel==>430mV, enable fls edge mode */ ++ reg = readl(usb2_phy0 + U2_ANA_CFG4); ++ reg = ana_cfg4_val(reg); ++ reg |= U2_VTXREF_SEL; ++ reg |= U2_FLS_EDGE_MODE; ++ writel(reg, usb2_phy0 + U2_ANA_CFG4); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy0); ++} ++ ++void bsp_usb2_phy0_config(struct phy *phy) ++{ ++ unsigned int reg; ++ void __iomem *usb2_phy0 = NULL; ++ ++ usb2_phy0 = ioremap(USB2_PHY0_BASE, __64K__); ++ if (usb2_phy0 == NULL) ++ return; ++ ++ /* usb2 phy0 pll enable */ ++ reg = readl(usb2_phy0 + PHY_PLL_OFFSET); ++ reg |= PHY_PLL_ENABLE; ++ writel(reg, usb2_phy0 + PHY_PLL_OFFSET); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy0); ++} ++ ++static void bsp_usb2_phy2_eye_config(struct phy *phy) ++{ ++ unsigned int reg; ++ unsigned int trim_val; ++ void __iomem *usb2_phy2 = NULL; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ usb2_phy2 = ioremap(USB2_PHY2_BASE, __64K__); ++ if (usb2_phy2 == NULL) ++ return; ++ ++ /* adjust the hstx mbias deen de */ ++ reg = readl(usb2_phy2 + U2_ANA_CFG0); ++ reg = ana_cfg0_val(reg); ++ reg |= U2_2_HSTX_MBIAS; ++ reg |= U2_2_HSTX_DEEN; ++ reg &= ~HSTX_DE_MASK; ++ reg |= U2_2_HSTX_DE; ++ writel(reg, usb2_phy2 + U2_ANA_CFG0); ++ udelay(U_LEVEL5); ++ ++ /* vdiscref sel and test tx set */ ++ reg = readl(usb2_phy2 + U2_ANA_CFG2); ++ reg = ana_cfg2_val(reg); ++ reg |= U2_2_VDISCREF_SEL; ++ reg |= U2_TEST_TX; ++ reg |= U2_TEST_TX_HALT_DEEN; ++ writel(reg, usb2_phy2 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ ++ /* OTP usb2 phy2 */ ++ trim_val = readl(priv->sys_ctrl); ++ trim_val = usb2_2_trim_val(trim_val); ++ if ((trim_val >= U2_TRIM_VAL_MIN) && (trim_val <= U2_TRIM_VAL_MAX)) { ++ reg = readl(usb2_phy2 + U2_ANA_CFG2); ++ reg = usb2_rt_trim_clr(reg); ++ reg |= usb2_rt_trim_set(trim_val); ++ writel(reg, usb2_phy2 + U2_ANA_CFG2); ++ udelay(U_LEVEL5); ++ } ++ ++ /* ATOP TEST bit */ ++ reg = readl(usb2_phy2 + U2_ANA_CFG3); ++ reg = ana_cfg3_val(reg); ++ reg |= U2_2_SLEW_RATE_OPT; ++ writel(reg, usb2_phy2 + U2_ANA_CFG3); ++ udelay(U_LEVEL5); ++ ++ reg = readl(usb2_phy2 + U2_ANA_CFG4); ++ reg = ana_cfg4_val(reg); ++#ifdef CONFIG_ARCH_SS528V100 ++ reg |= U2_VTXREF_SEL; ++#endif ++#ifdef CONFIG_ARCH_SS625V100 ++ reg |= U2_VTXREF_SEL_U3P; ++#endif ++ reg |= U2_FLS_EDGE_MODE; ++ writel(reg, usb2_phy2 + U2_ANA_CFG4); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy2); ++} ++ ++void bsp_usb2_phy2_config(struct phy *phy) ++{ ++ unsigned int reg; ++ void __iomem *usb2_phy2 = NULL; ++ ++ usb2_phy2 = ioremap(USB2_PHY2_BASE, __64K__); ++ if (usb2_phy2 == NULL) ++ return; ++ ++ /* usb2 phy2 pll enable */ ++ reg = readl(usb2_phy2 + PHY_PLL_OFFSET); ++ reg |= PHY_PLL_ENABLE; ++ writel(reg, usb2_phy2 + PHY_PLL_OFFSET); ++ udelay(U_LEVEL5); ++ ++ iounmap(usb2_phy2); ++} ++ ++void bsp_usb3_phy_config(struct phy *phy) ++{ ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* PI_CURRENT_TRIM ==>2'b00 to 2'b01 */ ++ writel(PI_CURRENT_TRIM_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0); ++ writel(PI_CURRENT_TRIM_VAL, priv->misc_ctrl + COMBPHY_CTRL0); ++ writel(PI_CURRENT_TRIM_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0); ++ udelay(U_LEVEL5); ++ ++ /* TX_SWING_COMP ==>4'b1000 to 4b'1100 */ ++ writel(TX_SWING_COMP_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0); ++ writel(TX_SWING_COMP_VAL, priv->misc_ctrl + COMBPHY_CTRL0); ++ writel(TX_SWING_COMP_ENABLE, priv->misc_ctrl + COMBPHY_CTRL0); ++ udelay(U_LEVEL5); ++} ++ ++void bsp_usb3_crg_config(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* USB3 enable */ ++ reg = readl(priv->misc_ctrl + USB_CTRL6); ++ reg &= ~U3_PORT_DISABLE; ++ writel(reg, priv->misc_ctrl + USB_CTRL6); ++ udelay(U_LEVEL6); ++ ++ /* ctrl0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3664); ++ reg |= USB3_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3664); ++ udelay(U_LEVEL6); ++ ++ /* combphy0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3676); ++ reg |= (COMBPHY0_SRST_REQ | COMBPHY0_TEST_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3676); ++ udelay(U_LEVEL6); ++ ++ /* usb2 phy0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3636); ++ reg |= (USB2_PHY0_REQ | USB2_PHY0_TREQ | USB2_PHY0_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3636); ++ udelay(U_LEVEL6); ++ ++ /* usb2 phy2 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3672); ++ reg |= (USB2_PHY2_REQ | USB2_PHY2_TREQ | USB2_PHY2_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3672); ++ udelay(U_LEVEL6); ++ ++ /* open usb2 phy0 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3636); ++ reg |= USB2_PHY0_XTAL_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3636); ++ udelay(U_LEVEL6); ++ ++ /* open usb2 phy2 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3672); ++ reg |= USB2_PHY2_XTAL_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3672); ++ udelay(U_LEVEL6); ++ ++ /* cancel usb2 phy0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3636); ++ reg &= ~(USB2_PHY0_REQ | USB2_PHY0_TREQ | USB2_PHY0_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3636); ++ mdelay(M_LEVEL1); ++ ++ /* cancel usb2 phy2 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3672); ++ reg &= ~(USB2_PHY2_REQ | USB2_PHY2_TREQ | USB2_PHY2_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3672); ++ mdelay(M_LEVEL1); ++ ++ /* open combphy0 clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3676); ++ reg |= COMBPHY0_REF_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3676); ++ udelay(U_LEVEL6); ++ ++ /* cancel combphy0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3676); ++ reg &= ~(COMBPHY0_SRST_REQ | COMBPHY0_TEST_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3676); ++ udelay(U_LEVEL5); ++ ++ /* open pipe/suspend/ref/bus clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3664); ++ reg |= USB3_BUS_CKEN; ++ reg |= USB3_REF_CKEN; ++ reg |= USB3_SUSPEND_CKEN; ++ reg |= USB3_UTMI_CKEN; ++ reg |= USB3_PIPE_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3664); ++ udelay(U_LEVEL6); ++ ++ /* open utmi clk */ ++ reg = readl(priv->peri_crg + PERI_CRG3632); ++ reg |= USB2_0_UTMI_CKEN; ++ writel(reg, priv->peri_crg + PERI_CRG3632); ++ udelay(U_LEVEL6); ++ ++ /* cancel ctrl0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3664); ++ reg &= ~USB3_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3664); ++ udelay(U_LEVEL6); ++} ++ ++void bsp_usb3_phy_on(struct phy *phy) ++{ ++ bsp_usb3_crg_config(phy); ++ ++ bsp_usb3_phy_config(phy); ++ ++ bsp_usb2_phy0_config(phy); ++ ++ bsp_usb2_phy0_eye_config(phy); ++ ++ bsp_usb2_phy2_config(phy); ++ ++ bsp_usb2_phy2_eye_config(phy); ++} ++EXPORT_SYMBOL(bsp_usb3_phy_on); ++ ++void bsp_usb3_phy_off(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ /* ctrl0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3664); ++ reg |= USB3_SRST_REQ; ++ writel(reg, priv->peri_crg + PERI_CRG3664); ++ udelay(U_LEVEL6); ++ ++ /* usb2 phy0 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3636); ++ reg |= (USB2_PHY0_REQ | USB2_PHY0_TREQ | USB2_PHY0_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3636); ++ udelay(U_LEVEL6); ++ ++ /* usb2 phy2 rst */ ++ reg = readl(priv->peri_crg + PERI_CRG3672); ++ reg |= (USB2_PHY2_REQ | USB2_PHY2_TREQ | USB2_PHY2_APB_SRST_REQ); ++ writel(reg, priv->peri_crg + PERI_CRG3672); ++ udelay(U_LEVEL6); ++} ++EXPORT_SYMBOL(bsp_usb3_phy_off); +diff --git a/drivers/phy/vendor/usb/phy-ss928v100-usb.c b/drivers/phy/vendor/usb/phy-ss928v100-usb.c +new file mode 100644 +index 000000000000..b3d1d9e39294 +--- /dev/null ++++ b/drivers/phy/vendor/usb/phy-ss928v100-usb.c +@@ -0,0 +1,358 @@ ++/* ++* ++* Copyright (c) 2012-2018 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++ ++#include "phy-bsp-usb.h" ++ ++#define PINOUT_REG_BASE (0x10230000) ++#define PITOUT_CTRL0_PWREN_OFFSET (0x44) ++#define PITOUT_CTRL1_PWREN_OFFSET (0X3C) ++#define PITOUT_CTRL1_VBUS_OFFSET (0x38) ++#define PINOUT_USB_VAL (0x1201) ++ ++#define PCIE_X2_MODE (0x0 << 16) ++#define USB3_MODE (0x1 << 16) ++#define PORT0U2_PORT1U3_MODE (0x2 << 16) ++#define COMBPHY_MODE_MASK (0x3 << 16) ++#define SYSSTAT 0x18 ++ ++#define USB3_CTRL_CRG 0x3940 ++#define USB3_CTRL_CRG_1 0x3960 ++#define USB2_PHY_CRG 0x38c0 ++#define USB2_PHY_CRG_1 0x38e0 ++#define USB3_PHY_CRG 0x3944 ++#define USB3_PHY_CRG_1 0x3964 ++#define USB3_U2_PHY_ADDR 0x10310000 ++#define USB3_U2_PHY_ADDR_1 0x10330000 ++#define USB3_CTRL_ADDR 0x10300000 ++#define USB3_CTRL_ADDR_1 0x10320000 ++ ++#define USB3_CTRL_CRG_DEFAULT_VALUE 0x30001 ++#define USB2_PHY_CRG_DEFAULT_VALUE 0x57 ++#define USB3_PHY_CRG_DEFAULT_VALUE 0x13 ++ ++#define USB3_CRG_PCLK_OCC_SEL (0x1 << 18) ++#define USB3_CRG_PIPE_CKEN (0x1 << 12) ++#define USB3_CRG_UTMI_CKEN (0x1 << 8) ++#define USB3_CRG_SUSPEND_CKEN (0x1 << 6) ++#define USB3_CRG_REF_CKEN (0x1 << 5) ++#define USB3_CRG_BUS_CKEN (0x1 << 4) ++#define USB3_CRG_SRST_REQ (0x1 << 0) ++ ++#define USB2_PHY_CRG_APB_SREQ (0x1 << 2) ++#define USB2_PHY_CRG_TREQ (0x1 << 1) ++#define USB2_PHY_CRG_REQ (0x1 << 0) ++ ++#define USB3_PHY_CRG_TREQ (0x1 << 1) ++#define USB3_PHY_CRG_REQ (0x1 << 0) ++ ++#define COMBPHY_REF_CKEN (0x1<<24) ++#define COMBPHY_SRST_REQ (0x1<<16) ++ ++#define USB3_VCC_SRST_REQ (0x1<<0) ++#define USB3_UTMI_CKSEL (0x1<<13) ++#define USB3_PCLK_OCC_SEL (0x1<<14) ++ ++#define USB2_PHY_PLLCK_ADDR_OFFSET 0x14 ++#define USB2_PHY_PLLCK_MASK 0x00000003 ++#define USB2_PHY_PLLCK_VAL ((0x3 << 0) & USB2_PHY_PLLCK_MASK) ++ ++#define GTXTHRCFG 0xc108 ++#define GRXTHRCFG 0xc10c ++#define REG_GCTL 0xc110 ++ ++#define PORT_CAP_DIR (0x3 << 12) ++#define DEFAULT_HOST_MOD (0x1 << 12) ++ ++#define USB_TXPKT_CNT_SEL (0x1 << 29) ++#define USB_TXPKT_CNT (0x11 << 24) ++#define USB_MAXTX_BURST_SIZE (0x1 << 20) ++#define CLEAN_USB3_GTXTHRCFG 0x0 ++ ++#define REG_GUSB3PIPECTL0 0xc2c0 ++#define PCS_SSP_SOFT_RESET (0x1 << 31) ++#define SUSPEND_USB3_SS_PHY (0x1 << 17) ++#define USB3_TX_MARGIN_VAL 0x10c0012 ++ ++#define USB3_GUSB2PHYCFGN 0xc200 ++#define USB3_SUSPENDUSB20_PHY (0x1 << 6) ++ ++#define ANA_CFG0_OFFSET (0x0) ++#define TX_DEEMPHASIS_ENABLE (0x1 << 5) ++#define TX_DEEMPHASIS_STRENGTH_MASK (0xF << 8) ++#define TX_DEEMPHASIS_STRENGTH_VAL (0xC << 8) ++#define MBIAS_MASK (0xF << 0) ++#define MBIAS_VAL (0xB << 0) ++#define ANA_CFG2_OFFSET (0x8) ++#define DEEMPHASIS_HALF_BIT_MASK (0xFF << 20) ++#define DEEMPHASIS_HALF_BIT_VAL (0x2 << 20) ++#define DISCONNECT_VREF_MASK (0x7 << 16) ++#define DISCONNECT_VREF_VAL (0x6 << 16) ++ ++static combphy_mode mode_flag; ++ ++static void usb_pinout_cfg(void) ++{ ++ void __iomem *pinout_regbase = ioremap(PINOUT_REG_BASE, __64K__); ++ writel(PINOUT_USB_VAL, pinout_regbase + PITOUT_CTRL0_PWREN_OFFSET); ++ writel(PINOUT_USB_VAL, pinout_regbase + PITOUT_CTRL1_PWREN_OFFSET); ++ writel(PINOUT_USB_VAL, pinout_regbase + PITOUT_CTRL1_VBUS_OFFSET); ++ udelay(U_LEVEL6); ++ iounmap(pinout_regbase); ++} ++ ++static void get_combphy_mode(struct phy *phy) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ ++ reg = readl(priv->sys_ctrl + SYSSTAT); ++ reg &= COMBPHY_MODE_MASK; ++ ++ switch (reg) { ++ case PCIE_X2_MODE: ++ mode_flag = PCIE_X2; ++ break; ++ case PORT0U2_PORT1U3_MODE: ++ mode_flag = PCIE_X1; ++ break; ++ case USB3_MODE: ++ mode_flag = USB3; ++ break; ++ default: ++ break; ++ } ++} ++ ++void usb_phy_reset(void __iomem *ctrl_crg_base, void __iomem *u2phy_crg_base, ++ void __iomem *u3phy_crg_base, void __iomem *u2_phy_base) ++{ ++ unsigned int reg; ++ ++ /* U3 phy TPOR &POR reset */ ++ reg = readl(u3phy_crg_base); ++ reg &= ~(USB3_PHY_CRG_TREQ | USB3_PHY_CRG_REQ); ++ writel(reg, u3phy_crg_base); ++ udelay(U_LEVEL6); // delay 200us ++ ++ /* U2 phy POR reset */ ++ reg = readl(u2phy_crg_base); ++ reg &= ~USB2_PHY_CRG_REQ; ++ writel(reg, u2phy_crg_base); ++ ++ reg = readl(u2_phy_base + USB2_PHY_PLLCK_ADDR_OFFSET); ++ reg &= ~USB2_PHY_PLLCK_MASK; ++ reg |= USB2_PHY_PLLCK_VAL; ++ writel(reg, u2_phy_base + USB2_PHY_PLLCK_ADDR_OFFSET); ++ mdelay(M_LEVEL1); // delay 2ms ++ ++ /* U2 phy TPOR reset */ ++ reg = readl(u2phy_crg_base); ++ reg &= ~USB2_PHY_CRG_TREQ; ++ writel(reg, u2phy_crg_base); ++ udelay(U_LEVEL6); // delay 200us ++} ++ ++static void usb3_crg_config(struct phy *phy, int index) ++{ ++ unsigned int reg; ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ void __iomem *ctrl_crg_base = NULL; ++ void __iomem *u2phy_crg_base = NULL; ++ void __iomem *u3phy_crg_base = NULL; ++ void __iomem *u2_phy_base = NULL; ++ ++ if (index == 0) { ++ ctrl_crg_base = priv->peri_crg + USB3_CTRL_CRG; ++ u2phy_crg_base = priv->peri_crg + USB2_PHY_CRG; ++ u3phy_crg_base = priv->peri_crg + USB3_PHY_CRG; ++ u2_phy_base = ioremap(USB3_U2_PHY_ADDR, __64K__); ++ } else if (index == 1) { ++ ctrl_crg_base = priv->peri_crg + USB3_CTRL_CRG_1; ++ u2phy_crg_base = priv->peri_crg + USB2_PHY_CRG_1; ++ u3phy_crg_base = priv->peri_crg + USB3_PHY_CRG_1; ++ u2_phy_base = ioremap(USB3_U2_PHY_ADDR_1, __64K__); ++ } else { ++ return; ++ } ++ if (u2_phy_base == NULL) ++ return; ++ /* enable port0 ss */ ++ ++ /* write default crg value */ ++ writel(USB3_CTRL_CRG_DEFAULT_VALUE, ctrl_crg_base); ++ writel(USB2_PHY_CRG_DEFAULT_VALUE, u2phy_crg_base); ++ writel(USB3_PHY_CRG_DEFAULT_VALUE, u3phy_crg_base); ++ udelay(U_LEVEL6); ++ ++ /* phy crg setting */ ++ reg = readl(u2phy_crg_base); ++ reg &= ~(USB2_PHY_CRG_APB_SREQ); ++ writel(reg, u2phy_crg_base); ++ udelay(U_LEVEL6); ++ ++ /* ctrl crg setting */ ++ /* usb3 occ pclk sel */ ++ reg = readl(ctrl_crg_base); ++ if (mode_flag == PCIE_X2) ++ reg |= USB3_CRG_PCLK_OCC_SEL; ++ else if (mode_flag == PCIE_X1 && index == 0) ++ reg |= USB3_CRG_PCLK_OCC_SEL; ++ else ++ reg &= ~(USB3_CRG_PCLK_OCC_SEL); ++ ++ reg |= (USB3_CRG_PIPE_CKEN | USB3_CRG_UTMI_CKEN | ++ USB3_CRG_SUSPEND_CKEN | USB3_CRG_REF_CKEN | USB3_CRG_BUS_CKEN); ++ writel(reg, ctrl_crg_base); ++ udelay(U_LEVEL6); // delay 200us ++ ++ usb_phy_reset(ctrl_crg_base, u2phy_crg_base, ++ u3phy_crg_base, u2_phy_base); ++ ++ /* ctrl crg reset release*/ ++ reg = readl(ctrl_crg_base); ++ reg &= ~USB3_CRG_SRST_REQ; ++ writel(reg, ctrl_crg_base); ++ udelay(U_LEVEL6); // delay 200us ++ ++ iounmap(u2_phy_base); ++ u2_phy_base = NULL; ++} ++ ++static void usb3_ctrl_config(struct phy *phy, int index) ++{ ++ unsigned int reg; ++ void __iomem *ctrl_base; ++ ++ if (index == 0) { ++ ctrl_base = ioremap(USB3_CTRL_ADDR, __64K__); ++ } else if (index == 1) { ++ ctrl_base = ioremap(USB3_CTRL_ADDR_1, __64K__); ++ } else { ++ return; ++ } ++ ++ reg = readl(ctrl_base + USB3_GUSB2PHYCFGN); ++ if (mode_flag == PCIE_X2) ++ reg &= ~(USB3_SUSPENDUSB20_PHY); ++ else if (mode_flag == PCIE_X1 && index == 0) ++ reg &= ~(USB3_SUSPENDUSB20_PHY); ++ else ++ reg |= (USB3_SUSPENDUSB20_PHY); ++ writel(reg, ctrl_base + USB3_GUSB2PHYCFGN); ++ udelay(U_LEVEL6); ++ ++ reg = readl(ctrl_base + REG_GUSB3PIPECTL0); ++ reg |= PCS_SSP_SOFT_RESET; ++ writel(reg, ctrl_base + REG_GUSB3PIPECTL0); ++ udelay(U_LEVEL6); ++ ++ reg = readl(ctrl_base + REG_GCTL); ++ reg &= ~PORT_CAP_DIR; ++ reg |= DEFAULT_HOST_MOD; /* [13:12] 01: Host; 10: Device; 11: OTG */ ++ writel(reg, ctrl_base + REG_GCTL); ++ udelay(U_LEVEL2); ++ ++ reg = readl(ctrl_base + REG_GUSB3PIPECTL0); ++ reg &= ~PCS_SSP_SOFT_RESET; ++ reg &= ~SUSPEND_USB3_SS_PHY; /* disable suspend */ ++ writel(reg, ctrl_base + REG_GUSB3PIPECTL0); ++ udelay(U_LEVEL2); ++ ++ reg &= CLEAN_USB3_GTXTHRCFG; ++ reg |= USB_TXPKT_CNT_SEL; ++ reg |= USB_TXPKT_CNT; ++ reg |= USB_MAXTX_BURST_SIZE; ++ writel(reg, ctrl_base + GTXTHRCFG); ++ udelay(U_LEVEL2); ++ writel(reg, ctrl_base + GRXTHRCFG); ++ udelay(U_LEVEL2); ++ ++ iounmap(ctrl_base); ++} ++ ++static void usb3_eye_config(struct phy *phy) ++{ ++ unsigned int reg; ++ void __iomem *u2_phy0_base = ioremap(USB3_U2_PHY_ADDR, __64K__); ++ void __iomem *u2_phy1_base = ioremap(USB3_U2_PHY_ADDR_1, __64K__); ++ if (u2_phy0_base == NULL) ++ return; ++ if (u2_phy1_base == NULL) ++ return; ++ ++ reg = readl(u2_phy0_base + ANA_CFG0_OFFSET); ++ reg |= TX_DEEMPHASIS_ENABLE; ++ reg &= ~(TX_DEEMPHASIS_STRENGTH_MASK | MBIAS_MASK); ++ reg |= (TX_DEEMPHASIS_STRENGTH_VAL | MBIAS_VAL); ++ writel(reg, u2_phy0_base + ANA_CFG0_OFFSET); ++ udelay(U_LEVEL6); ++ ++ reg = readl(u2_phy0_base + ANA_CFG2_OFFSET); ++ reg &= ~(DEEMPHASIS_HALF_BIT_MASK | DISCONNECT_VREF_MASK); ++ reg |= (DEEMPHASIS_HALF_BIT_VAL | DISCONNECT_VREF_VAL); ++ writel(reg, u2_phy0_base + ANA_CFG2_OFFSET); ++ udelay(U_LEVEL6); ++ ++ reg = readl(u2_phy1_base + ANA_CFG0_OFFSET); ++ reg |= TX_DEEMPHASIS_ENABLE; ++ reg &= ~(TX_DEEMPHASIS_STRENGTH_MASK | MBIAS_MASK); ++ reg |= (TX_DEEMPHASIS_STRENGTH_VAL | MBIAS_VAL); ++ writel(reg, u2_phy1_base + ANA_CFG0_OFFSET); ++ udelay(U_LEVEL6); ++ ++ reg = readl(u2_phy1_base + ANA_CFG2_OFFSET); ++ reg &= ~(DEEMPHASIS_HALF_BIT_MASK | DISCONNECT_VREF_MASK); ++ reg |= (DEEMPHASIS_HALF_BIT_VAL | DISCONNECT_VREF_VAL); ++ writel(reg, u2_phy1_base + ANA_CFG2_OFFSET); ++ udelay(U_LEVEL6); ++ ++ iounmap(u2_phy0_base); ++ iounmap(u2_phy1_base); ++} ++ ++void bsp_usb3_phy_on(struct phy *phy) ++{ ++ usb_pinout_cfg(); ++ udelay(U_LEVEL6); ++ get_combphy_mode(phy); ++ usb3_crg_config(phy, 0); ++ usb3_ctrl_config(phy, 0); ++ ++ usb3_crg_config(phy, 1); ++ usb3_ctrl_config(phy, 1); ++ ++ usb3_eye_config(phy); ++} ++EXPORT_SYMBOL(bsp_usb3_phy_on); ++ ++void bsp_usb3_phy_off(struct phy *phy) ++{ ++ struct bsp_priv *priv = phy_get_drvdata(phy); ++ /* write default crg value */ ++ writel(USB3_CTRL_CRG_DEFAULT_VALUE, priv->peri_crg + USB3_CTRL_CRG); ++ writel(USB2_PHY_CRG_DEFAULT_VALUE, priv->peri_crg + USB2_PHY_CRG); ++ writel(USB3_PHY_CRG_DEFAULT_VALUE, priv->peri_crg + USB3_PHY_CRG); ++ udelay(U_LEVEL6); ++ ++ writel(USB3_CTRL_CRG_DEFAULT_VALUE, priv->peri_crg + USB3_CTRL_CRG_1); ++ writel(USB2_PHY_CRG_DEFAULT_VALUE, priv->peri_crg + USB2_PHY_CRG_1); ++ writel(USB3_PHY_CRG_DEFAULT_VALUE, priv->peri_crg + USB3_PHY_CRG_1); ++ udelay(U_LEVEL6); ++} ++EXPORT_SYMBOL(bsp_usb3_phy_off); +diff --git a/drivers/phy/vendor/usb/phy-xvp-bsp-usb.c b/drivers/phy/vendor/usb/phy-xvp-bsp-usb.c +new file mode 100644 +index 000000000000..08dfa60778c7 +--- /dev/null ++++ b/drivers/phy/vendor/usb/phy-xvp-bsp-usb.c +@@ -0,0 +1,798 @@ ++/* ++* ++* Copyright (c) 2012-2021 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "phy-bsp-usb.h" ++ ++#define XVP_PHY_TRIM_OFFSET 0x0008 ++#define XVP_PHY_TRIM_MASK 0x1f00 ++#define xvp_phy_trim_val(a) (((a) << 8) & XVP_PHY_TRIM_MASK) ++ ++#define XVP_PHY_SVB_OFFSET 0x0000 ++#define XVP_PHY_SVB_MASK 0x0f000000 ++#define xvp_phy_svb_val(a) (((a) << 24) & XVP_PHY_SVB_MASK) ++ ++struct bsp_xvp_priv { ++ void __iomem *crg_base; ++ void __iomem *phy_base; ++ void __iomem *pin_base; ++ struct phy *phy; ++ struct device *dev; ++ struct clk **clks; ++ int num_clocks; ++ u32 phy_pll_offset; ++ u32 phy_pll_mask; ++ u32 phy_pll_val; ++ u32 crg_offset; ++ u32 crg_defal_mask; ++ u32 crg_defal_val; ++ u32 vbus_offset; ++ u32 vbus_val; ++ int vbus_flag; ++ u32 pwren_offset; ++ u32 pwren_val; ++ int pwren_flag; ++ u32 ana_cfg_0_eye_val; ++ u32 ana_cfg_0_offset; ++ int ana_cfg_0_flag; ++ u32 ana_cfg_2_eye_val; ++ u32 ana_cfg_2_offset; ++ int ana_cfg_2_flag; ++ u32 ana_cfg_4_eye_val; ++ u32 ana_cfg_4_offset; ++ int ana_cfg_4_flag; ++ struct reset_control *usb_phy_tpor_rst; ++ struct reset_control *usb_phy_por_rst; ++ u32 trim_otp_addr; ++ u32 trim_otp_mask; ++ u32 trim_otp_bit_offset; ++ u32 trim_otp_min; ++ u32 trim_otp_max; ++ int trim_flag; ++ u32 svb_otp_addr; ++ u32 svb_otp_predev5_min; ++ u32 svb_otp_predev5_max; ++ u32 svb_phy_predev5_val; ++ int svb_predev5_flag; ++ u32 svb_otp_predev4_min; ++ u32 svb_otp_predev4_max; ++ u32 svb_phy_predev4_val; ++ int svb_predev4_flag; ++ u32 svb_otp_predev3_min; ++ u32 svb_otp_predev3_max; ++ u32 svb_phy_predev3_val; ++ int svb_predev3_flag; ++ u32 svb_otp_predev2_min; ++ u32 svb_otp_predev2_max; ++ u32 svb_phy_predev2_val; ++ int svb_predev2_flag; ++ int svb_flag; ++}; ++ ++void bsp_usb_xvp_def_all_exist(struct bsp_xvp_priv *priv) ++{ ++ if (priv == NULL) ++ return; ++ ++ /* All parameters exist by default */ ++ priv->vbus_flag = 1; ++ ++ priv->pwren_flag = 1; ++ ++ priv->ana_cfg_0_flag = 1; ++ ++ priv->ana_cfg_2_flag = 1; ++ ++ priv->ana_cfg_4_flag = 1; ++ ++ priv->trim_flag = 1; ++ ++ priv->svb_predev5_flag = 1; ++ ++ priv->svb_predev4_flag = 1; ++ ++ priv->svb_predev3_flag = 1; ++ ++ priv->svb_predev2_flag = 1; ++ ++ priv->svb_flag = 1; ++} ++ ++void bsp_usb_xvp_get_eye_para(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return; ++ ++ if (dev->of_node == NULL) ++ return; ++ ++ /* ++ * Get phy eye parameters,if you want to change them,please open ++ * dtsi file and modify parameters at phy node. ++ */ ++ ret = of_property_read_u32(dev->of_node, "ana_cfg_0_eye_val", ++ &(priv->ana_cfg_0_eye_val)); ++ if (ret) ++ priv->ana_cfg_0_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "ana_cfg_0_offset", ++ &(priv->ana_cfg_0_offset)); ++ if (ret) ++ priv->ana_cfg_0_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "ana_cfg_2_eye_val", ++ &(priv->ana_cfg_2_eye_val)); ++ if (ret) ++ priv->ana_cfg_2_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "ana_cfg_2_offset", ++ &(priv->ana_cfg_2_offset)); ++ if (ret) ++ priv->ana_cfg_2_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "ana_cfg_4_eye_val", ++ &(priv->ana_cfg_4_eye_val)); ++ if (ret) ++ priv->ana_cfg_4_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "ana_cfg_4_offset", ++ &(priv->ana_cfg_4_offset)); ++ if (ret) ++ priv->ana_cfg_4_flag = 0; ++} ++ ++void bsp_usb_xvp_phy_eye_config(const struct bsp_xvp_priv *priv) ++{ ++ if (priv == NULL) ++ return; ++ ++ if (priv->ana_cfg_0_flag) ++ writel(priv->ana_cfg_0_eye_val, priv->phy_base + priv->ana_cfg_0_offset); ++ ++ if (priv->ana_cfg_2_flag) ++ writel(priv->ana_cfg_2_eye_val, priv->phy_base + priv->ana_cfg_2_offset); ++ ++ if (priv->ana_cfg_4_flag) ++ writel(priv->ana_cfg_4_eye_val, priv->phy_base + priv->ana_cfg_4_offset); ++} ++ ++void bsp_usb_xvp_get_trim_para(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return; ++ ++ if (dev->of_node == NULL) ++ return; ++ ++ /* get phy trim parameters */ ++ ret = of_property_read_u32(dev->of_node, "trim_otp_addr", ++ &(priv->trim_otp_addr)); ++ if (ret) ++ priv->trim_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "trim_otp_mask", ++ &(priv->trim_otp_mask)); ++ if (ret) ++ priv->trim_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "trim_otp_bit_offset", ++ &(priv->trim_otp_bit_offset)); ++ if (ret) ++ priv->trim_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "trim_otp_min", &(priv->trim_otp_min)); ++ if (ret) ++ priv->trim_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "trim_otp_max", &(priv->trim_otp_max)); ++ if (ret) ++ priv->trim_flag = 0; ++} ++ ++void bsp_usb_xvp_phy_trim_config(const struct bsp_xvp_priv *priv) ++{ ++ unsigned int trim_otp_val; ++ unsigned int reg; ++ void __iomem *phy_trim = NULL; ++ ++ if (priv == NULL) ++ return; ++ ++ if (priv->trim_flag) { ++ phy_trim = ioremap(priv->trim_otp_addr, __1K__); ++ if (phy_trim == NULL) ++ return; ++ ++ reg = readl(phy_trim); ++ trim_otp_val = (reg & priv->trim_otp_mask); ++ if ((trim_otp_val >= priv->trim_otp_min) && ++ (trim_otp_val <= priv->trim_otp_max)) { ++ /* set trim value to XVPV100 phy */ ++ reg = readl(priv->phy_base + XVP_PHY_TRIM_OFFSET); ++ reg &= ~XVP_PHY_TRIM_MASK; ++ reg |= xvp_phy_trim_val(trim_otp_val >> priv->trim_otp_bit_offset); ++ writel(reg, priv->phy_base + XVP_PHY_TRIM_OFFSET); ++ } ++ iounmap(phy_trim); ++ } ++} ++ ++void bsp_usb_xvp_get_svb_para_1(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return; ++ ++ if (dev->of_node == NULL) ++ return; ++ ++ /* get phy svb parmteters */ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_addr", & ++ (priv->svb_otp_addr)); ++ if (ret) ++ priv->svb_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev5_min", ++ &(priv->svb_otp_predev5_min)); ++ if (ret) ++ priv->svb_predev5_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev5_max", ++ &(priv->svb_otp_predev5_max)); ++ if (ret) ++ priv->svb_predev5_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_phy_predev5_val", ++ &(priv->svb_phy_predev5_val)); ++ if (ret) ++ priv->svb_predev5_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev4_min", ++ &(priv->svb_otp_predev4_min)); ++ if (ret) ++ priv->svb_predev4_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev4_max", ++ &(priv->svb_otp_predev4_max)); ++ if (ret) ++ priv->svb_predev4_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_phy_predev4_val", ++ &(priv->svb_phy_predev4_val)); ++ if (ret) ++ priv->svb_predev4_flag = 0; ++} ++ ++void bsp_usb_xvp_get_svb_para_2(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return; ++ ++ if (dev->of_node == NULL) ++ return; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev3_min", ++ &(priv->svb_otp_predev3_min)); ++ if (ret) ++ priv->svb_predev3_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev3_max", ++ &(priv->svb_otp_predev3_max)); ++ if (ret) ++ priv->svb_predev3_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_phy_predev3_val", ++ &(priv->svb_phy_predev3_val)); ++ if (ret) ++ priv->svb_predev3_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev2_min", ++ &(priv->svb_otp_predev2_min)); ++ if (ret) ++ priv->svb_predev2_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_otp_predev2_max", ++ &(priv->svb_otp_predev2_max)); ++ if (ret) ++ priv->svb_predev2_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "svb_phy_predev2_val", ++ &(priv->svb_phy_predev2_val)); ++ if (ret) ++ priv->svb_predev2_flag = 0; ++} ++ ++void bsp_usb_xvp_phy_svb_config(const struct bsp_xvp_priv *priv) ++{ ++ unsigned int reg; ++ unsigned int ret; ++ void __iomem *phy_svb = NULL; ++ ++ if (priv == NULL) ++ return; ++ ++ if (priv->svb_flag) { ++ phy_svb = ioremap(priv->svb_otp_addr, __1K__); ++ if (phy_svb == NULL) ++ return; ++ ++ ret = readl(phy_svb); ++ reg = readl(priv->phy_base + XVP_PHY_SVB_OFFSET); ++ reg &= ~XVP_PHY_SVB_MASK; ++ if ((ret >= priv->svb_otp_predev5_min) && ++ (ret < priv->svb_otp_predev5_max) && (priv->svb_predev5_flag)) ++ reg |= xvp_phy_svb_val(priv->svb_phy_predev5_val); ++ else if ((ret >= priv->svb_otp_predev4_min) && ++ (ret < priv->svb_otp_predev4_max) && (priv->svb_predev4_flag)) ++ reg |= xvp_phy_svb_val(priv->svb_phy_predev4_val); ++ else if ((ret >= priv->svb_otp_predev3_min) && ++ (ret <= priv->svb_otp_predev3_max) && (priv->svb_predev3_flag)) ++ reg |= xvp_phy_svb_val(priv->svb_phy_predev3_val); ++ else if ((ret > priv->svb_otp_predev2_min) && ++ (ret <= priv->svb_otp_predev2_max) && (priv->svb_predev2_flag)) ++ reg |= xvp_phy_svb_val(priv->svb_phy_predev2_val); ++ else ++ reg |= xvp_phy_svb_val(priv->svb_phy_predev4_val); ++ ++ writel(reg, priv->phy_base + XVP_PHY_SVB_OFFSET); ++ iounmap(phy_svb); ++ } ++} ++ ++static void bsp_usb_vbus_and_pwren_config(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return; ++ ++ if (dev->of_node == NULL) ++ return; ++ ++ /* Some chips do not have VBUS encapsulation and need to be configured */ ++ ret = of_property_read_u32(dev->of_node, "vbus_offset", &(priv->vbus_offset)); ++ if (ret) ++ priv->vbus_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "vbus_val", &(priv->vbus_val)); ++ if (ret) ++ priv->vbus_flag = 0; ++ ++ /* Some chips do not have PWREN encapsulation and need to be configured */ ++ ret = of_property_read_u32(dev->of_node, "pwren_offset", &(priv->pwren_offset)); ++ if (ret) ++ priv->pwren_flag = 0; ++ ++ ret = of_property_read_u32(dev->of_node, "pwren_val", &(priv->pwren_val)); ++ if (ret) ++ priv->pwren_flag = 0; ++ ++ if (priv->vbus_flag) ++ writel(priv->vbus_val, priv->pin_base + priv->vbus_offset); ++ ++ udelay(U_LEVEL2); ++ ++ if (priv->pwren_flag) ++ writel(priv->pwren_val, priv->pin_base + priv->pwren_offset); ++ ++ udelay(U_LEVEL2); ++} ++ ++static int bsp_usb_xvp_get_pll_clk(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return -EINVAL; ++ ++ if (dev->of_node == NULL) ++ return -EINVAL; ++ ++ /* Get phy pll clk config parameters from the phy node of the dtsi file */ ++ ret = of_property_read_u32(dev->of_node, "phy_pll_offset", ++ &(priv->phy_pll_offset)); ++ if (ret) { ++ dev_err(dev, "get phy_pll_offset failed: %d\n", ret); ++ return ret; ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "phy_pll_mask", &(priv->phy_pll_mask)); ++ if (ret) { ++ dev_err(dev, "get phy_pll_mask failed: %d\n", ret); ++ return ret; ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "phy_pll_val", &(priv->phy_pll_val)); ++ if (ret) { ++ dev_err(dev, "get phy_pll_val failed: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int bsp_usb_xvp_set_crg_val(const struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ unsigned int reg; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return -EINVAL; ++ ++ if (dev->of_node == NULL) ++ return -EINVAL; ++ ++ /* Get CRG default value from the phy node of the dtsi file */ ++ ret = of_property_read_u32(dev->of_node, "crg_offset", &(priv->crg_offset)); ++ if (ret) { ++ dev_err(dev, "get crg_offset failed: %d\n", ret); ++ return ret; ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "crg_defal_mask", ++ &(priv->crg_defal_mask)); ++ if (ret) { ++ dev_err(dev, "get crg_defal_mask failed: %d\n", ret); ++ return ret; ++ } ++ ++ ret = of_property_read_u32(dev->of_node, "crg_defal_val", ++ &(priv->crg_defal_val)); ++ if (ret) { ++ dev_err(dev, "get crg_defal_val failed: %d\n", ret); ++ return ret; ++ } ++ ++ /* write phy crg default value */ ++ reg = readl(priv->crg_base + priv->crg_offset); ++ reg &= ~priv->crg_defal_mask; ++ reg |= priv->crg_defal_val; ++ writel(reg, priv->crg_base + priv->crg_offset); ++ ++ return 0; ++} ++ ++static int bsp_usb_xvp_phy_get_para(struct device *dev, ++ struct bsp_xvp_priv *priv) ++{ ++ int ret; ++ ++ if ((dev == NULL) || (priv == NULL)) ++ return -EINVAL; ++ ++ bsp_usb_xvp_def_all_exist(priv); ++ ++ ret = bsp_usb_xvp_get_pll_clk(dev, priv); ++ if (ret) { ++ dev_err(dev, "get pll clk failed: %d\n", ret); ++ return ret; ++ } ++ ++ bsp_usb_xvp_get_trim_para(dev, priv); ++ bsp_usb_xvp_get_eye_para(dev, priv); ++ bsp_usb_xvp_get_svb_para_1(dev, priv); ++ bsp_usb_xvp_get_svb_para_2(dev, priv); ++ ++ return 0; ++} ++ ++static int bsp_usb_xvp_phy_get_clks(struct bsp_xvp_priv *priv, int count) ++{ ++ struct device *dev = priv->dev; ++ struct device_node *np = dev->of_node; ++ int i; ++ if (np == NULL) ++ return -EINVAL; ++ ++ priv->num_clocks = count; ++ ++ if (!count) ++ return 0; ++ ++ priv->clks = ++ devm_kcalloc(dev, priv->num_clocks, sizeof(struct clk *), GFP_KERNEL); ++ if (priv->clks == NULL) ++ return -ENOMEM; ++ ++ for (i = 0; i < priv->num_clocks; i++) { ++ struct clk *clk; ++ ++ clk = of_clk_get(np, i); ++ if (IS_ERR(clk)) { ++ while (--i >= 0) ++ clk_put(priv->clks[i]); ++ ++ devm_kfree(dev, priv->clks); ++ priv->clks = NULL; ++ return PTR_ERR(clk); ++ } ++ ++ priv->clks[i] = clk; ++ } ++ return 0; ++} ++ ++static int bsp_usb_xvp_clk_rst_config(struct platform_device *pdev, ++ struct bsp_xvp_priv *priv) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *np = pdev->dev.of_node; ++ int ret; ++ ++ ret = bsp_usb_xvp_phy_get_clks(priv, of_clk_get_parent_count(np)); ++ if (ret) { ++ dev_err(dev, "get xvp phy clk failed\n"); ++ return ret; ++ } ++ ++ priv->usb_phy_tpor_rst = devm_reset_control_get(dev, "phy_tpor_reset"); ++ if (IS_ERR_OR_NULL(priv->usb_phy_tpor_rst)) { ++ dev_err(dev, "get phy_tpor_reset failed: %d\n", ret); ++ return PTR_ERR(priv->usb_phy_tpor_rst); ++ } ++ ++ priv->usb_phy_por_rst = devm_reset_control_get(dev, "phy_por_reset"); ++ if (IS_ERR_OR_NULL(priv->usb_phy_por_rst)) { ++ dev_err(dev, "get phy_por_reset failed: %d\n", ret); ++ return PTR_ERR(priv->usb_phy_por_rst); ++ } ++ ++ return 0; ++} ++ ++static int bsp_usb_xvp_iomap(struct device_node *np, ++ struct bsp_xvp_priv *priv) ++{ ++ if ((np == NULL) || (priv == NULL)) ++ return -EINVAL; ++ ++ priv->phy_base = of_iomap(np, 0); ++ if (IS_ERR(priv->phy_base)) ++ return -ENOMEM; ++ ++ priv->crg_base = of_iomap(np, 1); ++ if (IS_ERR(priv->crg_base)) { ++ iounmap(priv->phy_base); ++ return -ENOMEM; ++ } ++ ++ priv->pin_base = of_iomap(np, 2); /* 2:index of the pin_base in dtsi */ ++ if (IS_ERR(priv->pin_base)) { ++ iounmap(priv->phy_base); ++ iounmap(priv->crg_base); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int bsp_usb_xvp_phy_init(struct phy *phy) ++{ ++ struct bsp_xvp_priv *priv = phy_get_drvdata(phy); ++ int i, ret; ++ unsigned int reg; ++ ++ for (i = 0; i < priv->num_clocks; i++) { ++ ret = clk_prepare_enable(priv->clks[i]); ++ if (ret < 0) { ++ while (--i >= 0) { ++ clk_disable_unprepare(priv->clks[i]); ++ clk_put(priv->clks[i]); ++ } ++ } ++ } ++ ++ udelay(U_LEVEL5); ++ ++ /* undo por reset */ ++ ret = reset_control_deassert(priv->usb_phy_por_rst); ++ if (ret) ++ return ret; ++ ++ /* pll out clk */ ++ reg = readl(priv->phy_base + priv->phy_pll_offset); ++ reg &= ~priv->phy_pll_mask; ++ reg |= priv->phy_pll_val; ++ writel(reg, priv->phy_base + priv->phy_pll_offset); ++ ++ mdelay(M_LEVEL1); ++ ++ /* undo tpor reset */ ++ ret = reset_control_deassert(priv->usb_phy_tpor_rst); ++ if (ret) ++ return ret; ++ ++ udelay(U_LEVEL6); ++ ++ bsp_usb_xvp_phy_eye_config(priv); ++ ++ bsp_usb_xvp_phy_trim_config(priv); ++ ++ bsp_usb_xvp_phy_svb_config(priv); ++ return 0; ++} ++ ++static int bsp_usb_xvp_phy_exit(struct phy *phy) ++{ ++ struct bsp_xvp_priv *priv = phy_get_drvdata(phy); ++ int i, ret; ++ ++ for (i = 0; i < priv->num_clocks; i++) ++ clk_disable_unprepare(priv->clks[i]); ++ ++ ret = reset_control_assert(priv->usb_phy_por_rst); ++ if (ret) ++ return ret; ++ ++ ret = reset_control_assert(priv->usb_phy_tpor_rst); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static const struct phy_ops bsp_usb_xvp_phy_ops = { ++ .init = bsp_usb_xvp_phy_init, ++ .exit = bsp_usb_xvp_phy_exit, ++ .owner = THIS_MODULE, ++}; ++ ++static int bsp_usb_xvp_phy_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct phy *phy = NULL; ++ struct bsp_xvp_priv *priv = NULL; ++ struct device_node *np = pdev->dev.of_node; ++ struct phy_provider *phy_provider = NULL; ++ int ret; ++ ++ phy = devm_phy_create(dev, dev->of_node, &bsp_usb_xvp_phy_ops); ++ if (IS_ERR(phy)) ++ return PTR_ERR(phy); ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (priv == NULL) ++ return -ENOMEM; ++ ++ ret = bsp_usb_xvp_iomap(np, priv); ++ if (ret) { ++ devm_kfree(dev, priv); ++ priv = NULL; ++ ++ return -ENOMEM; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ priv->dev = dev; ++ ++ ret = bsp_usb_xvp_clk_rst_config(pdev, priv); ++ if (ret) ++ goto xvp_unmap; ++ ++ ret = bsp_usb_xvp_phy_get_para(dev, priv); ++ if (ret) ++ goto xvp_unmap; ++ ++ bsp_usb_vbus_and_pwren_config(dev, priv); ++ ++ ret = bsp_usb_xvp_set_crg_val(dev, priv); ++ if (ret) ++ goto xvp_unmap; ++ ++ platform_set_drvdata(pdev, priv); ++ phy_set_drvdata(phy, priv); ++ ++ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); ++ if (IS_ERR(phy_provider)) { ++ ret = PTR_ERR(phy_provider); ++ goto xvp_unmap; ++ } ++ ++ return 0; ++xvp_unmap: ++ iounmap(priv->phy_base); ++ iounmap(priv->crg_base); ++ iounmap(priv->pin_base); ++ ++ devm_kfree(dev, priv); ++ priv = NULL; ++ ++ return ret; ++} ++ ++static int bsp_usb_xvp_phy_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct bsp_xvp_priv *priv = platform_get_drvdata(pdev); ++ int i; ++ ++ for (i = 0; i < priv->num_clocks; i++) ++ clk_put(priv->clks[i]); ++ ++ iounmap(priv->phy_base); ++ iounmap(priv->crg_base); ++ iounmap(priv->pin_base); ++ ++ devm_kfree(dev, priv); ++ priv = NULL; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM_SLEEP ++static int bsp_usb_xvp_phy_suspend(struct device *dev) ++{ ++ struct phy *phy = dev_get_drvdata(dev); ++ ++ if (bsp_usb_xvp_phy_exit(phy)) ++ return -1; ++ ++ return 0; ++} ++ ++static int bsp_usb_xvp_phy_resume(struct device *dev) ++{ ++ struct phy *phy = dev_get_drvdata(dev); ++ ++ if (bsp_usb_xvp_phy_init(phy)) ++ return -1; ++ ++ return 0; ++} ++#endif /* CONFIG_PM_SLEEP */ ++ ++static SIMPLE_DEV_PM_OPS(bsp_usb_pm_ops, bsp_usb_xvp_phy_suspend, ++ bsp_usb_xvp_phy_resume); ++ ++static const struct of_device_id bsp_usb_xvp_phy_of_match[] = { ++ { .compatible = "vendor,xvp-usb2-phy" }, ++ {}, ++}; ++ ++static struct platform_driver bsp_usb_xvp_phy_driver = { ++ .probe = bsp_usb_xvp_phy_probe, ++ .remove = bsp_usb_xvp_phy_remove, ++ .driver = { ++ .name = "bsp-usb-xvp-phy", ++ .pm = &bsp_usb_pm_ops, ++ .of_match_table = bsp_usb_xvp_phy_of_match, ++ } ++}; ++module_platform_driver(bsp_usb_xvp_phy_driver); ++MODULE_DESCRIPTION("Vendor USB XVP PHY driver"); ++MODULE_ALIAS("platform:bsp-usb-xvp-phy"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig +index 63be5362fd3a..903c743d9df3 100644 +--- a/drivers/pwm/Kconfig ++++ b/drivers/pwm/Kconfig +@@ -570,4 +570,13 @@ config PWM_ZX + To compile this driver as a module, choose M here: the module + will be called pwm-zx. + ++config PWM_BSP ++ tristate "Vendor PWM support" ++ depends on ARCH_BSP || COMPILE_TEST ++ help ++ Generic PWM framework driver for Vendor SoCs. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called pwm-bsp. ++ + endif +diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile +index cbdcd55d69ee..04bc1fbe2aa2 100644 +--- a/drivers/pwm/Makefile ++++ b/drivers/pwm/Makefile +@@ -16,6 +16,7 @@ obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o + obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o + obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o + obj-$(CONFIG_PWM_HIBVT) += pwm-hibvt.o ++obj-$(CONFIG_PWM_BSP) += pwm-bsp.o + obj-$(CONFIG_PWM_IMG) += pwm-img.o + obj-$(CONFIG_PWM_IMX1) += pwm-imx1.o + obj-$(CONFIG_PWM_IMX27) += pwm-imx27.o +diff --git a/drivers/pwm/pwm-bsp.c b/drivers/pwm/pwm-bsp.c +new file mode 100644 +index 000000000000..a142062f4a7b +--- /dev/null ++++ b/drivers/pwm/pwm-bsp.c +@@ -0,0 +1,434 @@ ++/* ++ * Copyright (c) 2016 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ ++/* reg addr of the xth chn. */ ++#define pwm_period_cfg_addr(x) (0x0000 + (0x100 * (x))) ++#define pwm_duty0_cfg_addr(x) (0x0004 + (0x100 * (x))) ++#define pwm_duty1_cfg_addr(x) (0x0008 + (0x100 * (x))) ++#define pwm_duty2_cfg_addr(x) (0x000C + (0x100 * (x))) ++#define pwm_num_cfg_addr(x) (0x0010 + (0x100 * (x))) ++#define pwm_ctrl_addr(x) (0x0014 + (0x100 * (x))) ++#define pwm_dt_value_cfg_addr(x) (0x0020 + (0x100 * (x))) ++#define pwm_dt_ctrl_cfg_addr(x) (0x0024 + (0x100 * (x))) ++#define pwm_sync_cfg_addr(x) (0x0030 + (0x100 * (x))) ++#define pwm_sync_delay_cfg_addr(x) (0x0034 + (0x100 * (x))) ++#define pwm_period_addr(x) (0x0040 + (0x100 * (x))) ++#define pwm_duty0_addr(x) (0x0044 + (0x100 * (x))) ++#define pwm_duty1_addr(x) (0x0048 + (0x100 * (x))) ++#define pwm_duty2_addr(x) (0x004C + (0x100 * (x))) ++#define pwm_num_addr(x) (0x0050 + (0x100 * (x))) ++#define pwm_ctrl_st_addr(x) (0x0054 + (0x100 * (x))) ++#define pwm_dt_value_addr(x) (0x0060 + (0x100 * (x))) ++#define pwm_dt_ctrl_addr(x) (0x0064 + (0x100 * (x))) ++#define pwm_sync_delay_addr(x) (0x0074 + (0x100 * (x))) ++ ++#define PWM_SYNC_START_ADDR 0x0ff0 ++ ++#define PWM_ALIGN_MODE_SHIFT 4 ++#define PWM_ALIGN_MODE_MASK GENMASK(5, 4) ++ ++#define PWM_PRE_DIV_SEL_SHIFT 8 ++#define PWM_PRE_DIV_SEL_MASK GENMASK(11, 8) ++ ++/* pwm dt value */ ++#define PWM_DT_A_SHIFT 0 ++#define PWM_DT_A_MASK GENMASK(31, 16) ++ ++#define PWM_DT_B_SHIFT 16 ++#define PWM_DT_B_MASK GENMASK(15, 0) ++ ++/* pwm dt ctrl */ ++#define PWM_DTS_OUT_0P_SHIFT 0 ++#define PWM_DTS_OUT_0P_MASK BIT(0) ++ ++#define PWM_DTS_OUT_0N_SHIFT 1 ++#define PWM_DTS_OUT_0N_MASK BIT(1) ++ ++#define PWM_DTS_OUT_1P_SHIFT 2 ++#define PWM_DTS_OUT_1P_MASK BIT(2) ++ ++#define PWM_DTS_OUT_1N_SHIFT 3 ++#define PWM_DTS_OUT_1N_MASK BIT(3) ++ ++#define PWM_DTS_OUT_2P_SHIFT 4 ++#define PWM_DTS_OUT_2P_MASK BIT(4) ++ ++#define PWM_DTS_OUT_2N_SHIFT 5 ++#define PWM_DTS_OUT_2N_MASK BIT(5) ++ ++#else ++ ++#define pwm_period_cfg_addr(x) (((x) * 0x20) + 0x0) ++#define pwm_duty0_cfg_addr(x) (((x) * 0x20) + 0x4) ++#define pwm_cfg2_addr(x) (((x) * 0x20) + 0x8) ++#define pwm_ctrl_addr(x) (((x) * 0x20) + 0xC) ++ ++#endif ++ ++/* pwm ctrl */ ++#define PWM_ENABLE_SHIFT 0 ++#define PWM_ENABLE_MASK BIT(0) ++ ++#define PWM_POLARITY_SHIFT 1 ++#define PWM_POLARITY_MASK BIT(1) ++ ++#define PWM_KEEP_SHIFT 2 ++#define PWM_KEEP_MASK BIT(2) ++ ++/* pwm period */ ++#define PWM_PERIOD_MASK GENMASK(31, 0) ++ ++/* pwm duty */ ++#define PWM_DUTY_MASK GENMASK(31, 0) ++ ++enum pwm_pre_div { ++ PWM_PRE_DIV_1 = 0, ++ PWM_PRE_DIV_2, ++ PWM_PRE_DIV_4, ++ PWM_PRE_DIV_8, ++ PWM_PRE_DIV_16, ++ PWM_PRE_DIV_32, ++ PWM_PRE_DIV_64, ++ PWM_PRE_DIV_128, ++ PWM_PRE_DIV_256, ++}; ++ ++enum pwm_align { ++ PWM_ALIGN_RIGHT = 0, ++ PWM_ALIGN_LEFT, ++ PWM_ALIGN_MIDDLE, ++}; ++ ++typedef enum { ++ PWM_CONTROLLER_0 = 0, ++ PWM_CONTROLLER_1, ++} pwm_controller_index; ++ ++typedef enum { ++ PWM_CHN_0 = 0, ++ PWM_CHN_1, ++ PWM_CHN_2, ++ PWM_CHN_3, ++ PWM_CHN_4, ++ PWM_CHN_5, ++ PWM_CHN_6, ++ PWM_CHN_7, ++ PWM_CHN_8, ++ PWM_CHN_9, ++ PWM_CHN_10, ++ PWM_CHN_11, ++ PWM_CHN_12, ++ PWM_CHN_13, ++ PWM_CHN_14, ++ PWM_CHN_15, ++} pwm_chn_index; ++ ++struct bsp_pwm_chip { ++ pwm_controller_index controller_index; ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ struct reset_control *rstc; ++}; ++ ++struct bsp_pwm_soc { ++ u32 num_pwms; ++ const char *pwm_name; ++}; ++ ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++#define CHIP_PWM_NUM 2 ++#define CHIP_PWM_CONTROLLER_0_NAME "pwm0" ++#define CHIP_PWM_CONTROLLER_1_NAME "pwm1" ++ ++static const struct bsp_pwm_soc pwm_soc[CHIP_PWM_NUM] = { ++ { .num_pwms = 16, .pwm_name = CHIP_PWM_CONTROLLER_0_NAME }, ++ { .num_pwms = 16, .pwm_name = CHIP_PWM_CONTROLLER_1_NAME }, ++}; ++#endif ++ ++static inline struct bsp_pwm_chip *to_bsp_pwm_chip(struct pwm_chip *chip) ++{ ++ return container_of(chip, struct bsp_pwm_chip, chip); ++} ++ ++static void bsp_pwm_set_bits(void __iomem *base, u32 offset, ++ u32 mask, u32 data) ++{ ++ void __iomem *address = base + offset; ++ u32 value; ++ ++ value = readl(address); ++ value &= ~mask; ++ value |= (data & mask); ++ writel(value, address); ++} ++ ++static void bsp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct bsp_pwm_chip *bsp_pwm_chip = to_bsp_pwm_chip(chip); ++ ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_ctrl_addr(pwm->hwpwm), ++ PWM_ENABLE_MASK, 0x1); ++} ++ ++static void bsp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct bsp_pwm_chip *bsp_pwm_chip = to_bsp_pwm_chip(chip); ++ ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_ctrl_addr(pwm->hwpwm), ++ PWM_ENABLE_MASK, 0x0); ++} ++ ++static bool bsp_pwm_is_complementary_chn(pwm_controller_index controller_index, pwm_chn_index chn_index) ++{ ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ if (((controller_index == PWM_CONTROLLER_0) && (chn_index == PWM_CHN_15)) || ++ ((controller_index == PWM_CONTROLLER_1) && ++ ((chn_index == PWM_CHN_0) || (chn_index == PWM_CHN_1)))) { ++ return 1; ++ } ++#endif ++ return 0; ++} ++ ++static void bsp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, ++ const struct pwm_state *state, unsigned int period_ns) ++{ ++ struct bsp_pwm_chip *bsp_pwm_chip = to_bsp_pwm_chip(chip); ++ u64 freq, period, duty, duty1, duty2; ++ ++ freq = div_u64(clk_get_rate(bsp_pwm_chip->clk), 1000000); ++ ++ period = div_u64(freq * period_ns, 1000); ++ duty = div_u64(period * state->duty_cycle, period_ns); ++ duty1 = div_u64(period * state->duty_cycle1, period_ns); ++ duty2 = div_u64(period * state->duty_cycle2, period_ns); ++ ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_ctrl_addr(pwm->hwpwm), ++ PWM_PRE_DIV_SEL_MASK, (PWM_PRE_DIV_1 << PWM_PRE_DIV_SEL_SHIFT)); ++#endif ++ ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_period_cfg_addr(pwm->hwpwm), ++ PWM_PERIOD_MASK, period); ++ ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_duty0_cfg_addr(pwm->hwpwm), ++ PWM_DUTY_MASK, duty); ++ ++ if (bsp_pwm_is_complementary_chn(bsp_pwm_chip->controller_index, pwm->hwpwm) == 1) { ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_duty1_cfg_addr(pwm->hwpwm), ++ PWM_DUTY_MASK, duty1); ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_duty2_cfg_addr(pwm->hwpwm), ++ PWM_DUTY_MASK, duty2); ++ } ++} ++ ++static void bsp_pwm_set_polarity(struct pwm_chip *chip, ++ struct pwm_device *pwm, ++ enum pwm_polarity polarity) ++{ ++ struct bsp_pwm_chip *bsp_pwm_chip = to_bsp_pwm_chip(chip); ++ ++ if (polarity == PWM_POLARITY_INVERSED) ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_ctrl_addr(pwm->hwpwm), ++ PWM_POLARITY_MASK, (0x1 << PWM_POLARITY_SHIFT)); ++ else ++ bsp_pwm_set_bits(bsp_pwm_chip->base, pwm_ctrl_addr(pwm->hwpwm), ++ PWM_POLARITY_MASK, (0x0 << PWM_POLARITY_SHIFT)); ++} ++ ++static void bsp_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, ++ struct pwm_state *state) ++{ ++ struct bsp_pwm_chip *bsp_pwm_chip = to_bsp_pwm_chip(chip); ++ void __iomem *base; ++ u32 freq, value; ++ ++ freq = div_u64(clk_get_rate(bsp_pwm_chip->clk), 1000000); ++ base = bsp_pwm_chip->base; ++ value = readl(base + pwm_period_cfg_addr(pwm->hwpwm)); ++ state->period = div_u64(value * 1000, freq); ++ ++ value = readl(base + pwm_duty0_cfg_addr(pwm->hwpwm)); ++ state->duty_cycle = div_u64(value * 1000, freq); ++ ++ if (bsp_pwm_is_complementary_chn(bsp_pwm_chip->controller_index, pwm->hwpwm) == 1) { ++ value = readl(base + pwm_duty1_cfg_addr(pwm->hwpwm)); ++ state->duty_cycle1 = div_u64(value * 1000, freq); ++ ++ value = readl(base + pwm_duty2_cfg_addr(pwm->hwpwm)); ++ state->duty_cycle2 = div_u64(value * 1000, freq); ++ } ++ ++ value = readl(base + pwm_ctrl_addr(pwm->hwpwm)); ++ state->enabled = (PWM_ENABLE_MASK & value); ++} ++ ++static int bsp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ++ const struct pwm_state *state) ++{ ++ if (state->polarity != pwm->state.polarity) ++ bsp_pwm_set_polarity(chip, pwm, state->polarity); ++ ++ if (state->period != pwm->state.period || ++ state->duty_cycle != pwm->state.duty_cycle || ++ state->duty_cycle1 != pwm->state.duty_cycle1 || ++ state->duty_cycle2 != pwm->state.duty_cycle2) ++ bsp_pwm_config(chip, pwm, state, state->period); ++ ++ if (state->enabled != pwm->state.enabled) { ++ if (state->enabled) ++ bsp_pwm_enable(chip, pwm); ++ else ++ bsp_pwm_disable(chip, pwm); ++ } ++ ++ return 0; ++} ++ ++static const struct pwm_ops bsp_pwm_ops = { ++ .get_state = bsp_pwm_get_state, ++ .apply = bsp_pwm_apply, ++ ++ .owner = THIS_MODULE, ++}; ++ ++static void bsp_pwm_probe_set_chip_ops(struct platform_device *pdev, struct bsp_pwm_chip *pwm_chip, int chip_loop) ++{ ++ pwm_chip->chip.ops = &bsp_pwm_ops; ++ pwm_chip->chip.dev = &pdev->dev; ++ pwm_chip->chip.base = -1; ++ pwm_chip->chip.npwm = pwm_soc[chip_loop].num_pwms; ++ pwm_chip->chip.of_xlate = of_pwm_xlate_with_flags; ++ pwm_chip->chip.of_pwm_n_cells = 3; ++} ++ ++static int bsp_pwm_probe(struct platform_device *pdev) ++{ ++ struct bsp_pwm_chip *pwm_chip, *pwm_chip_tmp; ++ struct resource *res; ++ int ret; ++ int i; ++ int chip_loop; ++ const char *pwm_name = NULL; ++ ++ pwm_chip_tmp = devm_kzalloc(&pdev->dev, sizeof(*pwm_chip_tmp) * CHIP_PWM_NUM, GFP_KERNEL); ++ if (pwm_chip_tmp == NULL) ++ return -ENOMEM; ++ ++ for (chip_loop = 0; chip_loop < CHIP_PWM_NUM; chip_loop++) { ++ pwm_chip = pwm_chip_tmp + chip_loop; ++ pwm_name = pwm_soc[chip_loop].pwm_name; ++ pwm_chip->controller_index = chip_loop; ++ pwm_chip->clk = devm_clk_get(&pdev->dev, pwm_name); ++ if (IS_ERR(pwm_chip->clk)) { ++ dev_err(&pdev->dev, "getting clock failed with %ld\n", ++ PTR_ERR(pwm_chip->clk)); ++ return PTR_ERR(pwm_chip->clk); ++ } ++ ++ bsp_pwm_probe_set_chip_ops(pdev, pwm_chip, chip_loop); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pwm_name); ++ pwm_chip->base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(pwm_chip->base)) ++ return PTR_ERR(pwm_chip->base); ++ ++ ret = clk_prepare_enable(pwm_chip->clk); ++ if (ret < 0) ++ return ret; ++ ++ pwm_chip->rstc = devm_reset_control_get_exclusive(&pdev->dev, pwm_name); ++ if (IS_ERR(pwm_chip->rstc)) { ++ clk_disable_unprepare(pwm_chip->clk); ++ return PTR_ERR(pwm_chip->rstc); ++ } ++ ++ reset_control_assert(pwm_chip->rstc); ++ msleep(30); ++ reset_control_deassert(pwm_chip->rstc); ++ ++ ret = pwmchip_add(&pwm_chip->chip); ++ if (ret < 0) { ++ clk_disable_unprepare(pwm_chip->clk); ++ return ret; ++ } ++ ++ for (i = 0; i < pwm_chip->chip.npwm; i++) { ++ bsp_pwm_set_bits(pwm_chip->base, pwm_ctrl_addr(i), ++ PWM_KEEP_MASK, (0x1 << PWM_KEEP_SHIFT)); ++ } ++ } ++ ++ platform_set_drvdata(pdev, pwm_chip_tmp); ++ ++ return 0; ++} ++ ++static int bsp_pwm_remove(struct platform_device *pdev) ++{ ++ int ret = 0; ++ int chip_loop; ++ struct bsp_pwm_chip *pwm_chip; ++ struct bsp_pwm_chip *pwm_chip_tmp; ++ ++ pwm_chip_tmp = platform_get_drvdata(pdev); ++ ++ for (chip_loop = 0; chip_loop < CHIP_PWM_NUM; chip_loop++) { ++ pwm_chip = pwm_chip_tmp + chip_loop; ++ reset_control_assert(pwm_chip->rstc); ++ msleep(30); ++ reset_control_deassert(pwm_chip->rstc); ++ ++ clk_disable_unprepare(pwm_chip->clk); ++ ++ ret |= pwmchip_remove(&pwm_chip->chip); ++ } ++ return ret; ++} ++ ++static const struct of_device_id bsp_pwm_of_match[] = { ++ { .compatible = "vendor,pwm", .data = &pwm_soc[0] }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(of, bsp_pwm_of_match); ++ ++static struct platform_driver bsp_pwm_driver = { ++ .driver = { ++ .name = "bsp-pwm", ++ .of_match_table = bsp_pwm_of_match, ++ }, ++ .probe = bsp_pwm_probe, ++ .remove = bsp_pwm_remove, ++}; ++module_platform_driver(bsp_pwm_driver); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/pwm/sysfs.c b/drivers/pwm/sysfs.c +index 9903c3a7eced..ab108b4a12a7 100644 +--- a/drivers/pwm/sysfs.c ++++ b/drivers/pwm/sysfs.c +@@ -103,6 +103,80 @@ static ssize_t duty_cycle_store(struct device *child, + return ret ? : size; + } + ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ ++static ssize_t duty_cycle1_show(struct device *child, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ const struct pwm_device *pwm = child_to_pwm_device(child); ++ struct pwm_state state; ++ ++ pwm_get_state(pwm, &state); ++ ++ return sprintf(buf, "%u\n", state.duty_cycle1); ++} ++ ++static ssize_t duty_cycle1_store(struct device *child, ++ struct device_attribute *attr, ++ const char *buf, size_t size) ++{ ++ struct pwm_export *export = child_to_pwm_export(child); ++ struct pwm_device *pwm = export->pwm; ++ struct pwm_state state; ++ unsigned int val; ++ int ret; ++ ++ ret = kstrtouint(buf, 0, &val); ++ if (ret) ++ return ret; ++ ++ mutex_lock(&export->lock); ++ pwm_get_state(pwm, &state); ++ state.duty_cycle1 = val; ++ ret = pwm_apply_state(pwm, &state); ++ mutex_unlock(&export->lock); ++ ++ return ret ? : size; ++} ++ ++static ssize_t duty_cycle2_show(struct device *child, ++ struct device_attribute *attr, ++ char *buf) ++{ ++ const struct pwm_device *pwm = child_to_pwm_device(child); ++ struct pwm_state state; ++ ++ pwm_get_state(pwm, &state); ++ ++ return sprintf(buf, "%u\n", state.duty_cycle2); ++} ++ ++static ssize_t duty_cycle2_store(struct device *child, ++ struct device_attribute *attr, ++ const char *buf, size_t size) ++{ ++ struct pwm_export *export = child_to_pwm_export(child); ++ struct pwm_device *pwm = export->pwm; ++ struct pwm_state state; ++ unsigned int val; ++ int ret; ++ ++ ret = kstrtouint(buf, 0, &val); ++ if (ret) ++ return ret; ++ ++ mutex_lock(&export->lock); ++ pwm_get_state(pwm, &state); ++ state.duty_cycle2 = val; ++ ret = pwm_apply_state(pwm, &state); ++ mutex_unlock(&export->lock); ++ ++ return ret ? : size; ++} ++ ++#endif ++ + static ssize_t enable_show(struct device *child, + struct device_attribute *attr, + char *buf) +@@ -231,6 +305,31 @@ static struct attribute *pwm_attrs[] = { + }; + ATTRIBUTE_GROUPS(pwm); + ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ ++#define PWM_BASE_0 0 ++#define PWM_BASE_16 16 ++ ++#define PWM_COMPLEMENTARY_CHN_0 0 ++#define PWM_COMPLEMENTARY_CHN_1 1 ++#define PWM_COMPLEMENTARY_CHN_15 15 ++ ++static DEVICE_ATTR_RW(duty_cycle1); ++static DEVICE_ATTR_RW(duty_cycle2); ++static struct attribute *pwm_pn_attrs[] = { ++ &dev_attr_period.attr, ++ &dev_attr_duty_cycle.attr, ++ &dev_attr_duty_cycle1.attr, ++ &dev_attr_duty_cycle2.attr, ++ &dev_attr_enable.attr, ++ &dev_attr_polarity.attr, ++ &dev_attr_capture.attr, ++ NULL ++}; ++ATTRIBUTE_GROUPS(pwm_pn); ++ ++#endif ++ + static void pwm_export_release(struct device *child) + { + struct pwm_export *export = child_to_pwm_export(child); +@@ -240,6 +339,9 @@ static void pwm_export_release(struct device *child) + + static int pwm_export_child(struct device *parent, struct pwm_device *pwm) + { ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ struct pwm_chip *chip = dev_get_drvdata(parent); ++#endif + struct pwm_export *export; + char *pwm_prop[2]; + int ret; +@@ -259,7 +361,17 @@ static int pwm_export_child(struct device *parent, struct pwm_device *pwm) + export->child.release = pwm_export_release; + export->child.parent = parent; + export->child.devt = MKDEV(0, 0); +- export->child.groups = pwm_groups; ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ if (((chip->base == PWM_BASE_0) && (pwm->hwpwm == PWM_COMPLEMENTARY_CHN_15)) || ++ ((chip->base == PWM_BASE_16) && ((pwm->hwpwm == PWM_COMPLEMENTARY_CHN_0) || ++ (pwm->hwpwm == PWM_COMPLEMENTARY_CHN_1)))) { ++ export->child.groups = pwm_pn_groups; ++ } else { ++#endif ++ export->child.groups = pwm_groups; ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ } ++#endif + dev_set_name(&export->child, "pwm%u", pwm->hwpwm); + + ret = device_register(&export->child); +diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c +index f7603c209e9d..896e765f078d 100644 +--- a/drivers/spi/spi-pl022.c ++++ b/drivers/spi/spi-pl022.c +@@ -35,6 +35,10 @@ + #include + #include + ++#ifdef CONFIG_ARCH_BSP ++#include ++#include ++#endif + /* + * This macro is used to define some register default values. + * reg is masked with mask, the OR:ed with an (again masked) +@@ -127,6 +131,18 @@ + /* This one is only in the PL023 variant */ + #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13) + ++#ifdef CONFIG_ARCH_BSP ++/* ++ * The Vendor version of this block adds some bits ++ * in SSP_CR1 ++ */ ++#define SSP_CR1_MASK_BIGEND_BSP (0x1UL << 4) ++#define SSP_CR1_MASK_ALTASENS_BSP (0x1UL << 6) ++ ++#define SSP_TX_FIFO_CR(r) (r + 0x28) ++#define SSP_RX_FIFO_CR(r) (r + 0x2C) ++#endif ++ + /* + * SSP Status Register - SSP_SR + */ +@@ -288,6 +304,10 @@ + + #define SPI_POLLING_TIMEOUT 1000 + ++#ifdef CONFIG_ARCH_BSP ++#define PL022_IDS_INDEX_BSP 4 ++#endif ++ + /* + * The type of reading going on on this chip + */ +@@ -330,6 +350,15 @@ struct vendor_data { + bool internal_cs_ctrl; + }; + ++#ifdef CONFIG_ARCH_BSP ++struct cs_data { ++ struct resource res; ++ void __iomem *virt_addr; ++ unsigned int cs_sb; ++ unsigned int cs_mask_bit; ++}; ++#endif ++ + /** + * struct pl022 - This is the private SSP driver data structure + * @adev: AMBA device model hookup +@@ -399,6 +428,9 @@ struct pl022 { + #endif + int cur_cs; + int *chipselects; ++#ifdef CONFIG_ARCH_BSP ++ struct cs_data *cs_data; ++#endif + }; + + /** +@@ -455,13 +487,41 @@ static void null_cs_control(u32 command) + static void internal_cs_control(struct pl022 *pl022, u32 command) + { + u32 tmp; ++#ifdef CONFIG_ARCH_BSP ++ struct amba_device *adev = pl022->adev; ++ struct amba_driver *adrv = container_of(adev->dev.driver, ++ struct amba_driver, drv); ++ ++ if (pl022->vendor->extended_cr && (adev->periphid == ++ adrv->id_table[PL022_IDS_INDEX_BSP].id)) { ++ if (pl022->cs_data) { ++ tmp = readl(pl022->cs_data->virt_addr); ++ tmp &= ~(pl022->cs_data->cs_mask_bit); ++ tmp |= ((u32)pl022->cur_cs) << pl022->cs_data->cs_sb; ++ writel(tmp, pl022->cs_data->virt_addr); ++ } + ++ if (command == SSP_CHIP_SELECT) ++ /* Enable SSP */ ++ writew((readw(SSP_CR1(pl022->virtbase)) | ++ SSP_CR1_MASK_SSE), ++ SSP_CR1(pl022->virtbase)); ++ else ++ /* disable SSP */ ++ writew((readw(SSP_CR1(pl022->virtbase)) & ++ (~SSP_CR1_MASK_SSE)), ++ SSP_CR1(pl022->virtbase)); ++ } else { ++#endif + tmp = readw(SSP_CSR(pl022->virtbase)); + if (command == SSP_CHIP_SELECT) + tmp &= ~BIT(pl022->cur_cs); + else + tmp |= BIT(pl022->cur_cs); + writew(tmp, SSP_CSR(pl022->virtbase)); ++#ifdef CONFIG_ARCH_BSP ++ } ++#endif + } + + static void pl022_cs_control(struct pl022 *pl022, u32 command) +@@ -561,8 +621,16 @@ static int flush(struct pl022 *pl022) + static void restore_state(struct pl022 *pl022) + { + struct chip_data *chip = pl022->cur_chip; ++#ifdef CONFIG_ARCH_BSP ++ struct amba_device *adev = pl022->adev; ++ struct amba_driver *adrv = container_of(adev->dev.driver, ++ struct amba_driver, drv); + ++ if (pl022->vendor->extended_cr && (adev->periphid != ++ adrv->id_table[PL022_IDS_INDEX_BSP].id)) ++#else + if (pl022->vendor->extended_cr) ++#endif + writel(chip->cr0, SSP_CR0(pl022->virtbase)); + else + writew(chip->cr0, SSP_CR0(pl022->virtbase)); +@@ -635,6 +703,15 @@ static void restore_state(struct pl022 *pl022) + GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \ + ) + ++#ifdef CONFIG_ARCH_BSP ++/* Vendor versions extend this register to use all 16 bits */ ++#define DEFAULT_SSP_REG_CR1_BSP ( \ ++ DEFAULT_SSP_REG_CR1 | \ ++ GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_BIGEND_BSP, 4) | \ ++ GEN_MASK_BITS(0x1, SSP_CR1_MASK_ALTASENS_BSP, 6) \ ++) ++#endif ++ + #define DEFAULT_SSP_REG_CPSR ( \ + GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \ + ) +@@ -654,8 +731,22 @@ static void load_ssp_default_config(struct pl022 *pl022) + writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase)); + writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase)); + } else if (pl022->vendor->extended_cr) { ++#ifdef CONFIG_ARCH_BSP ++ struct amba_device *adev = pl022->adev; ++ struct amba_driver *adrv = container_of(adev->dev.driver, ++ struct amba_driver, drv); ++ ++ if (adev->periphid == adrv->id_table[PL022_IDS_INDEX_BSP].id) { ++ writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); ++ writew(DEFAULT_SSP_REG_CR1_BSP, ++ SSP_CR1(pl022->virtbase)); ++ } else { ++#endif + writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase)); + writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase)); ++#ifdef CONFIG_ARCH_BSP ++ } ++#endif + } else { + writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase)); + writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase)); +@@ -1824,7 +1915,11 @@ static const struct pl022_config_chip pl022_default_chip_info = { + .com_mode = POLLING_TRANSFER, + .iface = SSP_INTERFACE_MOTOROLA_SPI, + .hierarchy = SSP_SLAVE, ++#ifdef CONFIG_ARCH_BSP ++ .slave_tx_disable = DRIVE_TX, ++#else + .slave_tx_disable = DO_NOT_DRIVE_TX, ++#endif + .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM, + .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC, + .ctrl_len = SSP_BITS_8, +@@ -1856,6 +1951,13 @@ static int pl022_setup(struct spi_device *spi) + unsigned int bits = spi->bits_per_word; + u32 tmp; + struct device_node *np = spi->dev.of_node; ++#ifdef CONFIG_ARCH_BSP ++ struct amba_device *adev = pl022->adev; ++ struct amba_driver *adrv = container_of(adev->dev.driver, ++ struct amba_driver, drv); ++ writel(0, SSP_TX_FIFO_CR(pl022->virtbase)); ++ writel(0, SSP_RX_FIFO_CR(pl022->virtbase)); ++#endif + + if (!spi->max_speed_hz) + return -EINVAL; +@@ -1877,8 +1979,14 @@ static int pl022_setup(struct spi_device *spi) + if (chip_info == NULL) { + if (np) { + chip_info_dt = pl022_default_chip_info; +- ++#ifdef CONFIG_ARCH_BSP ++ if(pl022->master->slave) ++ chip_info_dt.hierarchy = SSP_SLAVE; ++ else ++ chip_info_dt.hierarchy = SSP_MASTER; ++#else + chip_info_dt.hierarchy = SSP_MASTER; ++#endif + of_property_read_u32(np, "pl022,interface", + &chip_info_dt.iface); + of_property_read_u32(np, "pl022,com-mode", +@@ -1998,7 +2106,12 @@ static int pl022_setup(struct spi_device *spi) + chip->cpsr = clk_freq.cpsdvsr; + + /* Special setup for the ST micro extended control registers */ ++#ifdef CONFIG_ARCH_BSP ++ if (pl022->vendor->extended_cr && (adev->periphid != ++ adrv->id_table[PL022_IDS_INDEX_BSP].id)) { ++#else + if (pl022->vendor->extended_cr) { ++#endif + u32 etx; + + if (pl022->vendor->pl023) { +@@ -2032,6 +2145,22 @@ static int pl022_setup(struct spi_device *spi) + SSP_CR1_MASK_RXIFLSEL_ST, 7); + SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, + SSP_CR1_MASK_TXIFLSEL_ST, 10); ++#ifdef CONFIG_ARCH_BSP ++ } else if (pl022->vendor->extended_cr && (adev->periphid == ++ adrv->id_table[PL022_IDS_INDEX_BSP].id)) { ++ SSP_WRITE_BITS(chip->cr0, bits - 1, ++ SSP_CR0_MASK_DSS, 0); ++ SSP_WRITE_BITS(chip->cr0, chip_info->iface, ++ SSP_CR0_MASK_FRF, 4); ++ ++ if (spi->mode & SPI_LSB_FIRST) ++ tmp = !!SPI_LSB_FIRST; ++ else ++ tmp = !SPI_LSB_FIRST; ++ ++ SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_BIGEND_BSP, 4); ++ SSP_WRITE_BITS(chip->cr1, 0x1, SSP_CR1_MASK_ALTASENS_BSP, 6); ++#endif + } else { + SSP_WRITE_BITS(chip->cr0, bits - 1, + SSP_CR0_MASK_DSS, 0); +@@ -2117,14 +2246,36 @@ pl022_platform_data_dt_get(struct device *dev) + return pd; + } + ++#ifdef CONFIG_ARCH_BSP ++static void try_deassert_spi_reset(struct amba_device *adev) ++{ ++ struct reset_control *spi_rst = NULL; ++ ++ spi_rst = devm_reset_control_get(&adev->dev, "bsp_spi_rst"); ++ if (IS_ERR_OR_NULL(spi_rst)) ++ return; ++ ++ /* deassert reset if "resets" property is set */ ++ dev_info(&adev->dev, "deassert reset\n"); ++ reset_control_deassert(spi_rst); ++} ++#endif ++ + static int pl022_probe(struct amba_device *adev, const struct amba_id *id) + { + struct device *dev = &adev->dev; ++#ifdef CONFIG_ARCH_BSP ++ struct amba_driver *adrv = container_of(adev->dev.driver, ++ struct amba_driver, drv); ++#endif + struct pl022_ssp_controller *platform_info = + dev_get_platdata(&adev->dev); + struct spi_master *master; + struct pl022 *pl022 = NULL; /*Data for this driver */ + struct device_node *np = adev->dev.of_node; ++#ifdef CONFIG_ARCH_BSP ++ unsigned int slave_mode; ++#endif + int status = 0, i, num_cs; + + dev_info(&adev->dev, +@@ -2176,13 +2327,62 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) + master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware; + master->rt = platform_info->rt; + master->dev.of_node = dev->of_node; +- ++#ifdef CONFIG_ARCH_BSP ++ if (of_property_read_u32(np, "vendor,slave_mode", ++ &slave_mode) == 0) { ++ if (slave_mode == 1) { ++ master->slave = true; ++ } else if (slave_mode == 0) { ++ master->slave = false; ++ } else { ++ dev_err(&adev->dev, "spi Master/Slave mode err!!!\n"); ++ goto err_no_gpio; ++ } ++ } ++#endif + if (platform_info->num_chipselect && platform_info->chipselects) { + for (i = 0; i < num_cs; i++) + pl022->chipselects[i] = platform_info->chipselects[i]; + } else if (pl022->vendor->internal_cs_ctrl) { + for (i = 0; i < num_cs; i++) + pl022->chipselects[i] = i; ++ ++#ifdef CONFIG_ARCH_BSP ++ if ((adev->periphid == adrv->id_table[PL022_IDS_INDEX_BSP].id) ++ && pl022->vendor->extended_cr ++ && (num_cs > 1)) { ++ pl022->cs_data = devm_kzalloc(dev, ++ sizeof(struct cs_data), ++ GFP_KERNEL); ++ if (!pl022->cs_data) { ++ status = -ENOMEM; ++ goto err_no_mem; ++ } ++ ++ if (of_address_to_resource(np, 1, ++ &pl022->cs_data->res)) { ++ status = -EPROBE_DEFER; ++ goto err_no_gpio; ++ } ++ ++ if (of_property_read_u32(np, "spi_cs_sb", ++ &pl022->cs_data->cs_sb)) { ++ status = -EPROBE_DEFER; ++ goto err_no_gpio; ++ } ++ ++ if (of_property_read_u32(np, "spi_cs_mask_bit", ++ &pl022->cs_data->cs_mask_bit)) { ++ status = -EPROBE_DEFER; ++ goto err_no_gpio; ++ } ++ ++ pl022->cs_data->virt_addr = devm_ioremap(dev, ++ pl022->cs_data->res.start, ++ resource_size(&pl022->cs_data->res)); ++ } else ++ pl022->cs_data = NULL; ++#endif + } else if (IS_ENABLED(CONFIG_OF)) { + for (i = 0; i < num_cs; i++) { + int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); +@@ -2243,6 +2443,9 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) + dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n"); + goto err_no_clk_en; + } ++#ifdef CONFIG_ARCH_BSP ++ try_deassert_spi_reset(adev); ++#endif + + /* Initialize transfer pump */ + tasklet_init(&pl022->pump_transfers, pump_transfers, +@@ -2309,6 +2512,10 @@ static int pl022_probe(struct amba_device *adev, const struct amba_id *id) + err_no_ioremap: + amba_release_regions(adev); + err_no_ioregion: ++#ifdef CONFIG_ARCH_BSP ++ if (pl022->cs_data) ++ devm_iounmap(&adev->dev, pl022->cs_data->virt_addr); ++#endif + err_no_gpio: + err_no_mem: + spi_master_put(master); +@@ -2335,6 +2542,10 @@ pl022_remove(struct amba_device *adev) + + clk_disable_unprepare(pl022->clk); + amba_release_regions(adev); ++#ifdef CONFIG_ARCH_BSP ++ if (pl022->cs_data) ++ devm_iounmap(&adev->dev, pl022->cs_data->virt_addr); ++#endif + tasklet_disable(&pl022->pump_transfers); + } + +@@ -2445,6 +2656,17 @@ static struct vendor_data vendor_lsi = { + .internal_cs_ctrl = true, + }; + ++#ifdef CONFIG_ARCH_BSP ++static struct vendor_data vendor_bsp = { ++ .fifodepth = 256, ++ .max_bpw = 16, ++ .unidir = false, ++ .extended_cr = true, ++ .pl023 = false, ++ .loopback = true, ++ .internal_cs_ctrl = true, ++}; ++#endif + static const struct amba_id pl022_ids[] = { + { + /* +@@ -2485,6 +2707,17 @@ static const struct amba_id pl022_ids[] = { + .mask = 0x000fffff, + .data = &vendor_lsi, + }, ++#ifdef CONFIG_ARCH_BSP ++ { ++ /* ++ * Vendor derivative, this has a 16bit wide ++ * and 256 locations deep TX/RX FIFO ++ */ ++ .id = 0x00800022, ++ .mask = 0xffffffff, ++ .data = &vendor_bsp, ++ }, ++#endif + { 0, 0 }, + }; + +diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile +index ae86da0dc5bd..2f721d2cc8a5 100644 +--- a/drivers/usb/dwc3/Makefile ++++ b/drivers/usb/dwc3/Makefile +@@ -2,9 +2,9 @@ + # define_trace.h needs to know how to find our header + CFLAGS_trace.o := -I$(src) + +-obj-$(CONFIG_USB_DWC3) += dwc3.o ++obj-$(CONFIG_USB_DWC3) += dwc3.o dwc3-bsp.o + +-dwc3-y := core.o ++dwc3-y := core.o proc.o + + ifneq ($(CONFIG_TRACING),) + dwc3-y += trace.o +diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c +index d73f624ed42a..f7cd5400b5d4 100644 +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -39,6 +39,23 @@ + #include "debug.h" + + #define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000 /* ms */ ++#ifdef CONFIG_ARCH_BSP ++#include "dwc3-bsp.h" ++ ++/* ++ * Default to the number of outstanding pipelined transfer ++ * requests is 0x3[11:8], modify the field change to 0x7. ++ */ ++static void dwc3_outstanding_pipe_choose(struct dwc3 *dwc) ++{ ++ u32 reg; ++ ++ reg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG1); ++ reg &= ~DWC3_PIPE_TRANS_LIMIT_MASK; ++ reg |= DWC3_PIPE_TRANS_LIMIT; ++ dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, reg); ++} ++#endif + + /** + * dwc3_get_dr_mode - Validates and sets dr_mode +@@ -1308,7 +1325,12 @@ static void dwc3_get_properties(struct dwc3 *dwc) + */ + hird_threshold = 12; + ++#ifdef CONFIG_ARCH_BSP ++ dwc->maximum_speed = usb_get_max_speed(dev); ++#else + dwc->maximum_speed = usb_get_maximum_speed(dev); ++#endif ++ + dwc->dr_mode = usb_get_dr_mode(dev); + dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node); + +@@ -1344,6 +1366,10 @@ static void dwc3_get_properties(struct dwc3 *dwc) + device_property_read_u8(dev, "snps,tx-max-burst-prd", + &tx_max_burst_prd); + ++#ifdef CONFIG_ARCH_BSP ++ dwc->usb2_lpm_disable = device_property_read_bool(dev, ++ "snps,usb2-lpm-disable"); ++#endif + dwc->disable_scramble_quirk = device_property_read_bool(dev, + "snps,disable_scramble_quirk"); + dwc->u2exit_lfps_quirk = device_property_read_bool(dev, +@@ -1380,7 +1406,17 @@ static void dwc3_get_properties(struct dwc3 *dwc) + "snps,dis-tx-ipgap-linecheck-quirk"); + dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, + "snps,parkmode-disable-ss-quirk"); +- ++#ifdef CONFIG_ARCH_BSP ++ dwc->dis_initiate_u1 = device_property_read_bool(dev, ++ "snps,dis_initiate_u1"); ++ dwc->dis_initiate_u2 = device_property_read_bool(dev, ++ "snps,dis_initiate_u2"); ++ ++ dwc->eps_new_init = device_property_read_bool(dev, ++ "snps,eps_new_init"); ++ device_property_read_u32(dev, "eps_directions", ++ &dwc->eps_directions); ++#endif + dwc->tx_de_emphasis_quirk = device_property_read_bool(dev, + "snps,tx_de_emphasis_quirk"); + device_property_read_u8(dev, "snps,tx_de_emphasis", +@@ -1564,6 +1600,12 @@ static int dwc3_probe(struct platform_device *pdev) + platform_set_drvdata(pdev, dwc); + dwc3_cache_hwparams(dwc); + ++#ifdef CONFIG_ARCH_BSP ++ device_property_read_u32_array(dev, "eps_map", ++ dwc->dwceps_map_to_usbeps, ++ DWC3_NUM_EPS(&dwc->hwparams)); ++#endif ++ + spin_lock_init(&dwc->lock); + mutex_init(&dwc->mutex); + +@@ -1599,6 +1641,9 @@ static int dwc3_probe(struct platform_device *pdev) + goto err4; + } + ++#ifdef CONFIG_ARCH_BSP ++ dwc3_outstanding_pipe_choose(dwc); ++#endif + dwc3_check_params(dwc); + dwc3_debugfs_init(dwc); + +@@ -1608,6 +1653,10 @@ static int dwc3_probe(struct platform_device *pdev) + + pm_runtime_put(dev); + ++#ifdef CONFIG_ARCH_BSP ++ bsp_dwc3_exited(); ++ dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); ++#endif + return 0; + + err5: +diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h +index cbebe541f7e8..24e874afd7d9 100644 +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -32,6 +32,10 @@ + #include + + #define DWC3_MSG_MAX 500 ++#ifdef CONFIG_ARCH_BSP ++#define DWC3_PIPE_TRANS_LIMIT_MASK (0xf << 8) ++#define DWC3_PIPE_TRANS_LIMIT (0x7 << 8) ++#endif + + /* Global constants */ + #define DWC3_PULL_UP_TIMEOUT 500 /* ms */ +@@ -477,6 +481,10 @@ + #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18) + + #define DWC3_DSTS_RXFIFOEMPTY BIT(17) ++#ifdef CONFIG_ARCH_BSP ++#define DWC3_EVENT_PRAM_MAX_SOFFN 0x3fff ++#define DWC3_EVENT_PRAM_SOFFN_MASK 0x3fff ++#endif + + #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3) + #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3) +@@ -658,7 +666,11 @@ struct dwc3_event_buffer { + #define DWC3_EP_DIRECTION_TX true + #define DWC3_EP_DIRECTION_RX false + ++#ifdef CONFIG_ARCH_BSP ++#define DWC3_TRB_NUM 4096 ++#else + #define DWC3_TRB_NUM 256 ++#endif + + /** + * struct dwc3_ep - device side endpoint representation +@@ -726,8 +738,13 @@ struct dwc3_ep { + * By using u8 types we ensure that our % operator when incrementing + * enqueue and dequeue get optimized away by the compiler. + */ ++#ifdef CONFIG_ARCH_BSP ++ u32 trb_enqueue; ++ u32 trb_dequeue; ++#else + u8 trb_enqueue; + u8 trb_dequeue; ++#endif + + u8 number; + u8 type; +@@ -1093,6 +1110,10 @@ struct dwc3 { + struct dwc3_event_buffer *ev_buf; + struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM]; + ++#ifdef CONFIG_ARCH_BSP ++ u32 dwceps_map_to_usbeps[DWC3_ENDPOINTS_NUM]; ++#endif ++ + struct usb_gadget *gadget; + struct usb_gadget_driver *gadget_driver; + +@@ -1201,6 +1222,14 @@ struct dwc3 { + + u8 num_eps; + ++#ifdef CONFIG_ARCH_BSP ++/* ++ * NOTICE: eps_directions bitmap[0~31] 0: out ep, 1: in ep ++ * and used with total ep numbers(num_out_eps + num_in_eps) ++ */ ++#define DWC3_EPS_DEFAULT_DIRECTIONS 0xaaaaaaaa ++ u32 eps_directions; ++#endif + struct dwc3_hwparams hwparams; + struct dentry *root; + struct debugfs_regset32 *regset; +@@ -1216,6 +1245,13 @@ struct dwc3 { + u8 tx_thr_num_pkt_prd; + u8 tx_max_burst_prd; + ++ struct proc_dir_entry* parent_entry; ++ struct proc_dir_entry* csts_entry; ++ u8 udc_connect_status; ++#define UDC_DISCONNECTED 0 ++#define UDC_CONNECT_HOST 1 ++#define UDC_CONNECT_CHARGER 2 ++ + const char *hsphy_interface; + + unsigned connected:1; +@@ -1256,6 +1292,12 @@ struct dwc3 { + unsigned dis_tx_ipgap_linecheck_quirk:1; + unsigned parkmode_disable_ss_quirk:1; + ++#ifdef CONFIG_ARCH_BSP ++ unsigned dis_initiate_u1:1; ++ unsigned dis_initiate_u2:1; ++ unsigned eps_new_init:1; ++#endif ++ + unsigned tx_de_emphasis_quirk:1; + unsigned tx_de_emphasis:2; + +@@ -1523,6 +1565,11 @@ static inline void dwc3_otg_host_init(struct dwc3 *dwc) + { } + #endif + ++#ifdef CONFIG_ARCH_BSP ++int dwc3_proc_init(struct dwc3 *dwc); ++int dwc3_proc_shutdown(struct dwc3 *dwc); ++#endif ++ + /* power management interface */ + #if !IS_ENABLED(CONFIG_USB_DWC3_HOST) + int dwc3_gadget_suspend(struct dwc3 *dwc); +diff --git a/drivers/usb/dwc3/dwc3-bsp.c b/drivers/usb/dwc3/dwc3-bsp.c +new file mode 100644 +index 000000000000..503c8f4df07f +--- /dev/null ++++ b/drivers/usb/dwc3/dwc3-bsp.c +@@ -0,0 +1,441 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++* ++* Copyright (c) 2012-2018 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "dwc3-bsp.h" ++ ++#define USB3_CTRL 0x190 ++#define REG_SYS_STAT 0x8c ++#define PCIE_USB3_MODE_MASK (0x3 << 12) ++#define USB3_PCLK_OCC_SEL (0x1 << 30) ++ ++#define PERI_USB3_GTXTHRCFG 0x2310000 ++ ++#define REG_GUSB3PIPECTL0 0xc2c0 ++#define GTXTHRCFG 0xc108 ++ ++#define PCS_SSP_SOFT_RESET (0x1 << 31) ++#define SUSPEND_USB3_SS_PHY (0x1 << 17) ++ ++#define GUSB2PHYCFG_OFFSET 0xc200 ++#define GCTL_OFFSET 0xc110 ++#define GUCTL_OFFSET 0xc12C ++#define GFLADJ_OFFSET 0xc630 ++ ++#define U2_FREECLK_EXISTS (0x1 << 30) ++#define SOFITPSYNC (0x1 << 10) ++#define REFCLKPER_MASK 0xffc00000 ++#define REFCLKPER_VAL 0x29 ++#define set_refclkper(a) (((a) << 22) & REFCLKPER_MASK) ++ ++#define PLS1 (0x1 << 31) ++#define DECR_MASK 0x7f000000 ++#define DECR_VAL 0xa ++#define set_decr(a) (((a) << 24) & DECR_MASK) ++ ++#define LPM_SEL (0x1 << 23) ++#define FLADJ_MASK 0x003fff00 ++#define FLADJ_VAL 0x7f0 ++#define set_fladj(a) (((a) << 8) & FLADJ_MASK) ++ ++/* ss919v100 */ ++#define DOUBLE_PCIE_MODE 0x0 ++#define P0_PCIE_ADD_P1_USB3 (0x1 << 12) ++#define DOUBLE_USB3 (0x2 << 12) ++ ++/* ss318v100,ss918v100 */ ++#define PCIE_X1_MODE (0x0 << 12) ++#define USB3_MODE (0x1 << 12) ++ ++static struct bsp_priv *usb_priv = NULL; ++ ++#if defined(CONFIG_ARCH_SS919V100) || defined(CONFIG_ARCH_SS015V100) ++static int speed_adapt_for_ss919v100(struct device_node *np) ++{ ++ unsigned int ret; ++ unsigned int reg; ++ ++ if (np == NULL) ++ return -EINVAL; ++ ++ usb_priv->speed_id = -1; ++ ++ reg = readl(usb_priv->sys_ctrl + REG_SYS_STAT); ++ reg &= PCIE_USB3_MODE_MASK; ++ ++ switch (reg) { ++ case DOUBLE_PCIE_MODE: ++ ret = USB_SPEED_HIGH; ++ break; ++ case P0_PCIE_ADD_P1_USB3: ++ if (of_property_read_u32(np, "port_speed", &usb_priv->speed_id)) ++ usb_priv->speed_id = -1; ++ ++ if (usb_priv->speed_id == 0) ++ ret = USB_SPEED_HIGH; ++ else if (usb_priv->speed_id == 1) ++ ret = USB_SPEED_SUPER; ++ else ++ ret = USB_SPEED_UNKNOWN; ++ ++ break; ++ case DOUBLE_USB3: ++ ret = USB_SPEED_SUPER; ++ break; ++ default: ++ ret = USB_SPEED_UNKNOWN; ++ } ++ ++ return ret; ++} ++#endif ++ ++#if defined(CONFIG_ARCH_SS318V100) || defined(CONFIG_ARCH_SS918V100) ++static int speed_adapt_for_ss318v100(struct device *dev) ++{ ++ unsigned int ret; ++ unsigned int reg; ++ ++ if (dev == NULL) ++ return -EINVAL; ++ ++ reg = readl(usb_priv->sys_ctrl + REG_SYS_STAT); ++ reg &= PCIE_USB3_MODE_MASK; ++ ++ if (reg == PCIE_X1_MODE) ++ ret = USB_SPEED_HIGH; ++ else ++ ret = usb_get_maximum_speed(dev); ++ ++ return ret; ++} ++#endif ++ ++int usb_get_max_speed(struct device *dev) ++{ ++ unsigned int ret; ++ struct device_node *np = dev->of_node; ++ ++ if (np == NULL) ++ return -EINVAL; ++ ++ usb_priv = kzalloc(sizeof(struct bsp_priv), GFP_KERNEL); ++ if (usb_priv == NULL) ++ return -ENOMEM; ++ ++ usb_priv->peri_crg = of_iomap(np, DEV_NODE_FLAG1); ++ if (IS_ERR(usb_priv->peri_crg)) { ++ kfree(usb_priv); ++ usb_priv = NULL; ++ return -ENOMEM; ++ } ++ ++ usb_priv->sys_ctrl = of_iomap(np, DEV_NODE_FLAG2); ++ if (IS_ERR(usb_priv->sys_ctrl)) { ++ iounmap(usb_priv->peri_crg); ++ ++ kfree(usb_priv); ++ usb_priv = NULL; ++ return -ENOMEM; ++ } ++ ++#if defined(CONFIG_ARCH_SS919V100) || defined(CONFIG_ARCH_SS015V100) ++ ret = speed_adapt_for_ss919v100(np); ++#elif defined(CONFIG_ARCH_SS318V100) || defined(CONFIG_ARCH_SS918V100) ++ ret = speed_adapt_for_ss318v100(dev); ++#else ++ ret = usb_get_maximum_speed(dev); ++#endif ++ ++ iounmap(usb_priv->sys_ctrl); ++ iounmap(usb_priv->peri_crg); ++ ++ return ret; ++} ++EXPORT_SYMBOL(usb_get_max_speed); ++ ++void bsp_dwc3_exited(void) ++{ ++ if (usb_priv == NULL) ++ return; ++ ++ kfree(usb_priv); ++ usb_priv = NULL; ++} ++EXPORT_SYMBOL(bsp_dwc3_exited); ++ ++static int set_ctrl_crg_val(struct device_node *np, struct dwc3_bsp *bsp) ++{ ++ unsigned int ret; ++ unsigned int reg; ++ ++ if ((np == NULL) || (bsp == NULL)) ++ return -EINVAL; ++ ++ /* get usb ctrl crg para */ ++ ret = of_property_read_u32(np, "crg_offset", &bsp->crg_offset); ++ if (ret) ++ return ret; ++ ++ ret = of_property_read_u32(np, "crg_ctrl_def_mask", &bsp->crg_ctrl_def_mask); ++ if (ret) ++ return ret; ++ ++ ret = of_property_read_u32(np, "crg_ctrl_def_val", &bsp->crg_ctrl_def_val); ++ if (ret) ++ return ret; ++ ++ /* write usb ctrl crg default value */ ++ reg = readl(bsp->crg_base + bsp->crg_offset); ++ reg &= ~bsp->crg_ctrl_def_mask; ++ reg |= bsp->crg_ctrl_def_val; ++ writel(reg, bsp->crg_base + bsp->crg_offset); ++ ++ return 0; ++} ++ ++static int dwc3_bsp_clk_init(struct dwc3_bsp *bsp, int count) ++{ ++ struct device *dev = bsp->dev; ++ struct device_node *np = dev->of_node; ++ int i, ret; ++ ++ if (!count) ++ return -EINVAL; ++ ++ if (np == NULL) ++ return -EINVAL; ++ ++ bsp->num_clocks = count; ++ ++ bsp->clks = devm_kcalloc(dev, bsp->num_clocks, sizeof(struct clk *), ++ GFP_KERNEL); ++ if (bsp->clks == NULL) ++ return -ENOMEM; ++ ++ for (i = 0; i < bsp->num_clocks; i++) { ++ struct clk *clk; ++ ++ clk = of_clk_get(np, i); ++ if (IS_ERR(clk)) { ++ while (--i >= 0) ++ clk_put(bsp->clks[i]); ++ ++ ret = PTR_ERR(clk); ++ goto clk_free; ++ } ++ ++ ret = clk_prepare_enable(clk); ++ if (ret < 0) { ++ while (--i >= 0) { ++ clk_disable_unprepare(bsp->clks[i]); ++ clk_put(bsp->clks[i]); ++ } ++ clk_put(clk); ++ ++ goto clk_free; ++ } ++ ++ bsp->clks[i] = clk; ++ } ++ ++ return 0; ++clk_free: ++ devm_kfree(dev, bsp->clks); ++ bsp->clks = NULL; ++ ++ return ret; ++} ++ ++static void control_free_clk_config(struct dwc3_bsp *bsp) ++{ ++ unsigned int reg; ++ ++ if (bsp == NULL) ++ return; ++ ++ reg = readl(bsp->ctrl_base + GUSB2PHYCFG_OFFSET); ++ reg &= ~U2_FREECLK_EXISTS; ++ writel(reg, bsp->ctrl_base + GUSB2PHYCFG_OFFSET); ++ ++ reg = readl(bsp->ctrl_base + GCTL_OFFSET); ++ reg &= ~SOFITPSYNC; ++ writel(reg, bsp->ctrl_base + GCTL_OFFSET); ++ ++ reg = readl(bsp->ctrl_base + GUCTL_OFFSET); ++ reg &= ~REFCLKPER_MASK; ++ reg |= set_refclkper(REFCLKPER_VAL); ++ writel(reg, bsp->ctrl_base + GUCTL_OFFSET); ++ ++ reg = readl(bsp->ctrl_base + GFLADJ_OFFSET); ++ reg &= ~PLS1; ++ writel(reg, bsp->ctrl_base + GFLADJ_OFFSET); ++ ++ reg = readl(bsp->ctrl_base + GFLADJ_OFFSET); ++ reg &= ~DECR_MASK; ++ reg |= set_decr(DECR_VAL); ++ writel(reg, bsp->ctrl_base + GFLADJ_OFFSET); ++ ++ reg = readl(bsp->ctrl_base + GFLADJ_OFFSET); ++ reg |= LPM_SEL; ++ writel(reg, bsp->ctrl_base + GFLADJ_OFFSET); ++ ++ reg = readl(bsp->ctrl_base + GFLADJ_OFFSET); ++ reg &= ~FLADJ_MASK; ++ reg |= set_fladj(FLADJ_VAL); ++ writel(reg, bsp->ctrl_base + GFLADJ_OFFSET); ++} ++ ++static int dwc3_bsp_iomap(struct device_node *np, struct dwc3_bsp *bsp) ++{ ++ if ((np == NULL) || (bsp == NULL)) ++ return -EINVAL; ++ ++ bsp->ctrl_base = of_iomap(np, DEV_NODE_FLAG0); ++ if (IS_ERR(bsp->ctrl_base)) ++ return -ENOMEM; ++ ++ bsp->crg_base = of_iomap(np, DEV_NODE_FLAG1); ++ if (IS_ERR(bsp->crg_base)) { ++ iounmap(bsp->ctrl_base); ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int dwc3_bsp_probe(struct platform_device *pdev) ++{ ++ struct dwc3_bsp *bsp = NULL; ++ struct device *dev = &pdev->dev; ++ struct device_node *np = dev->of_node; ++ int ret, i; ++ ++ bsp = devm_kzalloc(dev, sizeof(*bsp), GFP_KERNEL); ++ if (bsp == NULL) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, bsp); ++ bsp->dev = dev; ++ ++ ret = dwc3_bsp_iomap(np, bsp); ++ if (ret) { ++ devm_kfree(dev, bsp); ++ bsp = NULL; ++ ++ return -ENOMEM; ++ } ++ ++ bsp->port_rst = devm_reset_control_get(dev, "vcc_reset"); ++ if (IS_ERR_OR_NULL(bsp->port_rst)) { ++ ret = PTR_ERR(bsp->port_rst); ++ goto dwc3_unmap; ++ } ++ ++ ret = set_ctrl_crg_val(np, bsp); ++ if (ret) ++ goto dwc3_unmap; ++ ++ reset_control_assert(bsp->port_rst); ++ ++ ret = dwc3_bsp_clk_init(bsp, of_clk_get_parent_count(np)); ++ if (ret) ++ goto dwc3_unmap; ++ ++ reset_control_deassert(bsp->port_rst); ++ ++ control_free_clk_config(bsp); ++ ++ udelay(U_LEVEL2); ++ ++ ret = of_platform_populate(np, NULL, NULL, dev); ++ if (ret) { ++ for (i = 0; i < bsp->num_clocks; i++) { ++ clk_disable_unprepare(bsp->clks[i]); ++ clk_put(bsp->clks[i]); ++ } ++ goto dwc3_unmap; ++ } ++ ++ return 0; ++dwc3_unmap: ++ iounmap(bsp->ctrl_base); ++ iounmap(bsp->crg_base); ++ ++ devm_kfree(dev, bsp); ++ bsp = NULL; ++ ++ return ret; ++} ++ ++static int dwc3_bsp_remove(struct platform_device *pdev) ++{ ++ struct dwc3_bsp *bsp = platform_get_drvdata(pdev); ++ struct device *dev = &pdev->dev; ++ int i; ++ ++ for (i = 0; i < bsp->num_clocks; i++) { ++ clk_disable_unprepare(bsp->clks[i]); ++ clk_put(bsp->clks[i]); ++ } ++ ++ reset_control_assert(bsp->port_rst); ++ ++ of_platform_depopulate(dev); ++ ++ iounmap(bsp->ctrl_base); ++ iounmap(bsp->crg_base); ++ ++ devm_kfree(dev, bsp); ++ bsp = NULL; ++ ++ return 0; ++} ++ ++static const struct of_device_id bsp_dwc3_match[] = { ++ { .compatible = "vendor,dwusb2" }, ++ { .compatible = "vendor,dwusb3" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bsp_dwc3_match); ++ ++static struct platform_driver dwc3_bsp_driver = { ++ .probe = dwc3_bsp_probe, ++ .remove = dwc3_bsp_remove, ++ .driver = { ++ .name = "bsp-dwc3", ++ .of_match_table = bsp_dwc3_match, ++ }, ++}; ++module_platform_driver(dwc3_bsp_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_DESCRIPTION("DesignWare USB3"); +diff --git a/drivers/usb/dwc3/dwc3-bsp.h b/drivers/usb/dwc3/dwc3-bsp.h +new file mode 100644 +index 000000000000..6c146dcb1ce7 +--- /dev/null ++++ b/drivers/usb/dwc3/dwc3-bsp.h +@@ -0,0 +1,47 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++* ++* Copyright (c) 2012-2018 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#ifndef USB_INCLUDE_DWC3_BSP_H ++#define USB_INCLUDE_DWC3_BSP_H ++ ++struct bsp_priv { ++ void __iomem *peri_crg; ++ void __iomem *sys_ctrl; ++ void __iomem *misc_ctrl; ++ unsigned int speed_id; ++}; ++ ++struct dwc3_bsp { ++ struct device *dev; ++ struct clk **clks; ++ int num_clocks; ++ void __iomem *ctrl_base; ++ void __iomem *crg_base; ++ struct reset_control *port_rst; ++ u32 crg_offset; ++ u32 crg_ctrl_def_mask; ++ u32 crg_ctrl_def_val; ++}; ++ ++extern int usb_get_max_speed(struct device *dev); ++extern void bsp_dwc3_exited(void); ++ ++#define DEV_NODE_FLAG0 0 ++#define DEV_NODE_FLAG1 1 ++#define DEV_NODE_FLAG2 2 ++ ++#define U_LEVEL2 200 ++ ++#endif +diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c +index 3cd294264372..df943cbabb3b 100644 +--- a/drivers/usb/dwc3/ep0.c ++++ b/drivers/usb/dwc3/ep0.c +@@ -281,6 +281,26 @@ void dwc3_ep0_out_start(struct dwc3 *dwc) + WARN_ON(ret < 0); + } + ++#ifdef CONFIG_ARCH_BSP ++static u32 dwc3_usbep_to_dwc3ep(struct dwc3 *dwc, u32 num) ++{ ++ u32 res = 0; ++ int i; ++ ++ if (!dwc) ++ return 0; ++ ++ for (i = 0; i < dwc->num_eps; i++) { ++ if (dwc->dwceps_map_to_usbeps[i] == num) { ++ res = i; ++ break; ++ } ++ } ++ ++ return res; ++} ++#endif ++ + static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) + { + struct dwc3_ep *dep; +@@ -291,6 +311,11 @@ static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) + if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) + epnum |= 1; + ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->eps_new_init) ++ epnum = dwc3_usbep_to_dwc3ep(dwc, epnum); ++#endif ++ + dep = dwc->eps[epnum]; + if (dep == NULL) + return NULL; +@@ -385,6 +410,11 @@ static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state, + if (set && dwc->dis_u1_entry_quirk) + return -EINVAL; + ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->dis_initiate_u1) ++ return -EINVAL; ++#endif ++ + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + if (set) + reg |= DWC3_DCTL_INITU1ENA; +@@ -408,6 +438,10 @@ static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state, + return -EINVAL; + if (set && dwc->dis_u2_entry_quirk) + return -EINVAL; ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->dis_initiate_u2) ++ return -EINVAL; ++#endif + + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + if (set) +@@ -638,10 +672,22 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) + * nothing is pending from application. + */ + reg = dwc3_readl(dwc->regs, DWC3_DCTL); ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->dis_initiate_u1) ++ reg &= (~DWC3_DCTL_ACCEPTU1ENA); ++ else ++ reg |= DWC3_DCTL_ACCEPTU1ENA; ++ ++ if (dwc->dis_initiate_u2) ++ reg &= (~DWC3_DCTL_ACCEPTU2ENA); ++ else ++ reg |= DWC3_DCTL_ACCEPTU2ENA; ++#else + if (!dwc->dis_u1_entry_quirk) + reg |= DWC3_DCTL_ACCEPTU1ENA; + if (!dwc->dis_u2_entry_quirk) + reg |= DWC3_DCTL_ACCEPTU2ENA; ++#endif + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + } + break; +diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c +index 28a1194f849f..2f894fa664c2 100644 +--- a/drivers/usb/dwc3/gadget.c ++++ b/drivers/usb/dwc3/gadget.c +@@ -27,6 +27,11 @@ + #include "gadget.h" + #include "io.h" + ++#ifdef CONFIG_ARCH_BSP ++static void dwc3_gadget_sync_connected_status(struct dwc3 *dwc); ++#endif ++ ++ + #define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \ + & ~((d)->interval - 1)) + +@@ -147,7 +152,11 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) + * if it is point to the link TRB, wrap around to the beginning. The + * link TRB is always at the last TRB entry. + */ ++#ifdef CONFIG_ARCH_BSP ++static void dwc3_ep_inc_trb(u32 *index) ++#else + static void dwc3_ep_inc_trb(u8 *index) ++#endif + { + (*index)++; + if (*index == (DWC3_TRB_NUM - 1)) +@@ -606,7 +615,15 @@ static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action) + * so on. We consider the direction bit as part of the physical + * endpoint number. So USB endpoint 0x81 is 0x03. + */ ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->eps_new_init) ++ params.param1 |= ++ DWC3_DEPCFG_EP_NUMBER(dwc->dwceps_map_to_usbeps[dep->number]); ++ else ++ params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); ++#else + params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number); ++#endif + + /* + * We must use the lower 16 TX FIFOs even though +@@ -677,7 +694,14 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action) + dep->flags |= DWC3_EP_ENABLED; + + reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->eps_new_init) ++ reg |= DWC3_DALEPENA_EP(dwc->dwceps_map_to_usbeps[dep->number]); ++ else ++ reg |= DWC3_DALEPENA_EP(dep->number); ++#else + reg |= DWC3_DALEPENA_EP(dep->number); ++#endif + dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); + + if (usb_endpoint_xfer_control(desc)) +@@ -801,7 +825,14 @@ static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep) + __dwc3_gadget_ep_set_halt(dep, 0, false); + + reg = dwc3_readl(dwc->regs, DWC3_DALEPENA); ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->eps_new_init) ++ reg &= ~DWC3_DALEPENA_EP(dwc->dwceps_map_to_usbeps[dep->number]); ++ else ++ reg &= ~DWC3_DALEPENA_EP(dep->number); ++#else + reg &= ~DWC3_DALEPENA_EP(dep->number); ++#endif + dwc3_writel(dwc->regs, DWC3_DALEPENA, reg); + + dwc3_remove_requests(dwc, dep, -ESHUTDOWN); +@@ -932,9 +963,17 @@ static void dwc3_gadget_ep_free_request(struct usb_ep *ep, + * index is 0, we will wrap backwards, skip the link TRB, and return + * the one just before that. + */ ++#ifdef CONFIG_ARCH_BSP ++static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u32 index) ++#else + static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) ++#endif + { ++#ifdef CONFIG_ARCH_BSP ++ u32 tmp = index; ++#else + u8 tmp = index; ++#endif + + if (!tmp) + tmp = DWC3_TRB_NUM - 1; +@@ -944,7 +983,11 @@ static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index) + + static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep) + { ++#ifdef CONFIG_ARCH_BSP ++ u32 trbs_left; ++#else + u8 trbs_left; ++#endif + + /* + * If the enqueue & dequeue are equal then the TRB ring is either full +@@ -995,6 +1038,9 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, + struct dwc3 *dwc = dep->dwc; + struct usb_gadget *gadget = dwc->gadget; + enum usb_device_speed speed = gadget->speed; ++#ifdef CONFIG_ARCH_BSP ++ unsigned int chain_skip = 0; ++#endif + + if (use_bounce_buffer) + dma = dep->dwc->bounce_addr; +@@ -1060,8 +1106,23 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, + mult--; + + trb->size |= DWC3_TRB_SIZE_PCM1(mult); ++#ifdef CONFIG_ARCH_BSP ++ /* ++ * If there are three transactions per mframe, ++ * and each transcation length = 1024B, no any ++ * chain trb needed, so skip it. ++ */ ++ chain_skip = 1; ++#endif + } ++#ifdef CONFIG_ARCH_BSP ++ if (speed == USB_SPEED_SUPER) ++ chain_skip = 1; ++#endif + } else { ++#ifdef CONFIG_ARCH_BSP ++ chain_skip = 1; ++#endif + trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS; + } + +@@ -1097,7 +1158,11 @@ static void dwc3_prepare_one_trb(struct dwc3_ep *dep, + if ((!no_interrupt && !chain) || must_interrupt) + trb->ctrl |= DWC3_TRB_CTRL_IOC; + ++#ifdef CONFIG_ARCH_BSP ++ if ((!chain_skip) && chain) ++#else + if (chain) ++#endif + trb->ctrl |= DWC3_TRB_CTRL_CHN; + else if (dep->stream_capable && is_last) + trb->ctrl |= DWC3_TRB_CTRL_LST; +@@ -2697,11 +2762,77 @@ static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum) + return 0; + } + ++#ifdef CONFIG_ARCH_BSP ++static int dwc3_gadget_init_hw_all_endpoints(struct dwc3 *dwc) ++{ ++ struct dwc3_ep *dep = NULL; ++ struct dwc3_hwparams *parms = &dwc->hwparams; ++ u32 direction = dwc->eps_directions; ++ u8 num_eps = DWC3_NUM_EPS(parms); ++ u8 num_in_eps = 0; ++ u8 num_out_eps = 0; ++ u8 epnum = 0; ++ u8 i; ++ int ret; ++ ++ if (!direction) ++ direction = DWC3_EPS_DEFAULT_DIRECTIONS; ++ ++ for (i = 0; i < num_eps; i++) { ++ if (direction & 0x1) ++ epnum = (num_in_eps++ << 1) + 1; ++ else ++ epnum = (num_out_eps++ << 1); ++ ++ dep = kzalloc(sizeof(*dep), GFP_KERNEL); ++ if (!dep) ++ return -ENOMEM; ++ ++ dep->dwc = dwc; ++ dep->number = i; ++ dep->direction = !!(direction & 0x1); ++ dep->regs = dwc->regs + DWC3_DEP_BASE(i); ++ dwc->eps[i] = dep; ++ snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1, ++ (epnum & 1) ? "in" : "out"); ++ ++ dep->endpoint.name = dep->name; ++ ++ if (epnum == 0 || epnum == 1) { ++ dep->endpoint.desc = &dwc3_gadget_ep0_desc; ++ dep->endpoint.comp_desc = NULL; ++ ret = dwc3_gadget_init_control_endpoint(dep); ++ } else if (dep->direction) { ++ ret = dwc3_gadget_init_in_endpoint(dep); ++ } else { ++ ret = dwc3_gadget_init_out_endpoint(dep); ++ } ++ ++ if (ret) ++ return ret; ++ ++ dep->endpoint.caps.dir_in = !!(direction & 0x1); ++ dep->endpoint.caps.dir_out = !(direction & 0x1); ++ direction = (direction >> 1); ++ ++ INIT_LIST_HEAD(&dep->pending_list); ++ INIT_LIST_HEAD(&dep->started_list); ++ INIT_LIST_HEAD(&dep->cancelled_list); ++ } ++ return 0; ++} ++#endif ++ + static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total) + { + u8 epnum; + + INIT_LIST_HEAD(&dwc->gadget->ep_list); ++#ifdef CONFIG_ARCH_BSP ++ if (dwc->eps_new_init) { ++ return dwc3_gadget_init_hw_all_endpoints(dwc); ++ } ++#endif + + for (epnum = 0; epnum < total; epnum++) { + int ret; +@@ -3731,6 +3862,10 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc, + default: + dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type); + } ++ ++#ifdef CONFIG_ARCH_BSP ++ dwc3_gadget_sync_connected_status(dwc); ++#endif + } + + static void dwc3_process_event_entry(struct dwc3 *dwc, +@@ -3994,7 +4129,9 @@ int dwc3_gadget_init(struct dwc3 *dwc) + ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps); + if (ret) + goto err4; +- ++#ifdef CONFIG_ARCH_BSP ++ dwc3_proc_init(dwc); ++#endif + ret = usb_add_gadget(dwc->gadget); + if (ret) { + dev_err(dwc->dev, "failed to add gadget\n"); +@@ -4086,3 +4223,75 @@ void dwc3_gadget_process_pending_events(struct dwc3 *dwc) + enable_irq(dwc->irq_gadget); + } + } ++ ++#ifdef CONFIG_ARCH_BSP ++/* ++ * dwc3_gadget_sync_connected_status() function just for ++ * user space get udc connected status. and this function ++ * just report three status: Disconnected, Connected host, ++ * Connected charger. ++ * ++ * After some tests, report connected udc connected status by ++ * DSTS register, [21:18]USB Link Status and [2:0] Connect Speed. ++ * ++ * How to identify whitch status is the UDC connected? ++ * 1. Host connected: ++ * Host would reset udc, so dwc3 core get reset event interrupt, ++ * dwc3_gadget_reset_interrupt() set dwc->connected = true, ++ * so check connected host by dwc->connected == true ++ * ++ * 2. Disconnected: ++ * When vbus detect 5V lose, dwc3 core generated a disconnect event intr. ++ * dwc3_gadget_disconnect_interrupt() set dwc->connected = false. ++ * so check disconnected by dwc->connected == false ++ * ++ * 3. Charger connected: (Fixedme) ++ * As dwc3 core size, DP keep pullup register when connected to charger. ++ * no any port reset action created, so dwc3 would entry FullSpeed mode. ++ * so chect connected charger by FullSpeed && dwc->connectd == false ++ * ++ */ ++static void dwc3_gadget_sync_connected_status(struct dwc3 *dwc) ++{ ++ u32 reg; ++ u8 speed; ++ u8 state; ++ int prev = UDC_DISCONNECTED; ++ ++ reg = dwc3_readl(dwc->regs, DWC3_DSTS); ++ speed = reg & DWC3_DSTS_CONNECTSPD; ++ state = DWC3_DSTS_USBLNKST(reg); ++ ++ /* ++ * step1 check is connected host? ++ */ ++ if (dwc->connected == true) { ++ if (prev != UDC_CONNECT_HOST) ++ dev_dbg(dwc->dev, "csts: Connect Host"); ++ dwc->udc_connect_status = UDC_CONNECT_HOST; ++ goto out; ++ } ++ ++ /* ++ * step2 disconectd status && fullspeed mode, ++ * as connected charger. ++ */ ++ if ((speed == DWC3_DSTS_FULLSPEED) && (state != DWC3_LINK_STATE_SS_DIS)) { ++ if (prev != UDC_CONNECT_CHARGER) ++ dev_dbg(dwc->dev, "csts: Connect Charger"); ++ dwc->udc_connect_status = UDC_CONNECT_CHARGER; ++ goto out; ++ } ++ ++ /* ++ * step3 not host and charger connected, so just ++ * disconnectd. ++ */ ++ if (prev != UDC_DISCONNECTED) ++ dev_dbg(dwc->dev, "csts: Disconnect"); ++ dwc->udc_connect_status = UDC_DISCONNECTED; ++ ++out: ++ prev = dwc->udc_connect_status; ++} ++#endif +diff --git a/drivers/usb/dwc3/proc.c b/drivers/usb/dwc3/proc.c +new file mode 100644 +index 000000000000..8d247280e5b3 +--- /dev/null ++++ b/drivers/usb/dwc3/proc.c +@@ -0,0 +1,132 @@ ++ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++* ++* Copyright (c) 2012-2018 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++#include ++#include ++#include ++#include ++#include ++ ++#include "core.h" ++ ++#define DWC3_PROC_ROOT "dwc3" ++#define DWC3_PROC_CONNECTED_STATUS "csts" ++ ++static struct proc_dir_entry *proc_dwc3_dir = NULL; ++static int proc_dwc3_dir_cnt = 0; ++ ++static void dwc3_stats_seq_printout(struct seq_file *s) ++{ ++ struct dwc3 *dwc = s->private; ++ ++ switch (dwc->udc_connect_status) { ++ case UDC_CONNECT_HOST: ++ seq_puts(s, "cnt2host\n"); ++ break; ++ case UDC_CONNECT_CHARGER: ++ seq_puts(s, "cnt2charger\n"); ++ break; ++ default: ++ seq_puts(s, "disconnected\n"); ++ break; ++ } ++} ++ ++/* define parameters where showed in proc file */ ++static int dwc3_stats_seq_show(struct seq_file *s, void *v) ++{ ++ if (s == NULL) ++ return -EINVAL; ++ ++ dwc3_stats_seq_printout(s); ++ return 0; ++} ++ ++/* proc file open */ ++static int dwc3_stats_proc_open(struct inode *inode, struct file *file) ++{ ++ if ((inode == NULL) || (file == NULL)) ++ return -EINVAL; ++ ++ return single_open(file, dwc3_stats_seq_show, PDE_DATA(inode)); ++}; ++ ++/* proc file operation */ ++static const struct proc_ops dwc3_stats_proc_ops = { ++ .proc_open = dwc3_stats_proc_open, ++ .proc_read = seq_read, ++ .proc_release = single_release, ++}; ++ ++int dwc3_proc_init(struct dwc3 *dwc) ++{ ++ struct proc_dir_entry *proc_entry = NULL; ++ ++ if (dwc == NULL) ++ return -EINVAL; ++ ++ if (proc_dwc3_dir == NULL) { ++ proc_entry = proc_mkdir(DWC3_PROC_ROOT, NULL); ++ if (proc_entry == NULL) { ++ pr_err("%s: failed to create proc file %s\n", ++ __func__, DWC3_PROC_ROOT); ++ return 1; ++ } ++ proc_dwc3_dir = proc_entry; ++ } ++ proc_dwc3_dir_cnt++; ++ ++ proc_entry = proc_mkdir(to_platform_device(dwc->dev)->name, proc_dwc3_dir); ++ if (proc_entry == NULL) { ++ pr_err("%s: failed to create proc file %s\n", ++ __func__, to_platform_device(dwc->dev)->name); ++ return -1; ++ } ++ dwc->parent_entry = proc_entry; ++ ++ proc_entry = proc_create_data(DWC3_PROC_CONNECTED_STATUS, ++ 0, dwc->parent_entry, ++ &dwc3_stats_proc_ops, dwc); ++ if (proc_entry == NULL) { ++ pr_err("%s: failed to create proc file %s\n", ++ __func__, DWC3_PROC_CONNECTED_STATUS); ++ return -1; ++ } ++ dwc->csts_entry = proc_entry; ++ ++ /* ++ * add here if more proc information need. ++ */ ++ return 0; ++} ++ ++int dwc3_proc_shutdown(struct dwc3 *dwc) ++{ ++ if (proc_dwc3_dir != NULL) { ++ remove_proc_entry(DWC3_PROC_CONNECTED_STATUS, dwc->parent_entry); ++ remove_proc_entry(to_platform_device(dwc->dev)->name, proc_dwc3_dir); ++ } ++ ++ if (proc_dwc3_dir_cnt) ++ proc_dwc3_dir_cnt--; ++ ++ if (proc_dwc3_dir_cnt == 0) { ++ remove_proc_entry(DWC3_PROC_ROOT, NULL); ++ proc_dwc3_dir = NULL; ++ } ++ ++ return 0; ++} +diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig +index 2d152571a7de..2b21e382b6da 100644 +--- a/drivers/usb/gadget/Kconfig ++++ b/drivers/usb/gadget/Kconfig +@@ -487,4 +487,12 @@ config USB_CONFIGFS_F_TCM + + source "drivers/usb/gadget/legacy/Kconfig" + ++if USB_F_UVC ++config MPP_TO_GADGET_UVC ++ bool "USB Gadget Webcam Data from MPP" ++ default n ++ help ++ Let Webcam function gets streaming data from mpp directly. ++endif ++ + endif # USB_GADGET +diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c +index d51ea1c052f2..dc07758ca74c 100644 +--- a/drivers/usb/gadget/configfs.c ++++ b/drivers/usb/gadget/configfs.c +@@ -1262,6 +1262,8 @@ static void purge_configs_funcs(struct gadget_info *gi) + cfg = container_of(c, struct config_usb_cfg, c); + + list_for_each_entry_safe_reverse(f, tmp, &c->functions, list) { ++ if (f->disable) ++ f->disable(f); + + list_move(&f->list, &cfg->func_list); + if (f->unbind) { +@@ -1270,6 +1272,8 @@ static void purge_configs_funcs(struct gadget_info *gi) + f->name, f); + f->unbind(c, f); + } ++ if (f->bind_deactivated) ++ usb_function_activate(f); + } + c->next_interface_id = 0; + memset(c->interface, 0, sizeof(c->interface)); +diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c +index 1eb4fa2e623f..6d68fa31c00f 100644 +--- a/drivers/usb/gadget/epautoconf.c ++++ b/drivers/usb/gadget/epautoconf.c +@@ -67,6 +67,7 @@ struct usb_ep *usb_ep_autoconfig_ss( + ) + { + struct usb_ep *ep; ++ u8 type; + + if (gadget->ops->match_ep) { + ep = gadget->ops->match_ep(gadget, desc, ep_comp); +@@ -74,16 +75,25 @@ struct usb_ep *usb_ep_autoconfig_ss( + goto found_ep; + } + ++ type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; + /* Second, look at endpoints until an unclaimed one looks usable */ +- list_for_each_entry (ep, &gadget->ep_list, ep_list) { +- if (usb_gadget_ep_match_desc(gadget, ep, desc, ep_comp)) +- goto found_ep; ++ /* Match all the endpoints of the project that do not match the driver */ ++ if (type == USB_ENDPOINT_XFER_INT) { ++ list_for_each_entry_reverse(ep, &gadget->ep_list, ep_list) { ++ if (usb_gadget_ep_match_desc(gadget, ep, desc, ep_comp)) ++ goto found_ep; ++ } ++ } else { ++ list_for_each_entry(ep, &gadget->ep_list, ep_list) { ++ if (usb_gadget_ep_match_desc(gadget, ep, desc, ep_comp)) ++ goto found_ep; ++ } + } + + /* Fail */ + return NULL; +-found_ep: + ++found_ep: + /* + * If the protocol driver hasn't yet decided on wMaxPacketSize + * and wants to know the maximum possible, provide the info. +diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c +index 950c9435beec..a92694ff6357 100644 +--- a/drivers/usb/gadget/function/f_mass_storage.c ++++ b/drivers/usb/gadget/function/f_mass_storage.c +@@ -307,6 +307,7 @@ struct fsg_common { + unsigned int bad_lun_okay:1; + unsigned int running:1; + unsigned int sysfs:1; ++ unsigned int actived:1; + + struct completion thread_notifier; + struct task_struct *thread_task; +@@ -1338,7 +1339,7 @@ static int do_start_stop(struct fsg_common *common) + + up_read(&common->filesem); + down_write(&common->filesem); +- fsg_lun_close(curlun); ++ common->actived = 0; + up_write(&common->filesem); + down_read(&common->filesem); + +@@ -1775,7 +1776,7 @@ static int check_command(struct fsg_common *common, int cmnd_size, + + /* If the medium isn't mounted and the command needs to access + * it, return an error. */ +- if (curlun && !fsg_lun_is_open(curlun) && needs_medium) { ++ if (curlun && !common->actived && needs_medium) { + curlun->sense_data = SS_MEDIUM_NOT_PRESENT; + return -EINVAL; + } +@@ -2234,6 +2235,7 @@ static int do_set_interface(struct fsg_common *common, struct fsg_dev *new_fsg) + } + + common->running = 0; ++ common->actived = 0; + if (!new_fsg || rc) + return rc; + +@@ -2277,7 +2279,7 @@ static int do_set_interface(struct fsg_common *common, struct fsg_dev *new_fsg) + bh->inreq->complete = bulk_in_complete; + bh->outreq->complete = bulk_out_complete; + } +- ++ common->actived = 1; + common->running = 1; + for (i = 0; i < ARRAY_SIZE(common->luns); ++i) + if (common->luns[i]) +diff --git a/drivers/usb/gadget/function/f_uac1.c b/drivers/usb/gadget/function/f_uac1.c +index e65f474ad7b3..1a156cb5fc47 100644 +--- a/drivers/usb/gadget/function/f_uac1.c ++++ b/drivers/usb/gadget/function/f_uac1.c +@@ -55,6 +55,17 @@ static inline struct f_uac1_opts *g_audio_to_uac1_opts(struct g_audio *audio) + #define F_AUDIO_AS_IN_INTERFACE 2 + /* Number of streaming interfaces */ + #define F_AUDIO_NUM_INTERFACES 2 ++#define F_AUDIO_ALL_INTERFACES_COUNT 3 ++ ++static struct usb_interface_assoc_descriptor uac_iad = { ++ .bLength = sizeof(uac_iad), ++ .bDescriptorType = USB_DT_INTERFACE_ASSOCIATION, ++ .bFirstInterface = 0, ++ .bInterfaceCount = F_AUDIO_ALL_INTERFACES_COUNT, ++ .bFunctionClass = USB_CLASS_AUDIO, ++ .bFunctionSubClass = 0, ++ .bFunctionProtocol = UAC_VERSION_1, ++}; + + /* B.3.1 Standard AC Interface Descriptor */ + static struct usb_interface_descriptor ac_interface_desc = { +@@ -254,7 +265,46 @@ static struct uac_iso_endpoint_descriptor as_iso_in_desc = { + .wLockDelay = 0, + }; + ++static struct usb_ss_ep_comp_descriptor as_ss_ep_comp = { ++ .bLength = sizeof(as_ss_ep_comp), ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++ .bMaxBurst = 0, ++ .bmAttributes = 0, ++ .wBytesPerInterval = cpu_to_le16(UAC1_OUT_EP_MAX_PACKET_SIZE), ++}; ++ + static struct usb_descriptor_header *f_audio_desc[] = { ++ (struct usb_descriptor_header *)&uac_iad, ++ (struct usb_descriptor_header *)&ac_interface_desc, ++ (struct usb_descriptor_header *)&ac_header_desc, ++ ++ (struct usb_descriptor_header *)&usb_out_it_desc, ++ (struct usb_descriptor_header *)&io_out_ot_desc, ++ (struct usb_descriptor_header *)&io_in_it_desc, ++ (struct usb_descriptor_header *)&usb_in_ot_desc, ++ ++ (struct usb_descriptor_header *)&as_out_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_out_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_out_header_desc, ++ ++ (struct usb_descriptor_header *)&as_out_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_out_desc, ++ ++ (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, ++ (struct usb_descriptor_header *)&as_in_interface_alt_1_desc, ++ (struct usb_descriptor_header *)&as_in_header_desc, ++ ++ (struct usb_descriptor_header *)&as_in_type_i_desc, ++ ++ (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&as_iso_in_desc, ++ NULL, ++}; ++ ++static struct usb_descriptor_header *f_audio_ss_desc[] = { ++ (struct usb_descriptor_header *)&uac_iad, + (struct usb_descriptor_header *)&ac_interface_desc, + (struct usb_descriptor_header *)&ac_header_desc, + +@@ -270,6 +320,7 @@ static struct usb_descriptor_header *f_audio_desc[] = { + (struct usb_descriptor_header *)&as_out_type_i_desc, + + (struct usb_descriptor_header *)&as_out_ep_desc, ++ (struct usb_descriptor_header *)&as_ss_ep_comp, + (struct usb_descriptor_header *)&as_iso_out_desc, + + (struct usb_descriptor_header *)&as_in_interface_alt_0_desc, +@@ -279,6 +330,7 @@ static struct usb_descriptor_header *f_audio_desc[] = { + (struct usb_descriptor_header *)&as_in_type_i_desc, + + (struct usb_descriptor_header *)&as_in_ep_desc, ++ (struct usb_descriptor_header *)&as_ss_ep_comp, + (struct usb_descriptor_header *)&as_iso_in_desc, + NULL, + }; +@@ -567,6 +619,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) + us = usb_gstrings_attach(cdev, uac1_strings, ARRAY_SIZE(strings_uac1)); + if (IS_ERR(us)) + return PTR_ERR(us); ++ uac_iad.iFunction = us[STR_AC_IF].id; + ac_interface_desc.iInterface = us[STR_AC_IF].id; + usb_out_it_desc.iTerminal = us[STR_USB_OUT_IT].id; + usb_out_it_desc.iChannelNames = us[STR_USB_OUT_IT_CH_NAMES].id; +@@ -603,6 +656,7 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) + status = usb_interface_id(c, f); + if (status < 0) + goto fail; ++ uac_iad.bFirstInterface = status; + ac_interface_desc.bInterfaceNumber = status; + uac1->ac_intf = status; + uac1->ac_alt = 0; +@@ -643,8 +697,8 @@ static int f_audio_bind(struct usb_configuration *c, struct usb_function *f) + audio->in_ep->desc = &as_in_ep_desc; + + /* copy descriptors, and track endpoint copies */ +- status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, NULL, +- NULL); ++ status = usb_assign_descriptors(f, f_audio_desc, f_audio_desc, ++ f_audio_ss_desc, NULL); + if (status) + goto fail; + +diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c +index 5d39aff263f0..ed413a3abbe5 100644 +--- a/drivers/usb/gadget/function/f_uvc.c ++++ b/drivers/usb/gadget/function/f_uvc.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -24,6 +25,8 @@ + #include + #include + ++#include ++ + #include "u_uvc.h" + #include "uvc.h" + #include "uvc_configfs.h" +@@ -43,6 +46,29 @@ MODULE_PARM_DESC(trace, "Trace level bitmask"); + #define UVC_STRING_CONTROL_IDX 0 + #define UVC_STRING_STREAMING_IDX 1 + ++#define SS_EP_BURST 0 ++#define SS_EP_ATTRIBUTES 0 ++#define SS_EP_MAX_PACKET_SIZE 1024 ++ ++#define SS_EP1_BURST 1 ++#define SS_EP1_ATTRIBUTES 0 ++#define SS_EP1_MAX_PACKET_SIZE 1024 ++ ++#define SS_EP2_BURST 8 ++#define SS_EP2_ATTRIBUTES 1 ++#define SS_EP2_MAX_PACKET_SIZE 1024 ++ ++#define SS_EP3_BURST 15 ++#define SS_EP3_ATTRIBUTES 1 ++#define SS_EP3_MAX_PACKET_SIZE 1024 ++ ++#define HS_EP_MAX_PACKET_SIZE 0x320 ++#define HS_EP1_MAX_PACKET_SIZE 0xBE0 ++#define HS_EP2_MAX_PACKET_SIZE 0x1380 ++#define HS_EP3_MAX_PACKET_SIZE 0x1400 ++ ++#define USB_ENDPOINT_MAXP_MASK 0x07ff ++ + static struct usb_string uvc_en_us_strings[] = { + [UVC_STRING_CONTROL_IDX].s = "UVC Camera", + [UVC_STRING_STREAMING_IDX].s = "Video Streaming", +@@ -116,7 +142,7 @@ static struct usb_interface_descriptor uvc_streaming_intf_alt0 = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, +- .bAlternateSetting = 0, ++ .bAlternateSetting = ALT_SETTING_0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_VIDEO, + .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, +@@ -128,7 +154,43 @@ static struct usb_interface_descriptor uvc_streaming_intf_alt1 = { + .bLength = USB_DT_INTERFACE_SIZE, + .bDescriptorType = USB_DT_INTERFACE, + .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, +- .bAlternateSetting = 1, ++ .bAlternateSetting = ALT_SETTING_1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, ++ .bInterfaceProtocol = 0x00, ++ .iInterface = 0, ++}; ++ ++static struct usb_interface_descriptor uvc_streaming_intf_alt2 = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, ++ .bAlternateSetting = ALT_SETTING_2, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, ++ .bInterfaceProtocol = 0x00, ++ .iInterface = 0, ++}; ++ ++static struct usb_interface_descriptor uvc_streaming_intf_alt3 = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, ++ .bAlternateSetting = ALT_SETTING_3, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_VIDEO, ++ .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, ++ .bInterfaceProtocol = 0x00, ++ .iInterface = 0, ++}; ++ ++static struct usb_interface_descriptor uvc_streaming_intf_alt4 = { ++ .bLength = USB_DT_INTERFACE_SIZE, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = UVC_INTF_VIDEO_STREAMING, ++ .bAlternateSetting = ALT_SETTING_4, + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_VIDEO, + .bInterfaceSubClass = UVC_SC_VIDEOSTREAMING, +@@ -147,6 +209,39 @@ static struct usb_endpoint_descriptor uvc_fs_streaming_ep = { + */ + }; + ++static struct usb_endpoint_descriptor uvc_fs_streaming_ep1 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ ++static struct usb_endpoint_descriptor uvc_fs_streaming_ep2 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ ++static struct usb_endpoint_descriptor uvc_fs_streaming_ep3 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ + static struct usb_endpoint_descriptor uvc_hs_streaming_ep = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, +@@ -158,6 +253,39 @@ static struct usb_endpoint_descriptor uvc_hs_streaming_ep = { + */ + }; + ++static struct usb_endpoint_descriptor uvc_hs_streaming_ep1 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ ++static struct usb_endpoint_descriptor uvc_hs_streaming_ep2 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ ++static struct usb_endpoint_descriptor uvc_hs_streaming_ep3 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ + static struct usb_endpoint_descriptor uvc_ss_streaming_ep = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, +@@ -170,6 +298,42 @@ static struct usb_endpoint_descriptor uvc_ss_streaming_ep = { + */ + }; + ++static struct usb_endpoint_descriptor uvc_ss_streaming_ep1 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ ++static struct usb_endpoint_descriptor uvc_ss_streaming_ep2 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ ++static struct usb_endpoint_descriptor uvc_ss_streaming_ep3 = { ++ .bLength = USB_DT_ENDPOINT_SIZE, ++ .bDescriptorType = USB_DT_ENDPOINT, ++ ++ .bEndpointAddress = USB_DIR_IN, ++ .bmAttributes = USB_ENDPOINT_SYNC_ASYNC ++ | USB_ENDPOINT_XFER_ISOC, ++ /* The wMaxPacketSize and bInterval values will be initialized from ++ * module parameters. ++ */ ++}; ++ + static struct usb_ss_ep_comp_descriptor uvc_ss_streaming_comp = { + .bLength = sizeof(uvc_ss_streaming_comp), + .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, +@@ -178,22 +342,58 @@ static struct usb_ss_ep_comp_descriptor uvc_ss_streaming_comp = { + */ + }; + ++static struct usb_ss_ep_comp_descriptor uvc_ss_streaming_comp1 = { ++ .bLength = sizeof(uvc_ss_streaming_comp1), ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++}; ++ ++static struct usb_ss_ep_comp_descriptor uvc_ss_streaming_comp2 = { ++ .bLength = sizeof(uvc_ss_streaming_comp2), ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++}; ++ ++static struct usb_ss_ep_comp_descriptor uvc_ss_streaming_comp3 = { ++ .bLength = sizeof(uvc_ss_streaming_comp3), ++ .bDescriptorType = USB_DT_SS_ENDPOINT_COMP, ++}; ++ + static const struct usb_descriptor_header * const uvc_fs_streaming[] = { +- (struct usb_descriptor_header *) &uvc_streaming_intf_alt1, +- (struct usb_descriptor_header *) &uvc_fs_streaming_ep, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt1, ++ (struct usb_descriptor_header *)&uvc_fs_streaming_ep, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt2, ++ (struct usb_descriptor_header *)&uvc_fs_streaming_ep1, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt3, ++ (struct usb_descriptor_header *)&uvc_fs_streaming_ep2, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt4, ++ (struct usb_descriptor_header *)&uvc_fs_streaming_ep3, + NULL, + }; + + static const struct usb_descriptor_header * const uvc_hs_streaming[] = { +- (struct usb_descriptor_header *) &uvc_streaming_intf_alt1, +- (struct usb_descriptor_header *) &uvc_hs_streaming_ep, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt1, ++ (struct usb_descriptor_header *)&uvc_hs_streaming_ep, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt2, ++ (struct usb_descriptor_header *)&uvc_hs_streaming_ep1, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt3, ++ (struct usb_descriptor_header *)&uvc_hs_streaming_ep2, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt4, ++ (struct usb_descriptor_header *)&uvc_hs_streaming_ep3, + NULL, + }; + + static const struct usb_descriptor_header * const uvc_ss_streaming[] = { +- (struct usb_descriptor_header *) &uvc_streaming_intf_alt1, +- (struct usb_descriptor_header *) &uvc_ss_streaming_ep, +- (struct usb_descriptor_header *) &uvc_ss_streaming_comp, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt1, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_ep, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_comp, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt2, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_ep1, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_comp1, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt3, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_ep2, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_comp2, ++ (struct usb_descriptor_header *)&uvc_streaming_intf_alt4, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_ep3, ++ (struct usb_descriptor_header *)&uvc_ss_streaming_comp3, + NULL, + }; + +@@ -217,6 +417,7 @@ uvc_function_ep0_complete(struct usb_ep *ep, struct usb_request *req) + sizeof(uvc_event->data.data)); + memcpy(&uvc_event->data.data, req->buf, uvc_event->data.length); + v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ iprec("v4l2 queue UVC_EVENT_DATA"); + } + } + +@@ -227,6 +428,10 @@ uvc_function_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + struct v4l2_event v4l2_event; + struct uvc_event *uvc_event = (void *)&v4l2_event.u.data; + ++ iprec("%s setup request 0x%02x 0x%02x value 0x%04x index 0x%04x length 0x%04x", ++ __func__, ctrl->bRequestType, ctrl->bRequest, le16_to_cpu(ctrl->wValue), ++ le16_to_cpu(ctrl->wIndex), le16_to_cpu(ctrl->wLength)); ++ + if ((ctrl->bRequestType & USB_TYPE_MASK) != USB_TYPE_CLASS) { + uvcg_info(f, "invalid request type\n"); + return -EINVAL; +@@ -246,6 +451,7 @@ uvc_function_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) + v4l2_event.type = UVC_EVENT_SETUP; + memcpy(&uvc_event->req, ctrl, sizeof(uvc_event->req)); + v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ iprec("v4l2 queue UVC_EVENT_SETUP"); + + return 0; + } +@@ -271,6 +477,66 @@ uvc_function_get_alt(struct usb_function *f, unsigned interface) + else + return uvc->video.ep->enabled ? 1 : 0; + } ++static int uvc_function_set_appropriate_ep(struct usb_function *f, unsigned alt) ++{ ++ struct uvc_device *uvc = to_uvc(f); ++ switch (alt) { ++ case ALT_SETTING_1: ++ if (f->config->cdev->gadget->speed == USB_SPEED_SUPER) { ++ uvc->video.ep->maxpacket = SS_EP_MAX_PACKET_SIZE; ++ uvc->video.ep->desc = &uvc_ss_streaming_ep; ++ uvc->video.ep->mult = SS_EP_ATTRIBUTES + 1; ++ uvc->video.ep->maxburst = SS_EP_BURST + 1; ++ uvc->video.ep->comp_desc = &uvc_ss_streaming_comp; ++ } else { ++ uvc->video.ep->desc = &uvc_hs_streaming_ep; ++ uvc->video.ep->maxpacket = uvc->video.ep->desc->wMaxPacketSize & USB_ENDPOINT_MAXP_MASK; ++ uvc->video.ep->mult = USB_EP_MAXP_MULT(uvc->video.ep->desc->wMaxPacketSize) + 1; ++ } ++ return 0; ++ case ALT_SETTING_2: ++ if (f->config->cdev->gadget->speed == USB_SPEED_SUPER) { ++ uvc->video.ep->maxpacket = SS_EP1_MAX_PACKET_SIZE; ++ uvc->video.ep->desc = &uvc_ss_streaming_ep1; ++ uvc->video.ep->mult = SS_EP1_ATTRIBUTES + 1; ++ uvc->video.ep->maxburst = SS_EP1_BURST + 1; ++ uvc->video.ep->comp_desc = &uvc_ss_streaming_comp1; ++ } else { ++ uvc->video.ep->desc = &uvc_hs_streaming_ep1; ++ uvc->video.ep->maxpacket = uvc->video.ep->desc->wMaxPacketSize & USB_ENDPOINT_MAXP_MASK; ++ uvc->video.ep->mult = USB_EP_MAXP_MULT(uvc->video.ep->desc->wMaxPacketSize) + 1; ++ } ++ return 0; ++ case ALT_SETTING_3: ++ if (f->config->cdev->gadget->speed == USB_SPEED_SUPER) { ++ uvc->video.ep->maxpacket = SS_EP2_MAX_PACKET_SIZE; ++ uvc->video.ep->desc = &uvc_ss_streaming_ep2; ++ uvc->video.ep->mult = SS_EP2_ATTRIBUTES + 1; ++ uvc->video.ep->maxburst = SS_EP2_BURST + 1; ++ uvc->video.ep->comp_desc = &uvc_ss_streaming_comp2; ++ } else { ++ uvc->video.ep->desc = &uvc_hs_streaming_ep2; ++ uvc->video.ep->maxpacket = uvc->video.ep->desc->wMaxPacketSize & USB_ENDPOINT_MAXP_MASK; ++ uvc->video.ep->mult = USB_EP_MAXP_MULT(uvc->video.ep->desc->wMaxPacketSize) + 1; ++ } ++ return 0; ++ case ALT_SETTING_4: ++ if (f->config->cdev->gadget->speed == USB_SPEED_SUPER) { ++ uvc->video.ep->maxpacket = SS_EP3_MAX_PACKET_SIZE; ++ uvc->video.ep->desc = &uvc_ss_streaming_ep3; ++ uvc->video.ep->mult = SS_EP3_ATTRIBUTES + 1; ++ uvc->video.ep->maxburst = SS_EP3_BURST + 1; ++ uvc->video.ep->comp_desc = &uvc_ss_streaming_comp3; ++ } else { ++ uvc->video.ep->desc = &uvc_hs_streaming_ep3; ++ uvc->video.ep->maxpacket = uvc->video.ep->desc->wMaxPacketSize & USB_ENDPOINT_MAXP_MASK; ++ uvc->video.ep->mult = USB_EP_MAXP_MULT(uvc->video.ep->desc->wMaxPacketSize) + 1; ++ } ++ return 0; ++ default: ++ return -EINVAL; ++ } ++} + + static int + uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) +@@ -282,6 +548,7 @@ uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) + int ret; + + uvcg_info(f, "%s(%u, %u)\n", __func__, interface, alt); ++ iprec("%s(%u, %u)", __func__, interface, alt); + + if (interface == uvc->control_intf) { + if (alt) +@@ -301,7 +568,7 @@ uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) + v4l2_event.type = UVC_EVENT_CONNECT; + uvc_event->speed = cdev->gadget->speed; + v4l2_event_queue(&uvc->vdev, &v4l2_event); +- ++ iprec("v4l2 queue UVC_EVENT_CONNECT"); + uvc->state = UVC_STATE_CONNECTED; + } + +@@ -316,44 +583,66 @@ uvc_function_set_alt(struct usb_function *f, unsigned interface, unsigned alt) + return alt ? -EINVAL : 0; + */ + +- switch (alt) { +- case 0: ++ if (alt == ALT_SETTING_0) { + if (uvc->state != UVC_STATE_STREAMING) + return 0; + + if (uvc->video.ep) + usb_ep_disable(uvc->video.ep); + +- memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ (void)memset_s(&v4l2_event, sizeof(v4l2_event), 0, sizeof(v4l2_event)); + v4l2_event.type = UVC_EVENT_STREAMOFF; + v4l2_event_queue(&uvc->vdev, &v4l2_event); +- ++ iprec("v4l2 queue UVC_EVENT_STREAMOFF"); + uvc->state = UVC_STATE_CONNECTED; + return 0; ++ } + +- case 1: +- if (uvc->state != UVC_STATE_CONNECTED) +- return 0; ++ if (alt > ALT_SETTING_4) ++ return -EINVAL; + +- if (!uvc->video.ep) +- return -EINVAL; ++ if (uvc->state != UVC_STATE_CONNECTED) ++ return 0; + +- uvcg_info(f, "reset UVC\n"); +- usb_ep_disable(uvc->video.ep); ++ if (!uvc->video.ep) ++ return -EINVAL; + +- ret = config_ep_by_speed(f->config->cdev->gadget, +- &(uvc->func), uvc->video.ep); +- if (ret) +- return ret; +- usb_ep_enable(uvc->video.ep); ++ INFO(cdev, "reset UVC\n"); ++ usb_ep_disable(uvc->video.ep); + +- memset(&v4l2_event, 0, sizeof(v4l2_event)); +- v4l2_event.type = UVC_EVENT_STREAMON; +- v4l2_event_queue(&uvc->vdev, &v4l2_event); +- return USB_GADGET_DELAYED_STATUS; ++ ret = config_ep_by_speed(f->config->cdev->gadget, ++ &(uvc->func), uvc->video.ep); ++ if (ret) ++ return ret; + +- default: +- return -EINVAL; ++ ret = uvc_function_set_appropriate_ep(f, alt); ++ if (ret) ++ return ret; ++ ++ usb_ep_enable(uvc->video.ep); ++ ++ memset(&v4l2_event, 0, sizeof(v4l2_event)); ++ v4l2_event.type = UVC_EVENT_STREAMON; ++ v4l2_event_queue(&uvc->vdev, &v4l2_event); ++ iprec("v4l2 queue UVC_EVENT_STREAMON"); ++ return USB_GADGET_DELAYED_STATUS; ++} ++ ++static void ++uvc_ep_recover(struct uvc_device *uvc, struct usb_function *f) ++{ ++ if (uvc->video.ep->enabled == false) ++ return; ++ ++ if (f->config->cdev->gadget->speed == USB_SPEED_SUPER) { ++ uvc->video.ep->desc = &uvc_ss_streaming_ep; ++ uvc->video.ep->mult = SS_EP_ATTRIBUTES + 1; ++ uvc->video.ep->maxburst = SS_EP_BURST + 1; ++ uvc->video.ep->comp_desc = &uvc_ss_streaming_comp; ++ } else { ++ uvc->video.ep->desc = &uvc_hs_streaming_ep; ++ uvc->video.ep->maxpacket = uvc->video.ep->desc->wMaxPacketSize & USB_ENDPOINT_MAXP_MASK; ++ uvc->video.ep->mult = USB_EP_MAXP_MULT(uvc->video.ep->desc->wMaxPacketSize) + 1; + } + } + +@@ -371,6 +660,7 @@ uvc_function_disable(struct usb_function *f) + + uvc->state = UVC_STATE_DISCONNECTED; + ++ uvc_ep_recover(uvc, f); + usb_ep_disable(uvc->video.ep); + usb_ep_disable(uvc->control_ep); + } +@@ -628,26 +918,70 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + max_packet_size = opts->streaming_maxpacket / 3; + } + +- uvc_fs_streaming_ep.wMaxPacketSize = +- cpu_to_le16(min(opts->streaming_maxpacket, 1023U)); ++ uvc_fs_streaming_ep.wMaxPacketSize = 0x100; + uvc_fs_streaming_ep.bInterval = opts->streaming_interval; + +- uvc_hs_streaming_ep.wMaxPacketSize = +- cpu_to_le16(max_packet_size | ((max_packet_mult - 1) << 11)); ++ uvc_fs_streaming_ep1.wMaxPacketSize = 0x200; ++ uvc_fs_streaming_ep1.bInterval = opts->streaming_interval; + ++ uvc_fs_streaming_ep2.wMaxPacketSize = 0x300; ++ uvc_fs_streaming_ep2.bInterval = opts->streaming_interval; ++ ++ uvc_fs_streaming_ep3.wMaxPacketSize = 0x3ff; ++ uvc_fs_streaming_ep3.bInterval = opts->streaming_interval; ++ ++ uvc_hs_streaming_ep.wMaxPacketSize = HS_EP_MAX_PACKET_SIZE; + /* A high-bandwidth endpoint must specify a bInterval value of 1 */ + if (max_packet_mult > 1) + uvc_hs_streaming_ep.bInterval = 1; + else + uvc_hs_streaming_ep.bInterval = opts->streaming_interval; + +- uvc_ss_streaming_ep.wMaxPacketSize = cpu_to_le16(max_packet_size); ++ uvc_hs_streaming_ep1.wMaxPacketSize = HS_EP1_MAX_PACKET_SIZE; ++ uvc_hs_streaming_ep1.bInterval = opts->streaming_interval; ++ ++ uvc_hs_streaming_ep2.wMaxPacketSize = HS_EP2_MAX_PACKET_SIZE; ++ uvc_hs_streaming_ep2.bInterval = opts->streaming_interval; ++ ++ uvc_hs_streaming_ep3.wMaxPacketSize = HS_EP3_MAX_PACKET_SIZE; ++ uvc_hs_streaming_ep3.bInterval = opts->streaming_interval; ++ ++ uvc_ss_streaming_ep.wMaxPacketSize = SS_EP_MAX_PACKET_SIZE; + uvc_ss_streaming_ep.bInterval = opts->streaming_interval; +- uvc_ss_streaming_comp.bmAttributes = max_packet_mult - 1; +- uvc_ss_streaming_comp.bMaxBurst = opts->streaming_maxburst; ++ ++ uvc_ss_streaming_ep1.wMaxPacketSize = SS_EP1_MAX_PACKET_SIZE; ++ uvc_ss_streaming_ep1.bInterval = opts->streaming_interval; ++ ++ uvc_ss_streaming_ep2.wMaxPacketSize = SS_EP2_MAX_PACKET_SIZE; ++ uvc_ss_streaming_ep2.bInterval = opts->streaming_interval; ++ ++ uvc_ss_streaming_ep3.wMaxPacketSize = SS_EP3_MAX_PACKET_SIZE; ++ uvc_ss_streaming_ep3.bInterval = opts->streaming_interval; ++ ++ uvc_ss_streaming_comp.bmAttributes = SS_EP_ATTRIBUTES; ++ uvc_ss_streaming_comp.bMaxBurst = SS_EP_BURST; ++ + uvc_ss_streaming_comp.wBytesPerInterval = +- cpu_to_le16(max_packet_size * max_packet_mult * +- (opts->streaming_maxburst + 1)); ++ cpu_to_le16(uvc_ss_streaming_ep.wMaxPacketSize * (uvc_ss_streaming_comp.bmAttributes + 1) ++ * (uvc_ss_streaming_comp.bMaxBurst + 1)); ++ ++ uvc_ss_streaming_comp1.bmAttributes = SS_EP1_ATTRIBUTES; ++ uvc_ss_streaming_comp1.bMaxBurst = SS_EP1_BURST; ++ uvc_ss_streaming_comp1.wBytesPerInterval = ++ cpu_to_le16(uvc_ss_streaming_ep1.wMaxPacketSize * (uvc_ss_streaming_comp1.bmAttributes + 1) ++ * (uvc_ss_streaming_comp1.bMaxBurst + 1)); ++ ++ uvc_ss_streaming_comp2.bmAttributes = SS_EP2_ATTRIBUTES; ++ uvc_ss_streaming_comp2.bMaxBurst = SS_EP2_BURST; ++ uvc_ss_streaming_comp2.wBytesPerInterval = ++ cpu_to_le16(uvc_ss_streaming_ep2.wMaxPacketSize * (uvc_ss_streaming_comp2.bmAttributes + 1) ++ * (uvc_ss_streaming_comp2.bMaxBurst + 1)); ++ ++ uvc_ss_streaming_comp3.bmAttributes = SS_EP3_ATTRIBUTES; ++ uvc_ss_streaming_comp3.bMaxBurst = SS_EP3_BURST; ++ uvc_ss_streaming_comp3.wBytesPerInterval = ++ cpu_to_le16(uvc_ss_streaming_ep3.wMaxPacketSize * (uvc_ss_streaming_comp3.bmAttributes + 1) ++ * (uvc_ss_streaming_comp3.bMaxBurst + 1)); + + /* Allocate endpoints. */ + ep = usb_ep_autoconfig(cdev->gadget, &uvc_control_ep); +@@ -675,6 +1009,18 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + uvc_hs_streaming_ep.bEndpointAddress = uvc->video.ep->address; + uvc_ss_streaming_ep.bEndpointAddress = uvc->video.ep->address; + ++ uvc_fs_streaming_ep1.bEndpointAddress = uvc->video.ep->address; ++ uvc_hs_streaming_ep1.bEndpointAddress = uvc->video.ep->address; ++ uvc_ss_streaming_ep1.bEndpointAddress = uvc->video.ep->address; ++ ++ uvc_fs_streaming_ep2.bEndpointAddress = uvc->video.ep->address; ++ uvc_hs_streaming_ep2.bEndpointAddress = uvc->video.ep->address; ++ uvc_ss_streaming_ep2.bEndpointAddress = uvc->video.ep->address; ++ ++ uvc_fs_streaming_ep3.bEndpointAddress = uvc->video.ep->address; ++ uvc_hs_streaming_ep3.bEndpointAddress = uvc->video.ep->address; ++ uvc_ss_streaming_ep3.bEndpointAddress = uvc->video.ep->address; ++ + us = usb_gstrings_attach(cdev, uvc_function_strings, + ARRAY_SIZE(uvc_en_us_strings)); + if (IS_ERR(us)) { +@@ -686,6 +1032,9 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + ret = us[UVC_STRING_STREAMING_IDX].id; + uvc_streaming_intf_alt0.iInterface = ret; + uvc_streaming_intf_alt1.iInterface = ret; ++ uvc_streaming_intf_alt2.iInterface = ret; ++ uvc_streaming_intf_alt3.iInterface = ret; ++ uvc_streaming_intf_alt4.iInterface = ret; + + /* Allocate interface IDs. */ + if ((ret = usb_interface_id(c, f)) < 0) +@@ -699,6 +1048,9 @@ uvc_function_bind(struct usb_configuration *c, struct usb_function *f) + goto error; + uvc_streaming_intf_alt0.bInterfaceNumber = ret; + uvc_streaming_intf_alt1.bInterfaceNumber = ret; ++ uvc_streaming_intf_alt2.bInterfaceNumber = ret; ++ uvc_streaming_intf_alt3.bInterfaceNumber = ret; ++ uvc_streaming_intf_alt4.bInterfaceNumber = ret; + uvc->streaming_intf = ret; + opts->streaming_interface = ret; + +@@ -790,6 +1142,11 @@ static struct usb_function_instance *uvc_alloc_inst(void) + struct uvc_descriptor_header **ctl_cls; + int ret; + ++ struct UVC_EXTENSION_UNIT_DESCRIPTOR(1, 2) *ed; ++ /* GUID of the UVC H.264 extension unit */ ++ static char extension_guid[] = {0x41, 0x76, 0x9E, 0xA2, 0x04, 0xDE, 0xE3, 0x47, ++ 0x8B, 0x2B, 0xF4, 0x34, 0x1A, 0xFF, 0x00, 0x3B}; ++ + opts = kzalloc(sizeof(*opts), GFP_KERNEL); + if (!opts) + return ERR_PTR(-ENOMEM); +@@ -825,6 +1182,20 @@ static struct usb_function_instance *uvc_alloc_inst(void) + pd->iProcessing = 0; + pd->bmVideoStandards = 0; + ++ ed = &opts->uvc_extension; ++ ed->bLength = UVC_DT_EXTENSION_UNIT_SIZE(1, 2); ++ ed->bDescriptorType = USB_DT_CS_INTERFACE; ++ ed->bDescriptorSubType = UVC_VC_EXTENSION_UNIT; ++ ed->bUnitID = 10; ++ memcpy(ed->guidExtensionCode, extension_guid, sizeof(extension_guid)); ++ ed->bNrInPins = 1; ++ ed->baSourceID[0] = 2; ++ ed->bNumControls = 15; ++ ed->bControlSize = 2; ++ ed->bmControls[0] = 1; ++ ed->bmControls[1] = 0; ++ ed->iExtension = 0; ++ + od = &opts->uvc_output_terminal; + od->bLength = UVC_DT_OUTPUT_TERMINAL_SIZE; + od->bDescriptorType = USB_DT_CS_INTERFACE; +@@ -848,8 +1219,9 @@ static struct usb_function_instance *uvc_alloc_inst(void) + ctl_cls[0] = NULL; /* assigned elsewhere by configfs */ + ctl_cls[1] = (struct uvc_descriptor_header *)cd; + ctl_cls[2] = (struct uvc_descriptor_header *)pd; +- ctl_cls[3] = (struct uvc_descriptor_header *)od; +- ctl_cls[4] = NULL; /* NULL-terminate */ ++ ctl_cls[3] = (struct uvc_descriptor_header *)ed; ++ ctl_cls[4] = (struct uvc_descriptor_header *)od; ++ ctl_cls[5] = NULL; /* NULL-terminate */ + opts->fs_control = + (const struct uvc_descriptor_header * const *)ctl_cls; + +@@ -858,8 +1230,9 @@ static struct usb_function_instance *uvc_alloc_inst(void) + ctl_cls[0] = NULL; /* assigned elsewhere by configfs */ + ctl_cls[1] = (struct uvc_descriptor_header *)cd; + ctl_cls[2] = (struct uvc_descriptor_header *)pd; +- ctl_cls[3] = (struct uvc_descriptor_header *)od; +- ctl_cls[4] = NULL; /* NULL-terminate */ ++ ctl_cls[3] = (struct uvc_descriptor_header *)ed; ++ ctl_cls[4] = (struct uvc_descriptor_header *)od; ++ ctl_cls[5] = NULL; /* NULL-terminate */ + opts->ss_control = + (const struct uvc_descriptor_header * const *)ctl_cls; + +diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c +index 95605b1ef4eb..6c8b8f5b7e0f 100644 +--- a/drivers/usb/gadget/function/u_audio.c ++++ b/drivers/usb/gadget/function/u_audio.c +@@ -613,7 +613,7 @@ void g_audio_cleanup(struct g_audio *g_audio) + uac = g_audio->uac; + card = uac->card; + if (card) +- snd_card_free(card); ++ snd_card_free_when_closed(card); + + kfree(uac->p_prm.ureq); + kfree(uac->c_prm.ureq); +diff --git a/drivers/usb/gadget/function/u_serial.c b/drivers/usb/gadget/function/u_serial.c +index 2caccbb6e014..7b54e814aefb 100644 +--- a/drivers/usb/gadget/function/u_serial.c ++++ b/drivers/usb/gadget/function/u_serial.c +@@ -81,6 +81,9 @@ + #define WRITE_BUF_SIZE 8192 /* TX only */ + #define GS_CONSOLE_BUF_SIZE 8192 + ++/* Prevents race conditions while accessing gser->ioport */ ++static DEFINE_SPINLOCK(serial_port_lock); ++ + /* console info */ + struct gs_console { + struct console console; +@@ -1376,8 +1379,10 @@ void gserial_disconnect(struct gserial *gser) + if (!port) + return; + ++ spin_lock_irqsave(&serial_port_lock, flags); ++ + /* tell the TTY glue not to do I/O here any more */ +- spin_lock_irqsave(&port->port_lock, flags); ++ spin_lock(&port->port_lock); + + gs_console_disconnect(port); + +@@ -1392,7 +1397,8 @@ void gserial_disconnect(struct gserial *gser) + tty_hangup(port->port.tty); + } + port->suspended = false; +- spin_unlock_irqrestore(&port->port_lock, flags); ++ spin_unlock(&port->port_lock); ++ spin_unlock_irqrestore(&serial_port_lock, flags); + + /* disable endpoints, aborting down any active I/O */ + usb_ep_disable(gser->out); +@@ -1426,10 +1432,19 @@ EXPORT_SYMBOL_GPL(gserial_suspend); + + void gserial_resume(struct gserial *gser) + { +- struct gs_port *port = gser->ioport; ++ struct gs_port *port; + unsigned long flags; + +- spin_lock_irqsave(&port->port_lock, flags); ++ spin_lock_irqsave(&serial_port_lock, flags); ++ port = gser->ioport; ++ ++ if (!port) { ++ spin_unlock_irqrestore(&serial_port_lock, flags); ++ return; ++ } ++ ++ spin_lock(&port->port_lock); ++ spin_unlock(&serial_port_lock); + port->suspended = false; + if (!port->start_delayed) { + spin_unlock_irqrestore(&port->port_lock, flags); +diff --git a/drivers/usb/gadget/function/u_uvc.h b/drivers/usb/gadget/function/u_uvc.h +index 9a01a7d4f17f..392ae14dcb41 100644 +--- a/drivers/usb/gadget/function/u_uvc.h ++++ b/drivers/usb/gadget/function/u_uvc.h +@@ -52,6 +52,7 @@ struct f_uvc_opts { + struct uvc_processing_unit_descriptor uvc_processing; + struct uvc_output_terminal_descriptor uvc_output_terminal; + struct uvc_color_matching_descriptor uvc_color_matching; ++ struct UVC_EXTENSION_UNIT_DESCRIPTOR(1, 2) uvc_extension; + + /* + * Control descriptors pointers arrays for full-/high-speed and +@@ -60,8 +61,8 @@ struct f_uvc_opts { + * descriptors. Used by configfs only, must not be touched by legacy + * gadgets. + */ +- struct uvc_descriptor_header *uvc_fs_control_cls[5]; +- struct uvc_descriptor_header *uvc_ss_control_cls[5]; ++ struct uvc_descriptor_header *uvc_fs_control_cls[6]; ++ struct uvc_descriptor_header *uvc_ss_control_cls[6]; + + /* + * Streaming descriptors for full-speed, high-speed and super-speed. +diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h +index 6c4fc4913f4f..8db9e5a95af2 100644 +--- a/drivers/usb/gadget/function/uvc.h ++++ b/drivers/usb/gadget/function/uvc.h +@@ -45,6 +45,12 @@ struct uvc_device; + #define UVC_WARN_MINMAX 0 + #define UVC_WARN_PROBE_DEF 1 + ++#define ALT_SETTING_0 0 ++#define ALT_SETTING_1 1 ++#define ALT_SETTING_2 2 ++#define ALT_SETTING_3 3 ++#define ALT_SETTING_4 4 ++ + extern unsigned int uvc_gadget_trace_param; + + #define uvc_trace(flag, msg...) \ +@@ -65,11 +71,38 @@ extern unsigned int uvc_gadget_trace_param; + /* ------------------------------------------------------------------------ + * Driver specific constants + */ ++#define UVC_SG_REQ + ++#ifdef UVC_SG_REQ ++#define UVC_NUM_REQUESTS 1 ++#else + #define UVC_NUM_REQUESTS 4 ++#endif + #define UVC_MAX_REQUEST_SIZE 64 + #define UVC_MAX_EVENTS 4 + ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++/* ------------------------------------------------------------------------ ++ * UVC packet operation ++ */ ++struct uvc_video; ++struct uvc_pack_trans { ++ struct list_head list; ++ ++ uint64_t addr; ++ unsigned int len; ++ unsigned int buf_used; ++ ++ bool is_frame_end; ++ bool need_free; ++ ++ struct uvc_pack *pack; ++ int frame_cnts; ++ struct uvc_video *video; ++ spinlock_t lock; ++}; ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ ++ + /* ------------------------------------------------------------------------ + * Structures + */ +@@ -87,7 +120,10 @@ struct uvc_video { + unsigned int height; + unsigned int imagesize; + struct mutex mutex; /* protects frame parameters */ +- ++#ifdef UVC_SG_REQ ++ unsigned int num_sgs; /* record base */ ++ __u8 *sg_buf; ++#endif + /* Requests */ + unsigned int req_size; + struct usb_request *req[UVC_NUM_REQUESTS]; +@@ -95,8 +131,13 @@ struct uvc_video { + struct list_head req_free; + spinlock_t req_lock; + ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ void (*encode) (struct usb_request *req, struct uvc_video *video, ++ struct uvc_pack_trans *pack); ++#else + void (*encode) (struct usb_request *req, struct uvc_video *video, + struct uvc_buffer *buf); ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + + /* Context data used by the completion handler */ + __u32 payload_size; +@@ -104,6 +145,9 @@ struct uvc_video { + + struct uvc_video_queue queue; + unsigned int fid; ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ volatile bool is_streaming; ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + }; + + enum uvc_state { +diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c +index 00fb58e50a15..af083ddf3529 100644 +--- a/drivers/usb/gadget/function/uvc_configfs.c ++++ b/drivers/usb/gadget/function/uvc_configfs.c +@@ -319,7 +319,49 @@ static ssize_t uvcg_default_processing_bm_controls_show( + return result; + } + +-UVC_ATTR_RO(uvcg_default_processing_, bm_controls, bmControls); ++static ssize_t uvcg_default_processing_bm_controls_store( ++ struct config_item *item, const char *page, size_t len) ++{ ++ struct config_group *group = to_config_group(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &group->cg_subsys->su_mutex; ++ struct uvc_processing_unit_descriptor *pd; ++ int ret, i; ++ const char *pg = page; ++ /* sign, base 2 representation, newline, terminator */ ++ char buf[1 + sizeof(u8) * 8 + 1 + 1]; ++ int idx; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ pd = &opts->uvc_processing; ++ ++ idx = 0; ++ while (pg - page < len) { ++ i = 0; ++ while (i < sizeof(buf) && (pg - page < len) && ++ *pg != '\0' && *pg != '\n') ++ buf[i++] = *pg++; ++ while ((pg - page < len) && (*pg == '\0' || *pg == '\n')) ++ ++pg; ++ buf[i] = '\0'; ++ ret = kstrtou8(buf, 0, &pd->bmControls[idx++]); ++ if (ret < 0) ++ goto end; ++ if (idx >= pd->bControlSize) ++ break; ++ } ++ ret = len; ++end: ++ mutex_unlock(&opts->lock); ++ mutex_unlock(su_mutex); ++ return ret; ++} ++ ++UVC_ATTR(uvcg_default_processing_, bm_controls, bmControls); + + static struct configfs_attribute *uvcg_default_processing_attrs[] = { + &uvcg_default_processing_attr_b_unit_id, +@@ -355,6 +397,106 @@ static const struct uvcg_config_group_type uvcg_processing_grp_type = { + }, + }; + ++/* ----------------------------------------------------------------------------- ++ * control/extension/default ++ */ ++ ++#define UVCG_DEFAULT_EXTENSION_ATTR(cname, aname, bits) \ ++static ssize_t uvcg_default_extension_##cname##_show( \ ++ struct config_item *item, char *page) \ ++{ \ ++ struct config_group *group = to_config_group(item); \ ++ struct f_uvc_opts *opts; \ ++ struct config_item *opts_item; \ ++ struct mutex *su_mutex = &group->cg_subsys->su_mutex; \ ++ struct UVC_EXTENSION_UNIT_DESCRIPTOR(1, 2) *ed; \ ++ int result; \ ++ \ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ ++ \ ++ opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; \ ++ opts = to_f_uvc_opts(opts_item); \ ++ ed = &opts->uvc_extension; \ ++ \ ++ mutex_lock(&opts->lock); \ ++ result = sprintf(page, "%u\n", le##bits##_to_cpu(ed->aname)); \ ++ mutex_unlock(&opts->lock); \ ++ \ ++ mutex_unlock(su_mutex); \ ++ return result; \ ++} \ ++ \ ++UVC_ATTR_RO(uvcg_default_extension_, cname, aname) ++ ++UVCG_DEFAULT_EXTENSION_ATTR(b_unit_id, bUnitID, 8); ++UVCG_DEFAULT_EXTENSION_ATTR(b_num_input_pins, bNrInPins, 8); ++UVCG_DEFAULT_EXTENSION_ATTR(i_extension, iExtension, 8); ++ ++#undef UVCG_DEFAULT_EXTENSION_ATTR ++ ++static ssize_t uvcg_default_extension_bm_controls_show( ++ struct config_item *item, char *page) ++{ ++ struct config_group *group = to_config_group(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &group->cg_subsys->su_mutex; ++ struct UVC_EXTENSION_UNIT_DESCRIPTOR(1, 2) *ed; ++ int result, i; ++ char *pg = page; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ed = &opts->uvc_extension; ++ ++ mutex_lock(&opts->lock); ++ for (result = 0, i = 0; i < ed->bControlSize; ++i) { ++ result += sprintf(pg, "%d\n", ed->bmControls[i]); ++ pg = page + result; ++ } ++ mutex_unlock(&opts->lock); ++ ++ mutex_unlock(su_mutex); ++ ++ return result; ++} ++ ++UVC_ATTR_RO(uvcg_default_extension_, bm_controls, bmControls); ++ ++static struct configfs_attribute *uvcg_default_extension_attrs[] = { ++ &uvcg_default_extension_attr_b_unit_id, ++ &uvcg_default_extension_attr_b_num_input_pins, ++ &uvcg_default_extension_attr_bm_controls, ++ &uvcg_default_extension_attr_i_extension, ++ NULL, ++}; ++ ++static const struct uvcg_config_group_type uvcg_default_extension_type = { ++ .type = { ++ .ct_item_ops = &uvcg_config_item_ops, ++ .ct_attrs = uvcg_default_extension_attrs, ++ .ct_owner = THIS_MODULE, ++ }, ++ .name = "default", ++}; ++ ++/* ----------------------------------------------------------------------------- ++ * control/extension ++ */ ++static const struct uvcg_config_group_type uvcg_extension_grp_type = { ++ .type = { ++ .ct_item_ops = &uvcg_config_item_ops, ++ .ct_owner = THIS_MODULE, ++ }, ++ .name = "extension", ++ .children = (const struct uvcg_config_group_type*[]) { ++ &uvcg_default_extension_type, ++ NULL, ++ }, ++}; ++ + /* ----------------------------------------------------------------------------- + * control/terminal/camera/default + */ +@@ -430,7 +572,50 @@ static ssize_t uvcg_default_camera_bm_controls_show( + return result; + } + +-UVC_ATTR_RO(uvcg_default_camera_, bm_controls, bmControls); ++static ssize_t uvcg_default_camera_bm_controls_store( ++ struct config_item *item, const char *page, size_t len) ++{ ++ struct config_group *group = to_config_group(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &group->cg_subsys->su_mutex; ++ struct uvc_camera_terminal_descriptor *cd; ++ int ret, i; ++ const char *pg = page; ++ /* sign, base 2 representation, newline, terminator */ ++ char buf[1 + sizeof(u8) * 8 + 1 + 1]; ++ int idx; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = group->cg_item.ci_parent->ci_parent->ci_parent-> ++ ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ cd = &opts->uvc_camera_terminal; ++ ++ idx = 0; ++ while (pg - page < len) { ++ i = 0; ++ while (i < sizeof(buf) && (pg - page < len) && ++ *pg != '\0' && *pg != '\n') ++ buf[i++] = *pg++; ++ while ((pg - page < len) && (*pg == '\0' || *pg == '\n')) ++ ++pg; ++ buf[i] = '\0'; ++ ret = kstrtou8(buf, 0, &cd->bmControls[idx++]); ++ if (ret < 0) ++ goto end; ++ if (idx >= cd->bControlSize) ++ break; ++ } ++ ret = len; ++end: ++ mutex_unlock(&opts->lock); ++ mutex_unlock(su_mutex); ++ return ret; ++} ++ ++UVC_ATTR(uvcg_default_camera_, bm_controls, bmControls); + + static struct configfs_attribute *uvcg_default_camera_attrs[] = { + &uvcg_default_camera_attr_b_terminal_id, +@@ -505,11 +690,68 @@ UVC_ATTR_RO(uvcg_default_output_, cname, aname) + UVCG_DEFAULT_OUTPUT_ATTR(b_terminal_id, bTerminalID, 8); + UVCG_DEFAULT_OUTPUT_ATTR(w_terminal_type, wTerminalType, 16); + UVCG_DEFAULT_OUTPUT_ATTR(b_assoc_terminal, bAssocTerminal, 8); +-UVCG_DEFAULT_OUTPUT_ATTR(b_source_id, bSourceID, 8); + UVCG_DEFAULT_OUTPUT_ATTR(i_terminal, iTerminal, 8); + + #undef UVCG_DEFAULT_OUTPUT_ATTR + ++static ssize_t uvcg_default_output_b_source_id_show(struct config_item *item, ++ char *page) ++{ ++ struct config_group *group = to_config_group(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &group->cg_subsys->su_mutex; ++ struct uvc_output_terminal_descriptor *cd; ++ int result; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = group->cg_item.ci_parent->ci_parent-> ++ ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ cd = &opts->uvc_output_terminal; ++ ++ mutex_lock(&opts->lock); ++ result = sprintf(page, "%u\n", le8_to_cpu(cd->bSourceID)); ++ mutex_unlock(&opts->lock); ++ ++ mutex_unlock(su_mutex); ++ ++ return result; ++} ++ ++static ssize_t uvcg_default_output_b_source_id_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct config_group *group = to_config_group(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &group->cg_subsys->su_mutex; ++ struct uvc_output_terminal_descriptor *cd; ++ int result; ++ u8 num; ++ ++ result = kstrtou8(page, 0, &num); ++ if (result) ++ return result; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = group->cg_item.ci_parent->ci_parent-> ++ ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ cd = &opts->uvc_output_terminal; ++ ++ mutex_lock(&opts->lock); ++ cd->bSourceID = num; ++ mutex_unlock(&opts->lock); ++ ++ mutex_unlock(su_mutex); ++ ++ return len; ++} ++UVC_ATTR(uvcg_default_output_, b_source_id, bSourceID); ++ + static struct configfs_attribute *uvcg_default_output_attrs[] = { + &uvcg_default_output_attr_b_terminal_id, + &uvcg_default_output_attr_w_terminal_type, +@@ -753,6 +995,7 @@ static const struct uvcg_config_group_type uvcg_control_grp_type = { + .children = (const struct uvcg_config_group_type*[]) { + &uvcg_control_header_grp_type, + &uvcg_processing_grp_type, ++ &uvcg_extension_grp_type, + &uvcg_terminal_grp_type, + &uvcg_control_class_grp_type, + NULL, +@@ -767,11 +1010,13 @@ static const struct uvcg_config_group_type uvcg_control_grp_type = { + static const char * const uvcg_format_names[] = { + "uncompressed", + "mjpeg", ++ "framebased" + }; + + enum uvcg_format_type { + UVCG_UNCOMPRESSED = 0, + UVCG_MJPEG, ++ UVCG_FRAME_FRAME_BASED, + }; + + struct uvcg_format { +@@ -1381,6 +1626,7 @@ static struct config_item *uvcg_frame_make(struct config_group *group, + return ERR_PTR(-EINVAL); + } + ++fmt->num_frames; ++ h->frame.b_frame_index = fmt->num_frames; + mutex_unlock(&opts->lock); + + config_item_init_type_name(&h->item, name, &uvcg_frame_type); +@@ -1422,30 +1668,321 @@ static void uvcg_format_set_indices(struct config_group *fmt) + } + + /* ----------------------------------------------------------------------------- +- * streaming/uncompressed/ ++ * frame_based + */ +- +-struct uvcg_uncompressed { +- struct uvcg_format fmt; +- struct uvc_format_uncompressed desc; ++struct uvcg_frame_based_frame { ++ struct config_item item; ++ enum uvcg_format_type fmt_type; ++ struct { ++ u8 b_length; ++ u8 b_descriptor_type; ++ u8 b_descriptor_subtype; ++ u8 b_frame_index; ++ u8 bm_capabilities; ++ u16 w_width; ++ u16 w_height; ++ u32 dw_min_bit_rate; ++ u32 dw_max_bit_rate; ++ u32 dw_default_frame_interval; ++ u8 b_frame_interval_type; ++ u32 dw_bytes_per_line; ++ } __attribute__((packed)) frame; ++ u32 *dw_frame_interval; + }; + +-static struct uvcg_uncompressed *to_uvcg_uncompressed(struct config_item *item) ++static struct uvcg_frame_based_frame *to_uvcg_frame_based_frame(struct config_item *item) + { +- return container_of( +- container_of(to_config_group(item), struct uvcg_format, group), +- struct uvcg_uncompressed, fmt); ++ return container_of(item, struct uvcg_frame_based_frame, item); + } + +-static struct configfs_group_operations uvcg_uncompressed_group_ops = { +- .make_item = uvcg_frame_make, +- .drop_item = uvcg_frame_drop, +-}; ++#define UVCG_FRAME_BASED_FRAME_ATTR(cname, aname, bits) \ ++static ssize_t uvcg_frame_based_frame_##cname##_show(struct config_item *item, char *page)\ ++{ \ ++ struct uvcg_frame_based_frame *f = to_uvcg_frame_based_frame(item); \ ++ struct f_uvc_opts *opts; \ ++ struct config_item *opts_item; \ ++ struct mutex *su_mutex = &f->item.ci_group->cg_subsys->su_mutex;\ ++ int result; \ ++ \ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ ++ \ ++ opts_item = f->item.ci_parent->ci_parent->ci_parent->ci_parent; \ ++ opts = to_f_uvc_opts(opts_item); \ ++ \ ++ mutex_lock(&opts->lock); \ ++ result = sprintf(page, "%d\n", f->frame.cname); \ ++ mutex_unlock(&opts->lock); \ ++ \ ++ mutex_unlock(su_mutex); \ ++ return result; \ ++} \ ++ \ ++static ssize_t uvcg_frame_based_frame_##cname##_store(struct config_item *item, \ ++ const char *page, size_t len)\ ++{ \ ++ struct uvcg_frame_based_frame *f = to_uvcg_frame_based_frame(item); \ ++ struct f_uvc_opts *opts; \ ++ struct config_item *opts_item; \ ++ struct uvcg_format *fmt; \ ++ struct mutex *su_mutex = &f->item.ci_group->cg_subsys->su_mutex;\ ++ int ret; \ ++ typeof(f->frame.cname) num; \ ++ \ ++ ret = kstrtou##bits(page, 0, &num); \ ++ if (ret) \ ++ return ret; \ ++ \ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ ++ \ ++ opts_item = f->item.ci_parent->ci_parent->ci_parent->ci_parent; \ ++ opts = to_f_uvc_opts(opts_item); \ ++ fmt = to_uvcg_format(f->item.ci_parent); \ ++ \ ++ mutex_lock(&opts->lock); \ ++ if (fmt->linked || opts->refcnt) { \ ++ ret = -EBUSY; \ ++ goto end; \ ++ } \ ++ \ ++ f->frame.cname = num; \ ++ ret = len; \ ++end: \ ++ mutex_unlock(&opts->lock); \ ++ mutex_unlock(su_mutex); \ ++ return ret; \ ++} \ ++ \ ++UVC_ATTR(uvcg_frame_based_frame_, cname, aname); + +-static ssize_t uvcg_uncompressed_guid_format_show(struct config_item *item, +- char *page) ++static ssize_t uvcg_frame_based_frame_b_frame_index_show(struct config_item *item, ++ char *page) + { +- struct uvcg_uncompressed *ch = to_uvcg_uncompressed(item); ++ struct uvcg_frame_based_frame *f = to_uvcg_frame_based_frame(item); ++ struct uvcg_format *fmt; ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct config_item *fmt_item; ++ struct mutex *su_mutex = &f->item.ci_group->cg_subsys->su_mutex; ++ int result; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ fmt_item = f->item.ci_parent; ++ fmt = to_uvcg_format(fmt_item); ++ ++ if (!fmt->linked) { ++ result = -EBUSY; ++ goto out; ++ } ++ ++ opts_item = fmt_item->ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ++ mutex_lock(&opts->lock); ++ result = sprintf(page, "%u\n", f->frame.b_frame_index); ++ mutex_unlock(&opts->lock); ++ ++out: ++ mutex_unlock(su_mutex); ++ return result; ++} ++ ++UVC_ATTR_RO(uvcg_frame_based_frame_, b_frame_index, bFrameIndex); ++ ++UVCG_FRAME_BASED_FRAME_ATTR(bm_capabilities, bmCapabilities, 8); ++UVCG_FRAME_BASED_FRAME_ATTR(w_width, wWidth, 16); ++UVCG_FRAME_BASED_FRAME_ATTR(w_height, wHeight, 16); ++UVCG_FRAME_BASED_FRAME_ATTR(dw_min_bit_rate, dwMinBitRate, 32); ++UVCG_FRAME_BASED_FRAME_ATTR(dw_max_bit_rate, dwMaxBitRate, 32); ++UVCG_FRAME_BASED_FRAME_ATTR(dw_default_frame_interval, dwDefaultFrameInterval, 32); ++UVCG_FRAME_BASED_FRAME_ATTR(dw_bytes_per_line, dwBytesPerLine, 32); ++ ++#undef UVCG_FRAME_BASED_FRAME_ATTR ++ ++static ssize_t uvcg_frame_based_frame_dw_frame_interval_show(struct config_item *item, ++ char *page) ++{ ++ struct uvcg_frame_based_frame *frm = to_uvcg_frame_based_frame(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &frm->item.ci_group->cg_subsys->su_mutex; ++ int result, i; ++ char *pg = page; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = frm->item.ci_parent->ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ++ mutex_lock(&opts->lock); ++ for (result = 0, i = 0; i < frm->frame.b_frame_interval_type; ++i) { ++ result += sprintf(pg, "%u\n", frm->dw_frame_interval[i]); ++ pg = page + result; ++ } ++ mutex_unlock(&opts->lock); ++ ++ mutex_unlock(su_mutex); ++ return result; ++} ++ ++static ssize_t uvcg_frame_based_frame_dw_frame_interval_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct uvcg_frame_based_frame *ch = to_uvcg_frame_based_frame(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct uvcg_format *fmt; ++ struct mutex *su_mutex = &ch->item.ci_group->cg_subsys->su_mutex; ++ int ret = 0, n = 0; ++ u32 *frm_intrv, *tmp; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = ch->item.ci_parent->ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ fmt = to_uvcg_format(ch->item.ci_parent); ++ ++ mutex_lock(&opts->lock); ++ if (fmt->linked || opts->refcnt) { ++ ret = -EBUSY; ++ goto end; ++ } ++ ++ ret = __uvcg_iter_frm_intrv(page, len, __uvcg_count_frm_intrv, &n); ++ if (ret) ++ goto end; ++ ++ tmp = frm_intrv = kcalloc(n, sizeof(u32), GFP_KERNEL); ++ if (!frm_intrv) { ++ ret = -ENOMEM; ++ goto end; ++ } ++ ++ ret = __uvcg_iter_frm_intrv(page, len, __uvcg_fill_frm_intrv, &tmp); ++ if (ret) { ++ kfree(frm_intrv); ++ goto end; ++ } ++ ++ kfree(ch->dw_frame_interval); ++ ch->dw_frame_interval = frm_intrv; ++ ch->frame.b_frame_interval_type = n; ++ sort(ch->dw_frame_interval, n, sizeof(*ch->dw_frame_interval), ++ uvcg_config_compare_u32, NULL); ++ ret = len; ++ ++end: ++ mutex_unlock(&opts->lock); ++ mutex_unlock(su_mutex); ++ return ret; ++} ++ ++UVC_ATTR(uvcg_frame_based_frame_, dw_frame_interval, dwFrameInterval); ++ ++static struct configfs_attribute *uvcg_frame_based_frame_attrs[] = { ++ &uvcg_frame_based_frame_attr_b_frame_index, ++ &uvcg_frame_based_frame_attr_bm_capabilities, ++ &uvcg_frame_based_frame_attr_w_width, ++ &uvcg_frame_based_frame_attr_w_height, ++ &uvcg_frame_based_frame_attr_dw_min_bit_rate, ++ &uvcg_frame_based_frame_attr_dw_max_bit_rate, ++ &uvcg_frame_based_frame_attr_dw_default_frame_interval, ++ &uvcg_frame_based_frame_attr_dw_frame_interval, ++ &uvcg_frame_based_frame_attr_dw_bytes_per_line, ++ NULL, ++}; ++ ++static const struct config_item_type uvcg_frame_based_frame_type = { ++ .ct_item_ops = &uvcg_config_item_ops, ++ .ct_attrs = uvcg_frame_based_frame_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_item *uvcg_frame_based_frame_make(struct config_group *group, ++ const char *name) ++{ ++ struct uvcg_frame_based_frame *h; ++ struct uvcg_format *fmt; ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ ++ h = kzalloc(sizeof(*h), GFP_KERNEL); ++ if (!h) ++ return ERR_PTR(-ENOMEM); ++ ++ h->frame.b_descriptor_type = USB_DT_CS_INTERFACE; ++ h->frame.b_frame_index = 1; ++ h->frame.w_width = 640; ++ h->frame.w_height = 360; ++ h->frame.dw_min_bit_rate = 18432000; ++ h->frame.dw_max_bit_rate = 55296000; ++ h->frame.dw_default_frame_interval = 333333; ++ h->frame.dw_bytes_per_line = 0; ++ ++ opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ++ mutex_lock(&opts->lock); ++ fmt = to_uvcg_format(&group->cg_item); ++ if (fmt->type == UVCG_FRAME_FRAME_BASED) { ++ h->frame.b_descriptor_subtype = UVC_VS_FRAME_FRAME_BASED; ++ h->fmt_type = UVCG_FRAME_FRAME_BASED; ++ } else { ++ mutex_unlock(&opts->lock); ++ kfree(h); ++ return ERR_PTR(-EINVAL); ++ } ++ ++fmt->num_frames; ++ h->frame.b_frame_index = fmt->num_frames; ++ mutex_unlock(&opts->lock); ++ ++ config_item_init_type_name(&h->item, name, &uvcg_frame_based_frame_type); ++ ++ return &h->item; ++} ++ ++static void uvcg_frame_based_frame_drop(struct config_group *group, struct config_item *item) ++{ ++ struct uvcg_frame_based_frame *h = to_uvcg_frame_based_frame(item); ++ struct uvcg_format *fmt; ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ ++ opts_item = group->cg_item.ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ++ mutex_lock(&opts->lock); ++ fmt = to_uvcg_format(&group->cg_item); ++ --fmt->num_frames; ++ kfree(h); ++ mutex_unlock(&opts->lock); ++} ++ ++/* ----------------------------------------------------------------------------- ++ * streaming/uncompressed/ ++ */ ++ ++struct uvcg_uncompressed { ++ struct uvcg_format fmt; ++ struct uvc_format_uncompressed desc; ++}; ++ ++static struct uvcg_uncompressed *to_uvcg_uncompressed(struct config_item *item) ++{ ++ return container_of( ++ container_of(to_config_group(item), struct uvcg_format, group), ++ struct uvcg_uncompressed, fmt); ++} ++ ++static struct configfs_group_operations uvcg_uncompressed_group_ops = { ++ .make_item = uvcg_frame_make, ++ .drop_item = uvcg_frame_drop, ++}; ++ ++static ssize_t uvcg_uncompressed_guid_format_show(struct config_item *item, ++ char *page) ++{ ++ struct uvcg_uncompressed *ch = to_uvcg_uncompressed(item); + struct f_uvc_opts *opts; + struct config_item *opts_item; + struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; +@@ -1856,6 +2393,252 @@ static const struct uvcg_config_group_type uvcg_mjpeg_grp_type = { + .name = "mjpeg", + }; + ++/* ----------------------------------------------------------------------------- ++ * streaming/frame_based/ ++ */ ++ ++struct uvcg_frame_based_format { ++ struct uvcg_format fmt; ++ struct uvc_frame_based_format_desc desc; ++}; ++ ++static struct uvcg_frame_based_format *to_uvcg_frame_based_format(struct config_item *item) ++{ ++ return container_of( ++ container_of(to_config_group(item), struct uvcg_format, group), ++ struct uvcg_frame_based_format, fmt); ++} ++ ++static struct configfs_group_operations uvcg_frame_based_format_group_ops = { ++ .make_item = uvcg_frame_based_frame_make, ++ .drop_item = uvcg_frame_based_frame_drop, ++}; ++ ++static ssize_t uvcg_frame_based_guid_format_show(struct config_item *item, ++ char *page) ++{ ++ struct uvcg_frame_based_format *ch = to_uvcg_frame_based_format(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = ch->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ++ mutex_lock(&opts->lock); ++ memcpy(page, ch->desc.guidFormat, sizeof(ch->desc.guidFormat)); ++ mutex_unlock(&opts->lock); ++ ++ mutex_unlock(su_mutex); ++ ++ return sizeof(ch->desc.guidFormat); ++} ++ ++static ssize_t uvcg_frame_based_guid_format_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct uvcg_frame_based_format *ch = to_uvcg_frame_based_format(item); ++ struct f_uvc_opts *opts; ++ struct config_item *opts_item; ++ struct mutex *su_mutex = &ch->fmt.group.cg_subsys->su_mutex; ++ int ret; ++ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ ++ ++ opts_item = ch->fmt.group.cg_item.ci_parent->ci_parent->ci_parent; ++ opts = to_f_uvc_opts(opts_item); ++ ++ mutex_lock(&opts->lock); ++ if (ch->fmt.linked || opts->refcnt) { ++ ret = -EBUSY; ++ goto end; ++ } ++ ++ memcpy(ch->desc.guidFormat, page, ++ min(sizeof(ch->desc.guidFormat), len)); ++ ret = sizeof(ch->desc.guidFormat); ++ ++end: ++ mutex_unlock(&opts->lock); ++ mutex_unlock(su_mutex); ++ return ret; ++} ++ ++UVC_ATTR(uvcg_frame_based_, guid_format, guidFormat); ++ ++#define UVCG_FRAME_BASED_FORMAT_ATTR_RO(cname, aname, bits) \ ++static ssize_t uvcg_frame_based_format_##cname##_show(struct config_item *item, char *page)\ ++{ \ ++ struct uvcg_frame_based_format *u = to_uvcg_frame_based_format(item); \ ++ struct f_uvc_opts *opts; \ ++ struct config_item *opts_item; \ ++ struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ ++ int result; \ ++ \ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ ++ \ ++ opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ ++ opts = to_f_uvc_opts(opts_item); \ ++ \ ++ mutex_lock(&opts->lock); \ ++ result = sprintf(page, "%u\n", le##bits##_to_cpu(u->desc.aname)); \ ++ mutex_unlock(&opts->lock); \ ++ \ ++ mutex_unlock(su_mutex); \ ++ return result; \ ++} \ ++ \ ++UVC_ATTR_RO(uvcg_frame_based_format_, cname, aname) ++ ++#define UVCG_FRAME_BASED_FORMAT_ATTR(cname, aname, bits) \ ++static ssize_t uvcg_frame_based_format_##cname##_show(struct config_item *item, char *page)\ ++{ \ ++ struct uvcg_frame_based_format *u = to_uvcg_frame_based_format(item); \ ++ struct f_uvc_opts *opts; \ ++ struct config_item *opts_item; \ ++ struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ ++ int result; \ ++ \ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ ++ \ ++ opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ ++ opts = to_f_uvc_opts(opts_item); \ ++ \ ++ mutex_lock(&opts->lock); \ ++ result = sprintf(page, "%u\n", le##bits##_to_cpu(u->desc.aname)); \ ++ mutex_unlock(&opts->lock); \ ++ \ ++ mutex_unlock(su_mutex); \ ++ return result; \ ++} \ ++ \ ++static ssize_t \ ++uvcg_frame_based_format_##cname##_store(struct config_item *item, \ ++ const char *page, size_t len) \ ++{ \ ++ struct uvcg_frame_based_format *u = to_uvcg_frame_based_format(item); \ ++ struct f_uvc_opts *opts; \ ++ struct config_item *opts_item; \ ++ struct mutex *su_mutex = &u->fmt.group.cg_subsys->su_mutex; \ ++ int ret; \ ++ u8 num; \ ++ \ ++ mutex_lock(su_mutex); /* for navigating configfs hierarchy */ \ ++ \ ++ opts_item = u->fmt.group.cg_item.ci_parent->ci_parent->ci_parent;\ ++ opts = to_f_uvc_opts(opts_item); \ ++ \ ++ mutex_lock(&opts->lock); \ ++ if (u->fmt.linked || opts->refcnt) { \ ++ ret = -EBUSY; \ ++ goto end; \ ++ } \ ++ \ ++ ret = kstrtou8(page, 0, &num); \ ++ if (ret) \ ++ goto end; \ ++ \ ++ u->desc.aname = num; \ ++ ret = len; \ ++end: \ ++ mutex_unlock(&opts->lock); \ ++ mutex_unlock(su_mutex); \ ++ return ret; \ ++} \ ++ \ ++UVC_ATTR(uvcg_frame_based_format_, cname, aname) ++ ++UVCG_FRAME_BASED_FORMAT_ATTR_RO(b_format_index, bFormatIndex, 8); ++UVCG_FRAME_BASED_FORMAT_ATTR(b_default_frame_index, bDefaultFrameIndex, 8); ++UVCG_FRAME_BASED_FORMAT_ATTR_RO(b_aspect_ratio_x, bAspectRatioX, 8); ++UVCG_FRAME_BASED_FORMAT_ATTR_RO(b_aspect_ratio_y, bAspectRatioY, 8); ++UVCG_FRAME_BASED_FORMAT_ATTR_RO(bm_interface_flags, bmInterfaceFlags, 8); ++ ++#undef UVCG_FRAME_BASED_FORMAT_ATTR ++#undef UVCG_FRAME_BASED_FORMAT_ATTR_RO ++ ++static inline ssize_t ++uvcg_frame_based_format_bma_controls_show(struct config_item *item, char *page) ++{ ++ struct uvcg_frame_based_format *u = to_uvcg_frame_based_format(item); ++ return uvcg_format_bma_controls_show(&u->fmt, page); ++} ++ ++static inline ssize_t ++uvcg_frame_based_format_bma_controls_store(struct config_item *item, ++ const char *page, size_t len) ++{ ++ struct uvcg_frame_based_format *u = to_uvcg_frame_based_format(item); ++ return uvcg_format_bma_controls_store(&u->fmt, page, len); ++} ++ ++UVC_ATTR(uvcg_frame_based_format_, bma_controls, bmaControls); ++ ++static struct configfs_attribute *uvcg_frame_based_format_attrs[] = { ++ &uvcg_frame_based_format_attr_b_format_index, ++ &uvcg_frame_based_attr_guid_format, ++ &uvcg_frame_based_format_attr_b_default_frame_index, ++ &uvcg_frame_based_format_attr_b_aspect_ratio_x, ++ &uvcg_frame_based_format_attr_b_aspect_ratio_y, ++ &uvcg_frame_based_format_attr_bm_interface_flags, ++ &uvcg_frame_based_format_attr_bma_controls, ++ NULL, ++}; ++ ++static struct config_item_type uvcg_frame_based_format_type = { ++ .ct_item_ops = &uvcg_config_item_ops, ++ .ct_group_ops = &uvcg_frame_based_format_group_ops, ++ .ct_attrs = uvcg_frame_based_format_attrs, ++ .ct_owner = THIS_MODULE, ++}; ++ ++static struct config_group *uvcg_frame_based_format_make(struct config_group *group, ++ const char *name) ++{ ++ static char guid[] = { /*Declear frame frame based as H264*/ ++ 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00, ++ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71 ++ }; ++ struct uvcg_frame_based_format *h; ++ ++ h = kzalloc(sizeof(*h), GFP_KERNEL); ++ if (!h) ++ return ERR_PTR(-ENOMEM); ++ ++ h->desc.bLength = UVC_DT_FRAME_BASED_FORMAT_SIZE; ++ h->desc.bDescriptorType = USB_DT_CS_INTERFACE; ++ h->desc.bDescriptorSubType = UVC_VS_FORMAT_FRAME_BASED; ++ memcpy(h->desc.guidFormat, guid, sizeof(guid)); ++ h->desc.bBitsPerPixel = 16; ++ h->desc.bDefaultFrameIndex = 1; ++ h->desc.bAspectRatioX = 0; ++ h->desc.bAspectRatioY = 0; ++ h->desc.bmInterfaceFlags = 0; ++ h->desc.bCopyProtect = 0; ++ h->desc.bVariableSize = 1; ++ ++ h->fmt.type = UVCG_FRAME_FRAME_BASED; ++ config_group_init_type_name(&h->fmt.group, name, ++ &uvcg_frame_based_format_type); ++ ++ return &h->fmt.group; ++} ++ ++static struct configfs_group_operations uvcg_frame_based_format_grp_ops = { ++ .make_group = uvcg_frame_based_format_make, ++}; ++ ++static const struct uvcg_config_group_type uvcg_frame_based_format_grp_type = { ++ .type = { ++ .ct_item_ops = &uvcg_config_item_ops, ++ .ct_group_ops = &uvcg_frame_based_format_grp_ops, ++ .ct_owner = THIS_MODULE, ++ }, ++ .name = "framebased", ++}; ++ + /* ----------------------------------------------------------------------------- + * streaming/color_matching/default + */ +@@ -2049,6 +2832,11 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, + container_of(fmt, struct uvcg_mjpeg, fmt); + + *size += sizeof(m->desc); ++ } else if (fmt->type == UVCG_FRAME_FRAME_BASED) { ++ struct uvcg_frame_based_format *h = ++ container_of(fmt, struct uvcg_frame_based_format, fmt); ++ ++ *size += sizeof(h->desc); + } else { + return -EINVAL; + } +@@ -2057,7 +2845,14 @@ static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n, + case UVCG_FRAME: { + struct uvcg_frame *frm = priv1; + int sz = sizeof(frm->dw_frame_interval); ++ if (frm->frame.b_descriptor_subtype == UVC_VS_FRAME_FRAME_BASED) { ++ struct uvcg_frame_based_frame *fb_frm = priv1; ++ *size += sizeof(fb_frm->frame); ++ *size += fb_frm->frame.b_frame_interval_type * sizeof(fb_frm->dw_frame_interval); + ++ ++*count; ++ return 0; ++ } + *size += sizeof(frm->frame); + *size += frm->frame.b_frame_interval_type * sz; + } +@@ -2123,6 +2918,15 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, + m->desc.bNumFrameDescriptors = fmt->num_frames; + memcpy(*dest, &m->desc, sizeof(m->desc)); + *dest += sizeof(m->desc); ++ } else if (fmt->type == UVCG_FRAME_FRAME_BASED) { ++ struct uvc_frame_based_format_desc *ffb = *dest; ++ struct uvcg_frame_based_format *h = ++ container_of(fmt, struct uvcg_frame_based_format, fmt); ++ ++ memcpy(*dest, &h->desc, sizeof(h->desc)); ++ *dest += sizeof(h->desc); ++ ffb->bNumFrameDescriptors = fmt->num_frames; ++ ffb->bFormatIndex = n + 1; + } else { + return -EINVAL; + } +@@ -2131,7 +2935,19 @@ static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n, + case UVCG_FRAME: { + struct uvcg_frame *frm = priv1; + struct uvc_descriptor_header *h = *dest; +- ++ if (frm->frame.b_descriptor_subtype == UVC_VS_FRAME_FRAME_BASED) { ++ struct uvcg_frame_based_frame *fb_frm = priv1; ++ sz = sizeof(fb_frm->frame); ++ memcpy(*dest, &fb_frm->frame, sz); ++ *dest += sz; ++ sz = fb_frm->frame.b_frame_interval_type * ++ sizeof(*fb_frm->dw_frame_interval); ++ memcpy(*dest, fb_frm->dw_frame_interval, sz); ++ *dest += sz; ++ h->bLength = UVC_DT_FRAME_BASED_FRAME_SIZE( ++ fb_frm->frame.b_frame_interval_type); ++ return 0; ++ } + sz = sizeof(frm->frame); + memcpy(*dest, &frm->frame, sz); + *dest += sz; +@@ -2357,6 +3173,7 @@ static const struct uvcg_config_group_type uvcg_streaming_grp_type = { + &uvcg_streaming_header_grp_type, + &uvcg_uncompressed_grp_type, + &uvcg_mjpeg_grp_type, ++ &uvcg_frame_based_format_grp_type, + &uvcg_color_matching_grp_type, + &uvcg_streaming_class_grp_type, + NULL, +diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c +index 65abd55ce234..c774cc1037de 100644 +--- a/drivers/usb/gadget/function/uvc_v4l2.c ++++ b/drivers/usb/gadget/function/uvc_v4l2.c +@@ -19,6 +19,8 @@ + #include + #include + ++#include ++ + #include "f_uvc.h" + #include "uvc.h" + #include "uvc_queue.h" +@@ -34,7 +36,7 @@ uvc_send_response(struct uvc_device *uvc, struct uvc_request_data *data) + { + struct usb_composite_dev *cdev = uvc->func.config->cdev; + struct usb_request *req = uvc->control_req; +- ++ iprec("%s", __func__); + if (data->length < 0) + return usb_ep_set_halt(cdev->gadget->ep0); + +@@ -57,7 +59,11 @@ struct uvc_format { + + static struct uvc_format uvc_formats[] = { + { 16, V4L2_PIX_FMT_YUYV }, ++ { 12, V4L2_PIX_FMT_NV21 }, ++ { 12, V4L2_PIX_FMT_NV12 }, + { 0, V4L2_PIX_FMT_MJPEG }, ++ { 0, V4L2_PIX_FMT_H264 }, ++ { 0, V4L2_PIX_FMT_H265 }, + }; + + static int +@@ -163,6 +169,7 @@ uvc_v4l2_qbuf(struct file *file, void *fh, struct v4l2_buffer *b) + struct video_device *vdev = video_devdata(file); + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + int ret; + + ret = uvcg_queue_buffer(&video->queue, b); +@@ -172,16 +179,24 @@ uvc_v4l2_qbuf(struct file *file, void *fh, struct v4l2_buffer *b) + schedule_work(&video->pump); + + return ret; ++#else /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ ++ schedule_work(&video->pump); ++ return 0; ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + } + + static int + uvc_v4l2_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b) + { ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ return 0; ++#else + struct video_device *vdev = video_devdata(file); + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; + + return uvcg_dequeue_buffer(&video->queue, b, file->f_flags & O_NONBLOCK); ++#endif + } + + static int +@@ -191,15 +206,17 @@ uvc_v4l2_streamon(struct file *file, void *fh, enum v4l2_buf_type type) + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; + int ret; +- ++ iprec("[%s] before uvcg_video_enable", __func__); ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + if (type != video->queue.queue.type) + return -EINVAL; +- ++#endif + /* Enable UVC video. */ + ret = uvcg_video_enable(video, 1); + if (ret < 0) + return ret; + ++ iprec("[%s] uvcg_video_enable return: %d", __func__, ret); + /* + * Complete the alternate setting selection setup phase now that + * userspace is ready to provide video frames. +@@ -216,10 +233,11 @@ uvc_v4l2_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) + struct video_device *vdev = video_devdata(file); + struct uvc_device *uvc = video_get_drvdata(vdev); + struct uvc_video *video = &uvc->video; +- ++ iprec("%s", __func__); ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + if (type != video->queue.queue.type) + return -EINVAL; +- ++#endif + return uvcg_video_enable(video, 0); + } + +diff --git a/drivers/usb/gadget/function/uvc_video.c b/drivers/usb/gadget/function/uvc_video.c +index 5ce548c2359d..9c62560dfb90 100644 +--- a/drivers/usb/gadget/function/uvc_video.c ++++ b/drivers/usb/gadget/function/uvc_video.c +@@ -12,16 +12,288 @@ + #include + #include + #include +- ++#include + #include + ++#include ++ + #include "uvc.h" + #include "uvc_queue.h" + #include "uvc_video.h" + ++#include ++#include ++#include ++ ++/*************************************************************/ ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++#define MAX_FRAME 1 ++static struct uvc_pack_trans g_uvc_pack; ++ ++/* the caller shoulud hold g_uvc_pack.lock */ ++static void clean_untrans_frame(bool need_clean_all) ++{ ++ struct uvc_pack_trans *p; ++ ++ int rem = MAX_FRAME; ++ if (need_clean_all == 1) ++ rem = 0; ++ ++ while ((g_uvc_pack.frame_cnts > rem) && !list_empty(&g_uvc_pack.list)) { ++ p = list_first_entry(&g_uvc_pack.list, struct uvc_pack_trans, list); ++ list_del(&p->list); ++ ++ if (p->need_free) ++ p->pack->callback_func(p->pack); ++ if (p->is_frame_end) ++ g_uvc_pack.frame_cnts--; ++ ++ kfree(p->pack); ++ kfree(p); ++ } ++} ++ ++/* the caller shoulud hold g_uvc_pack.lock */ ++static void pack_save_to_list(struct uvc_pack_trans *ptr, ++ struct uvc_pack *pack, bool is_frame_end, bool free) ++{ ++ ptr->pack = (struct uvc_pack *)kmalloc(sizeof(struct uvc_pack), GFP_KERNEL); ++ memcpy(ptr->pack, pack, sizeof(struct uvc_pack)); ++ ++ ptr->is_frame_end = is_frame_end; ++ ptr->need_free = free; ++ ptr->buf_used = 0; ++ ++ list_add_tail(&ptr->list, &g_uvc_pack.list); ++ ++ if (is_frame_end) { ++ g_uvc_pack.frame_cnts++; ++ if (g_uvc_pack.frame_cnts > MAX_FRAME) { ++ clean_untrans_frame(0); ++ } ++ if (unlikely(g_uvc_pack.video->is_streaming == false)) { ++ clean_untrans_frame(1); ++ } ++ } ++} ++ ++int uvc_recv_pack(struct uvc_pack *pack) ++{ ++ struct uvc_pack_trans *p = NULL; ++ struct uvc_pack_trans *q = NULL; ++ uint64_t end_virt_addr; ++ unsigned long flags; ++ ++ if (pack->buf_vir_addr == 0 || pack->pack_vir_addr == 0 || pack->pack_len == 0) { ++ printk(KERN_EMERG"[Error][uvc_recv_pack] Get NULL pointer addr or illegal length!"); ++ ++ clean_untrans_frame(1); ++ ++ if (pack->callback_func != NULL) ++ pack->callback_func(pack); ++ ++ return 0; ++ } ++ ++ end_virt_addr = pack->buf_vir_addr + pack->buf_size; ++ ++ if ((pack->pack_vir_addr < pack->buf_vir_addr) || (pack->pack_vir_addr > end_virt_addr)) { ++ printk(KERN_EMERG"[Error][uvc_recv_pack] Get illegal pack_vir_addr!"); ++ ++ clean_untrans_frame(1); ++ ++ if (pack->callback_func != NULL) ++ pack->callback_func(pack); ++ ++ return 0; ++ } ++ spin_lock_irqsave(&g_uvc_pack.lock, flags); ++ ++ p = (struct uvc_pack_trans *)kmalloc(sizeof(struct uvc_pack_trans), GFP_KERNEL); ++ if (p == NULL) { ++ printk("[Warning][uvc_recv_pack]Can not alloc uvc_pack_trans!"); ++ return -1; ++ } ++ if (pack->pack_vir_addr + pack->pack_len > end_virt_addr) { ++ p->len = end_virt_addr - pack->pack_vir_addr; ++ p->addr = pack->pack_vir_addr; ++ pack_save_to_list(p, pack, false, false); ++ ++ q = (struct uvc_pack_trans *)kmalloc(sizeof(struct uvc_pack_trans), GFP_KERNEL); ++ if (q == NULL) { ++ printk("[Warning][uvc_recv_pack]Can not alloc uvc_pack_trans!"); ++ return -1; ++ } ++ q->len = pack->pack_len - (end_virt_addr - pack->pack_vir_addr); ++ q->addr = pack->buf_vir_addr; ++ pack_save_to_list(q, pack, pack->is_frame_end, true); ++ } else { ++ p->len = pack->pack_len; ++ p->addr = pack->pack_vir_addr; ++ pack_save_to_list(p, pack, pack->is_frame_end, true); ++ } ++ ++ spin_unlock_irqrestore(&g_uvc_pack.lock, flags); ++ ++ return 0; ++} ++EXPORT_SYMBOL(uvc_recv_pack); ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ ++ + /* -------------------------------------------------------------------------- + * Video codecs + */ ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++static int ++uvc_video_encode_header(struct uvc_video *video, struct uvc_pack_trans *pack, ++ u8 *data, int len) ++{ ++ data[0] = 2; ++ data[1] = UVC_STREAM_EOH | video->fid; ++ ++ if ((pack->len - pack->buf_used <= len - 2) && pack->is_frame_end) ++ data[1] |= UVC_STREAM_EOF; ++ ++ return 2; ++} ++ ++static int ++uvc_video_encode_data(struct uvc_video *video, struct uvc_pack_trans *pack, ++ u8 *data, int len) ++{ ++ unsigned int nbytes; ++ void *mem; ++ ++ /* Copy video data to the USB buffer. */ ++ mem = (void *)pack->addr + pack->buf_used; ++ nbytes = min((unsigned int)len, pack->len - pack->buf_used); ++ ++ memcpy(data, mem, nbytes); ++ pack->buf_used += nbytes; ++ ++ return nbytes; ++} ++ ++static void ++uvc_video_encode_bulk(struct usb_request *req, struct uvc_video *video, ++ struct uvc_pack_trans *pack) ++{ ++ void *mem = req->buf; ++ int len = video->req_size; ++ int ret; ++ ++ /* Add a header at the beginning of the payload. */ ++ if (video->payload_size == 0) { ++ ret = uvc_video_encode_header(video, pack, mem, len); ++ video->payload_size += ret; ++ mem += ret; ++ len -= ret; ++ } ++ ++ /* Process video data. */ ++ len = min((int)(video->max_payload_size - video->payload_size), len); ++ ret = uvc_video_encode_data(video, pack, mem, len); ++ ++ video->payload_size += ret; ++ len -= ret; ++ ++ req->length = video->req_size - len; ++ req->zero = video->payload_size == video->max_payload_size; ++ ++ if (pack->len == pack->buf_used) { ++ pack->buf_used = 0; ++ video->fid ^= UVC_STREAM_FID; ++ ++ video->payload_size = 0; ++ } ++ ++ if (video->payload_size == video->max_payload_size || ++ pack->len == pack->buf_used) ++ video->payload_size = 0; ++} ++ ++/* the caller shoulud hold g_uvc_pack.lock */ ++static void ++uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video, ++ struct uvc_pack_trans *g_pack) ++{ ++ int ret; ++ struct uvc_pack_trans *pack = NULL; ++#ifdef UVC_SG_REQ ++ int len; ++ int ttllen = 0; ++ unsigned int sg_idx; ++ u8 *mem = NULL; ++ ++ for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) { ++ if (unlikely(list_empty(&g_pack->list) || (g_pack->frame_cnts == 0))) ++ break; ++ ++ pack = list_first_entry(&g_pack->list, struct uvc_pack_trans, list); ++ ++ mem = sg_virt(&req->sg[sg_idx]); ++ len = video->req_size; ++ ++ /* Add the header. */ ++ ret = uvc_video_encode_header(video, pack, mem, len); ++ mem += ret; ++ len -= ret; ++ ++ /* Process video data. */ ++ ret = uvc_video_encode_data(video, pack, mem, len); ++ len -= ret; ++ ++ /* Sync sg buffer len , default is 1024 or 3072 */ ++ sg_set_buf(&req->sg[sg_idx], sg_virt(&req->sg[sg_idx]), ++ video->req_size - len); ++ ttllen += video->req_size - len; ++ ++ if (pack->len == pack->buf_used) { ++ pack->buf_used = 0; ++ ++ list_del(&pack->list); ++ if (pack->need_free) ++ pack->pack->callback_func(pack->pack); ++ ++ if (pack->is_frame_end) { ++ g_pack->frame_cnts--; ++ video->fid ^= UVC_STREAM_FID; ++ kfree(pack->pack); ++ kfree(pack); ++ break; ++ } ++ ++ kfree(pack->pack); ++ kfree(pack); ++ } ++ } ++ req->num_sgs = sg_idx + 1; ++ sg_mark_end(&req->sg[sg_idx]); ++ req->length = ttllen; ++#else /* UVC_SG_REQ */ ++ void *mem = req->buf; ++ int len = video->req_size; ++ ++ /* Add the header. */ ++ ret = uvc_video_encode_header(video, pack, mem, len); ++ mem += ret; ++ len -= ret; ++ ++ /* Process video data. */ ++ ret = uvc_video_encode_data(video, pack, mem, len); ++ len -= ret; ++ ++ req->length = video->req_size - len; ++ ++ if (pack->len == pack->buf_used) { ++ pack->buf_used = 0; ++ if (pack->is_frame_end) ++ video->fid ^= UVC_STREAM_FID; ++ } ++#endif /* UVC_SG_REQ */ ++} ++ ++#else /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + + static int + uvc_video_encode_header(struct uvc_video *video, struct uvc_buffer *buf, +@@ -98,6 +370,43 @@ static void + uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video, + struct uvc_buffer *buf) + { ++ int ret; ++#ifdef UVC_SG_REQ ++ int len; ++ int ttllen = 0; ++ unsigned int sg_idx; ++ u8 *mem = NULL; ++ ++ for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) { ++ mem = sg_virt(&req->sg[sg_idx]); ++ len = video->req_size; ++ ++ /* Add the header. */ ++ ret = uvc_video_encode_header(video, buf, mem, len); ++ mem += ret; ++ len -= ret; ++ ++ /* Process video data. */ ++ ret = uvc_video_encode_data(video, buf, mem, len); ++ len -= ret; ++ ++ /* Sync sg buffer len , default is 1024 or 3072 */ ++ sg_set_buf(&req->sg[sg_idx], sg_virt(&req->sg[sg_idx]), ++ video->req_size - len); ++ ttllen += video->req_size - len; ++ ++ if (buf->bytesused == video->queue.buf_used) { ++ video->queue.buf_used = 0; ++ buf->state = UVC_BUF_STATE_DONE; ++ uvcg_queue_next_buffer(&video->queue, buf); ++ video->fid ^= UVC_STREAM_FID; ++ break; ++ } ++ } ++ req->num_sgs = sg_idx + 1; ++ sg_mark_end(&req->sg[sg_idx]); ++ req->length = ttllen; ++#else /* UVC_SG_REQ */ + void *mem = req->buf; + int len = video->req_size; + int ret; +@@ -119,8 +428,9 @@ uvc_video_encode_isoc(struct usb_request *req, struct uvc_video *video, + uvcg_queue_next_buffer(&video->queue, buf); + video->fid ^= UVC_STREAM_FID; + } ++#endif /* UVC_SG_REQ */ + } +- ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + /* -------------------------------------------------------------------------- + * Request handling + */ +@@ -129,14 +439,26 @@ static int uvcg_video_ep_queue(struct uvc_video *video, struct usb_request *req) + { + int ret; + ++ /* ++ * Fixme, this is just to workaround the warning by udc core when the ep ++ * is disabled, this may happens when the uvc application is still ++ * streaming new data while the uvc gadget driver has already recieved ++ * the streamoff but the streamoff event is not yet received by the app ++ */ ++ if (!video->ep->enabled) ++ return -EINVAL; ++ + ret = usb_ep_queue(video->ep, req, GFP_ATOMIC); + if (ret < 0) { + uvcg_err(&video->uvc->func, "Failed to queue request (%d).\n", + ret); + +- /* Isochronous endpoints can't be halted. */ +- if (usb_endpoint_xfer_bulk(video->ep->desc)) +- usb_ep_set_halt(video->ep); ++ /* If the endpoint is disabled the descriptor may be NULL. */ ++ if (video->ep->desc) { ++ /* Isochronous endpoints can't be halted. */ ++ if (usb_endpoint_xfer_bulk(video->ep->desc)) ++ usb_ep_set_halt(video->ep); ++ } + } + + return ret; +@@ -146,7 +468,9 @@ static void + uvc_video_complete(struct usb_ep *ep, struct usb_request *req) + { + struct uvc_video *video = req->context; ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + struct uvc_video_queue *queue = &video->queue; ++#endif + unsigned long flags; + + switch (req->status) { +@@ -155,14 +479,18 @@ uvc_video_complete(struct usb_ep *ep, struct usb_request *req) + + case -ESHUTDOWN: /* disconnect from host. */ + uvcg_dbg(&video->uvc->func, "VS request cancelled.\n"); ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + uvcg_queue_cancel(queue, 1); ++#endif + break; + + default: + uvcg_warn(&video->uvc->func, + "VS request completed with status %d.\n", + req->status); ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + uvcg_queue_cancel(queue, 0); ++#endif + } + + spin_lock_irqsave(&video->req_lock, flags); +@@ -176,9 +504,27 @@ static int + uvc_video_free_requests(struct uvc_video *video) + { + unsigned int i; ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ unsigned long flags; ++#endif ++#ifdef UVC_SG_REQ ++ unsigned int sg_idx; ++#endif + + for (i = 0; i < UVC_NUM_REQUESTS; ++i) { + if (video->req[i]) { ++#ifdef UVC_SG_REQ ++ for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) ++ if (sg_page(&video->req[i]->sg[sg_idx])) { ++ kfree(sg_virt(&video->req[i]->sg[sg_idx])); ++ video->req[i]->num_mapped_sgs = 0; ++ } ++ ++ if (video->req[i]->sg) { ++ kfree(video->req[i]->sg); ++ video->req[i]->sg = NULL; ++ } ++#endif + usb_ep_free_request(video->ep, video->req[i]); + video->req[i] = NULL; + } +@@ -189,6 +535,14 @@ uvc_video_free_requests(struct uvc_video *video) + } + } + ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ spin_lock_irqsave(&g_uvc_pack.lock, flags); ++ clean_untrans_frame(1); ++ g_uvc_pack.video->is_streaming = false; ++ spin_unlock_irqrestore(&g_uvc_pack.lock, flags); ++ ++#endif ++ + INIT_LIST_HEAD(&video->req_free); + video->req_size = 0; + return 0; +@@ -200,6 +554,11 @@ uvc_video_alloc_requests(struct uvc_video *video) + unsigned int req_size; + unsigned int i; + int ret = -ENOMEM; ++#ifdef UVC_SG_REQ ++ struct scatterlist *sg; ++ unsigned int num_sgs; ++ unsigned int sg_idx; ++#endif + + BUG_ON(video->req_size); + +@@ -207,6 +566,35 @@ uvc_video_alloc_requests(struct uvc_video *video) + * max_t(unsigned int, video->ep->maxburst, 1) + * (video->ep->mult); + ++#ifdef UVC_SG_REQ ++ num_sgs = ((video->imagesize / (req_size - 2)) + 1); ++ video->num_sgs = num_sgs; ++ ++ for (i = 0; i < UVC_NUM_REQUESTS; ++i) { ++ sg = kmalloc(num_sgs * sizeof(struct scatterlist), GFP_ATOMIC); ++ if (sg == NULL) ++ goto error; ++ sg_init_table(sg, num_sgs); ++ ++ video->req[i] = usb_ep_alloc_request(video->ep, GFP_KERNEL); ++ if (video->req[i] == NULL) ++ goto error; ++ ++ for (sg_idx = 0 ; sg_idx < num_sgs ; sg_idx++) { ++ video->sg_buf = kmalloc(req_size, GFP_KERNEL); ++ if (video->sg_buf == NULL) ++ goto error; ++ sg_set_buf(&sg[sg_idx], video->sg_buf, req_size); ++ } ++ video->req[i]->sg = sg; ++ video->req[i]->num_sgs = num_sgs; ++ video->req[i]->length = 0; ++ video->req[i]->complete = uvc_video_complete; ++ video->req[i]->context = video; ++ ++ list_add_tail(&video->req[i]->list, &video->req_free); ++ } ++#else + for (i = 0; i < UVC_NUM_REQUESTS; ++i) { + video->req_buffer[i] = kmalloc(req_size, GFP_KERNEL); + if (video->req_buffer[i] == NULL) +@@ -223,7 +611,7 @@ uvc_video_alloc_requests(struct uvc_video *video) + + list_add_tail(&video->req[i]->list, &video->req_free); + } +- ++#endif + video->req_size = req_size; + + return 0; +@@ -243,9 +631,69 @@ uvc_video_alloc_requests(struct uvc_video *video) + * This function fills the available USB requests (listed in req_free) with + * video data from the queued buffers. + */ ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++static void uvcg_video_pump(struct work_struct *work) ++{ ++ struct uvc_video *video = container_of(work, struct uvc_video, pump); ++ struct usb_request *req; ++ unsigned long flags; ++ int ret; ++ ++ if (g_uvc_pack.video->is_streaming == false) ++ return; ++ ++ while (1) { ++ /* Retrieve the first available USB request, protected by the ++ * request lock. ++ */ ++ spin_lock_irqsave(&video->req_lock, flags); ++ if (list_empty(&video->req_free)) { ++ spin_unlock_irqrestore(&video->req_lock, flags); ++ return; ++ } ++ req = list_first_entry(&video->req_free, struct usb_request, ++ list); ++ list_del(&req->list); ++ spin_unlock_irqrestore(&video->req_lock, flags); ++ ++ /* Retrieve the first available video buffer and fill the ++ * request, protected by the video queue irqlock. ++ */ ++ spin_lock_irqsave(&g_uvc_pack.lock, flags); ++ if (list_empty(&g_uvc_pack.list) || (g_uvc_pack.frame_cnts == 0)) { ++ spin_unlock_irqrestore(&g_uvc_pack.lock, flags); ++ break; ++ } ++ ++#ifdef UVC_SG_REQ ++ sg_unmark_end(&req->sg[req->num_sgs - 1]); ++#endif ++ ++ video->encode(req, video, &g_uvc_pack); ++ ++ /* Queue the USB request */ ++ ret = uvcg_video_ep_queue(video, req); ++ if (ret < 0) { ++ spin_unlock_irqrestore(&g_uvc_pack.lock, flags); ++ break; ++ } ++ ++ spin_unlock_irqrestore(&g_uvc_pack.lock, flags); ++ } ++ ++ spin_lock_irqsave(&video->req_lock, flags); ++#ifdef UVC_SG_REQ ++ sg_unmark_end(&req->sg[req->num_sgs - 1]); ++#endif ++ list_add_tail(&req->list, &video->req_free); ++ spin_unlock_irqrestore(&video->req_lock, flags); ++ return; ++} ++#else /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + static void uvcg_video_pump(struct work_struct *work) + { + struct uvc_video *video = container_of(work, struct uvc_video, pump); ++ + struct uvc_video_queue *queue = &video->queue; + struct usb_request *req; + struct uvc_buffer *buf; +@@ -276,6 +724,10 @@ static void uvcg_video_pump(struct work_struct *work) + break; + } + ++#ifdef UVC_SG_REQ ++ sg_unmark_end(&req->sg[req->num_sgs - 1]); ++#endif ++ + video->encode(req, video, buf); + + /* Queue the USB request */ +@@ -289,10 +741,14 @@ static void uvcg_video_pump(struct work_struct *work) + } + + spin_lock_irqsave(&video->req_lock, flags); ++#ifdef UVC_SG_REQ ++ sg_unmark_end(&req->sg[req->num_sgs - 1]); ++#endif + list_add_tail(&req->list, &video->req_free); + spin_unlock_irqrestore(&video->req_lock, flags); + return; + } ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ + + /* + * Enable or disable the video stream. +@@ -301,7 +757,11 @@ int uvcg_video_enable(struct uvc_video *video, int enable) + { + unsigned int i; + int ret; ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ unsigned long flags; ++#endif + ++ iprec("[%s] %d", __func__, enable); + if (video->ep == NULL) { + uvcg_info(&video->uvc->func, + "Video enable failed, device is uninitialized.\n"); +@@ -317,12 +777,16 @@ int uvcg_video_enable(struct uvc_video *video, int enable) + usb_ep_dequeue(video->ep, video->req[i]); + + uvc_video_free_requests(video); ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + uvcg_queue_enable(&video->queue, 0); ++#endif + return 0; + } + ++#if !(IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC)) + if ((ret = uvcg_queue_enable(&video->queue, 1)) < 0) + return ret; ++#endif + + if ((ret = uvc_video_alloc_requests(video)) < 0) + return ret; +@@ -333,6 +797,12 @@ int uvcg_video_enable(struct uvc_video *video, int enable) + } else + video->encode = uvc_video_encode_isoc; + ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ spin_lock_irqsave(&g_uvc_pack.lock, flags); ++ g_uvc_pack.video->is_streaming = true; ++ spin_unlock_irqrestore(&g_uvc_pack.lock, flags); ++#endif ++ + schedule_work(&video->pump); + + return ret; +@@ -343,6 +813,13 @@ int uvcg_video_enable(struct uvc_video *video, int enable) + */ + int uvcg_video_init(struct uvc_video *video, struct uvc_device *uvc) + { ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++ INIT_LIST_HEAD(&g_uvc_pack.list); ++ spin_lock_init(&g_uvc_pack.lock); ++ g_uvc_pack.frame_cnts = 0; ++ video->is_streaming = false; ++ g_uvc_pack.video = video; ++#endif + INIT_LIST_HEAD(&video->req_free); + spin_lock_init(&video->req_lock); + INIT_WORK(&video->pump, uvcg_video_pump); +@@ -359,4 +836,3 @@ int uvcg_video_init(struct uvc_video *video, struct uvc_device *uvc) + &video->mutex); + return 0; + } +- +diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c +index a10f41c4a3f2..601829a6b4ba 100644 +--- a/drivers/usb/gadget/udc/renesas_usb3.c ++++ b/drivers/usb/gadget/udc/renesas_usb3.c +@@ -2568,7 +2568,6 @@ static int renesas_usb3_remove(struct platform_device *pdev) + debugfs_remove_recursive(usb3->dentry); + device_remove_file(&pdev->dev, &dev_attr_role); + +- cancel_work_sync(&usb3->role_work); + usb_role_switch_unregister(usb3->role_sw); + + usb_del_gadget_udc(&usb3->gadget); +diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c +index 3e5563308145..169513c45f87 100644 +--- a/drivers/usb/serial/option.c ++++ b/drivers/usb/serial/option.c +@@ -597,6 +597,9 @@ static void option_instat_callback(struct urb *urb); + #define SIERRA_VENDOR_ID 0x1199 + #define SIERRA_PRODUCT_EM9191 0x90d3 + ++/* TD tech products*/ ++#define TDTECH_VENDOR_ID 0x3466 ++ + /* Device flags */ + + /* Highest interface number which can be used with NCTRL() and RSVD() */ +@@ -616,6 +619,11 @@ static void option_instat_callback(struct urb *urb); + + + static const struct usb_device_id option_ids[] = { ++ { USB_VENDOR_AND_INTERFACE_INFO(0x3505, 0xFF, 0x03, 0x12)}, //Lierda AT ++ { USB_VENDOR_AND_INTERFACE_INFO(0x3505, 0xFF, 0x03, 0x14)}, //Lierda Diag Command ++ { USB_VENDOR_AND_INTERFACE_INFO(0x3505, 0xFF, 0x03, 0x13)}, //Lierda Diag Data ++ { USB_VENDOR_AND_INTERFACE_INFO(0x3505, 0xFF, 0x03, 0x03)}, //Lierda Cali ++ { USB_VENDOR_AND_INTERFACE_INFO(0x3505, 0xFF, 0x03, 0x01)}, //Lierda Modem + { USB_DEVICE(MEIG_VENDOR_ID, MEIG_PRODUCT_SLM790) }, + { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) }, + { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) }, +@@ -2216,6 +2224,102 @@ static const struct usb_device_id option_ids[] = { + { USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1D) }, + { } /* Terminating entry */ + }; + MODULE_DEVICE_TABLE(usb, option_ids); +diff --git a/drivers/vendor/Kconfig b/drivers/vendor/Kconfig +new file mode 100644 +index 000000000000..16c8d40eed64 +--- /dev/null ++++ b/drivers/vendor/Kconfig +@@ -0,0 +1,5 @@ ++menu "Vendor driver support" ++ ++source "drivers/vendor/cma/Kconfig" ++source "drivers/vendor/npu/Kconfig" ++endmenu +diff --git a/drivers/vendor/Makefile b/drivers/vendor/Makefile +new file mode 100644 +index 000000000000..f58e85332764 +--- /dev/null ++++ b/drivers/vendor/Makefile +@@ -0,0 +1,3 @@ ++obj-$(CONFIG_CMA) += cma/ ++obj-$(CONFIG_VENDOR_NPU) += npu/ ++obj-y += peri/ +diff --git a/drivers/vendor/cma/Kconfig b/drivers/vendor/cma/Kconfig +new file mode 100644 +index 000000000000..7472dccd8952 +--- /dev/null ++++ b/drivers/vendor/cma/Kconfig +@@ -0,0 +1,16 @@ ++ ++config CMA_MEM_SHARED ++ bool "Support sharing CMA memory with the heap" ++ depends on CMA && DMA_CMA ++ default no ++ help ++ Support sharing CMA memory with the heap. ++ ++config CMA_ADVANCE_SHARE ++ bool "Support cma advance share" ++ depends on CMA && DMA_CMA ++ select CMA_MEM_SHARED ++ default no ++ help ++ Support advance sharing CMA memory with the heap. ++ CMA Multiplex Ratio will be improved when this macro defined. +diff --git a/drivers/vendor/cma/Makefile b/drivers/vendor/cma/Makefile +new file mode 100644 +index 000000000000..97d57397963f +--- /dev/null ++++ b/drivers/vendor/cma/Makefile +@@ -0,0 +1,2 @@ ++ ++obj-$(CONFIG_CMA) += cma.o +diff --git a/drivers/vendor/cma/cma.c b/drivers/vendor/cma/cma.c +new file mode 100644 +index 000000000000..cd3dfcce3600 +--- /dev/null ++++ b/drivers/vendor/cma/cma.c +@@ -0,0 +1,176 @@ ++/* ++ * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2020-2023. All rights reserved. ++ */ ++#include ++#include ++ ++static u32 num_zones; ++static struct cma_zone bsp_zone[ZONE_MAX]; ++static int use_bootargs; ++ ++unsigned int get_cma_size(void) ++{ ++ u32 i; ++ u64 total = 0; ++ ++ for (i = 0; i < num_zones; i++) ++ total += bsp_zone[i].nbytes; ++ ++ return (unsigned int)(total >> 20); /* unit M: shift right 20 bits */ ++} ++ ++int is_cma_address(phys_addr_t phys, unsigned long size) ++{ ++ phys_addr_t start, end; ++ u32 i; ++ ++ for (i = 0; i < num_zones; i++) { ++ start = bsp_zone[i].phys_start; ++ end = bsp_zone[i].phys_start + bsp_zone[i].nbytes; ++ ++ if ((phys >= start) && ((phys + size) <= end)) ++ return 1; /* Yes, found! */ ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(is_cma_address); ++ ++static int __init bsp_mmz_parse_cmdline(char *s) ++{ ++ char *line = NULL, *tmp = NULL; ++ char tmpline[256]; ++ int ret; ++ ++ if (s == NULL) { ++ pr_info("There is no cma zone!\n"); ++ return 0; ++ } ++ ret = strncpy_s(tmpline, sizeof(tmpline), s, sizeof(tmpline) - 1); ++ if (ret) { ++ printk("%s:strncpy_s failed\n", __func__); ++ return ret; ++ } ++ ++ tmpline[sizeof(tmpline) - 1] = '\0'; ++ tmp = tmpline; ++ ++ while ((line = strsep(&tmp, ":")) != NULL) { ++ int i; ++ char *argv[6]; ++ ++ for (i = 0; (argv[i] = strsep(&line, ",")) != NULL;) ++ if (++i == ARRAY_SIZE(argv)) ++ break; ++ ++ if (num_zones >= ZONE_MAX) ++ return 0; ++ bsp_zone[num_zones].pdev.coherent_dma_mask = DMA_BIT_MASK(64); ++ if (i == 4) { ++ strlcpy(bsp_zone[num_zones].name, argv[0], NAME_LEN_MAX); ++ bsp_zone[num_zones].gfp = (uintptr_t)memparse(argv[1], NULL); ++ bsp_zone[num_zones].phys_start = (uintptr_t)memparse(argv[2], NULL); ++ bsp_zone[num_zones].nbytes = (uintptr_t)memparse(argv[3], NULL); ++ } ++ ++ else if (i == 6) { ++ strlcpy(bsp_zone[num_zones].name, argv[0], NAME_LEN_MAX); ++ bsp_zone[num_zones].gfp = (uintptr_t)memparse(argv[1], NULL); ++ bsp_zone[num_zones].phys_start = (uintptr_t)memparse(argv[2], NULL); ++ bsp_zone[num_zones].nbytes = (uintptr_t)memparse(argv[3], NULL); ++ bsp_zone[num_zones].alloc_type = (uintptr_t)memparse(argv[4], NULL); ++ bsp_zone[num_zones].block_align = (uintptr_t)memparse(argv[5], NULL); ++ } else { ++ pr_err("ion parameter is not correct\n"); ++ continue; ++ } ++ ++ num_zones++; ++ } ++ if (num_zones != 0) ++ use_bootargs = 1; ++ ++ return 0; ++} ++early_param("mmz", bsp_mmz_parse_cmdline); ++ ++phys_addr_t get_zones_start(void) ++{ ++ u32 i; ++ phys_addr_t lowest_zone_base = memblock_end_of_DRAM(); ++ ++ for (i = 0; i < num_zones; i++) { ++ if (lowest_zone_base > bsp_zone[i].phys_start) ++ lowest_zone_base = bsp_zone[i].phys_start; ++ } ++ ++ return lowest_zone_base; ++} ++EXPORT_SYMBOL(get_zones_start); ++ ++struct cma_zone *get_cma_zone(const char *name) ++{ ++ u32 i; ++ ++ if (name == NULL) ++ return NULL; ++ for (i = 0; i < num_zones; i++) ++ if (strcmp(bsp_zone[i].name, name) == 0) ++ break; ++ ++ if (i == num_zones) ++ return NULL; ++ ++ return &bsp_zone[i]; ++} ++EXPORT_SYMBOL(get_cma_zone); ++ ++struct device *get_cma_device(const char *name) ++{ ++ u32 i; ++ ++ if (name == NULL) ++ return NULL; ++ ++ for (i = 0; i < num_zones; i++) ++ if (strcmp(bsp_zone[i].name, name) == 0) ++ break; ++ ++ if (i == num_zones) ++ return NULL; ++ ++ return &bsp_zone[i].pdev; ++} ++EXPORT_SYMBOL(get_cma_device); ++ ++int __init declare_heap_memory(void) ++{ ++ u32 i; ++ int ret = 0; ++ ++ if (use_bootargs == 0) { ++ pr_info("cma zone is not set!\n"); ++ return ret; ++ } ++ ++ for (i = 0; i < num_zones; i++) { ++ ret = dma_contiguous_reserve_area(bsp_zone[i].nbytes, ++ bsp_zone[i].phys_start, 0, &bsp_zone[i].pdev.cma_area, true); ++ if (ret) ++ panic("declare cma zone %s base: %lux size:%lux MB failed. ret:%d", ++ bsp_zone[i].name, (unsigned long)bsp_zone[i].phys_start, ++ (unsigned long)bsp_zone[i].nbytes >> 20, ret); ++ ++ bsp_zone[i].phys_start = cma_get_base(bsp_zone[i].pdev.cma_area); ++ bsp_zone[i].nbytes = cma_get_size(bsp_zone[i].pdev.cma_area); ++ } ++ ++ return ret; ++} ++ ++static int bsp_mmz_setup(struct reserved_mem *rmem) ++{ ++ return 0; ++} ++RESERVEDMEM_OF_DECLARE(cma, "bsp-mmz", bsp_mmz_setup); ++ +diff --git a/drivers/vendor/npu/Kconfig b/drivers/vendor/npu/Kconfig +new file mode 100644 +index 000000000000..f986784037d5 +--- /dev/null ++++ b/drivers/vendor/npu/Kconfig +@@ -0,0 +1,7 @@ ++ ++config VENDOR_NPU ++ bool "Vendor NPU Feature" ++ default n ++ help ++ Support Vendor NPU. ++ +diff --git a/drivers/vendor/npu/Makefile b/drivers/vendor/npu/Makefile +new file mode 100644 +index 000000000000..e6f29554a159 +--- /dev/null ++++ b/drivers/vendor/npu/Makefile +@@ -0,0 +1,6 @@ ++ ++KBUILD_CFLAGS += -Werror ++ ++obj-$(CONFIG_VENDOR_NPU) += npu_svm.o ++obj-$(CONFIG_VENDOR_NPU) += npu_misc.o ++obj-$(CONFIG_VENDOR_NPU) += smmu_power_on.o +diff --git a/drivers/vendor/npu/npu_misc.c b/drivers/vendor/npu/npu_misc.c +new file mode 100644 +index 000000000000..879365801549 +--- /dev/null ++++ b/drivers/vendor/npu/npu_misc.c +@@ -0,0 +1,770 @@ ++/* ++ * Copyright (c) Shenshu Technologies Co., Ltd. 2020-2021. All rights reserved. ++ * Description: npu misc ++ * Version: Initial Draft ++ * Create: 2020-01-16 ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "linux/securec.h" ++ ++#define NPU_MISC_DEVICE_NAME "nmsc" ++ ++#define NPU_MISC_IOCTL_GET_PHYS 0xfff4 ++#define NPU_MISC_IOCTL_ADD_DBF 0xfff5 ++#define NPU_MISC_IOCTL_RMV_DBF 0xfff6 ++ ++#ifdef MISC_MEM_DBG ++#define NPU_MISC_IOCTL_DATA_COPY_TEST 0xfff8 ++#define NPU_MISC_IOCTL_SHOW_MEM 0xfff9 ++#endif ++ ++#define NPU_DBF_INDEX_VALID_FLAG 0x0 ++ ++#define NPU_MODULE_ID 0xAA ++#define NPU_MISC_SIG_INDEX_VALUE 2048 ++ ++#define NPU_MISC_MAX_DMA_BUF_TABLE 10 ++#define NPU_MISC_MAX_INDEX_VALUE (NPU_MISC_SIG_INDEX_VALUE * NPU_MISC_MAX_DMA_BUF_TABLE) ++ ++struct nmsc_device { ++ unsigned long long id; ++ struct miscdevice miscdev; ++ struct device *dev; ++}; ++ ++/* dbf(dma buffer fd) process */ ++struct dbf_process { ++ unsigned int flag; ++ unsigned int index; ++ struct dma_buf *dma_buf; ++ struct rb_node rb_node; ++}; ++ ++struct data_copy_info { ++ unsigned long long src_addr_info; ++ unsigned long long dst_addr_info; ++ unsigned int src_size; ++ unsigned int dst_size; ++}; ++ ++struct kva_map_params { ++ unsigned long long user_va; /* addr info from user space */ ++ void *kva; /* kernel virtual addr */ ++ void *buf_handle; /* buffer handle, e.g. dma buffer handle */ ++}; ++ ++struct mem_show_params { ++ unsigned long long user_addr_info; ++ unsigned int size; ++ unsigned int flag; /* 0: show vitual mem, 1: show physical mem */ ++}; ++ ++static struct mutex dbf_process_mutex; ++ ++struct dma_buf_table_index { ++ unsigned int valid_index; ++ unsigned int cur_table_index; ++ struct dma_buf** buff_index_table[NPU_MISC_MAX_DMA_BUF_TABLE]; // index for dma_buf table . ++}; ++ ++struct dfb_manager { ++ struct rb_root dfb_process_root; // rb tree to store dma_buffer info ++ struct dma_buf_table_index buf_table; ++}; ++ ++static struct dfb_manager dfb_man; ++ ++static char *nmsc_cmd_to_string(unsigned int cmd) ++{ ++ switch (cmd) { ++ case NPU_MISC_IOCTL_ADD_DBF: ++ return "add dma buffer fd"; ++ case NPU_MISC_IOCTL_RMV_DBF: ++ return "remove dma buffer fd"; ++#ifdef MISC_MEM_DBG ++ case NPU_MISC_IOCTL_GET_PHYS: ++ return "get phys"; ++ case NPU_MISC_IOCTL_DATA_COPY_TEST: ++ return "data copy test"; ++#endif ++ default: ++ return "unsupported"; ++ } ++} ++static struct nmsc_device *file_to_sdev(struct file *file) ++{ ++ return container_of(file->private_data, struct nmsc_device, miscdev); ++} ++#ifdef USE_ION ++ ++static void *kal_mem_handle_get(long fd, unsigned int module_id) ++{ ++ struct dma_buf *dmabuf = NULL; ++ ++ dmabuf = dma_buf_get(fd); ++ if (IS_ERR_OR_NULL(dmabuf)) { ++ pr_err("osal get handle failed!\n"); ++ return NULL; ++ } ++ ++ pr_debug("%s: module_id=%d get handle,ref:%pa,!\n", __func__, ++ module_id, &(dmabuf->file->f_count.counter)); ++ ++ return (void *)dmabuf; ++} ++ ++static void kal_mem_ref_put(void *handle, unsigned int module_id) ++{ ++ struct dma_buf *dmabuf = NULL; ++ ++ if (IS_ERR_OR_NULL(handle)) { ++ pr_err("%s, osal err args!\n", __func__); ++ return; ++ } ++ ++ dmabuf = (struct dma_buf *)handle; ++ dma_buf_put(dmabuf); ++ pr_debug("%s: module_id=%d put handle,ref:%pa,!\n", __func__, ++ module_id, &(dmabuf->file->f_count.counter)); ++ return; ++} ++ ++/* map cpu addr */ ++static void *kal_mem_kmap(void *handle, unsigned long offset, int cache) ++{ ++ void *virt = NULL; ++ struct dma_buf *dmabuf = NULL; ++ int ret; ++ ++ if (IS_ERR_OR_NULL(handle)) { ++ pr_err("%s, osal err args!\n", __func__); ++ return NULL; ++ } ++ dmabuf = (struct dma_buf *)handle; ++ ret = set_buffer_cached(dmabuf, cache); ++ if (ret) { ++ pr_err("osal set cache attr failed!\n"); ++ return NULL; ++ } ++ ++ virt = dma_buf_kmap(dmabuf, offset >> PAGE_SHIFT); ++ if (virt == NULL) { ++ set_buffer_cached(dmabuf, !cache); ++ pr_err("osal map failed!\n"); ++ return NULL; ++ } ++ ++ return virt; ++} ++ ++/* unmap cpu addr */ ++static void kal_mem_kunmap(void *handle, void *virt, unsigned long offset) ++{ ++ struct dma_buf *dmabuf = NULL; ++ ++ if (IS_ERR_OR_NULL(handle) || virt == NULL) { ++ pr_err("%s, osal err args!\n", __func__); ++ return; ++ } ++ ++ dmabuf = (struct dma_buf *)handle; ++ dma_buf_kunmap(dmabuf, offset >> PAGE_SHIFT, virt); ++} ++struct dma_buf *npu_misc_get_dma_buf(unsigned int db_idx) ++{ ++ struct dma_buf *temp = NULL; ++ unsigned int table_index; ++ unsigned int dma_index; ++ if (db_idx >= NPU_MISC_MAX_INDEX_VALUE) { ++ pr_err("%s, db_idx err args!\n", __func__); ++ return NULL; ++ } ++ ++ mutex_lock(&dbf_process_mutex); ++ table_index = db_idx / NPU_MISC_SIG_INDEX_VALUE; ++ dma_index = db_idx % NPU_MISC_SIG_INDEX_VALUE; ++ if (table_index > dfb_man.buf_table.cur_table_index) { ++ pr_err("%s, db_idx = %d is out of range! current table index = %d.\n", ++ __func__, db_idx, dfb_man.buf_table.cur_table_index); ++ return NULL; ++ } ++ temp = dfb_man.buf_table.buff_index_table[table_index][dma_index]; ++ if (temp == NULL) ++ pr_err("ERROR: db_idx = %d, has no dmabuff stored!!!\n", db_idx); ++ ++ mutex_unlock(&dbf_process_mutex); ++ return temp; ++} ++EXPORT_SYMBOL_GPL(npu_misc_get_dma_buf); ++ ++ ++int npu_kva_map(struct kva_map_params *kva_para) ++{ ++ unsigned int db_idx; ++ unsigned int buf_offset; ++ void *dma_buf = NULL; ++ void *kva = NULL; ++ if (kva_para == NULL) { ++ pr_err("%s[%d]: kva_para is illegal\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ db_idx = (unsigned int)(kva_para->user_va >> 32); // high 32 bit is used to save dfb index ++ if ((db_idx >> 24) != NPU_DBF_INDEX_VALID_FLAG) { // flag in in offset 24 bit ++ pr_err("%s[%d]: invalid user addr info \n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ buf_offset = (unsigned int)(kva_para->user_va & 0xFFFFFFFF); ++ ++ dma_buf = (void *)npu_misc_get_dma_buf(db_idx & 0x00FFFFFF); ++ if (dma_buf == NULL) { ++ pr_err("%s[%d]: fail get dma buf handle\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ kva_para->buf_handle = dma_buf; ++ ++ kva = kal_mem_kmap(dma_buf, buf_offset, 0); ++ if (kva == NULL) { ++ pr_err("%s[%d]: fail to map src address \n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ kva_para->kva = kva + buf_offset % PAGE_SIZE; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(npu_kva_map); ++ ++ ++int npu_kva_unmap(struct kva_map_params *kva_para) ++{ ++ void *kva = NULL; ++ unsigned int buf_offset; ++ ++ if (kva_para->kva == NULL || kva_para->buf_handle == NULL) { ++ pr_err("%s[%d]: invalid parameters\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ buf_offset = (unsigned int)(kva_para->user_va & 0xFFFFFFFF); ++ kva = kva_para->kva - buf_offset % PAGE_SIZE; ++ kal_mem_kunmap((void *)kva_para->buf_handle, kva, buf_offset); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(npu_kva_unmap); ++ ++static struct dbf_process *find_dfb_process(struct dma_buf *dma_buf) ++{ ++ struct rb_node *node = dfb_man.dfb_process_root.rb_node; ++ ++ while (node != NULL) { ++ struct dbf_process *process = NULL; ++ process = rb_entry(node, struct dbf_process, rb_node); ++ if (dma_buf < process->dma_buf) ++ node = node->rb_left; ++ else if (dma_buf > process->dma_buf) ++ node = node->rb_right; ++ else ++ return process; ++ } ++ ++ return NULL; ++} ++ ++static void delete_dfb_process(struct dbf_process *process) ++{ ++ rb_erase(&process->rb_node, &dfb_man.dfb_process_root); ++ RB_CLEAR_NODE(&process->rb_node); ++} ++ ++static unsigned int get_valid_index(struct dma_buf_table_index *buff_table) ++{ ++ unsigned int index; ++ unsigned int update_index; ++ unsigned int table_index; ++ unsigned int dma_index; ++ ++ if (buff_table == NULL) { ++ pr_err("%s[%d], buff_table_index is null!!\n", __func__, __LINE__); ++ return -1; ++ } ++ ++ index = buff_table->valid_index; ++ update_index = index + 1; ++ while (update_index < NPU_MISC_MAX_INDEX_VALUE) { ++ table_index = update_index / NPU_MISC_SIG_INDEX_VALUE; ++ dma_index = update_index % NPU_MISC_SIG_INDEX_VALUE; ++ if (table_index <= buff_table->cur_table_index && buff_table->buff_index_table[table_index][dma_index] == NULL) { ++ break; ++ } else if (table_index > buff_table->cur_table_index) { ++ // malloc ++ dfb_man.buf_table.cur_table_index = table_index; ++ dfb_man.buf_table.buff_index_table[table_index] = ++ kzalloc(sizeof(struct dma_buf*) * NPU_MISC_SIG_INDEX_VALUE, GFP_ATOMIC); ++ if (dfb_man.buf_table.buff_index_table[table_index] == NULL) { ++ pr_err("devm_kzalloc failed, unable to malloc buff_index_table space.\n"); ++ return -1; ++ } ++ break; ++ } ++ ++ update_index++; ++ } ++ ++ if (index >= NPU_MISC_MAX_INDEX_VALUE) { ++ pr_err("no valid index can be used, current index = %d, max index = %d!!!\n", ++ index, NPU_MISC_MAX_INDEX_VALUE); ++ return -1; ++ } ++ ++ buff_table->valid_index = update_index; ++ return index; ++} ++ ++static int reset_index(unsigned int index) ++{ ++ unsigned int table_index; ++ unsigned int dma_index; ++ ++ table_index = index / NPU_MISC_SIG_INDEX_VALUE; ++ dma_index = index % NPU_MISC_SIG_INDEX_VALUE; ++ if (table_index > dfb_man.buf_table.cur_table_index) { ++ pr_err("%s, db_idx = %d is out of range! current table index = %d.\n", ++ __func__, index, dfb_man.buf_table.cur_table_index); ++ return -1; ++ } ++ ++ dfb_man.buf_table.buff_index_table[table_index][dma_index] = 0; ++ if (dfb_man.buf_table.valid_index > index) ++ dfb_man.buf_table.valid_index = index; ++ ++ return 0; ++} ++static int add_dfb_node(struct dma_buf *dma_buf, unsigned int *dfb_idx) ++{ ++ struct rb_node **p = &dfb_man.dfb_process_root.rb_node; ++ struct rb_node *parent = NULL; ++ struct dbf_process *process = NULL; ++ unsigned int table_index; ++ unsigned int dma_index; ++ ++ mutex_lock(&dbf_process_mutex); ++ while (*p) { ++ struct dbf_process *tmp_process = NULL; ++ parent = *p; ++ tmp_process = rb_entry(parent, struct dbf_process, rb_node); ++ if (dma_buf < tmp_process->dma_buf) { ++ p = &(*p)->rb_left; ++ } else if (dma_buf > tmp_process->dma_buf) { ++ p = &(*p)->rb_right; ++ } else { ++ *dfb_idx = tmp_process->index; // asid already in the tree. ++ mutex_unlock(&dbf_process_mutex); ++ return 0; ++ } ++ } ++ ++ process = kzalloc(sizeof(*process), GFP_ATOMIC); ++ if (process == NULL) { ++ pr_err("%s, Fail to kzalloc memory for dfb node!\n", __func__); ++ mutex_unlock(&dbf_process_mutex); ++ return -1; ++ } ++ ++ process->flag = 0xA5A5A5A5; ++ process->dma_buf = dma_buf; ++ ++ process->index = get_valid_index(&dfb_man.buf_table); ++ if (process->index == -1) { ++ mutex_unlock(&dbf_process_mutex); ++ pr_err("%s, line: %d, Fail to get valid index!\n", __func__, __LINE__); ++ return -1; ++ } ++ ++ table_index = process->index / NPU_MISC_SIG_INDEX_VALUE; ++ dma_index = process->index % NPU_MISC_SIG_INDEX_VALUE; ++ dfb_man.buf_table.buff_index_table[table_index][dma_index] = dma_buf; ++ ++ rb_link_node(&process->rb_node, parent, p); ++ rb_insert_color(&process->rb_node, &dfb_man.dfb_process_root); ++ *dfb_idx = process->index; ++ mutex_unlock(&dbf_process_mutex); ++ return 0; ++} ++ ++static int rmv_dfb_node(struct dma_buf *dma_buf) ++{ ++ int ret; ++ struct dbf_process *temp_process = NULL; ++ ++ mutex_lock(&dbf_process_mutex); ++ temp_process = find_dfb_process(dma_buf); ++ if (temp_process == NULL) { ++ pr_err("%s, Fail to find dfb process, no such dma buff!\n", __func__); ++ mutex_unlock(&dbf_process_mutex); ++ return -1; ++ } ++ ret = reset_index(temp_process->index); ++ if (ret != 0) { ++ pr_err("%s, Fail to reset index!\n", __func__); ++ mutex_unlock(&dbf_process_mutex); ++ return ret; ++ } ++ ++ delete_dfb_process(temp_process); ++ kfree(temp_process); ++ temp_process = NULL; ++ ++ mutex_unlock(&dbf_process_mutex); ++ return ret; ++} ++ ++static int npu_misc_dbf_add(unsigned long __user *arg) ++{ ++ int err, db_fd; ++ unsigned int db_idx; ++ void *dma_buf = NULL; ++ unsigned long user_addr_info; ++ ++ if (arg == NULL) ++ return -EINVAL; ++ ++ if (get_user(user_addr_info, arg)) ++ return -EFAULT; ++ ++ db_fd = (int)(user_addr_info & 0xFFFFFFFF); ++ dma_buf = kal_mem_handle_get(db_fd, NPU_MODULE_ID); ++ if (dma_buf == NULL) { ++ pr_err("%s[%d]: call osal_mem_handle_get failure\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ err = add_dfb_node(dma_buf, &db_idx); ++ if (err < 0) { ++ pr_err("%s[%d]: fail to add dfb node, err = %d\n", __FUNCTION__, __LINE__, err); ++ kal_mem_ref_put(dma_buf, NPU_MODULE_ID); ++ return -EFAULT; ++ } ++ ++ db_idx |= (NPU_DBF_INDEX_VALID_FLAG << 24); ++ ++ if (dma_buf != NULL) { ++ kal_mem_ref_put(dma_buf, NPU_MODULE_ID); ++ } ++ ++ return put_user(db_idx, arg); ++} ++ ++static int npu_misc_dbf_rmv(unsigned long __user *arg) ++{ ++ int err, db_fd; ++ void *dma_buf = NULL; ++ unsigned long dbf_value; ++ ++ if (arg == NULL) ++ return -EINVAL; ++ ++ if (get_user(dbf_value, arg)) ++ return -EFAULT; ++ ++ db_fd = (int)(dbf_value & 0xFFFFFFFF); ++ ++ dma_buf = kal_mem_handle_get(db_fd, NPU_MODULE_ID); ++ if (dma_buf == NULL) { ++ pr_err("%s[%d]: call osal_mem_handle_get failure\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ err = rmv_dfb_node((struct dma_buf *)dma_buf); ++ if (err < 0) { ++ pr_err("%s[%d]: fail to rmv dfb node\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ if (dma_buf != NULL) { ++ kal_mem_ref_put(dma_buf, NPU_MODULE_ID); ++ } ++ ++ return err; ++} ++#endif ++ ++#ifdef MISC_MEM_DBG ++static int npu_misc_data_copy_test(struct data_copy_info *copy_info) ++{ ++ int err; ++ struct kva_map_params src_kva_para = {0}; ++ struct kva_map_params dst_kva_para = {0}; ++ ++ src_kva_para.user_va = copy_info->src_addr_info; ++ err = npu_kva_map(&src_kva_para); ++ if (err != 0) { ++ pr_err("%s[%d]: Error: fail to kmap source address \n", __FUNCTION__, __LINE__); ++ err = -EFAULT; ++ goto __err_exit; ++ } ++ ++ dst_kva_para.user_va = copy_info->dst_addr_info; ++ err = npu_kva_map(&dst_kva_para); ++ if (err != 0) { ++ pr_err("%s[%d]: Error: fail to kmap source address \n", __FUNCTION__, __LINE__); ++ err = -EFAULT; ++ goto __err_exit; ++ } ++ ++ if (src_kva_para.kva + copy_info->src_size >= dst_kva_para.kva) { ++ pr_err("%s[%d]: Error: copy address override \n", __FUNCTION__, __LINE__); ++ err = -EFAULT; ++ goto __err_exit; ++ } ++ ++ err = memcpy_s(dst_kva_para.kva, copy_info->dst_size, src_kva_para.kva, copy_info->src_size); ++ ++__err_exit: ++ if (src_kva_para.kva != NULL) ++ npu_kva_unmap(&src_kva_para); ++ if (dst_kva_para.kva != NULL) ++ npu_kva_unmap(&dst_kva_para); ++ return err; ++} ++ ++static int npu_misc_show_mem(struct device *dev, struct mem_show_params *mem_params) ++{ ++ int err, db_fd; ++ unsigned int buf_offset, i; ++ void *dma_buf = NULL; ++ void *kva = NULL; ++ char *ptr = NULL; ++ ++ db_fd = (int)(mem_params->user_addr_info >> 32); // high 32 bit is used to save dma buffer fd ++ buf_offset = (unsigned int)(mem_params->user_addr_info & 0xFFFFFFFF); ++ ++ dma_buf = kal_mem_handle_get(db_fd, NPU_MODULE_ID); ++ if (dma_buf == NULL) { ++ pr_err("%s[%d]: call osal_mem_handle_get failure\n", __FUNCTION__, __LINE__); ++ return -EFAULT; ++ } ++ ++ kva = kal_mem_kmap(dma_buf, buf_offset, 0); ++ if (kva == NULL) { ++ pr_err("%s[%d]: fail to map src address \n", __FUNCTION__, __LINE__); ++ err = -EFAULT; ++ goto __err_exit; ++ } ++ ++ ptr = (char *)(uintptr_t)kva; ++ for (i = 0; i < mem_params->size; i++) { ++ if (i % 16 == 0) /* 16 bytes align for print output */ ++ dev_info(dev, "\n"); ++ ++ dev_info(dev, "0x%x ", ptr[i]); ++ } ++ dev_info(dev, "\n"); ++ ++ err = 0; ++__err_exit: ++ if (kva != NULL) ++ kal_mem_kunmap(dma_buf, kva, buf_offset); ++ if (dma_buf != NULL) ++ kal_mem_ref_put(dma_buf, NPU_MODULE_ID); ++ return err; ++} ++#endif ++ ++static long npu_misc_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int err = -EINVAL; ++ struct nmsc_device *sdev = file_to_sdev(file); ++#ifdef MISC_MEM_DBG ++ struct data_copy_info params; ++ struct mem_show_params mem_show; ++#endif ++ ++ if (arg == 0) ++ return -EINVAL; ++ ++ switch (cmd) { ++#ifdef USE_ION ++ case NPU_MISC_IOCTL_ADD_DBF: ++ err = npu_misc_dbf_add((unsigned long __user *)arg); ++ break; ++ case NPU_MISC_IOCTL_RMV_DBF: ++ err = npu_misc_dbf_rmv((unsigned long __user *)arg); ++ break; ++#endif ++#ifdef MISC_MEM_DBG ++ case NPU_MISC_IOCTL_DATA_COPY_TEST: ++ err = copy_from_user(¶ms, (void __user *)arg, sizeof(params)); ++ if (err) { ++ dev_err(sdev->dev, "fail to copy params\n"); ++ return -EFAULT; ++ } ++ err = npu_misc_data_copy_test(¶ms); ++ break; ++ case NPU_MISC_IOCTL_SHOW_MEM: ++ err = copy_from_user(&mem_show, (void __user *)arg, sizeof(mem_show)); ++ if (err) { ++ dev_err(sdev->dev, "fail to copy params\n"); ++ return -EFAULT; ++ } ++ err = npu_misc_show_mem(sdev->dev, &mem_show); ++ break; ++#endif ++ default: ++ err = -EINVAL; ++ break; ++ } ++ ++ if (err) ++ dev_err(sdev->dev, "%s: %s failed err = %d\n", __func__, nmsc_cmd_to_string(cmd), err); ++ ++ return err; ++} ++ ++static int npu_misc_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static const struct file_operations npu_misc_fops = { ++ .owner = THIS_MODULE, ++ .open = npu_misc_open, ++ .unlocked_ioctl = npu_misc_ioctl, ++}; ++ ++static int npu_misc_device_probe(struct platform_device *pdev) ++{ ++ int err; ++ struct device *dev = &pdev->dev; ++ struct nmsc_device *sdev = NULL; ++ ++ sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL); ++ if (sdev == NULL) ++ return -ENOMEM; ++ ++ sdev->dev = dev; ++ sdev->miscdev.minor = MISC_DYNAMIC_MINOR; ++ sdev->miscdev.fops = &npu_misc_fops; ++ sdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, NPU_MISC_DEVICE_NAME); ++ if (sdev->miscdev.name == NULL) ++ err = -ENOMEM; ++ ++ dev_set_drvdata(dev, sdev); ++ err = misc_register(&sdev->miscdev); ++ if (err) { ++ dev_err(dev, "Unable to register misc device\n"); ++ return err; ++ } ++ ++ dfb_man.dfb_process_root = RB_ROOT; ++ dfb_man.buf_table.cur_table_index = 0; ++ dfb_man.buf_table.buff_index_table[0] = kzalloc(sizeof(struct dma_buf*) * NPU_MISC_SIG_INDEX_VALUE, GFP_ATOMIC); ++ if (dfb_man.buf_table.buff_index_table[0] == NULL) { ++ dev_err(dev, "devm_kzalloc failed, unable to malloc buff_index_table space.\n"); ++ return err; ++ } ++ mutex_init(&dbf_process_mutex); ++ ++ return err; ++} ++ ++static int npu_misc_device_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct nmsc_device *sdev = dev_get_drvdata(dev); ++ int i; ++ ++ for (i = 0; i <= dfb_man.buf_table.cur_table_index; i++) ++ kfree(dfb_man.buf_table.buff_index_table[i]); ++ ++ misc_deregister(&sdev->miscdev); ++ ++ return 0; ++} ++ ++static const struct of_device_id npu_misc_of_match[] = { ++ { .compatible = "vendor,npu_misc_device_drv" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, npu_misc_of_match); ++ ++ ++static struct platform_driver npu_misc_driver = { ++ .probe = npu_misc_device_probe, ++ .remove = npu_misc_device_remove, ++ .driver = { ++ .name = "npu_misc_device_drv", ++ .of_match_table = npu_misc_of_match, ++ }, ++}; ++ ++static void npu_misc_dev_release(struct device *dev) ++{ ++ return; ++} ++ ++static struct platform_device npu_misc_device = { ++ .name = "npu_misc_device_drv", ++ .id = -1, ++ .dev = { ++ .platform_data = NULL, ++ .release = npu_misc_dev_release, ++ }, ++}; ++ ++static int __init npu_drv_misc_platform_init(void) ++{ ++ int ret; ++ ++ ret = platform_device_register(&npu_misc_device); ++ if (ret < 0) { ++ printk("call platform_device_register failed!\n"); ++ return ret; ++ } ++ ++ ret = platform_driver_register(&npu_misc_driver); ++ if (ret) { ++ platform_device_unregister(&npu_misc_device); ++ printk("insmod npu misc platform driver fail. ret=%d\n", ret); ++ return ret; ++ } ++ ++ return ret; ++} ++module_init(npu_drv_misc_platform_init); ++ ++static void __exit npu_drv_misc_platform_exit(void) ++{ ++ platform_driver_unregister(&npu_misc_driver); ++ platform_device_unregister(&npu_misc_device); ++} ++module_exit(npu_drv_misc_platform_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("NPU MISC DRIVER"); ++MODULE_VERSION("V1.0"); ++ +diff --git a/drivers/vendor/npu/npu_svm.c b/drivers/vendor/npu/npu_svm.c +new file mode 100644 +index 000000000000..4368390f6ba6 +--- /dev/null ++++ b/drivers/vendor/npu/npu_svm.c +@@ -0,0 +1,1370 @@ ++/* ++ * Copyright (c) Shenshu Technologies Co., Ltd. 2020-2021. All rights reserved. ++ * Description: npu svm ++ * Version: Initial Draft ++ * Create: 2020-01-16 ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include "linux/vendor/sva_ext.h" ++ ++#define SVM_DEVICE_NAME "svm" ++#define ASID_SHIFT 48 ++#define CORE_SID 0 /* for core sid register */ ++ ++#define SVM_IOCTL_PROCESS_BIND 0xffff ++#define SVM_IOCTL_PAGE_TABLE_SYNC 0xfffd ++ ++struct core_device { ++ struct device dev; ++ struct iommu_group *group; ++ struct iommu_domain *domain; ++ u8 smmu_bypass; ++ struct list_head entry; ++}; ++ ++struct svm_device { ++ unsigned long long id; ++ struct miscdevice miscdev; ++ struct device *dev; ++ phys_addr_t l2buff; ++ unsigned long l2size; ++}; ++ ++struct svm_bind_process { ++ pid_t vpid; ++ u64 ttbr; ++ u64 tcr; ++ int pasid; ++#define SVM_BIND_PID (1 << 0) ++ u32 flags; ++}; ++ ++struct svm_pg_sync_para { ++ u64 vaddr; ++ u32 len; ++}; ++ ++/* ++ * svm_process is released in svm_notifier_release() when mm refcnt ++ * goes down to 0. We should access svm_process only in the context ++ * where mm_struct is valid, which means wes should always get mm ++ * refcnt first (unless we are operating on current task). ++ */ ++struct svm_process { ++ struct pid *pid; ++ struct mm_struct *mm; ++ unsigned long asid; ++ struct rb_node rb_node; ++ struct mmu_notifier notifier; ++ /* For postponed release */ ++ struct rcu_head rcu; ++ int pasid; ++ struct mutex mutex; ++ struct svm_device *sdev; ++ struct iommu_sva *handle; ++}; ++ ++typedef void (*smmu_clk_live_func)(void); ++ ++static smmu_clk_live_func g_smmu_clk_live_enter = NULL; ++static smmu_clk_live_func g_smmu_clk_live_exit = NULL; ++ ++#define SVM_DEV_MAX 2 ++static struct rb_root svm_process_root[SVM_DEV_MAX] = {RB_ROOT, RB_ROOT}; ++ ++static struct mutex svm_process_mutex; ++ ++static DECLARE_RWSEM(svm_sem); ++ ++static unsigned int probe_index = 0; ++ ++static void *npu_dts_sys_peri = NULL; ++#define NPU_SVM_DEV_NAME "svm_npu" ++#define NPU_SMMU_DEV_NAME "smmu_npu" ++#define NPU_CRG_NAME "npu_crg_6560" ++ ++/* for SS928V100) */ ++#define SVP_NPU_SVM_DEV_NAME "svm_pqp" ++#define SVP_NPU_SMMU_DEV_NAME "smmu_pqp" ++#define SVP_NPU_CRG_NAME "pqp_crg_6592" ++ ++#define SVM_DEV_NAME_LEN 64 ++#define CRG_NAME_LEN 16 ++#define CLK_EN_BIT 4 ++ ++struct svm_dev_wl_mng { ++ char svm_dev_name[SVM_DEV_NAME_LEN]; ++ char smmu_dev_name[SVM_DEV_NAME_LEN]; ++ char crg_name[CRG_NAME_LEN]; ++ int crg_offset; ++ bool is_inited; ++ bool is_suspend; ++ void *dev; ++}; ++static struct mutex svm_dev_pm_mutex; ++ ++static struct svm_dev_wl_mng svm_dev_white_list[SVM_DEV_MAX] = { ++ { NPU_SVM_DEV_NAME, NPU_SMMU_DEV_NAME, NPU_CRG_NAME, false, false, NULL } , ++ { SVP_NPU_SVM_DEV_NAME, SVP_NPU_SMMU_DEV_NAME, SVP_NPU_CRG_NAME, false, false, NULL } ++}; ++ ++static char *svm_cmd_to_string(unsigned int cmd) ++{ ++ switch (cmd) { ++ case SVM_IOCTL_PROCESS_BIND: ++ return "bind"; ++ case SVM_IOCTL_PAGE_TABLE_SYNC: ++ return "sync page table"; ++ default: ++ return "unsupported"; ++ } ++} ++ ++static int svm_device_get_smmu_devno(struct svm_device *sdev) ++{ ++ int i; ++ const char *device_name = dev_name(sdev->dev); ++ ++ if (device_name == NULL) ++ return -1; ++ ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ if (strnstr(device_name, svm_dev_white_list[i].svm_dev_name, SVM_DEV_NAME_LEN) != NULL) ++ return i; ++ } ++ return -1; ++} ++ ++static struct svm_process *find_svm_process(unsigned long asid, int smmu_devid) ++{ ++ struct rb_node *node = svm_process_root[smmu_devid].rb_node; ++ ++ while (node != NULL) { ++ struct svm_process *process = NULL; ++ ++ process = rb_entry(node, struct svm_process, rb_node); ++ if (asid < process->asid) { ++ node = node->rb_left; ++ } else if (asid > process->asid) { ++ node = node->rb_right; ++ } else { ++ return process; ++ } ++ } ++ ++ return NULL; ++} ++ ++static void insert_svm_process(struct svm_process *process, int smmu_devid) ++{ ++ struct rb_node **p = &svm_process_root[smmu_devid].rb_node; ++ struct rb_node *parent = NULL; ++ ++ while (*p) { ++ struct svm_process *tmp_process = NULL; ++ ++ parent = *p; ++ tmp_process = rb_entry(parent, struct svm_process, rb_node); ++ if (process->asid < tmp_process->asid) { ++ p = &(*p)->rb_left; ++ } else if (process->asid > tmp_process->asid) { ++ p = &(*p)->rb_right; ++ } else { ++ WARN_ON_ONCE(1); ++ return; ++ } ++ } ++ ++ rb_link_node(&process->rb_node, parent, p); ++ rb_insert_color(&process->rb_node, &svm_process_root[smmu_devid]); ++} ++ ++static void delete_svm_process(struct svm_process *process) ++{ ++ int smmu_devid; ++ ++ smmu_devid = svm_device_get_smmu_devno(process->sdev); ++ if (smmu_devid < 0) ++ pr_err("fail to get smmu dev number\n"); ++ ++ rb_erase(&process->rb_node, &svm_process_root[smmu_devid]); ++ RB_CLEAR_NODE(&process->rb_node); ++} ++ ++struct bus_type svm_bus_type = { ++ .name = "svm-bus", ++}; ++ ++static inline struct core_device *to_core_device(struct device *d) ++{ ++ return container_of(d, struct core_device, dev); ++} ++ ++static int svm_unbind_core(struct device *dev, void *data) ++{ ++ struct svm_process *process = data; ++ struct core_device *cdev = to_core_device(dev); ++ ++ if (cdev->smmu_bypass) ++ return 0; ++ if (!process->handle) ++ return -EINVAL; ++ ++ iommu_sva_unbind_device(process->handle); ++ process->handle = NULL; ++ return 0; ++} ++ ++static int svm_bind_core(struct device *dev, void *data) ++{ ++ struct task_struct *task = NULL; ++ struct svm_process *process = data; ++ struct core_device *cdev = to_core_device(dev); ++ struct iommu_sva *handle; ++ ++ if (cdev->smmu_bypass) ++ return 0; ++ ++ task = get_pid_task(process->pid, PIDTYPE_PID); ++ if (task == NULL) { ++ pr_err("failed to get task_struct\n"); ++ return -ESRCH; ++ } ++ ++ handle = iommu_sva_bind_device(&cdev->dev, task->mm, NULL); ++ if (IS_ERR(handle)) { ++ pr_err("failed to bind the device\n"); ++ return PTR_ERR(handle); ++ } ++ ++ process->pasid = iommu_sva_get_pasid(handle); ++ if (process->pasid == IOMMU_PASID_INVALID) { ++ iommu_sva_unbind_device(handle); ++ return -ENODEV; ++ } ++ ++ process->handle = handle; ++ put_task_struct(task); ++ ++ return 0; ++} ++ ++static void svm_bind_cores(struct svm_process *process) ++{ ++ device_for_each_child(process->sdev->dev, process, svm_bind_core); ++} ++ ++static void svm_unbind_cores(struct svm_process *process) ++{ ++ mutex_lock(&svm_dev_pm_mutex); ++ device_for_each_child(process->sdev->dev, process, svm_unbind_core); ++ mutex_unlock(&svm_dev_pm_mutex); ++} ++ ++static void cdev_device_release(struct device *dev) ++{ ++ struct core_device *cdev = to_core_device(dev); ++ ++ kfree(cdev); ++} ++ ++static int svm_remove_core(struct device *dev, void *data) ++{ ++ int err; ++ struct core_device *cdev = to_core_device(dev); ++ ++ if (cdev->smmu_bypass == 0) { ++ err = iommu_dev_disable_feature(&cdev->dev, IOMMU_DEV_FEAT_SVA); ++ if (err) { ++ dev_err(&cdev->dev, "failed to disable sva feature, %d\n", err); ++ } ++ err = iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_IOPF); ++ if (err) { ++ dev_err(&cdev->dev, "failed to disable iopf feature, %d\n", err); ++ } ++ iommu_detach_group(cdev->domain, cdev->group); ++ iommu_group_put(cdev->group); ++ iommu_domain_free(cdev->domain); ++ } ++ device_unregister(&cdev->dev); ++ ++ return 0; ++} ++ ++static int svm_register_device(struct svm_device *sdev, struct device_node *np, struct core_device **pcdev) ++{ ++ int err; ++ char *name = NULL; ++ struct core_device *cdev = NULL; ++ ++ name = devm_kasprintf(sdev->dev, GFP_KERNEL, "svm%llu_%s", sdev->id, np->name); ++ if (name == NULL) ++ return -ENOMEM; ++ ++ cdev = kzalloc(sizeof(*cdev), GFP_KERNEL); ++ if (cdev == NULL) ++ return -ENOMEM; ++ ++ cdev->dev.of_node = np; ++ cdev->dev.parent = sdev->dev; ++ cdev->dev.bus = &svm_bus_type; ++ cdev->dev.release = cdev_device_release; ++ cdev->smmu_bypass = of_property_read_bool(np, "vendor,smmu_bypass"); ++ dev_set_name(&cdev->dev, "%s", name); ++ ++ err = device_register(&cdev->dev); ++ if (err) { ++ dev_info(&cdev->dev, "core_device register failed\n"); ++ kfree(cdev); ++ return err; ++ } ++ *pcdev = cdev; ++ return 0; ++} ++ ++static int svm_iommu_attach_group(struct svm_device *sdev, struct core_device *cdev) ++{ ++ int err; ++ ++ cdev->group = iommu_group_get(&cdev->dev); ++ if (IS_ERR_OR_NULL(cdev->group)) { ++ dev_err(&cdev->dev, "smmu is not right configured\n"); ++ return -ENXIO; ++ } ++ ++ cdev->domain = iommu_domain_alloc(sdev->dev->bus); ++ if (cdev->domain == NULL) { ++ dev_err(&cdev->dev, "failed to alloc domain\n"); ++ iommu_group_put(cdev->group); ++ return -ENOMEM; ++ } ++ ++ err = iommu_attach_group(cdev->domain, cdev->group); ++ if (err) { ++ dev_err(&cdev->dev, "failed group to domain\n"); ++ iommu_group_put(cdev->group); ++ iommu_domain_free(cdev->domain); ++ return err; ++ } ++ ++ return 0; ++} ++ ++static int svm_of_add_core(struct svm_device *sdev, struct device_node *np) ++{ ++ int err; ++ struct resource res; ++ struct core_device *cdev = NULL; ++ ++ err = svm_register_device(sdev, np, &cdev); ++ if (err) { ++ dev_info(&cdev->dev, "fail to register svm device\n"); ++ return err; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 18, 0)) ++ err = of_dma_configure(&cdev->dev, np, true); ++#else ++ err = of_dma_configure(&cdev->dev, np); ++#endif ++ if (err) { ++ dev_dbg(&cdev->dev, "of_dma_configure failed\n"); ++ goto err_unregister_dev; ++ } ++ ++ err = of_address_to_resource(np, 0, &res); ++ if (err) ++ dev_info(&cdev->dev, "no reg, FW should install the sid\n"); ++ ++ /* If core device is smmu bypass, request direct map. */ ++ if (cdev->smmu_bypass) { ++ err = iommu_request_dm_for_dev(&cdev->dev); ++ if (err) ++ dev_err(&cdev->dev, "request domain for dev error\n"); ++ ++ return err; ++ } ++ err = svm_iommu_attach_group(sdev, cdev); ++ if (err) { ++ dev_err(&cdev->dev, "failed to init sva device\n"); ++ goto err_unregister_dev; ++ } ++ ++ err = iommu_dev_enable_feature(&cdev->dev, IOMMU_DEV_FEAT_IOPF); ++ if (err) { ++ dev_err(&cdev->dev, "failed to enable iopf feature, %d\n", err); ++ goto err_detach_group; ++ } ++ ++ err = iommu_dev_enable_feature(&cdev->dev, IOMMU_DEV_FEAT_SVA); ++ if (err) { ++ dev_err(&cdev->dev, "failed to enable sva feature, %d\n", err); ++ goto err_detach_group; ++ } ++ ++ return 0; ++err_detach_group: ++ iommu_detach_group(cdev->domain, cdev->group); ++ iommu_domain_free(cdev->domain); ++ iommu_group_put(cdev->group); ++err_unregister_dev: ++ device_unregister(&cdev->dev); ++ return err; ++} ++ ++static void svm_notifier_free(struct mmu_notifier *mn) ++{ ++ struct svm_process *process = NULL; ++ ++ process = container_of(mn, struct svm_process, notifier); ++ arm64_mm_context_put(process->mm); ++ kfree(process); ++} ++ ++static void svm_process_release(struct svm_process *process) ++{ ++ delete_svm_process(process); ++ put_pid(process->pid); ++ mmu_notifier_put(&process->notifier); ++} ++ ++static void svm_notifier_release(struct mmu_notifier *mn, struct mm_struct *mm) ++{ ++ struct svm_process *process = NULL; ++ process = container_of(mn, struct svm_process, notifier); ++ ++ svm_smmu_clk_live_enter(); ++ svm_unbind_cores(process); ++ svm_smmu_clk_live_exit(); ++ ++ mutex_lock(&svm_process_mutex); ++ svm_process_release(process); ++ mutex_unlock(&svm_process_mutex); ++} ++ ++/* ++ * Device CPU have the ability of DVM, which means when control CPU flush ++ * TLB, it will notify the device CPU by hardware instead of mmu_notifier. ++ */ ++static struct mmu_notifier_ops svm_process_mmu_notifier = { ++ .release = svm_notifier_release, ++ .free_notifier = svm_notifier_free, ++}; ++ ++static struct svm_process *svm_process_alloc(struct svm_device *sdev, struct pid *pid, ++ struct mm_struct *mm, unsigned long asid) ++{ ++ struct svm_process *process = kzalloc(sizeof(*process), GFP_ATOMIC); ++ if (process == NULL) ++ return ERR_PTR(-ENOMEM); ++ ++ process->sdev = sdev; ++ process->pid = pid; ++ process->mm = mm; ++ process->asid = asid; ++ mutex_init(&process->mutex); ++ process->notifier.ops = &svm_process_mmu_notifier; ++ ++ return process; ++} ++ ++static int get_task_info(struct task_struct *task, struct pid **ppid, struct mm_struct **pmm, unsigned long *pasid) ++{ ++ unsigned long asid; ++ struct pid *pid = NULL; ++ struct mm_struct *mm = NULL; ++ ++ pid = get_task_pid(task, PIDTYPE_PID); ++ if (pid == NULL) ++ return -EINVAL; ++ ++ mm = get_task_mm(task); ++ if (mm == NULL) { ++ put_pid(pid); ++ return -EINVAL; ++ } ++ ++ asid = arm64_mm_context_get(mm); ++ if (asid == 0) { ++ mmput(mm); ++ put_pid(pid); ++ return -ENOSPC; ++ } ++ ++ *ppid = pid; ++ *pmm = mm; ++ *pasid = asid; ++ return 0; ++} ++ ++static int svm_process_bind(struct task_struct *task, struct svm_device *sdev, ++ u64 *ttbr, u64 *tcr, int *pasid) ++{ ++ int err; ++ unsigned long asid; ++ struct pid *pid = NULL; ++ struct svm_process *process = NULL; ++ struct mm_struct *mm = NULL; ++ int smmu_devid = svm_device_get_smmu_devno(sdev); ++ if ((ttbr == NULL) || (tcr == NULL) || (pasid == NULL) || smmu_devid < 0) ++ return -EINVAL; ++ ++ err = get_task_info(task, &pid, &mm, &asid); ++ if (err != 0) ++ return err; ++ ++ /* If a svm_process already exists, use it */ ++ mutex_lock(&svm_process_mutex); ++ process = find_svm_process(asid, smmu_devid); ++ if (process == NULL) { ++ process = svm_process_alloc(sdev, pid, mm, asid); ++ if (IS_ERR(process)) { ++ err = PTR_ERR(process); ++ mutex_unlock(&svm_process_mutex); ++ goto err_put_mm_context; ++ } ++ ++ err = mmu_notifier_register(&process->notifier, mm); ++ if (err) { ++ mutex_unlock(&svm_process_mutex); ++ goto err_free_svm_process; ++ } ++ ++ insert_svm_process(process, smmu_devid); ++ svm_bind_cores(process); ++ mutex_unlock(&svm_process_mutex); ++ } else { ++ mutex_unlock(&svm_process_mutex); ++ arm64_mm_context_put(mm); ++ put_pid(pid); ++ } ++ ++ *ttbr = virt_to_phys(mm->pgd) | (asid << ASID_SHIFT); ++ *tcr = read_sysreg(tcr_el1); ++ *pasid = process->pasid; ++ ++ mmput(mm); ++ return 0; ++ ++err_free_svm_process: ++ kfree(process); ++ process = NULL; ++err_put_mm_context: ++ arm64_mm_context_put(mm); ++ mmput(mm); ++ put_pid(pid); ++ ++ return err; ++} ++ ++static struct svm_device *file_to_sdev(struct file *file) ++{ ++ return container_of(file->private_data, struct svm_device, miscdev); ++} ++ ++static struct svm_dev_wl_mng *svm_device_get_mng(const char *device_name) ++{ ++ int i; ++ int svm_name_len; ++ if (device_name == NULL) ++ return NULL; ++ ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ svm_name_len = strlen(svm_dev_white_list[i].svm_dev_name); ++ if (strncmp(device_name, svm_dev_white_list[i].svm_dev_name, svm_name_len) == 0) { ++ pr_debug("strncmp will return i = %d, svm_dev_name = %s, smmu_dev_name = %s\n", ++ i, svm_dev_white_list[i].svm_dev_name, svm_dev_white_list[i].smmu_dev_name); ++ return &svm_dev_white_list[i]; ++ } ++ } ++ return NULL; ++} ++static bool svm_device_is_power_on(const char *device_name) ++{ ++ int i; ++ unsigned int svm_name_len; ++ unsigned int smmu_name_len; ++ unsigned int device_name_len; ++ unsigned int smmu_name_offset; ++ unsigned int read_val; ++ if (device_name == NULL || npu_dts_sys_peri == NULL || strlen(device_name) >= PATH_MAX) ++ return false; ++ device_name_len = strlen(device_name); ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ svm_name_len = strlen(svm_dev_white_list[i].svm_dev_name); ++ smmu_name_len = strlen(svm_dev_white_list[i].smmu_dev_name); ++ smmu_name_offset = device_name_len > smmu_name_len ? device_name_len - smmu_name_len : 0; ++ if (strncmp(device_name, svm_dev_white_list[i].svm_dev_name, svm_name_len) == 0 || ++ strncmp(device_name + smmu_name_offset, svm_dev_white_list[i].smmu_dev_name, smmu_name_len) == 0) { ++ if (npu_dts_sys_peri == NULL) { ++ pr_err("error : npu_dts_sys_peri is illegal\n"); ++ return false; ++ } ++ read_val = readl_relaxed(npu_dts_sys_peri + svm_dev_white_list[i].crg_offset); ++ pr_debug("npu_dts_sys_peri = 0x%llx offset = 0x%x val = 0x%x, smmu_name_offset = %u\n", ++ (uint64_t)(uintptr_t)npu_dts_sys_peri, svm_dev_white_list[i].crg_offset, read_val, smmu_name_offset); ++ if ((read_val & BIT(CLK_EN_BIT)) != 0) ++ return true; ++ } ++ } ++ pr_err("error : device name = %s ,smmu_name_offset = %u, svm is not powner on , please powner on svm first.\n", ++ device_name, smmu_name_offset); ++ return false; ++} ++ ++static int svm_device_post_probe(const char *device_name); ++static int svm_open(struct inode *inode, struct file *file) ++{ ++ int ret; ++ struct svm_dev_wl_mng *dev_mng = NULL; ++ struct svm_device *sdev = file_to_sdev(file); ++ const char *device_name = dev_name(sdev->dev); ++ ++ if (!svm_device_is_power_on(device_name)) { ++ dev_err(sdev->dev, "svm_open: svm is not power on\n"); ++ return -EFAULT; ++ } ++ ++ dev_mng = svm_device_get_mng(device_name); ++ if (dev_mng == NULL) { ++ dev_err(sdev->dev, "fail to get svm device mng\n"); ++ return -EFAULT; ++ } ++ ++ mutex_lock(&svm_dev_pm_mutex); ++ if (dev_mng->is_inited == false) { ++ ret = arm_smmu_device_post_probe(dev_mng->smmu_dev_name); ++ if (ret != 0) { ++ dev_err(sdev->dev, "fail to do smmu post probe\n"); ++ goto err_exit; ++ } ++ ++ ret = svm_device_post_probe(dev_mng->svm_dev_name); ++ if (ret != 0) { ++ dev_err(sdev->dev, "fail to do svm post probe\n"); ++ goto err_exit; ++ } ++ dev_mng->is_inited = true; ++ } else { ++ if (dev_mng->is_suspend == true) { ++ ret = arm_smmu_device_resume(dev_mng->smmu_dev_name); ++ if (ret != 0) { ++ dev_err(sdev->dev, "fail to resume smmu\n"); ++ goto err_exit; ++ } ++ dev_mng->is_suspend = false; ++ } ++ } ++ mutex_unlock(&svm_dev_pm_mutex); ++ return 0; ++ ++err_exit: ++ mutex_unlock(&svm_dev_pm_mutex); ++ return -EFAULT; ++} ++ ++static struct task_struct *svm_get_task(struct svm_bind_process params) ++{ ++ struct task_struct *task = NULL; ++ ++ if (params.flags & ~SVM_BIND_PID) ++ return ERR_PTR(-EINVAL); ++ ++ if (params.flags & SVM_BIND_PID) { ++ struct mm_struct *mm = NULL; ++ ++ rcu_read_lock(); ++ task = find_task_by_vpid(params.vpid); ++ if (task != NULL) ++ get_task_struct(task); ++ rcu_read_unlock(); ++ if (task == NULL) ++ return ERR_PTR(-ESRCH); ++ ++ /* check the permission */ ++ mm = mm_access(task, PTRACE_MODE_ATTACH_REALCREDS); ++ if (IS_ERR_OR_NULL(mm)) { ++ pr_err("cannot access mm\n"); ++ put_task_struct(task); ++ return ERR_PTR(-ESRCH); ++ } ++ ++ mmput(mm); ++ } else { ++ get_task_struct(current); ++ task = current; ++ } ++ ++ return task; ++} ++ ++int svm_get_pasid(pid_t vpid, int dev_id __maybe_unused) ++{ ++ int pasid; ++ unsigned long asid; ++ struct task_struct *task = NULL; ++ struct mm_struct *mm = NULL; ++ struct svm_process *process = NULL; ++ struct svm_bind_process params; ++ ++ params.flags = SVM_BIND_PID; ++ params.vpid = vpid; ++ params.pasid = -1; ++ params.ttbr = 0; ++ params.tcr = 0; ++ task = svm_get_task(params); ++ if (IS_ERR(task)) ++ return PTR_ERR(task); ++ ++ mm = get_task_mm(task); ++ if (mm == NULL) { ++ pasid = -EINVAL; ++ goto put_task; ++ } ++ ++ asid = arm64_mm_context_get(mm); ++ if (asid == 0) { ++ pasid = -ENOSPC; ++ goto put_mm; ++ } ++ ++ mutex_lock(&svm_process_mutex); ++ process = find_svm_process(asid, dev_id); ++ mutex_unlock(&svm_process_mutex); ++ if (process != NULL) ++ pasid = process->pasid; ++ else ++ pasid = -ESRCH; ++ ++ arm64_mm_context_put(mm); ++put_mm: ++ mmput(mm); ++put_task: ++ put_task_struct(task); ++ ++ return pasid; ++} ++EXPORT_SYMBOL_GPL(svm_get_pasid); ++ ++static void pte_flush_range(pmd_t *pmd, unsigned long addr, unsigned long end) ++{ ++ pte_t *pte = NULL; ++ pte_t *pte4k = NULL; ++ ++ pte = pte_offset_map(pmd, addr); ++ ++ pte4k = (pte_t *)round_down((u64)pte, PAGE_SIZE); ++ __flush_dcache_area(pte4k, PAGE_SIZE); ++ ++ pte_unmap(pte); ++} ++ ++static void pmd_flush_range(pud_t *pud, unsigned long addr, unsigned long end) ++{ ++ pmd_t *pmd = NULL; ++ pmd_t *pmd4k = NULL; ++ unsigned long next; ++ ++ pmd = pmd_offset(pud, addr); ++ pmd4k = (pmd_t *)round_down((u64)pmd, PAGE_SIZE); ++ ++ do { ++ next = pmd_addr_end(addr, end); ++ pte_flush_range(pmd, addr, next); ++ pmd++; ++ addr = next; ++ } while (addr != end); ++ ++ __flush_dcache_area(pmd4k, PAGE_SIZE); ++} ++ ++static void pud_flush_range(pgd_t *pgd, unsigned long addr, unsigned long end) ++{ ++ p4d_t *p4d = NULL; ++ pud_t *pud = NULL; ++#if CONFIG_PGTABLE_LEVELS > 3 ++ pud_t *pud4k = NULL; ++#endif ++ unsigned long next; ++ ++ p4d = p4d_offset(pgd, addr); ++ pud = pud_offset(p4d, addr); ++#if CONFIG_PGTABLE_LEVELS > 3 ++ pud4k = (pud_t *)round_down((u64)pud, PAGE_SIZE); ++#endif ++ ++ do { ++ next = pud_addr_end(addr, end); ++ pmd_flush_range(pud, addr, next); ++ pud++; ++ addr = next; ++ } while (addr != end); ++ ++#if CONFIG_PGTABLE_LEVELS > 3 ++ __flush_dcache_area(pud4k, PAGE_SIZE); ++#endif ++} ++ ++int svm_flush_cache(struct mm_struct *mm, unsigned long addr, size_t size) ++{ ++ pgd_t *pgd = NULL; ++ pgd_t *pgd4k = NULL; ++ unsigned long next; ++ unsigned long end = addr + PAGE_ALIGN(size); ++ const char *device_name = NULL; ++ unsigned long asid; ++ struct svm_process *process = NULL; ++ struct device *dev = NULL; ++ struct iommu_domain *domain = NULL; ++ int i = 0; ++ ++ if (mm == NULL) { ++ printk("%s: mm is null !!!!!\n", __FUNCTION__); ++ return -1; ++ } ++ ++ asid = arm64_mm_context_get(mm); ++ if (asid == 0) { ++ printk("%s: get asid failed !!!!!\n", __FUNCTION__); ++ return -1; ++ } ++ pgd = pgd_offset(mm, addr); ++ pgd4k = (pgd_t *)round_down((u64)pgd, PAGE_SIZE); ++ ++ do { ++ next = pgd_addr_end(addr, end); ++ pud_flush_range(pgd, addr, next); ++ pgd++; ++ addr = next; ++ } while (addr != end); ++ ++ __flush_dcache_area(pgd4k, PAGE_SIZE); ++ ++ mutex_lock(&svm_dev_pm_mutex); ++ for (; i < SVM_DEV_MAX; i++) { ++ process = find_svm_process(asid, i); ++ if (process == NULL || process->handle == NULL || process->handle->dev == NULL) { ++ continue; ++ } ++ dev = process->handle->dev; ++ domain = iommu_get_domain_for_dev(dev); ++ device_name = arm_smmu_get_device_name(domain); ++ if (svm_device_is_power_on(device_name) == true) { ++ domain->ops->inv_iotlb_range(domain, mm, end - PAGE_ALIGN(size), PAGE_ALIGN(size)); ++ } ++ } ++ mutex_unlock(&svm_dev_pm_mutex); ++ arm64_mm_context_put(mm); ++ return 0; ++} ++EXPORT_SYMBOL_GPL(svm_flush_cache); ++ ++static int svm_vma_check(const struct vm_area_struct *pvma1, const struct vm_area_struct *pvma2, ++ unsigned long vm_start, unsigned long vm_end) ++{ ++ if (pvma1 != pvma2) { ++ pr_err("ERROR: pvma1:[0x%lx,0x%lx) and pvma2:[0x%lx,0x%lx) are not equal\n", ++ pvma1->vm_start, pvma1->vm_end, pvma2->vm_start, pvma2->vm_end); ++ return -1; ++ } ++ ++ if ((pvma1->vm_flags & VM_WRITE) == 0) { ++ pr_err("ERROR vma flag:0x%lx\n", pvma1->vm_flags); ++ return -1; ++ } ++ ++ if (pvma1->vm_start > vm_start) { ++ pr_err("cannot find corresponding vma, vm[%lx, %lx], user range[%lx,%lx]\n", ++ pvma1->vm_start, pvma1->vm_end, vm_start, vm_end); ++ return -1; ++ } ++ ++ if (pvma1->vm_ops == NULL || pvma1->vm_file == NULL) { ++ pr_err("pvma1->vm_flags = 0x%lx, pvma2->vm_flags = 0x%lx, vm_ops = 0x%lx, vm_file = 0x%lx\n", ++ pvma1->vm_flags, pvma2->vm_flags, (uintptr_t)pvma1->vm_ops, (uintptr_t)pvma1->vm_file); ++ return -1; ++ } ++ return 0; ++} ++ ++static long svm_page_table_sync(unsigned long __user *arg) ++{ ++ int ret = -EINVAL; ++ struct svm_pg_sync_para remap_para; ++ struct vm_area_struct *pvma1 = NULL; ++ struct vm_area_struct *pvma2 = NULL; ++ unsigned long end; ++ ++ if (arg == NULL) { ++ pr_err("arg is invalid.\n"); ++ return ret; ++ } ++ ++ ret = copy_from_user(&remap_para, (void __user *)arg, sizeof(remap_para)); ++ if (ret) { ++ pr_err("failed to copy args from user space.\n"); ++ return ret; ++ } ++ ++ if (U64_MAX - remap_para.len < remap_para.vaddr) { ++ pr_err("vaddr or len is too large.\n"); ++ return -1; ++ } ++ end = remap_para.vaddr + remap_para.len; ++ down_read(¤t->mm->mmap_lock); ++ pvma1 = find_vma(current->mm, remap_para.vaddr); ++ if (pvma1 == NULL) { ++ up_read(¤t->mm->mmap_lock); ++ pr_err("ERROR: pvma1 is null, vir addr = 0x%llx or len = %d is illegal.\n", remap_para.vaddr, remap_para.len); ++ return -1; ++ } ++ ++ pvma2 = find_vma(current->mm, end - 1); ++ if (pvma2 == NULL) { ++ up_read(¤t->mm->mmap_lock); ++ pr_err("ERROR: pvma2 is null, vir addr = 0x%llx or len = %d is illegal.\n", remap_para.vaddr, remap_para.len); ++ return -1; ++ } ++ up_read(¤t->mm->mmap_lock); ++ ++ ret = svm_vma_check(pvma1, pvma2, remap_para.vaddr, end); ++ if (ret != 0) { ++ pr_err("ERROR vma_check failed vir addr = 0x%llx or len = %d is illegal.\n", remap_para.vaddr, remap_para.len); ++ return -ESRCH; ++ } ++ ++ if (end > pvma1->vm_end || end < remap_para.vaddr) { ++ ret = -EINVAL; ++ pr_err("memory length is out of range, vaddr:%pK, len:%u.\n", (void *)remap_para.vaddr, remap_para.len); ++ return ret; ++ } ++ ++ svm_flush_cache(pvma1->vm_mm, remap_para.vaddr, remap_para.len); ++ return 0; ++} ++ ++static long svm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int err = -EINVAL; ++ struct svm_bind_process params; ++ struct task_struct *task = NULL; ++ struct svm_device *sdev = file_to_sdev(file); ++ if (arg == 0 || sdev == NULL) ++ return -EINVAL; ++ ++ if (cmd == SVM_IOCTL_PROCESS_BIND) { ++ if (copy_from_user(¶ms, (void __user *)arg, sizeof(params))) { ++ dev_err(sdev->dev, "fail to copy params\n"); ++ return -EFAULT; ++ } ++ } ++ if (!svm_device_is_power_on(dev_name(sdev->dev))) { ++ dev_err(sdev->dev, "svm_ioctl: svm is not power on\n"); ++ return -EFAULT; ++ } ++ ++ switch (cmd) { ++ case SVM_IOCTL_PROCESS_BIND: ++ task = svm_get_task(params); ++ if (IS_ERR(task)) { ++ dev_err(sdev->dev, "failed to get task\n"); ++ return PTR_ERR(task); ++ } ++ err = svm_process_bind(task, sdev, ¶ms.ttbr, ¶ms.tcr, ¶ms.pasid); ++ if (err) { ++ put_task_struct(task); ++ dev_err(sdev->dev, "failed to bind task %d\n", err); ++ return err; ++ } ++ put_task_struct(task); ++ if (copy_to_user((void __user *)arg, ¶ms, sizeof(params))) ++ err = -EFAULT; ++ break; ++ case SVM_IOCTL_PAGE_TABLE_SYNC: ++ err = svm_page_table_sync((unsigned long __user*)arg); ++ break; ++ default: ++ err = -EINVAL; ++ break; ++ } ++ ++ if (err) ++ dev_err(sdev->dev, "%s: %s failed err = %d\n", __func__, svm_cmd_to_string(cmd), err); ++ ++ return err; ++} ++ ++static int svm_release(struct inode *inode_ptr, struct file *file_ptr) ++{ ++ return 0; ++} ++ ++static const struct file_operations svm_fops = { ++ .owner = THIS_MODULE, ++ .open = svm_open, ++ .unlocked_ioctl = svm_ioctl, ++ .release = svm_release, ++}; ++ ++static int svm_init_core(struct svm_device *sdev, struct device_node *np) ++{ ++ int err = 0; ++ struct device_node *child = NULL; ++ struct device *dev = sdev->dev; ++ ++ down_write(&svm_sem); ++ if (svm_bus_type.iommu_ops == NULL) { ++ err = bus_register(&svm_bus_type); ++ if (err) { ++ up_write(&svm_sem); ++ dev_err(dev, "failed to register svm_bus_type\n"); ++ return err; ++ } ++ ++ err = bus_set_iommu(&svm_bus_type, dev->bus->iommu_ops); ++ if (err) { ++ up_write(&svm_sem); ++ dev_err(dev, "failed to set iommu for svm_bus_type\n"); ++ goto err_unregister_bus; ++ } ++ } else if (svm_bus_type.iommu_ops != dev->bus->iommu_ops) { ++ err = -EBUSY; ++ up_write(&svm_sem); ++ dev_err(dev, "iommu_ops configured, but changed!\n"); ++ return err; ++ } ++ up_write(&svm_sem); ++ ++ for_each_available_child_of_node(np, child) { ++ err = svm_of_add_core(sdev, child); ++ if (err) ++ device_for_each_child(dev, NULL, svm_remove_core); ++ } ++ ++ return err; ++ ++err_unregister_bus: ++ bus_unregister(&svm_bus_type); ++ ++ return err; ++} ++ ++static int svm_device_wl_process(struct platform_device *pdev, struct device *dev) ++{ ++ int i; ++ ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ if (strnstr(pdev->name, svm_dev_white_list[i].svm_dev_name, SVM_DEV_NAME_LEN) != NULL) { ++ svm_dev_white_list[i].dev = (void *)dev; ++ return 0; ++ } ++ } ++ return -1; ++} ++static int svm_get_sys_and_crg(const struct device *dev) ++{ ++ unsigned int crg_base; ++ unsigned int crg_size; ++ int i; ++ int svm_name_len; ++ const char *device_name = dev_name(dev); ++ struct device_node *np = dev->of_node; ++ ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ svm_name_len = strlen(svm_dev_white_list[i].svm_dev_name); ++ if (strncmp(device_name, svm_dev_white_list[i].svm_dev_name, svm_name_len) == 0) { ++ pr_debug("svm_get_sys_and_crg : strncmp will return i = %d, svm_dev_name = %s, smmu_dev_name = %s\n", ++ i, svm_dev_white_list[i].svm_dev_name, svm_dev_white_list[i].smmu_dev_name); ++ break; ++ } ++ } ++ if (i == SVM_DEV_MAX) { ++ dev_err(dev, "defer probe svm device, device name = %s not match\n", device_name); ++ return -EPROBE_DEFER; ++ } ++ if (of_property_read_u32(np, "crg-base", &crg_base) != 0 || ++ of_property_read_u32(np, "crg-size", &crg_size) != 0 || ++ of_property_read_u32(np, svm_dev_white_list[i].crg_name, &svm_dev_white_list[i].crg_offset) != 0) { ++ pr_warn("Warning: missing crg-base property in dts tree, we don't support smmu powner on check!!!\n"); ++ npu_dts_sys_peri = NULL; ++ } else { ++ npu_dts_sys_peri = ioremap(crg_base, crg_size); ++ } ++ dev_dbg(dev, " read crg_offset i = %d, crg_name = %s, crg_offset = 0x%x \n", ++ i, svm_dev_white_list[i].crg_name, svm_dev_white_list[i].crg_offset); ++ return 0; ++} ++static int svm_device_probe(struct platform_device *pdev) ++{ ++ int err; ++ struct device *dev = &pdev->dev; ++ struct svm_device *sdev = NULL; ++ struct device_node *np = dev->of_node; ++ ++ if (np == NULL) ++ return -ENODEV; ++ ++ if (!dev->bus || !dev->bus->iommu_ops) { ++ /* If SMMU is not probed, it should defer probe of this driver */ ++ dev_dbg(dev, "this dev bus is NULL or defer probe svm device\n"); ++ return -EPROBE_DEFER; ++ } ++ sdev = devm_kzalloc(dev, sizeof(*sdev), GFP_KERNEL); ++ if (sdev == NULL) ++ return -ENOMEM; ++ ++ sdev->id = probe_index; ++ sdev->dev = dev; ++ sdev->miscdev.minor = MISC_DYNAMIC_MINOR; ++ sdev->miscdev.fops = &svm_fops; ++ sdev->miscdev.name = devm_kasprintf(dev, GFP_KERNEL, SVM_DEVICE_NAME"%llu", sdev->id); ++ if (sdev->miscdev.name == NULL) ++ err = -ENOMEM; ++ ++ dev_set_drvdata(dev, sdev); ++ err = misc_register(&sdev->miscdev); ++ if (err) { ++ dev_err(dev, "Unable to register misc device\n"); ++ return err; ++ } ++ ++ if (svm_device_wl_process(pdev, dev) != 0) { ++ err = svm_init_core(sdev, np); ++ if (err) { ++ dev_err(dev, "failed to init cores\n"); ++ goto err_unregister_misc; ++ } ++ } ++ probe_index++; ++ if (svm_get_sys_and_crg(dev) != 0) { ++ dev_err(dev, "failed to svm_get_sys_and_crg, device error.\n"); ++ goto err_unregister_misc; ++ } ++ ++ mutex_init(&svm_process_mutex); ++ mutex_init(&svm_dev_pm_mutex); ++ dev_info(dev, "svm probe ok.\n"); ++ ++ return err; ++err_unregister_misc: ++ misc_deregister(&sdev->miscdev); ++ return err; ++} ++ ++static int svm_device_post_probe(const char *device_name) ++{ ++ int err, i; ++ struct device *dev = NULL; ++ struct svm_device *sdev = NULL; ++ ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ if (strnstr(device_name, svm_dev_white_list[i].svm_dev_name, SVM_DEV_NAME_LEN) != NULL) { ++ dev = (struct device *)svm_dev_white_list[i].dev; ++ break; ++ } ++ } ++ ++ if (dev == NULL || i >= SVM_DEV_MAX) { ++ dev_err(dev, "faile to find svm device in white list \n"); ++ return -1; ++ } ++ ++ sdev = dev_get_drvdata(dev); ++ if (sdev == NULL) { ++ dev_err(dev, "failed get drv data\n"); ++ return -1; ++ } ++ ++ err = svm_init_core(sdev, dev->of_node); ++ if (err) { ++ dev_err(dev, "failed to init cores\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++int svm_smmu_device_suspend(const char *device_name) ++{ ++ int ret = 0; ++ struct svm_dev_wl_mng *dev_mng = NULL; ++ ++ dev_mng = svm_device_get_mng(device_name); ++ if (dev_mng == NULL) ++ return -1; ++ ++ mutex_lock(&svm_dev_pm_mutex); ++ if (dev_mng->is_suspend == false) { ++ dev_mng->is_suspend = true; ++ ret = arm_smmu_device_suspend(dev_mng->smmu_dev_name); ++ } ++ mutex_unlock(&svm_dev_pm_mutex); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(svm_smmu_device_suspend); ++ ++int svm_smmu_device_resume(const char *device_name) ++{ ++ int ret = 0; ++ struct svm_dev_wl_mng *dev_mng = NULL; ++ ++ dev_mng = svm_device_get_mng(device_name); ++ if (dev_mng == NULL) ++ return -1; ++ ++ mutex_lock(&svm_dev_pm_mutex); ++ if (dev_mng->is_suspend == true) { ++ ret = arm_smmu_device_resume(dev_mng->smmu_dev_name); ++ dev_mng->is_suspend = false; ++ } ++ mutex_unlock(&svm_dev_pm_mutex); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(svm_smmu_device_resume); ++ ++void svm_smmu_device_reset_lock(void) ++{ ++ mutex_lock(&svm_dev_pm_mutex); ++ return; ++} ++EXPORT_SYMBOL(svm_smmu_device_reset_lock); ++ ++int svm_smmu_device_reset(const char *device_name) ++{ ++ int ret = -1; ++ struct svm_dev_wl_mng *dev_mng = NULL; ++ ++ dev_mng = svm_device_get_mng(device_name); ++ if (dev_mng == NULL) ++ return -1; ++ ++ if (dev_mng->is_suspend == false) ++ ret = arm_smmu_device_reset_ex(dev_mng->smmu_dev_name); ++ return ret; ++} ++EXPORT_SYMBOL(svm_smmu_device_reset); ++ ++void svm_smmu_device_reset_unlock(void) ++{ ++ mutex_unlock(&svm_dev_pm_mutex); ++ return; ++} ++EXPORT_SYMBOL(svm_smmu_device_reset_unlock); ++ ++ ++int svm_smmu_clk_live_process_register(smmu_clk_live_func enter, smmu_clk_live_func exit) ++{ ++ if (g_smmu_clk_live_enter == NULL) ++ g_smmu_clk_live_enter = enter; ++ ++ if (g_smmu_clk_live_exit == NULL) ++ g_smmu_clk_live_exit = exit; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(svm_smmu_clk_live_process_register); ++ ++ ++void svm_smmu_clk_live_enter(void) ++{ ++ if (g_smmu_clk_live_enter != NULL) ++ g_smmu_clk_live_enter(); ++} ++EXPORT_SYMBOL_GPL(svm_smmu_clk_live_enter); ++ ++void svm_smmu_clk_live_exit(void) ++{ ++ if (g_smmu_clk_live_exit != NULL) ++ g_smmu_clk_live_exit(); ++} ++EXPORT_SYMBOL_GPL(svm_smmu_clk_live_exit); ++ ++static bool svm_device_is_inited(const char *device_name) ++{ ++ int i; ++ ++ if (device_name == NULL) ++ return false; ++ ++ for (i = 0; i < SVM_DEV_MAX; i++) { ++ if (strnstr(device_name, svm_dev_white_list[i].svm_dev_name, SVM_DEV_NAME_LEN) != NULL) { ++ if (svm_dev_white_list[i].is_inited == true) ++ return true; ++ } ++ } ++ return false; ++} ++ ++static int svm_device_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct svm_device *sdev = dev_get_drvdata(dev); ++ const char *device_name = dev_name(dev); ++ ++ mutex_lock(&svm_dev_pm_mutex); ++ if (npu_dts_sys_peri != NULL) { ++ iounmap(npu_dts_sys_peri); ++ npu_dts_sys_peri = NULL; ++ } ++ mutex_unlock(&svm_dev_pm_mutex); ++ ++ svm_smmu_clk_live_enter(); ++ if (svm_device_is_inited(device_name)) ++ device_for_each_child(sdev->dev, NULL, svm_remove_core); ++ svm_smmu_clk_live_exit(); ++ ++ misc_deregister(&sdev->miscdev); ++ return 0; ++} ++ ++static void svm_device_shutdown(struct platform_device *pdev) ++{ ++ svm_device_remove(pdev); ++ return; ++} ++ ++static const struct of_device_id svm_of_match[] = { ++ { .compatible = "vendor,svm" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, svm_of_match); ++ ++static struct platform_driver svm_driver = { ++ .probe = svm_device_probe, ++ .remove = svm_device_remove, ++ .shutdown = svm_device_shutdown, ++ .driver = { ++ .name = SVM_DEVICE_NAME, ++ .of_match_table = svm_of_match, ++ }, ++}; ++ ++module_platform_driver(svm_driver); ++ ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/vendor/npu/smmu_power_on.c b/drivers/vendor/npu/smmu_power_on.c +new file mode 100644 +index 000000000000..ce0579115499 +--- /dev/null ++++ b/drivers/vendor/npu/smmu_power_on.c +@@ -0,0 +1,91 @@ ++/* ++ * Copyright (c) Shenshu Technologies Co., Ltd. 2020-2021. All rights reserved. ++ * Description: smmu pm ++ * Version: Initial Draft ++ * Create: 2020-01-16 ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define VENDOR_TOP_CTL_BASE (0x30000) ++ ++#define SMMU_LP_REQ (VENDOR_TOP_CTL_BASE + 0) ++#define TCU_QREQN_CG BIT(0) ++#define TCU_QREQN_PD BIT(1) ++ ++#define SMMU_LP_ACK (VENDOR_TOP_CTL_BASE + 0x4) ++#define TCU_QACCEPTN_CG BIT(0) ++#define TCU_QACCEPTN_PD BIT(4) ++ ++/* TBU reg */ ++#define SMMU_TBU_CR (0) ++#define TBU_EN_REQ BIT(0) ++ ++#define SMMU_TBU_CRACK (0x4) ++#define TBU_EN_ACK BIT(0) ++#define TBU_CONNECTED BIT(1) ++ ++#define ARM_SMMU_POLL_TIMEOUT_US 100 ++ ++static int npu_reg_bit_set_with_ack(void __iomem *base, unsigned int req_off, ++ unsigned int ack_off, unsigned int req_bit, unsigned int ack_bit) ++{ ++ u32 reg = 0; ++ u32 val = 0; ++ ++ val = readl_relaxed(base + req_off); ++ val |= req_bit; ++ writel_relaxed(val, base + req_off); ++ return readl_relaxed_poll_timeout(base + ack_off, reg, ++ reg & ack_bit, 1, ARM_SMMU_POLL_TIMEOUT_US); ++} ++ ++ ++int svm_smmu_power_on(void *base, unsigned int tcu_offset, unsigned int tbu_offset) ++{ ++ int ret; ++ void __iomem *tmp_base; ++ u32 reg; ++ ++ /****************tcu configure***************/ ++ tmp_base = (void __iomem *)base + tcu_offset; ++ /* Request leave power-down mode */ ++ ret = npu_reg_bit_set_with_ack(tmp_base, SMMU_LP_REQ, SMMU_LP_ACK, TCU_QREQN_CG, TCU_QACCEPTN_CG); ++ if (ret) { ++ /* To do , delete this log temporary */ ++ return -EINVAL; ++ } ++ /* Request leave clock-gating mode */ ++ ret = npu_reg_bit_set_with_ack(tmp_base, SMMU_LP_REQ, SMMU_LP_ACK, TCU_QREQN_PD, TCU_QACCEPTN_PD); ++ if (ret) { ++ printk("npu_reg_bit_set_with_ack failed !%s\n", __func__); ++ return -EINVAL; ++ } ++ ++ /****************tbu configure***************/ ++ /* enable AICore tbu */ ++ tmp_base = (void __iomem *)base + tbu_offset; ++ /* enable TBU request */ ++ npu_reg_bit_set_with_ack(tmp_base, SMMU_TBU_CR, SMMU_TBU_CRACK, TBU_EN_REQ, TBU_EN_ACK); ++ ++ /* check TBU enable acknowledge */ ++ reg = readl_relaxed(tmp_base + SMMU_TBU_CRACK); ++ if ((reg & TBU_CONNECTED) == 0) { ++ printk("%s:----------->Fail to CONNECTE TBU failed!\n", __func__); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL(svm_smmu_power_on); ++ ++ ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/vendor/peri/Makefile b/drivers/vendor/peri/Makefile +new file mode 100644 +index 000000000000..1a0c92eaea6f +--- /dev/null ++++ b/drivers/vendor/peri/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_ARCH_SS928V100) += peri_io_ss928v100.o ++obj-$(CONFIG_ARCH_SS927V100) += peri_io_ss928v100.o +diff --git a/drivers/vendor/peri/peri_io_ss928v100.c b/drivers/vendor/peri/peri_io_ss928v100.c +new file mode 100644 +index 000000000000..1d292650fe51 +--- /dev/null ++++ b/drivers/vendor/peri/peri_io_ss928v100.c +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (c) 2022-2022 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++ ++static DEFINE_SPINLOCK(peri_lock); ++ ++unsigned long bsp_peri_lock(enum bsp_peri_type type) ++{ ++ unsigned long flags = 0; ++ ++ switch(type) { ++ case BSP_PERI_SDIO: ++ spin_lock_irqsave(&peri_lock, flags); ++ default: ++ break; ++ } ++ return flags; ++} ++ ++void bsp_peri_unlock(unsigned long flags, enum bsp_peri_type type) ++{ ++ switch(type) { ++ case BSP_PERI_SDIO: ++ spin_unlock_irqrestore(&peri_lock, flags); ++ default: ++ break; ++ } ++} ++ +diff --git a/fs/read_write.c b/fs/read_write.c +index 371a5a76f30e..cc1558d0441f 100644 +--- a/fs/read_write.c ++++ b/fs/read_write.c +@@ -500,6 +500,7 @@ ssize_t vfs_read(struct file *file, char __user *buf, size_t count, loff_t *pos) + inc_syscr(current); + return ret; + } ++EXPORT_SYMBOL(vfs_read); + + static ssize_t new_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos) + { +@@ -610,6 +611,7 @@ ssize_t vfs_write(struct file *file, const char __user *buf, size_t count, loff_ + file_end_write(file); + return ret; + } ++EXPORT_SYMBOL(vfs_write); + + /* file_ppos returns &file->f_pos or NULL if file is stream */ + static inline loff_t *file_ppos(struct file *file) +diff --git a/include/dt-bindings/clock/ss928v100_clock.h b/include/dt-bindings/clock/ss928v100_clock.h +new file mode 100644 +index 000000000000..d3cd2dcb76fc +--- /dev/null ++++ b/include/dt-bindings/clock/ss928v100_clock.h +@@ -0,0 +1,146 @@ ++/* ++ * Copyright (c) 2016-2017 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ * ++ */ ++ ++#ifndef __DTS_SS928V100_CLOCK_H ++#define __DTS_SS928V100_CLOCK_H ++ ++/* fixed rate */ ++#define SS928V100_FIXED_2400M 1 ++#define SS928V100_FIXED_1200M 2 ++#define SS928V100_FIXED_1188M 3 ++#define SS928V100_FIXED_896M 4 ++#define SS928V100_FIXED_800M 5 ++#define SS928V100_FIXED_792M 6 ++#define SS928V100_FIXED_786M 7 ++#define SS928V100_FIXED_750M 8 ++#define SS928V100_FIXED_700M 9 ++#define SS928V100_FIXED_672M 10 ++#define SS928V100_FIXED_600M 11 ++#define SS928V100_FIXED_594M 12 ++#define SS928V100_FIXED_560M 13 ++#define SS928V100_FIXED_500M 14 ++#define SS928V100_FIXED_475M 15 ++#define SS928V100_FIXED_396M 16 ++#define SS928V100_FIXED_300M 17 ++#define SS928V100_FIXED_297M 18 ++#define SS928V100_FIXED_257M 19 ++#define SS928V100_FIXED_250M 20 ++#define SS928V100_FIXED_200M 21 ++#define SS928V100_FIXED_198M 22 ++#define SS928V100_FIXED_187P_5M 23 ++#define SS928V100_FIXED_150M 24 ++#define SS928V100_FIXED_148P_5M 25 ++#define SS928V100_FIXED_134M 26 ++#define SS928V100_FIXED_108M 27 ++#define SS928V100_FIXED_100M 28 ++#define SS928V100_FIXED_99M 29 ++#define SS928V100_FIXED_74P_25M 30 ++#define SS928V100_FIXED_72M 31 ++#define SS928V100_FIXED_64M 32 ++#define SS928V100_FIXED_60M 33 ++#define SS928V100_FIXED_54M 34 ++#define SS928V100_FIXED_50M 35 ++#define SS928V100_FIXED_49P_5M 36 ++#define SS928V100_FIXED_37P_125M 37 ++#define SS928V100_FIXED_36M 38 ++#define SS928V100_FIXED_27M 39 ++#define SS928V100_FIXED_25M 40 ++#define SS928V100_FIXED_24M 41 ++#define SS928V100_FIXED_12M 42 ++#define SS928V100_FIXED_12P_288M 43 ++#define SS928V100_FIXED_6M 44 ++#define SS928V100_FIXED_3M 45 ++#define SS928V100_FIXED_1P_6M 46 ++#define SS928V100_FIXED_400K 47 ++#define SS928V100_FIXED_100K 48 ++ ++#define SS928V100_I2C0_CLK 50 ++#define SS928V100_I2C1_CLK 51 ++#define SS928V100_I2C2_CLK 52 ++#define SS928V100_I2C3_CLK 53 ++#define SS928V100_I2C4_CLK 54 ++#define SS928V100_I2C5_CLK 55 ++ ++#define SS928V100_SPI0_CLK 62 ++#define SS928V100_SPI1_CLK 63 ++#define SS928V100_SPI2_CLK 64 ++#define SS928V100_SPI3_CLK 65 ++ ++#define SS928V100_EDMAC_CLK 69 ++#define SS928V100_EDMAC_AXICLK 70 ++ ++/* mux clocks */ ++#define SS928V100_PWM0_MUX 72 ++#define SS928V100_PWM1_MUX 73 ++#define SS928V100_I2C0_MUX 74 ++#define SS928V100_I2C1_MUX 75 ++#define SS928V100_I2C2_MUX 76 ++#define SS928V100_I2C3_MUX 77 ++#define SS928V100_I2C4_MUX 78 ++#define SS928V100_I2C5_MUX 79 ++#define SS928V100_FMC_MUX 80 ++#define SS928V100_HPAXI_MUX 81 ++#define SS928V100_DDRAXI_MUX 82 ++#define SS928V100_MMC0_MUX 83 ++#define SS928V100_UART0_MUX 84 ++#define SS928V100_UART1_MUX 85 ++#define SS928V100_UART2_MUX 86 ++#define SS928V100_UART3_MUX 87 ++#define SS928V100_UART4_MUX 88 ++#define SS928V100_UART5_MUX 89 ++ ++/* gate clocks */ ++#define SS928V100_FMC_CLK 90 ++#define SS928V100_UART0_CLK 91 ++#define SS928V100_UART1_CLK 92 ++#define SS928V100_UART2_CLK 93 ++#define SS928V100_UART3_CLK 94 ++#define SS928V100_UART4_CLK 95 ++#define SS928V100_UART5_CLK 96 ++#define SS928V100_MMC0_CLK 97 ++#define SS928V100_MMC1_CLK 98 ++#define SS928V100_MMC2_CLK 99 ++#define SS928V100_MMC3_CLK 100 ++ ++#define SS928V100_ETH_CLK 101 ++#define SS928V100_ETH_MACIF_CLK 102 ++#define SS928V100_ETH1_CLK 103 ++#define SS928V100_ETH1_MACIF_CLK 104 ++ ++/* complex */ ++#define SS928V100_MAC0_CLK 110 ++#define SS928V100_MAC1_CLK 111 ++#define SS928V100_SATA_CLK 112 ++#define SS928V100_USB_CLK 113 ++#define SS928V100_USB1_CLK 114 ++ ++#define SS928V100_MMC1_MUX 115 ++#define SS928V100_MMC2_MUX 116 ++ ++/* lsadc clocks */ ++#define SS928V100_LSADC_CLK 120 ++#define SS928V100_PWM0_CLK 121 ++#define SS928V100_PWM1_CLK 122 ++ ++/* pll clocks */ ++#define SS928V100_APLL_CLK 250 ++ ++#define SS928V100_CRG_NR_CLKS 256 ++ ++#endif /* __DTS_SS928V100_CLOCK_H */ ++ +diff --git a/include/linux/bsp_cma.h b/include/linux/bsp_cma.h +new file mode 100644 +index 000000000000..02bcd5518708 +--- /dev/null ++++ b/include/linux/bsp_cma.h +@@ -0,0 +1,52 @@ ++/* ++ * Copyright (c) 2019 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++#ifndef __BSP_CMA_H__ ++#define __BSP_CMA_H__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define NAME_LEN_MAX 64 ++#define ZONE_MAX 64 ++ ++struct cma_zone { ++ struct device pdev; ++ char name[NAME_LEN_MAX]; ++ gfp_t gfp; ++ phys_addr_t phys_start; ++ phys_addr_t nbytes; ++ u32 alloc_type; ++ u32 block_align; ++}; ++ ++#ifdef CONFIG_CMA ++int is_cma_address(phys_addr_t phys, unsigned long size); ++phys_addr_t get_zones_start(void); ++struct cma_zone *get_cma_zone(const char *name); ++struct device *get_cma_device(const char *name); ++int __init declare_heap_memory(void); ++#endif /* CONFIG_CMA */ ++ ++#endif +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index 03a5de5f99f4..e3caf4f19870 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -22,6 +22,7 @@ + #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ + /* unused */ + /* unused */ ++#define CLK_IS_BASIC BIT(5) + #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ + #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ + #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ +diff --git a/include/linux/edmac.h b/include/linux/edmac.h +new file mode 100644 +index 000000000000..b937e8e6047e +--- /dev/null ++++ b/include/linux/edmac.h +@@ -0,0 +1,80 @@ ++/* ++ * ++ * Copyright (c) 2015-2021 Shenshu Technologies Co., Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef __DMAC_H__ ++#define __DMAC_H__ ++ ++#define DMAC_ERROR_BASE 0x64 ++ ++#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE + 0x10) ++#define DMAC_CHN_ERROR (DMAC_ERROR_BASE + 0x11) ++#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE + 0x12) ++#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE + 0x13) ++#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE + 0x14) ++#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE + 0xe) ++ ++#ifdef CONFIG_EDMAC ++extern int dma_driver_init(void); ++extern int dmac_channelclose(unsigned int channel); ++extern int dmac_channelstart(unsigned int u32channel); ++extern int dmac_channel_allocate(void); ++ ++extern int dmac_start_m2p(unsigned int channel, unsigned int pmemaddr, ++ unsigned int uwperipheralid, ++ unsigned int uwnumtransfers, ++ unsigned int next_lli_addr); ++extern int dmac_m2p_transfer(unsigned long long memaddr, unsigned int uwperipheralid, ++ unsigned int length); ++extern int dmac_channel_free(unsigned int channel); ++ ++extern int do_dma_m2p(unsigned long long memaddr, unsigned int peripheral_addr, ++ unsigned int length); ++extern int do_dma_p2m(unsigned long mem_addr, unsigned int peripheral_addr, ++ unsigned int length); ++extern int dmac_wait(int channel); ++ ++extern int dmac_start_m2m(unsigned int channel, unsigned long psource, ++ unsigned long pdest, unsigned int uwnumtransfers); ++extern int dmac_m2m_transfer(unsigned long source, unsigned long dest, ++ unsigned int length); ++extern int dmac_register_isr(unsigned int channel, void *pisr); ++extern int free_dmalli_space(unsigned int *ppheadlli, unsigned int page_num); ++extern int dmac_start_llim2p(unsigned int channel, unsigned int *pfirst_lli, ++ unsigned int uwperipheralid); ++extern int dmac_buildllim2m(const unsigned long *ppheadlli, ++ unsigned long psource, ++ unsigned long pdest, ++ unsigned int totaltransfersize, ++ unsigned int uwnumtransfers); ++ ++extern int dmac_start_llim2m(unsigned int channel, const unsigned long *pfirst_lli); ++ ++extern int allocate_dmalli_space(struct device *dev, unsigned long *ppheadlli, ++ unsigned int page_num); ++#endif /* CONFIG_EDMAC*/ ++ ++ ++/*structure for LLI*/ ++typedef struct dmac_lli { ++ //must be 64Byte aligned ++ unsigned long next_lli; ++ unsigned int reserved[5]; ++ unsigned int count; ++ unsigned long src_addr; ++ unsigned long dest_addr; ++ unsigned int config; ++ unsigned int pad[51]; ++} dmac_lli; ++#endif +diff --git a/include/linux/i2c.h b/include/linux/i2c.h +index 58a721c23eca..6d33e0afc713 100644 +--- a/include/linux/i2c.h ++++ b/include/linux/i2c.h +@@ -128,6 +128,23 @@ static inline int i2c_master_send_dmasafe(const struct i2c_client *client, + /* Transfer num messages. + */ + int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); ++ ++#ifdef CONFIG_ARCH_BSP ++ ++extern int bsp_i2c_master_send(const struct i2c_client *client, const char *buf, ++ int count); ++ ++extern int bsp_i2c_master_send_mul_reg(const struct i2c_client *client, const char *buf, ++ unsigned int count, unsigned int reg_data_width); ++ ++extern int bsp_i2c_master_recv(const struct i2c_client *client, char *buf, ++ int count); ++ ++extern int bsp_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, ++ int num); ++ ++#endif ++ + /* Unlocked flavor */ + int __i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num); + +diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h +index f015fa185253..33bfd817a26d 100644 +--- a/include/linux/iio/iio.h ++++ b/include/linux/iio/iio.h +@@ -694,6 +694,13 @@ struct iio_dev *devm_iio_device_alloc(struct device *parent, int sizeof_priv); + __printf(2, 3) + struct iio_trigger *devm_iio_trigger_alloc(struct device *dev, + const char *fmt, ...); ++ ++#ifdef CONFIG_ARCH_BSP ++int devm_iio_device_match(struct device *dev, void *res, void *data); ++void devm_iio_device_free(struct device *dev, struct iio_dev *indio_dev); ++void devm_iio_device_unregister(struct device *dev, struct iio_dev *indio_dev); ++#endif ++ + /** + * iio_buffer_enabled() - helper function to test if the buffer is enabled + * @indio_dev: IIO device structure for device +diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h +index 27b994e42ec4..4cde111e425b 100644 +--- a/include/linux/io-pgtable.h ++++ b/include/linux/io-pgtable.h +@@ -25,6 +25,8 @@ enum io_pgtable_fmt { + * @tlb_flush_walk: Synchronously invalidate all intermediate TLB state + * (sometimes referred to as the "walk cache") for a virtual + * address range. ++ * @tlb_flush_leaf: Synchronously invalidate all leaf TLB state for a virtual ++ * address range. + * @tlb_add_page: Optional callback to queue up leaf TLB invalidation for a + * single page. IOMMUs that cannot batch TLB invalidation + * operations efficiently will typically issue them here, but +@@ -38,6 +40,8 @@ struct iommu_flush_ops { + void (*tlb_flush_all)(void *cookie); + void (*tlb_flush_walk)(unsigned long iova, size_t size, size_t granule, + void *cookie); ++ void (*tlb_flush_leaf)(unsigned long iova, size_t size, size_t granule, ++ void *cookie); + void (*tlb_add_page)(struct iommu_iotlb_gather *gather, + unsigned long iova, size_t granule, void *cookie); + }; +@@ -82,14 +86,6 @@ struct io_pgtable_cfg { + * + * IO_PGTABLE_QUIRK_ARM_TTBR1: (ARM LPAE format) Configure the table + * for use in the upper half of a split address space. +- * +- * IO_PGTABLE_QUIRK_ARM_HD: Support hardware management of dirty status. +- * +- * IO_PGTABLE_QUIRK_ARM_BBML1: ARM SMMU supports BBM Level 1 behavior +- * when changing block size. +- * +- * IO_PGTABLE_QUIRK_ARM_BBML2: ARM SMMU supports BBM Level 2 behavior +- * when changing block size. + */ + #define IO_PGTABLE_QUIRK_ARM_NS BIT(0) + #define IO_PGTABLE_QUIRK_NO_PERMS BIT(1) +@@ -97,9 +93,6 @@ struct io_pgtable_cfg { + #define IO_PGTABLE_QUIRK_ARM_MTK_EXT BIT(3) + #define IO_PGTABLE_QUIRK_NON_STRICT BIT(4) + #define IO_PGTABLE_QUIRK_ARM_TTBR1 BIT(5) +- #define IO_PGTABLE_QUIRK_ARM_HD BIT(6) +- #define IO_PGTABLE_QUIRK_ARM_BBML1 BIT(7) +- #define IO_PGTABLE_QUIRK_ARM_BBML2 BIT(8) + unsigned long quirks; + unsigned long pgsize_bitmap; + unsigned int ias; +@@ -167,18 +160,6 @@ struct io_pgtable_ops { + size_t size, struct iommu_iotlb_gather *gather); + phys_addr_t (*iova_to_phys)(struct io_pgtable_ops *ops, + unsigned long iova); +- size_t (*split_block)(struct io_pgtable_ops *ops, unsigned long iova, +- size_t size); +- size_t (*merge_page)(struct io_pgtable_ops *ops, unsigned long iova, +- phys_addr_t phys, size_t size, int prot); +- int (*sync_dirty_log)(struct io_pgtable_ops *ops, +- unsigned long iova, size_t size, +- unsigned long *bitmap, unsigned long base_iova, +- unsigned long bitmap_pgshift); +- int (*clear_dirty_log)(struct io_pgtable_ops *ops, +- unsigned long iova, size_t size, +- unsigned long *bitmap, unsigned long base_iova, +- unsigned long bitmap_pgshift); + }; + + /** +@@ -239,6 +220,13 @@ io_pgtable_tlb_flush_walk(struct io_pgtable *iop, unsigned long iova, + iop->cfg.tlb->tlb_flush_walk(iova, size, granule, iop->cookie); + } + ++static inline void ++io_pgtable_tlb_flush_leaf(struct io_pgtable *iop, unsigned long iova, ++ size_t size, size_t granule) ++{ ++ iop->cfg.tlb->tlb_flush_leaf(iova, size, granule, iop->cookie); ++} ++ + static inline void + io_pgtable_tlb_add_page(struct io_pgtable *iop, + struct iommu_iotlb_gather * gather, unsigned long iova, +diff --git a/include/linux/ioasid.h b/include/linux/ioasid.h +index af1c9d62e642..e9dacd4b9f6b 100644 +--- a/include/linux/ioasid.h ++++ b/include/linux/ioasid.h +@@ -34,16 +34,13 @@ struct ioasid_allocator_ops { + #if IS_ENABLED(CONFIG_IOASID) + ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, ioasid_t max, + void *private); +-void ioasid_free(ioasid_t ioasid); ++void ioasid_get(ioasid_t ioasid); ++bool ioasid_put(ioasid_t ioasid); + void *ioasid_find(struct ioasid_set *set, ioasid_t ioasid, + bool (*getter)(void *)); + int ioasid_register_allocator(struct ioasid_allocator_ops *allocator); + void ioasid_unregister_allocator(struct ioasid_allocator_ops *allocator); + int ioasid_set_data(ioasid_t ioasid, void *data); +-static inline bool pasid_valid(ioasid_t ioasid) +-{ +- return ioasid != INVALID_IOASID; +-} + + #else /* !CONFIG_IOASID */ + static inline ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, +@@ -52,7 +49,14 @@ static inline ioasid_t ioasid_alloc(struct ioasid_set *set, ioasid_t min, + return INVALID_IOASID; + } + +-static inline void ioasid_free(ioasid_t ioasid) { } ++static inline void ioasid_get(ioasid_t ioasid) ++{ ++} ++ ++static inline bool ioasid_put(ioasid_t ioasid) ++{ ++ return false; ++} + + static inline void *ioasid_find(struct ioasid_set *set, ioasid_t ioasid, + bool (*getter)(void *)) +@@ -74,10 +78,5 @@ static inline int ioasid_set_data(ioasid_t ioasid, void *data) + return -ENOTSUPP; + } + +-static inline bool pasid_valid(ioasid_t ioasid) +-{ +- return false; +-} +- + #endif /* CONFIG_IOASID */ + #endif /* __LINUX_IOASID_H */ +diff --git a/include/linux/iommu.h b/include/linux/iommu.h +index 47294a3a398e..3f54ff2c15e3 100644 +--- a/include/linux/iommu.h ++++ b/include/linux/iommu.h +@@ -87,11 +87,6 @@ struct iommu_domain { + void *handler_token; + struct iommu_domain_geometry geometry; + void *iova_cookie; +- struct mutex switch_log_lock; +- KABI_RESERVE(1) +- KABI_RESERVE(2) +- KABI_RESERVE(3) +- KABI_RESERVE(4) + }; + + enum iommu_cap { +@@ -222,10 +217,6 @@ struct iommu_iotlb_gather { + * @device_group: find iommu group for a particular device + * @domain_get_attr: Query domain attributes + * @domain_set_attr: Change domain attributes +- * @support_dirty_log: Check whether domain supports dirty log tracking +- * @switch_dirty_log: Perform actions to start|stop dirty log tracking +- * @sync_dirty_log: Sync dirty log from IOMMU into a dirty bitmap +- * @clear_dirty_log: Clear dirty log of IOMMU by a mask bitmap + * @get_resv_regions: Request list of reserved regions for a device + * @put_resv_regions: Free list of reserved regions for a device + * @apply_resv_region: Temporary helper call-back for iova reserved ranges +@@ -265,50 +256,36 @@ struct iommu_ops { + int (*attach_dev)(struct iommu_domain *domain, struct device *dev); + void (*detach_dev)(struct iommu_domain *domain, struct device *dev); + int (*map)(struct iommu_domain *domain, unsigned long iova, +- phys_addr_t paddr, size_t size, int prot, gfp_t gfp); ++ phys_addr_t paddr, size_t size, int prot, gfp_t gfp); + size_t (*unmap)(struct iommu_domain *domain, unsigned long iova, +- size_t size, struct iommu_iotlb_gather *iotlb_gather); ++ size_t size, struct iommu_iotlb_gather *iotlb_gather); + void (*flush_iotlb_all)(struct iommu_domain *domain); ++ void (*inv_iotlb_range)(struct iommu_domain *domain, ++ struct mm_struct *mm, unsigned long start, unsigned long end); + void (*iotlb_sync_map)(struct iommu_domain *domain, unsigned long iova, +- size_t size); ++ size_t size); + void (*iotlb_sync)(struct iommu_domain *domain, +- struct iommu_iotlb_gather *iotlb_gather); ++ struct iommu_iotlb_gather *iotlb_gather); + phys_addr_t (*iova_to_phys)(struct iommu_domain *domain, dma_addr_t iova); + struct iommu_device *(*probe_device)(struct device *dev); + void (*release_device)(struct device *dev); + void (*probe_finalize)(struct device *dev); + struct iommu_group *(*device_group)(struct device *dev); + int (*domain_get_attr)(struct iommu_domain *domain, +- enum iommu_attr attr, void *data); ++ enum iommu_attr attr, void *data); + int (*domain_set_attr)(struct iommu_domain *domain, +- enum iommu_attr attr, void *data); +- +- /* +- * Track dirty log. Note: Don't concurrently call these interfaces with +- * other ops that access underlying page table. +- */ +- bool (*support_dirty_log)(struct iommu_domain *domain); +- int (*switch_dirty_log)(struct iommu_domain *domain, bool enable, +- unsigned long iova, size_t size, int prot); +- int (*sync_dirty_log)(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, unsigned long base_iova, +- unsigned long bitmap_pgshift); +- int (*clear_dirty_log)(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, unsigned long base_iova, +- unsigned long bitmap_pgshift); ++ enum iommu_attr attr, void *data); + + /* Request/Free a list of reserved regions for a device */ + void (*get_resv_regions)(struct device *dev, struct list_head *list); + void (*put_resv_regions)(struct device *dev, struct list_head *list); + void (*apply_resv_region)(struct device *dev, +- struct iommu_domain *domain, +- struct iommu_resv_region *region); ++ struct iommu_domain *domain, ++ struct iommu_resv_region *region); + + /* Window handling functions */ + int (*domain_window_enable)(struct iommu_domain *domain, u32 wnd_nr, +- phys_addr_t paddr, u64 size, int prot); ++ phys_addr_t paddr, u64 size, int prot); + void (*domain_window_disable)(struct iommu_domain *domain, u32 wnd_nr); + + int (*of_xlate)(struct device *dev, struct of_phandle_args *args); +@@ -345,24 +322,8 @@ struct iommu_ops { + + int (*def_domain_type)(struct device *dev); + +- KABI_DEPRECATE_FN(int, bind_guest_msi, struct iommu_domain *domain, +- dma_addr_t giova, phys_addr_t gpa, size_t size) +- KABI_DEPRECATE_FN(void, unbind_guest_msi, struct iommu_domain *domain, +- dma_addr_t giova) +- +- int (*dev_get_config)(struct device *dev, int type, void *data); +- int (*dev_set_config)(struct device *dev, int type, void *data); +- + unsigned long pgsize_bitmap; + struct module *owner; +- KABI_RESERVE(1) +- KABI_RESERVE(2) +- KABI_RESERVE(3) +- KABI_RESERVE(4) +- KABI_RESERVE(5) +- KABI_RESERVE(6) +- KABI_RESERVE(7) +- KABI_RESERVE(8) + }; + + /** +@@ -392,7 +353,7 @@ struct iommu_device { + struct iommu_fault_event { + struct iommu_fault fault; + struct list_head list; +- _KABI_DEPRECATE(u64, expire); ++ u64 expire; + }; + + /** +@@ -407,7 +368,7 @@ struct iommu_fault_param { + iommu_dev_fault_handler_t handler; + void *data; + struct list_head faults; +- _KABI_DEPRECATE(struct timer_list, timer); ++ struct timer_list timer; + struct mutex lock; + }; + +@@ -506,8 +467,6 @@ extern int iommu_attach_pasid_table(struct iommu_domain *domain, + extern void iommu_detach_pasid_table(struct iommu_domain *domain); + extern struct iommu_domain *iommu_get_domain_for_dev(struct device *dev); + extern struct iommu_domain *iommu_get_dma_domain(struct device *dev); +-extern size_t iommu_pgsize(struct iommu_domain *domain, +- unsigned long addr_merge, size_t size); + extern int iommu_map(struct iommu_domain *domain, unsigned long iova, + phys_addr_t paddr, size_t size, int prot); + extern int iommu_map_atomic(struct iommu_domain *domain, unsigned long iova, +@@ -579,20 +538,6 @@ extern int iommu_domain_get_attr(struct iommu_domain *domain, enum iommu_attr, + void *data); + extern int iommu_domain_set_attr(struct iommu_domain *domain, enum iommu_attr, + void *data); +-extern bool iommu_support_dirty_log(struct iommu_domain *domain); +-extern int iommu_switch_dirty_log(struct iommu_domain *domain, bool enable, +- unsigned long iova, size_t size, int prot); +-extern int iommu_sync_dirty_log(struct iommu_domain *domain, unsigned long iova, +- size_t size, unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift); +-extern int iommu_clear_dirty_log(struct iommu_domain *domain, unsigned long iova, +- size_t dma_size, unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long bitmap_pgshift); +- +-extern int iommu_dev_set_config(struct device *dev, int type, void *data); +-extern int iommu_dev_get_config(struct device *dev, int type, void *data); + + /* Window handling function prototypes */ + extern int iommu_domain_window_enable(struct iommu_domain *domain, u32 wnd_nr, +@@ -603,8 +548,7 @@ extern void iommu_domain_window_disable(struct iommu_domain *domain, u32 wnd_nr) + extern int report_iommu_fault(struct iommu_domain *domain, struct device *dev, + unsigned long iova, int flags); + +-extern void __acpi_device_create_direct_mappings(struct iommu_group *group, +- struct device *acpi_device); ++extern int iommu_request_dm_for_dev(struct device *dev); + + static inline void iommu_flush_iotlb_all(struct iommu_domain *domain) + { +@@ -994,37 +938,7 @@ static inline int iommu_domain_set_attr(struct iommu_domain *domain, + return -EINVAL; + } + +-static inline bool iommu_support_dirty_log(struct iommu_domain *domain) +-{ +- return false; +-} +- +-static inline int iommu_switch_dirty_log(struct iommu_domain *domain, +- bool enable, unsigned long iova, +- size_t size, int prot) +-{ +- return -EINVAL; +-} +- +-static inline int iommu_sync_dirty_log(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long pgshift) +-{ +- return -EINVAL; +-} +- +-static inline int iommu_clear_dirty_log(struct iommu_domain *domain, +- unsigned long iova, size_t size, +- unsigned long *bitmap, +- unsigned long base_iova, +- unsigned long pgshift) +-{ +- return -EINVAL; +-} +- +-static inline int iommu_device_register(struct iommu_device *iommu) ++static inline int iommu_device_register(struct iommu_device *iommu) + { + return -ENODEV; + } +@@ -1207,18 +1121,6 @@ iommu_sva_bind_group(struct iommu_group *group, struct mm_struct *mm, + return NULL; + } + +-static inline +-int iommu_dev_set_config(struct device *dev, int type, void *data) +-{ +- return -ENODEV; +-} +- +-static inline +-int iommmu_dev_get_config(struct device *dev, int type, void *data) +-{ +- return -ENODEV; +-} +- + #endif /* CONFIG_IOMMU_API */ + + /** +diff --git a/include/linux/iova.h b/include/linux/iova.h +index 3cb469b366d7..a0637abffee8 100644 +--- a/include/linux/iova.h ++++ b/include/linux/iova.h +@@ -26,7 +26,7 @@ struct iova_magazine; + struct iova_cpu_rcache; + + #define IOVA_RANGE_CACHE_MAX_SIZE 6 /* log of max cached IOVA range size (in pages) */ +-#define MAX_GLOBAL_MAGS CONFIG_IOVA_MAX_GLOBAL_MAGS /* magazines per bin */ ++#define MAX_GLOBAL_MAGS 32 /* magazines per bin */ + + struct iova_rcache { + spinlock_t lock; +@@ -95,7 +95,6 @@ struct iova_domain { + flush-queues */ + atomic_t fq_timer_on; /* 1 when timer is active, 0 + when not */ +- struct work_struct free_iova_work; + }; + + static inline unsigned long iova_size(struct iova *iova) +@@ -133,7 +132,7 @@ static inline unsigned long iova_pfn(struct iova_domain *iovad, dma_addr_t iova) + return iova >> iova_shift(iovad); + } + +-#if IS_REACHABLE(CONFIG_IOMMU_IOVA) ++#if IS_ENABLED(CONFIG_IOMMU_IOVA) + int iova_cache_get(void); + void iova_cache_put(void); + +diff --git a/include/linux/iprec.h b/include/linux/iprec.h +new file mode 100755 +index 000000000000..1bc1b5ed2a1c +--- /dev/null ++++ b/include/linux/iprec.h +@@ -0,0 +1,51 @@ ++#ifndef IPREC_H ++#define IPREC_H ++ ++#include ++ ++#define IPREC "iprec" ++#define IPREC_DUMP "dump" ++#define IPREC_DLAY "delay" ++#define IPREC_LINE "line" ++#define IPREC_LOCK "lock" ++#define IPREC_DEFAULT_DLAY 800 ++#define IPREC_DEFAULT_LINE 2000 ++#define IPREC_STR_LEN 512 ++ ++#define LOG_IPREC_ON 1 ++#define LOG_IPREC_OFF 0 ++ ++#define LOG_IPREC_SWITCH LOG_IPREC_OFF ++ ++char *iprec_tm(void); ++char *iprec_pool(void); ++void iprec_inc(void); ++void iprec_slock(void); ++int iprec_glock(void); ++spinlock_t *iprec_spinlock(void); ++ ++ ++#if (LOG_IPREC_SWITCH == LOG_IPREC_ON) ++ ++#define iprec_fmt(fmt) fmt ++ ++#define iprec(fmt, ...) \ ++ do { \ ++ unsigned long flags; \ ++ spin_lock_irqsave(iprec_spinlock(), flags); \ ++ if (!iprec_glock()) { \ ++ sprintf_s(iprec_pool(), IPREC_STR_LEN, "%s " \ ++ iprec_fmt(fmt), iprec_tm(), ##__VA_ARGS__); \ ++ iprec_inc();} \ ++ spin_unlock_irqrestore(iprec_spinlock(), flags); \ ++ } while (0) ++ ++#else ++ ++#define iprec(fmt, ...) ++ ++#endif // LOG_IPREC_SWITCH ++ ++ ++#endif // IPREC_H ++ +diff --git a/include/linux/mfd/bsp_fmc.h b/include/linux/mfd/bsp_fmc.h +new file mode 100644 +index 000000000000..e5aebf659005 +--- /dev/null ++++ b/include/linux/mfd/bsp_fmc.h +@@ -0,0 +1,480 @@ ++/* ++ * Header file for Vendor Flash Memory Controller Driver ++ * ++ * Copyright (c) 2016 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef __BSP_FMC_H_ ++#define __BSP_FMC_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define _512B (512) ++#define _1K (1024) ++#define _2K (2048) ++#define _4K (4096) ++#define _8K (8192) ++#define _16K (16384) ++#define _32K (32768) ++#define _64K (0x10000UL) ++#define _128K (0x20000UL) ++#define _256K (0x40000UL) ++#define _512K (0x80000UL) ++#define _1M (0x100000UL) ++#define _2M (0x200000UL) ++#define _4M (0x400000UL) ++#define _8M (0x800000UL) ++#define _16M (0x1000000UL) ++#define _32M (0x2000000UL) ++#define _64M (0x4000000UL) ++#define _128M (0x8000000UL) ++#define _256M (0x10000000UL) ++#define _512M (0x20000000UL) ++#define _1G (0x40000000ULL) ++#define _2G (0x80000000ULL) ++#define _4G (0x100000000ULL) ++#define _8G (0x200000000ULL) ++#define _16G (0x400000000ULL) ++#define _64G (0x1000000000ULL) ++ ++#define FMC_MEM_LEN _16M ++#define FMC_MAX_DMA_LEN _8K ++#define MAX_OOB_LEN _512B ++#define MAX_PAGE_SIZE _8K ++#define BUFF_LEN 128 ++ ++/* FMC REG MAP */ ++#define FMC_CFG 0x00 ++#define fmc_cfg_spi_nand_sel(_type) (((_size) & 0x3) << 11) ++#define SPI_NOR_ADDR_MODE BIT(10) ++#define FMC_CFG_OP_MODE_MASK BIT_MASK(0) ++#define FMC_CFG_OP_MODE_BOOT 0 ++#define FMC_CFG_OP_MODE_NORMAL 1 ++#define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10) ++#define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10) ++ ++#define fmc_cfg_block_size(_size) (((_size) & 0x3) << 8) ++#define fmc_cfg_ecc_type(_type) (((_type) & 0x7) << 5) ++#define fmc_cfg_page_size(_size) (((_size) & 0x3) << 3) ++#define fmc_cfg_flash_sel(_type) (((_type) & 0x3) << 1) ++#define fmc_cfg_op_mode(_mode) ((_mode) & 0x1) ++ ++#define SPI_NAND_MFR_OTHER 0x0 ++#define SPI_NAND_MFR_WINBOND 0x1 ++#define SPI_NAND_MFR_ESMT 0x2 ++#define SPI_NAND_MFR_MICRON 0x3 ++ ++#define SPI_NAND_SEL_SHIFT 11 ++#define SPI_NAND_SEL_MASK (0x3 << SPI_NAND_SEL_SHIFT) ++ ++#define SPI_NOR_ADDR_MODE_3_BYTES 0x0 ++#define SPI_NOR_ADDR_MODE_4_BYTES 0x1 ++ ++#define SPI_NOR_ADDR_MODE_SHIFT 10 ++#define SPI_NOR_ADDR_MODE_MASK (0x1 << SPI_NOR_ADDR_MODE_SHIFT) ++ ++#define BLOCK_SIZE_64_PAGE 0x0 ++#define BLOCK_SIZE_128_PAGE 0x1 ++#define BLOCK_SIZE_256_PAGE 0x2 ++#define BLOCK_SIZE_512_PAGE 0x3 ++ ++#define BLOCK_SIZE_MASK (0x3 << 8) ++ ++#define ECC_TYPE_0BIT 0x0 ++#define ECC_TYPE_8BIT 0x1 ++#define ECC_TYPE_16BIT 0x2 ++#define ECC_TYPE_24BIT 0x3 ++#define ECC_TYPE_28BIT 0x4 ++#define ECC_TYPE_40BIT 0x5 ++#define ECC_TYPE_64BIT 0x6 ++ ++#define ECC_TYPE_SHIFT 5 ++#define ECC_TYPE_MASK (0x7 << ECC_TYPE_SHIFT) ++ ++#define PAGE_SIZE_2KB 0x0 ++#define PAGE_SIZE_4KB 0x1 ++#define PAGE_SIZE_8KB 0x2 ++#define PAGE_SIZE_16KB 0x3 ++ ++#define PAGE_SIZE_SHIFT 3 ++#define PAGE_SIZE_MASK (0x3 << PAGE_SIZE_SHIFT) ++ ++#define FLASH_TYPE_SPI_NOR 0x0 ++#define FLASH_TYPE_SPI_NAND 0x1 ++#define FLASH_TYPE_NAND 0x2 ++#define FLASH_TYPE_UNKNOWN 0x3 ++ ++#define FLASH_TYPE_SEL_MASK (0x3 << 1) ++#define get_spi_flash_type(_reg) (((_reg) >> 1) & 0x3) ++ ++#define FMC_GLOBAL_CFG 0x04 ++#define FMC_GLOBAL_CFG_WP_ENABLE BIT(6) ++#define FMC_GLOBAL_CFG_RANDOMIZER_EN (1 << 2) ++#define FLASH_TYPE_SEL_MASK (0x3 << 1) ++#define fmc_cfg_flash_sel(_type) (((_type) & 0x3) << 1) ++ ++#define FMC_GLOBAL_CFG_DTR_MODE BIT(11) ++#define FMC_SPI_TIMING_CFG 0x08 ++#define timing_cfg_tcsh(nr) (((nr) & 0xf) << 8) ++#define timing_cfg_tcss(nr) (((nr) & 0xf) << 4) ++#define timing_cfg_tshsl(nr) ((nr) & 0xf) ++ ++#define CS_HOLD_TIME 0x6 ++#define CS_SETUP_TIME 0x6 ++#define CS_DESELECT_TIME 0xf ++ ++#define FMC_PND_PWIDTH_CFG 0x0c ++#define pwidth_cfg_rw_hcnt(_n) (((_n) & 0xf) << 8) ++#define pwidth_cfg_r_lcnt(_n) (((_n) & 0xf) << 4) ++#define pwidth_cfg_w_lcnt(_n) ((_n) & 0xf) ++ ++#define RW_H_WIDTH (0xa) ++#define R_L_WIDTH (0xa) ++#define W_L_WIDTH (0xa) ++ ++#define FMC_INT 0x18 ++#define FMC_INT_AHB_OP BIT(7) ++#define FMC_INT_WR_LOCK BIT(6) ++#define FMC_INT_DMA_ERR BIT(5) ++#define FMC_INT_ERR_ALARM BIT(4) ++#define FMC_INT_ERR_INVALID BIT(3) ++#define FMC_INT_ERR_INVALID_MASK (0x8) ++#define FMC_INT_ERR_VALID BIT(2) ++#define FMC_INT_ERR_VALID_MASK (0x4) ++#define FMC_INT_OP_FAIL BIT(1) ++#define FMC_INT_OP_DONE BIT(0) ++ ++#define FMC_INT_EN 0x1c ++#define FMC_INT_EN_AHB_OP BIT(7) ++#define FMC_INT_EN_WR_LOCK BIT(6) ++#define FMC_INT_EN_DMA_ERR BIT(5) ++#define FMC_INT_EN_ERR_ALARM BIT(4) ++#define FMC_INT_EN_ERR_INVALID BIT(3) ++#define FMC_INT_EN_ERR_VALID BIT(2) ++#define FMC_INT_EN_OP_FAIL BIT(1) ++#define FMC_INT_EN_OP_DONE BIT(0) ++ ++#define FMC_INT_CLR 0x20 ++#define FMC_INT_CLR_AHB_OP BIT(7) ++#define FMC_INT_CLR_WR_LOCK BIT(6) ++#define FMC_INT_CLR_DMA_ERR BIT(5) ++#define FMC_INT_CLR_ERR_ALARM BIT(4) ++#define FMC_INT_CLR_ERR_INVALID BIT(3) ++#define FMC_INT_CLR_ERR_VALID BIT(2) ++#define FMC_INT_CLR_OP_FAIL BIT(1) ++#define FMC_INT_CLR_OP_DONE BIT(0) ++ ++#define FMC_INT_CLR_ALL 0xff ++ ++#define FMC_CMD 0x24 ++#define fmc_cmd_cmd2(_cmd) (((_cmd) & 0xff) << 8) ++#define fmc_cmd_cmd1(_cmd) ((_cmd) & 0xff) ++ ++#define FMC_ADDRH 0x28 ++#define fmc_addrh_set(_addr) ((_addr) & 0xff) ++ ++#define FMC_ADDRL 0x2c ++#define fmc_addrl_block_mask(_page) ((_page) & 0xffffffc0) ++#define fmc_addrl_block_h_mask(_page) (((_page) & 0xffff) << 16) ++#define fmc_addrl_block_l_mask(_page) ((_page) & 0xffc0) ++ ++#define READ_ID_ADDR 0x00 ++#define PROTECT_ADDR 0xa0 ++#define FEATURE_ADDR 0xb0 ++#define STATUS_ADDR 0xc0 ++#define FMC_OP_CFG 0x30 ++#define op_cfg_fm_cs(_cs) ((_cs) << 11) ++#define op_cfg_force_cs_en(_en) ((_en) << 10) ++#define op_cfg_mem_if_type(_type) (((_type) & 0x7) << 7) ++#define op_cfg_addr_num(_addr) (((_addr) & 0x7) << 4) ++#define op_cfg_dummy_num(_dummy) ((_dummy) & 0xf) ++#define OP_CFG_OEN_EN (0x1 << 13) ++ ++#define IF_TYPE_SHIFT 7 ++#define IF_TYPE_MASK (0x7 << IF_TYPE_SHIFT) ++ ++#define READ_ID_ADDR_NUM 1 ++#define FEATURES_OP_ADDR_NUM 1 ++#define STD_OP_ADDR_NUM 3 ++ ++#define FMC_SPI_OP_ADDR 0x34 ++ ++#define FMC_DATA_NUM 0x38 ++#define fmc_data_num_cnt(_n) ((_n) & 0x3fff) ++ ++#define SPI_NOR_SR_LEN 1 /* Status Register length */ ++#define SPI_NOR_CR_LEN 1 /* Config Register length */ ++#define FEATURES_DATA_LEN 1 ++#define READ_OOB_BB_LEN 1 ++ ++#define PROTECT_BRWD_MASK BIT(7) ++#define PROTECT_BP3_MASK BIT(6) ++#define PROTECT_BP2_MASK BIT(5) ++#define PROTECT_BP1_MASK BIT(4) ++#define PROTECT_BP0_MASK BIT(3) ++ ++#define any_bp_enable(_val) ((PROTECT_BP3_MASK & _val) || (PROTECT_BP2_MASK & _val) || \ ++ (PROTECT_BP1_MASK & _val) || (PROTECT_BP0_MASK & _val)) ++ ++#define ALL_BP_MASK (PROTECT_BP3_MASK | PROTECT_BP2_MASK | \ ++ PROTECT_BP1_MASK | PROTECT_BP0_MASK) ++ ++#define FEATURE_ECC_ENABLE (1 << 4) ++#define FEATURE_QE_ENABLE (1 << 0) ++ ++#define FMC_OP 0x3c ++#define FMC_OP_DUMMY_EN BIT(8) ++#define FMC_OP_CMD1_EN BIT(7) ++#define FMC_OP_ADDR_EN BIT(6) ++#define FMC_OP_WRITE_DATA_EN BIT(5) ++#define FMC_OP_CMD2_EN BIT(4) ++#define FMC_OP_WAIT_READY_EN BIT(3) ++#define FMC_OP_READ_DATA_EN BIT(2) ++#define FMC_OP_READ_STATUS_EN BIT(1) ++#define FMC_OP_REG_OP_START BIT(0) ++ ++#define FMC_OP_DMA 0x68 ++#define FMC_DMA_LEN 0x40 ++#define fmc_dma_len_set(_len) ((_len) & 0x0fffffff) ++ ++#define FMC_DMA_AHB_CTRL 0x48 ++#define FMC_DMA_AHB_CTRL_DMA_PP_EN BIT(3) ++#define FMC_DMA_AHB_CTRL_BURST16_EN BIT(2) ++#define FMC_DMA_AHB_CTRL_BURST8_EN BIT(1) ++#define FMC_DMA_AHB_CTRL_BURST4_EN BIT(0) ++ ++#define ALL_BURST_ENABLE (FMC_DMA_AHB_CTRL_BURST16_EN | \ ++ FMC_DMA_AHB_CTRL_BURST8_EN | \ ++ FMC_DMA_AHB_CTRL_BURST4_EN) ++ ++#define FMC_DMA_ADDR_OFFSET 4096 ++ ++#define FMC_DMA_SADDR_D0 0x4c ++ ++#define FMC_DMA_SADDR_D1 0x50 ++ ++#define FMC_DMA_SADDR_D2 0x54 ++ ++#define FMC_DMA_SADDR_D3 0x58 ++ ++#define FMC_DMA_SADDR_OOB 0x5c ++ ++#ifdef CONFIG_64BIT ++#define FMC_DMA_BIT_SHIFT_LENTH 32 ++#define FMC_DMA_SADDRH_D0 0x200 ++#define FMC_DMA_SADDRH_SHIFT 0x3LL ++#define FMC_DMA_SADDRH_MASK (FMC_DMA_SADDRH_SHIFT << FMC_DMA_BIT_SHIFT_LENTH) ++ ++#define FMC_DMA_SADDRH_OOB 0x210 ++#endif ++ ++#define FMC_DMA_BLK_SADDR 0x60 ++#define fmc_dma_blk_saddr_set(_addr) ((_addr) & 0xffffff) ++ ++#define FMC_DMA_BLK_LEN 0x64 ++#define fmc_dma_blk_len_set(_len) ((_len) & 0xffff) ++ ++#define FMC_OP_CTRL 0x68 ++#define op_ctrl_rd_opcode(code) (((code) & 0xff) << 16) ++#define op_ctrl_wr_opcode(code) (((code) & 0xff) << 8) ++#define op_ctrl_rd_op_sel(_op) (((_op) & 0x3) << 4) ++#define op_ctrl_dma_op(_type) ((_type) << 2) ++#define op_ctrl_rw_op(op) ((op) << 1) ++#define OP_CTRL_DMA_OP_READY BIT(0) ++ ++#define RD_OP_READ_ALL_PAGE 0x0 ++#define RD_OP_READ_OOB 0x1 ++#define RD_OP_BLOCK_READ 0x2 ++ ++#define RD_OP_SHIFT 4 ++#define RD_OP_MASK (0x3 << RD_OP_SHIFT) ++ ++#define OP_TYPE_DMA 0x0 ++#define OP_TYPE_REG 0x1 ++ ++#define FMC_OP_READ 0x0 ++#define FMC_OP_WRITE 0x1 ++#define RW_OP_READ 0x0 ++#define RW_OP_WRITE 0x1 ++ ++#define FMC_OP_PARA 0x70 ++#define FMC_OP_PARA_RD_OOB_ONLY BIT(1) ++ ++#define FMC_BOOT_SET 0x74 ++#define FMC_BOOT_SET_DEVICE_ECC_EN BIT(3) ++#define FMC_BOOT_SET_BOOT_QUAD_EN BIT(1) ++ ++#define FMC_STATUS 0xac ++ ++#ifndef FMC_VERSION ++#define FMC_VERSION 0xbc ++#endif ++ ++/* fmc IP version */ ++#ifndef FMC_VER_100 ++#define FMC_VER_100 (0x100) ++#endif ++ ++/* DMA address align with 32 bytes. */ ++#define FMC_DMA_ALIGN 32 ++ ++#define FMC_CHIP_DELAY 25 ++#define FMC_ECC_ERR_NUM0_BUF0 0xc0 ++#define get_ecc_err_num(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff) ++ ++#define DISABLE 0 ++#define ENABLE 1 ++ ++#define FMC_REG_ADDRESS_LEN 0x200 ++ ++#define FMC_MAX_READY_WAIT_JIFFIES (HZ) ++ ++#define MAX_SPI_NOR_ID_LEN 8 ++#define MAX_NAND_ID_LEN 8 ++#define MAX_SPI_NAND_ID_LEN 3 ++ ++#define GET_OP 0 ++#define SET_OP 1 ++ ++#define STATUS_ECC_MASK (0x3 << 4) ++#define STATUS_P_FAIL_MASK (1 << 3) ++#define STATUS_E_FAIL_MASK (1 << 2) ++#define STATUS_WEL_MASK (1 << 1) ++#define STATUS_OIP_MASK (1 << 0) ++ ++#define FMC_VERSION 0xbc ++ ++/* fmc IP version */ ++#define FMC_VER_100 (0x100) ++ ++#define CONFIG_SPI_NAND_MAX_CHIP_NUM (1) ++ ++#define CONFIG_FMC100_MAX_NAND_CHIP (1) ++ ++#define get_page_index(host) \ ++ ((host->addr_value[0] >> 16) | (host->addr_value[1] << 16)) ++#define FMC_MAX_CHIP_NUM 2 ++ ++extern unsigned char fmc_cs_user[]; ++ ++#define fmc_readl(_host, _reg) \ ++ (readl((char *)_host->regbase + (_reg))) ++ ++#define fmc_readb( _addr) \ ++ (readb((void __iomem *)(_addr))) ++ ++#define fmc_readw( _addr) \ ++ (readw((void __iomem *)(_addr))) ++ ++#define fmc_writel(_host, _reg, _value) \ ++ (writel((u_int)(_value), ((char *)_host->regbase + (_reg)))) ++ ++#define fmc_writeb(_val, _addr) \ ++ (writeb((u_int)(_val), ((char *)_addr))) ++ ++#define FMC_WAIT_TIMEOUT 0x2000000 ++ ++#define fmc_cmd_wait_cpu_finish(_host) \ ++ do { \ ++ unsigned regval, timeout = FMC_WAIT_TIMEOUT * 2; \ ++ do { \ ++ regval = fmc_readl((_host), FMC_OP); \ ++ --timeout; \ ++ } while ((regval & FMC_OP_REG_OP_START) && timeout); \ ++ if (!timeout) \ ++ pr_info("Error: Wait cmd cpu finish timeout!\n"); \ ++ } while (0) ++ ++#define fmc_dma_wait_int_finish(_host) \ ++ do { \ ++ unsigned regval, timeout = FMC_WAIT_TIMEOUT; \ ++ do { \ ++ regval = fmc_readl((_host), FMC_INT); \ ++ --timeout; \ ++ } while ((!(regval & FMC_INT_OP_DONE) && timeout)); \ ++ if (!timeout) \ ++ pr_info("Error: Wait dma int finish timeout!\n"); \ ++ } while (0) ++ ++#define fmc_dma_wait_cpu_finish(_host) \ ++ do { \ ++ unsigned regval, timeout = FMC_WAIT_TIMEOUT; \ ++ do { \ ++ regval = fmc_readl((_host), FMC_OP_CTRL); \ ++ --timeout; \ ++ } while ((regval & OP_CTRL_DMA_OP_READY) && timeout); \ ++ if (!timeout) \ ++ pr_info("Error: Wait dma cpu finish timeout!\n"); \ ++ } while (0) ++ ++#define BT_DBG 0 /* Boot init debug print */ ++#define ER_DBG 0 /* Erase debug print */ ++#define WR_DBG 0 /* Write debug print */ ++#define RD_DBG 0 /* Read debug print */ ++#define QE_DBG 0 /* Quad Enable debug print */ ++#define OP_DBG 0 /* OP command debug print */ ++#define DMA_DB 0 /* DMA read or write debug print */ ++#define AC_DBG 0 /* 3-4byte Address Cycle */ ++#define SR_DBG 0 /* Status Register debug print */ ++#define CR_DBG 0 /* Config Register debug print */ ++#define FT_DBG 0 /* Features debug print */ ++#define WE_DBG 0 /* Write Enable debug print */ ++#define BP_DBG 0 /* Block Protection debug print */ ++#define EC_DBG 0 /* enable/disable ecc0 and randomizer */ ++#define PM_DBG 0 /* power management debug */ ++ ++#define fmc_pr(_type, _fmt, arg...) \ ++ do { \ ++ if (_type) \ ++ db_msg(_fmt, ##arg) \ ++ } while (0) ++ ++#define db_msg(_fmt, arg...) \ ++ pr_info("%s(%d): " _fmt, __func__, __LINE__, ##arg); ++ ++#define db_bug(fmt, args...) \ ++ do { \ ++ pr_info("%s(%d): BUG: " fmt, __FILE__, __LINE__, ##args); \ ++ while (1) \ ++ ; \ ++ } while (0) ++ ++enum fmc_iftype { ++ IF_TYPE_STD, ++ IF_TYPE_DUAL, ++ IF_TYPE_DIO, ++ IF_TYPE_QUAD, ++ IF_TYPE_QIO, ++}; ++ ++struct bsp_fmc { ++ void __iomem *regbase; ++ void __iomem *iobase; ++ struct clk *clk; ++ struct mutex lock; ++ void *buffer; ++ dma_addr_t dma_buffer; ++ unsigned int dma_len; ++}; ++ ++struct fmc_cmd_op { ++ unsigned char cs; ++ unsigned char cmd; ++ unsigned char l_cmd; ++ unsigned char addr_h; ++ unsigned int addr_l; ++ unsigned int data_no; ++ unsigned short option; ++ unsigned short op_cfg; ++}; ++ ++extern struct mutex fmc_switch_mutex; ++ ++#endif /* __BSP_FMC_H_ */ +diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h +index e3eaf458787a..70128b118c9f 100644 +--- a/include/linux/mm_types.h ++++ b/include/linux/mm_types.h +@@ -611,6 +611,9 @@ struct mm_struct { + #ifdef CONFIG_IOMMU_SVA + u32 pasid; + #endif ++#ifdef CONFIG_IOMMU_SUPPORT ++ u32 pasid; ++#endif + + #ifdef CONFIG_MEMORY_RELIABLE + /* total used reliable pages */ +diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h +index 40d7e98fc990..cbd9a1a2cc55 100644 +--- a/include/linux/mmc/host.h ++++ b/include/linux/mmc/host.h +@@ -173,6 +173,7 @@ struct mmc_host_ops { + */ + int (*multi_io_quirk)(struct mmc_card *card, + unsigned int direction, int blk_size); ++ int (*card_info_save)(struct mmc_host *host); + }; + + struct mmc_cqe_ops { +@@ -281,6 +282,11 @@ struct mmc_host { + unsigned int f_min; + unsigned int f_max; + unsigned int f_init; ++ unsigned int type; ++#define MMC_HOST_TYPE_MMC 0 /* MMC card */ ++#define MMC_HOST_TYPE_SD 1 /* SD card */ ++#define MMC_HOST_TYPE_SDIO 2 /* SDIO card */ ++#define MMC_HOST_TYPE_SD_COMBO 3 /* SD combo (IO+mem) card */ + u32 ocr_avail; + u32 ocr_avail_sdio; /* SDIO-specific OCR */ + u32 ocr_avail_sd; /* SD-specific OCR */ +@@ -289,7 +295,7 @@ struct mmc_host { + u32 max_current_330; + u32 max_current_300; + u32 max_current_180; +- ++ + #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ + #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ + #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +@@ -425,6 +431,12 @@ struct mmc_host { + + struct delayed_work detect; + int detect_change; /* card detect flag */ ++ ++ u32 card_status; ++#define MMC_CARD_UNINIT 0 ++#define MMC_CARD_INIT 1 ++#define MMC_CARD_INIT_FAIL 2 ++ + struct mmc_slot slot; + + const struct mmc_bus_ops *bus_ops; /* current bus driver */ +diff --git a/include/linux/pwm.h b/include/linux/pwm.h +index a13ff383fa1d..cf447184a299 100644 +--- a/include/linux/pwm.h ++++ b/include/linux/pwm.h +@@ -58,6 +58,10 @@ enum { + struct pwm_state { + u64 period; + u64 duty_cycle; ++#if (defined(CONFIG_ARCH_SS928V100) || defined(CONFIG_ARCH_SS927V100)) ++ unsigned int duty_cycle1; ++ unsigned int duty_cycle2; ++#endif + enum pwm_polarity polarity; + bool enabled; + }; +diff --git a/include/linux/securec.h b/include/linux/securec.h +new file mode 100644 +index 000000000000..d93305600689 +--- /dev/null ++++ b/include/linux/securec.h +@@ -0,0 +1,629 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: The user of this secure c library should include this header file in you source code. ++ * This header file declare all supported API prototype of the library, ++ * such as memcpy_s, strcpy_s, wcscpy_s,strcat_s, strncat_s, sprintf_s, scanf_s, and so on. ++ * Create: 2014-02-25 ++ * Notes: Do not modify this file by yourself. ++ */ ++ ++#ifndef SECUREC_H_5D13A042_DC3F_4ED9_A8D1_882811274C27 ++#define SECUREC_H_5D13A042_DC3F_4ED9_A8D1_882811274C27 ++ ++#include "securectype.h" ++#ifndef SECUREC_HAVE_STDARG_H ++#define SECUREC_HAVE_STDARG_H 1 ++#endif ++ ++#if SECUREC_HAVE_STDARG_H ++#include ++#endif ++ ++#ifndef SECUREC_HAVE_ERRNO_H ++#define SECUREC_HAVE_ERRNO_H 1 ++#endif ++ ++/* EINVAL ERANGE may defined in errno.h */ ++#if SECUREC_HAVE_ERRNO_H ++#if SECUREC_IN_KERNEL ++#include ++#else ++#include ++#endif ++#endif ++ ++/* Define error code */ ++#if defined(SECUREC_NEED_ERRNO_TYPE) || !defined(__STDC_WANT_LIB_EXT1__) || \ ++ (defined(__STDC_WANT_LIB_EXT1__) && (!__STDC_WANT_LIB_EXT1__)) ++#ifndef SECUREC_DEFINED_ERRNO_TYPE ++#define SECUREC_DEFINED_ERRNO_TYPE ++/* Just check whether macrodefinition exists. */ ++#ifndef errno_t ++typedef int errno_t; ++#endif ++#endif ++#endif ++ ++/* Success */ ++#ifndef EOK ++#define EOK 0 ++#endif ++ ++#ifndef EINVAL ++/* The src buffer is not correct and destination buffer can not be reset */ ++#define EINVAL 22 ++#endif ++ ++#ifndef EINVAL_AND_RESET ++/* Once the error is detected, the dest buffer must be reset! Value is 22 or 128 */ ++#define EINVAL_AND_RESET 150 ++#endif ++ ++#ifndef ERANGE ++/* The destination buffer is not long enough and destination buffer can not be reset */ ++#define ERANGE 34 ++#endif ++ ++#ifndef ERANGE_AND_RESET ++/* Once the error is detected, the dest buffer must be reset! Value is 34 or 128 */ ++#define ERANGE_AND_RESET 162 ++#endif ++ ++#ifndef EOVERLAP_AND_RESET ++/* Once the buffer overlap is detected, the dest buffer must be reset! Value is 54 or 128 */ ++#define EOVERLAP_AND_RESET 182 ++#endif ++ ++/* If you need export the function of this library in Win32 dll, use __declspec(dllexport) */ ++#ifndef SECUREC_API ++#if defined(SECUREC_DLL_EXPORT) ++#define SECUREC_API __declspec(dllexport) ++#elif defined(SECUREC_DLL_IMPORT) ++#define SECUREC_API __declspec(dllimport) ++#else ++/* ++ * Standardized function declaration. If a security function is declared in the your code, ++ * it may cause a compilation alarm,Please delete the security function you declared. ++ * Adding extern under windows will cause the system to have inline functions to expand, ++ * so do not add the extern in default ++ */ ++#if defined(_MSC_VER) ++#define SECUREC_API ++#else ++#define SECUREC_API extern ++#endif ++#endif ++#endif ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++/* ++ * Description: The GetHwSecureCVersion function get SecureC Version string and version number. ++ * Parameter: verNumber - to store version number (for example value is 0x500 | 0xa) ++ * Return: version string ++ */ ++SECUREC_API const char *GetHwSecureCVersion(unsigned short *verNumber); ++ ++#if SECUREC_ENABLE_MEMSET ++/* ++ * Description: The memset_s function copies the value of c (converted to an unsigned char) into each of ++ * the first count characters of the object pointed to by dest. ++ * Parameter: dest - destination address ++ * Parameter: destMax - The maximum length of destination buffer ++ * Parameter: c - the value to be copied ++ * Parameter: count - copies count bytes of value to dest ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t memset_s(void *dest, size_t destMax, int c, size_t count); ++#endif ++ ++#ifndef SECUREC_ONLY_DECLARE_MEMSET ++#define SECUREC_ONLY_DECLARE_MEMSET 0 ++#endif ++ ++#if !SECUREC_ONLY_DECLARE_MEMSET ++ ++#if SECUREC_ENABLE_MEMMOVE ++/* ++ * Description: The memmove_s function copies n characters from the object pointed to by src ++ * into the object pointed to by dest. ++ * Parameter: dest - destination address ++ * Parameter: destMax - The maximum length of destination buffer ++ * Parameter: src - source address ++ * Parameter: count - copies count bytes from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_MEMCPY ++/* ++ * Description: The memcpy_s function copies n characters from the object pointed to ++ * by src into the object pointed to by dest. ++ * Parameter: dest - destination address ++ * Parameter: destMax - The maximum length of destination buffer ++ * Parameter: src - source address ++ * Parameter: count - copies count bytes from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_STRCPY ++/* ++ * Description: The strcpy_s function copies the string pointed to by strSrc (including ++ * the terminating null character) into the array pointed to by strDest ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) ++ * Parameter: strSrc - source address ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc); ++#endif ++ ++#if SECUREC_ENABLE_STRNCPY ++/* ++ * Description: The strncpy_s function copies not more than n successive characters (not including ++ * the terminating null character) from the array pointed to by strSrc to the array pointed to by strDest. ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) ++ * Parameter: strSrc - source address ++ * Parameter: count - copies count characters from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_STRCAT ++/* ++ * Description: The strcat_s function appends a copy of the string pointed to by strSrc (including ++ * the terminating null character) to the end of the string pointed to by strDest. ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null wide character) ++ * Parameter: strSrc - source address ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc); ++#endif ++ ++#if SECUREC_ENABLE_STRNCAT ++/* ++ * Description: The strncat_s function appends not more than n successive characters (not including ++ * the terminating null character) ++ * from the array pointed to by strSrc to the end of the string pointed to by strDest. ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) ++ * Parameter: strSrc - source address ++ * Parameter: count - copies count characters from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_VSPRINTF ++/* ++ * Description: The vsprintf_s function is equivalent to the vsprintf function except for the parameter destMax ++ * and the explicit runtime-constraints violation ++ * Parameter: strDest - produce output according to a format,write to the character string strDest. ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null wide character) ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of characters printed(not including the terminating null byte '\0'), ++ * If an error occurred Return: -1. ++ */ ++SECUREC_API int vsprintf_s(char *strDest, size_t destMax, const char *format, ++ va_list argList) SECUREC_ATTRIBUTE(3, 0); ++#endif ++ ++#if SECUREC_ENABLE_SPRINTF ++/* ++ * Description: The sprintf_s function is equivalent to the sprintf function except for the parameter destMax ++ * and the explicit runtime-constraints violation ++ * Parameter: strDest - produce output according to a format ,write to the character string strDest. ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') ++ * Parameter: format - format string ++ * Return: the number of characters printed(not including the terminating null byte '\0'), ++ * If an error occurred Return: -1. ++*/ ++SECUREC_API int sprintf_s(char *strDest, size_t destMax, const char *format, ...) SECUREC_ATTRIBUTE(3, 4); ++#endif ++ ++#if SECUREC_ENABLE_VSNPRINTF ++/* ++ * Description: The vsnprintf_s function is equivalent to the vsnprintf function except for ++ * the parameter destMax/count and the explicit runtime-constraints violation ++ * Parameter: strDest - produce output according to a format ,write to the character string strDest. ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') ++ * Parameter: count - do not write more than count bytes to strDest(not including the terminating null byte '\0') ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of characters printed(not including the terminating null byte '\0'), ++ * If an error occurred Return: -1.Pay special attention to returning -1 when truncation occurs. ++ */ ++SECUREC_API int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, ++ va_list argList) SECUREC_ATTRIBUTE(4, 0); ++#endif ++ ++#if SECUREC_ENABLE_SNPRINTF ++/* ++ * Description: The snprintf_s function is equivalent to the snprintf function except for ++ * the parameter destMax/count and the explicit runtime-constraints violation ++ * Parameter: strDest - produce output according to a format ,write to the character string strDest. ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') ++ * Parameter: count - do not write more than count bytes to strDest(not including the terminating null byte '\0') ++ * Parameter: format - format string ++ * Return: the number of characters printed(not including the terminating null byte '\0'), ++ * If an error occurred Return: -1.Pay special attention to returning -1 when truncation occurs. ++ */ ++SECUREC_API int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, ++ ...) SECUREC_ATTRIBUTE(4, 5); ++#endif ++ ++#if SECUREC_SNPRINTF_TRUNCATED ++/* ++ * Description: The vsnprintf_truncated_s function is equivalent to the vsnprintf_s function except ++ * no count parameter and return value ++ * Parameter: strDest - produce output according to a format ,write to the character string strDest ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of characters printed(not including the terminating null byte '\0'), ++ * If an error occurred Return: -1.Pay special attention to returning destMax - 1 when truncation occurs ++*/ ++SECUREC_API int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, ++ va_list argList) SECUREC_ATTRIBUTE(3, 0); ++ ++/* ++ * Description: The snprintf_truncated_s function is equivalent to the snprintf_s function except ++ * no count parameter and return value ++ * Parameter: strDest - produce output according to a format,write to the character string strDest. ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null byte '\0') ++ * Parameter: format - format string ++ * Return: the number of characters printed(not including the terminating null byte '\0'), ++ * If an error occurred Return: -1.Pay special attention to returning destMax - 1 when truncation occurs. ++ */ ++SECUREC_API int snprintf_truncated_s(char *strDest, size_t destMax, ++ const char *format, ...) SECUREC_ATTRIBUTE(3, 4); ++#endif ++ ++#if SECUREC_ENABLE_SCANF ++/* ++ * Description: The scanf_s function is equivalent to fscanf_s with the argument stdin ++ * interposed before the arguments to scanf_s ++ * Parameter: format - format string ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int scanf_s(const char *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_VSCANF ++/* ++ * Description: The vscanf_s function is equivalent to scanf_s, with the variable argument list replaced by argList ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int vscanf_s(const char *format, va_list argList); ++#endif ++ ++#if SECUREC_ENABLE_SSCANF ++/* ++ * Description: The sscanf_s function is equivalent to fscanf_s, except that input is obtained from a ++ * string (specified by the argument buffer) rather than from a stream ++ * Parameter: buffer - read character from buffer ++ * Parameter: format - format string ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int sscanf_s(const char *buffer, const char *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_VSSCANF ++/* ++ * Description: The vsscanf_s function is equivalent to sscanf_s, with the variable argument list ++ * replaced by argList ++ * Parameter: buffer - read character from buffer ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int vsscanf_s(const char *buffer, const char *format, va_list argList); ++#endif ++ ++#if SECUREC_ENABLE_FSCANF ++/* ++ * Description: The fscanf_s function is equivalent to fscanf except that the c, s, and [ conversion specifiers ++ * apply to a pair of arguments (unless assignment suppression is indicated by a *) ++ * Parameter: stream - stdio file stream ++ * Parameter: format - format string ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int fscanf_s(FILE *stream, const char *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_VFSCANF ++/* ++ * Description: The vfscanf_s function is equivalent to fscanf_s, with the variable argument list ++ * replaced by argList ++ * Parameter: stream - stdio file stream ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int vfscanf_s(FILE *stream, const char *format, va_list argList); ++#endif ++ ++#if SECUREC_ENABLE_STRTOK ++/* ++ * Description: The strtok_s function parses a string into a sequence of strToken, ++ * replace all characters in strToken string that match to strDelimit set with 0. ++ * On the first call to strtok_s the string to be parsed should be specified in strToken. ++ * In each subsequent call that should parse the same string, strToken should be NULL ++ * Parameter: strToken - the string to be delimited ++ * Parameter: strDelimit - specifies a set of characters that delimit the tokens in the parsed string ++ * Parameter: context - is a pointer to a char * variable that is used internally by strtok_s function ++ * Return: On the first call returns the address of the first non \0 character, otherwise NULL is returned. ++ * In subsequent calls, the strtoken is set to NULL, and the context set is the same as the previous call, ++ * return NULL if the *context string length is equal 0, otherwise return *context. ++ */ ++SECUREC_API char *strtok_s(char *strToken, const char *strDelimit, char **context); ++#endif ++ ++#if SECUREC_ENABLE_GETS && !SECUREC_IN_KERNEL ++/* ++ * Description: The gets_s function reads at most one less than the number of characters specified ++ * by destMax from the stream pointed to by stdin, into the array pointed to by buffer ++ * Parameter: buffer - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null character) ++ * Return: buffer if there was no runtime-constraint violation,If an error occurred Return: NULL. ++ */ ++SECUREC_API char *gets_s(char *buffer, size_t destMax); ++#endif ++ ++#if SECUREC_ENABLE_WCHAR_FUNC ++#if SECUREC_ENABLE_MEMCPY ++/* ++ * Description: The wmemcpy_s function copies n successive wide characters from the object pointed to ++ * by src into the object pointed to by dest. ++ * Parameter: dest - destination address ++ * Parameter: destMax - The maximum length of destination buffer ++ * Parameter: src - source address ++ * Parameter: count - copies count wide characters from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t wmemcpy_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_MEMMOVE ++/* ++ * Description: The wmemmove_s function copies n successive wide characters from the object ++ * pointed to by src into the object pointed to by dest. ++ * Parameter: dest - destination address ++ * Parameter: destMax - The maximum length of destination buffer ++ * Parameter: src - source address ++ * Parameter: count - copies count wide characters from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t wmemmove_s(wchar_t *dest, size_t destMax, const wchar_t *src, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_STRCPY ++/* ++ * Description: The wcscpy_s function copies the wide string pointed to by strSrc(including the terminating ++ * null wide character) into the array pointed to by strDest ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer ++ * Parameter: strSrc - source address ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t wcscpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); ++#endif ++ ++#if SECUREC_ENABLE_STRNCPY ++/* ++ * Description: The wcsncpy_s function copies not more than n successive wide characters (not including the ++ * terminating null wide character) from the array pointed to by strSrc to the array pointed to by strDest ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) ++ * Parameter: strSrc - source address ++ * Parameter: count - copies count wide characters from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t wcsncpy_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_STRCAT ++/* ++ * Description: The wcscat_s function appends a copy of the wide string pointed to by strSrc (including the ++ * terminating null wide character) to the end of the wide string pointed to by strDest ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) ++ * Parameter: strSrc - source address ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t wcscat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc); ++#endif ++ ++#if SECUREC_ENABLE_STRNCAT ++/* ++ * Description: The wcsncat_s function appends not more than n successive wide characters (not including the ++ * terminating null wide character) from the array pointed to by strSrc to the end of the wide string pointed to ++ * by strDest. ++ * Parameter: strDest - destination address ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating wide character) ++ * Parameter: strSrc - source address ++ * Parameter: count - copies count wide characters from the src ++ * Return: EOK if there was no runtime-constraint violation ++ */ ++SECUREC_API errno_t wcsncat_s(wchar_t *strDest, size_t destMax, const wchar_t *strSrc, size_t count); ++#endif ++ ++#if SECUREC_ENABLE_STRTOK ++/* ++ * Description: The wcstok_s function is the wide-character equivalent of the strtok_s function ++ * Parameter: strToken - the string to be delimited ++ * Parameter: strDelimit - specifies a set of characters that delimit the tokens in the parsed string ++ * Parameter: context - is a pointer to a char * variable that is used internally by strtok_s function ++ * Return: a pointer to the first character of a token, or a null pointer if there is no token ++ * or there is a runtime-constraint violation. ++ */ ++SECUREC_API wchar_t *wcstok_s(wchar_t *strToken, const wchar_t *strDelimit, wchar_t **context); ++#endif ++ ++#if SECUREC_ENABLE_VSPRINTF ++/* ++ * Description: The vswprintf_s function is the wide-character equivalent of the vsprintf_s function ++ * Parameter: strDest - produce output according to a format,write to the character string strDest ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null) ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of characters printed(not including the terminating null wide character), ++ * If an error occurred Return: -1. ++ */ ++SECUREC_API int vswprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, va_list argList); ++#endif ++ ++#if SECUREC_ENABLE_SPRINTF ++/* ++ * Description: The swprintf_s function is the wide-character equivalent of the sprintf_s function ++ * Parameter: strDest - produce output according to a format,write to the character string strDest ++ * Parameter: destMax - The maximum length of destination buffer(including the terminating null) ++ * Parameter: format - format string ++ * Return: the number of characters printed(not including the terminating null wide character), ++ * If an error occurred Return: -1. ++ */ ++SECUREC_API int swprintf_s(wchar_t *strDest, size_t destMax, const wchar_t *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_FSCANF ++/* ++ * Description: The fwscanf_s function is the wide-character equivalent of the fscanf_s function ++ * Parameter: stream - stdio file stream ++ * Parameter: format - format string ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int fwscanf_s(FILE *stream, const wchar_t *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_VFSCANF ++/* ++ * Description: The vfwscanf_s function is the wide-character equivalent of the vfscanf_s function ++ * Parameter: stream - stdio file stream ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int vfwscanf_s(FILE *stream, const wchar_t *format, va_list argList); ++#endif ++ ++#if SECUREC_ENABLE_SCANF ++/* ++ * Description: The wscanf_s function is the wide-character equivalent of the scanf_s function ++ * Parameter: format - format string ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int wscanf_s(const wchar_t *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_VSCANF ++/* ++ * Description: The vwscanf_s function is the wide-character equivalent of the vscanf_s function ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int vwscanf_s(const wchar_t *format, va_list argList); ++#endif ++ ++#if SECUREC_ENABLE_SSCANF ++/* ++ * Description: The swscanf_s function is the wide-character equivalent of the sscanf_s function ++ * Parameter: buffer - read character from buffer ++ * Parameter: format - format string ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int swscanf_s(const wchar_t *buffer, const wchar_t *format, ...); ++#endif ++ ++#if SECUREC_ENABLE_VSSCANF ++/* ++ * Description: The vswscanf_s function is the wide-character equivalent of the vsscanf_s function ++ * Parameter: buffer - read character from buffer ++ * Parameter: format - format string ++ * Parameter: argList - instead of a variable number of arguments ++ * Return: the number of input items assigned, If an error occurred Return: -1. ++ */ ++SECUREC_API int vswscanf_s(const wchar_t *buffer, const wchar_t *format, va_list argList); ++#endif ++#endif /* SECUREC_ENABLE_WCHAR_FUNC */ ++#endif ++ ++/* Those functions are used by macro,must declare hare, also for without function declaration warning */ ++extern errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count); ++extern errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc); ++ ++#if SECUREC_WITH_PERFORMANCE_ADDONS ++/* Those functions are used by macro */ ++extern errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count); ++extern errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count); ++extern errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count); ++extern errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count); ++ ++/* The strcpy_sp is a macro, not a function in performance optimization mode. */ ++#define strcpy_sp(dest, destMax, src) ((__builtin_constant_p((destMax)) && \ ++ __builtin_constant_p((src))) ? \ ++ SECUREC_STRCPY_SM((dest), (destMax), (src)) : \ ++ strcpy_s((dest), (destMax), (src))) ++ ++/* The strncpy_sp is a macro, not a function in performance optimization mode. */ ++#define strncpy_sp(dest, destMax, src, count) ((__builtin_constant_p((count)) && \ ++ __builtin_constant_p((destMax)) && \ ++ __builtin_constant_p((src))) ? \ ++ SECUREC_STRNCPY_SM((dest), (destMax), (src), (count)) : \ ++ strncpy_s((dest), (destMax), (src), (count))) ++ ++/* The strcat_sp is a macro, not a function in performance optimization mode. */ ++#define strcat_sp(dest, destMax, src) ((__builtin_constant_p((destMax)) && \ ++ __builtin_constant_p((src))) ? \ ++ SECUREC_STRCAT_SM((dest), (destMax), (src)) : \ ++ strcat_s((dest), (destMax), (src))) ++ ++/* The strncat_sp is a macro, not a function in performance optimization mode. */ ++#define strncat_sp(dest, destMax, src, count) ((__builtin_constant_p((count)) && \ ++ __builtin_constant_p((destMax)) && \ ++ __builtin_constant_p((src))) ? \ ++ SECUREC_STRNCAT_SM((dest), (destMax), (src), (count)) : \ ++ strncat_s((dest), (destMax), (src), (count))) ++ ++/* The memcpy_sp is a macro, not a function in performance optimization mode. */ ++#define memcpy_sp(dest, destMax, src, count) (__builtin_constant_p((count)) ? \ ++ (SECUREC_MEMCPY_SM((dest), (destMax), (src), (count))) : \ ++ (__builtin_constant_p((destMax)) ? \ ++ (((size_t)(destMax) > 0 && \ ++ (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_MEM_MAX_LEN)) ? \ ++ memcpy_sOptTc((dest), (destMax), (src), (count)) : ERANGE) : \ ++ memcpy_sOptAsm((dest), (destMax), (src), (count)))) ++ ++/* The memset_sp is a macro, not a function in performance optimization mode. */ ++#define memset_sp(dest, destMax, c, count) (__builtin_constant_p((count)) ? \ ++ (SECUREC_MEMSET_SM((dest), (destMax), (c), (count))) : \ ++ (__builtin_constant_p((destMax)) ? \ ++ (((((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_MEM_MAX_LEN)) ? \ ++ memset_sOptTc((dest), (destMax), (c), (count)) : ERANGE) : \ ++ memset_sOptAsm((dest), (destMax), (c), (count)))) ++ ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +diff --git a/include/linux/securectype.h b/include/linux/securectype.h +new file mode 100644 +index 000000000000..69e79c2f9013 +--- /dev/null ++++ b/include/linux/securectype.h +@@ -0,0 +1,585 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Define internal used macro and data type. The marco of SECUREC_ON_64BITS ++ * will be determined in this header file, which is a switch for part ++ * of code. Some macro are used to suppress warning by MS compiler. ++ * Create: 2014-02-25 ++ * Notes: User can change the value of SECUREC_STRING_MAX_LEN and SECUREC_MEM_MAX_LEN ++ * macro to meet their special need, but The maximum value should not exceed 2G. ++ */ ++/* ++ * [Standardize-exceptions]: Performance-sensitive ++ * [reason]: Strict parameter verification has been done before use ++ */ ++ ++#ifndef SECURECTYPE_H_A7BBB686_AADA_451B_B9F9_44DACDAE18A7 ++#define SECURECTYPE_H_A7BBB686_AADA_451B_B9F9_44DACDAE18A7 ++ ++#ifndef SECUREC_USING_STD_SECURE_LIB ++#if defined(_MSC_VER) && _MSC_VER >= 1400 ++#if defined(__STDC_WANT_SECURE_LIB__) && (!__STDC_WANT_SECURE_LIB__) ++/* Security functions have been provided since vs2005, default use of system library functions */ ++#define SECUREC_USING_STD_SECURE_LIB 0 ++#else ++#define SECUREC_USING_STD_SECURE_LIB 1 ++#endif ++#else ++#define SECUREC_USING_STD_SECURE_LIB 0 ++#endif ++#endif ++ ++/* Compatibility with older Secure C versions, shielding VC symbol redefinition warning */ ++#if defined(_MSC_VER) && (_MSC_VER >= 1400) && (!SECUREC_USING_STD_SECURE_LIB) ++#ifndef SECUREC_DISABLE_CRT_FUNC ++#define SECUREC_DISABLE_CRT_FUNC 1 ++#endif ++#ifndef SECUREC_DISABLE_CRT_IMP ++#define SECUREC_DISABLE_CRT_IMP 1 ++#endif ++#else /* MSC VER */ ++#ifndef SECUREC_DISABLE_CRT_FUNC ++#define SECUREC_DISABLE_CRT_FUNC 0 ++#endif ++#ifndef SECUREC_DISABLE_CRT_IMP ++#define SECUREC_DISABLE_CRT_IMP 0 ++#endif ++#endif ++ ++#if SECUREC_DISABLE_CRT_FUNC ++#ifdef __STDC_WANT_SECURE_LIB__ ++#undef __STDC_WANT_SECURE_LIB__ ++#endif ++#define __STDC_WANT_SECURE_LIB__ 0 ++#endif ++ ++#if SECUREC_DISABLE_CRT_IMP ++#ifdef _CRTIMP_ALTERNATIVE ++#undef _CRTIMP_ALTERNATIVE ++#endif ++#define _CRTIMP_ALTERNATIVE /* Comment Microsoft *_s function */ ++#endif ++ ++/* Compile in kernel under macro control */ ++#ifndef SECUREC_IN_KERNEL ++#ifdef __KERNEL__ ++#define SECUREC_IN_KERNEL 1 ++#else ++#define SECUREC_IN_KERNEL 0 ++#endif ++#endif ++ ++/* make kernel symbols of functions available to loadable modules */ ++#ifndef SECUREC_EXPORT_KERNEL_SYMBOL ++#if SECUREC_IN_KERNEL ++#define SECUREC_EXPORT_KERNEL_SYMBOL 1 ++#else ++#define SECUREC_EXPORT_KERNEL_SYMBOL 0 ++#endif ++#endif ++ ++#if SECUREC_IN_KERNEL ++#ifndef SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_SCANF_FILE 0 ++#endif ++#ifndef SECUREC_ENABLE_WCHAR_FUNC ++#define SECUREC_ENABLE_WCHAR_FUNC 0 ++#endif ++#else /* SECUREC_IN_KERNEL */ ++#ifndef SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_SCANF_FILE 1 ++#endif ++#ifndef SECUREC_ENABLE_WCHAR_FUNC ++#define SECUREC_ENABLE_WCHAR_FUNC 1 ++#endif ++#endif ++ ++/* Default secure function declaration, default declarations for non-standard functions */ ++#ifndef SECUREC_SNPRINTF_TRUNCATED ++#define SECUREC_SNPRINTF_TRUNCATED 1 ++#endif ++ ++#if SECUREC_USING_STD_SECURE_LIB ++#if defined(_MSC_VER) && _MSC_VER >= 1400 ++/* Declare secure functions that are not available in the VS compiler */ ++#ifndef SECUREC_ENABLE_MEMSET ++#define SECUREC_ENABLE_MEMSET 1 ++#endif ++/* VS 2005 have vsnprintf_s function */ ++#ifndef SECUREC_ENABLE_VSNPRINTF ++#define SECUREC_ENABLE_VSNPRINTF 0 ++#endif ++#ifndef SECUREC_ENABLE_SNPRINTF ++/* VS 2005 have vsnprintf_s function Adapt the snprintf_s of the security function */ ++#define snprintf_s _snprintf_s ++#define SECUREC_ENABLE_SNPRINTF 0 ++#endif ++/* Before VS 2010 do not have v functions */ ++#if _MSC_VER <= 1600 || defined(SECUREC_FOR_V_SCANFS) ++#ifndef SECUREC_ENABLE_VFSCANF ++#define SECUREC_ENABLE_VFSCANF 1 ++#endif ++#ifndef SECUREC_ENABLE_VSCANF ++#define SECUREC_ENABLE_VSCANF 1 ++#endif ++#ifndef SECUREC_ENABLE_VSSCANF ++#define SECUREC_ENABLE_VSSCANF 1 ++#endif ++#endif ++ ++#else /* MSC VER */ ++#ifndef SECUREC_ENABLE_MEMSET ++#define SECUREC_ENABLE_MEMSET 0 ++#endif ++#ifndef SECUREC_ENABLE_SNPRINTF ++#define SECUREC_ENABLE_SNPRINTF 0 ++#endif ++#ifndef SECUREC_ENABLE_VSNPRINTF ++#define SECUREC_ENABLE_VSNPRINTF 0 ++#endif ++#endif ++ ++#ifndef SECUREC_ENABLE_MEMMOVE ++#define SECUREC_ENABLE_MEMMOVE 0 ++#endif ++#ifndef SECUREC_ENABLE_MEMCPY ++#define SECUREC_ENABLE_MEMCPY 0 ++#endif ++#ifndef SECUREC_ENABLE_STRCPY ++#define SECUREC_ENABLE_STRCPY 0 ++#endif ++#ifndef SECUREC_ENABLE_STRNCPY ++#define SECUREC_ENABLE_STRNCPY 0 ++#endif ++#ifndef SECUREC_ENABLE_STRCAT ++#define SECUREC_ENABLE_STRCAT 0 ++#endif ++#ifndef SECUREC_ENABLE_STRNCAT ++#define SECUREC_ENABLE_STRNCAT 0 ++#endif ++#ifndef SECUREC_ENABLE_SPRINTF ++#define SECUREC_ENABLE_SPRINTF 0 ++#endif ++#ifndef SECUREC_ENABLE_VSPRINTF ++#define SECUREC_ENABLE_VSPRINTF 0 ++#endif ++#ifndef SECUREC_ENABLE_SSCANF ++#define SECUREC_ENABLE_SSCANF 0 ++#endif ++#ifndef SECUREC_ENABLE_VSSCANF ++#define SECUREC_ENABLE_VSSCANF 0 ++#endif ++#ifndef SECUREC_ENABLE_SCANF ++#define SECUREC_ENABLE_SCANF 0 ++#endif ++#ifndef SECUREC_ENABLE_VSCANF ++#define SECUREC_ENABLE_VSCANF 0 ++#endif ++ ++#ifndef SECUREC_ENABLE_FSCANF ++#define SECUREC_ENABLE_FSCANF 0 ++#endif ++#ifndef SECUREC_ENABLE_VFSCANF ++#define SECUREC_ENABLE_VFSCANF 0 ++#endif ++#ifndef SECUREC_ENABLE_STRTOK ++#define SECUREC_ENABLE_STRTOK 0 ++#endif ++#ifndef SECUREC_ENABLE_GETS ++#define SECUREC_ENABLE_GETS 0 ++#endif ++ ++#else /* SECUREC USE STD SECURE LIB */ ++ ++#ifndef SECUREC_ENABLE_MEMSET ++#define SECUREC_ENABLE_MEMSET 1 ++#endif ++#ifndef SECUREC_ENABLE_MEMMOVE ++#define SECUREC_ENABLE_MEMMOVE 1 ++#endif ++#ifndef SECUREC_ENABLE_MEMCPY ++#define SECUREC_ENABLE_MEMCPY 1 ++#endif ++#ifndef SECUREC_ENABLE_STRCPY ++#define SECUREC_ENABLE_STRCPY 1 ++#endif ++#ifndef SECUREC_ENABLE_STRNCPY ++#define SECUREC_ENABLE_STRNCPY 1 ++#endif ++#ifndef SECUREC_ENABLE_STRCAT ++#define SECUREC_ENABLE_STRCAT 1 ++#endif ++#ifndef SECUREC_ENABLE_STRNCAT ++#define SECUREC_ENABLE_STRNCAT 1 ++#endif ++#ifndef SECUREC_ENABLE_SPRINTF ++#define SECUREC_ENABLE_SPRINTF 1 ++#endif ++#ifndef SECUREC_ENABLE_VSPRINTF ++#define SECUREC_ENABLE_VSPRINTF 1 ++#endif ++#ifndef SECUREC_ENABLE_SNPRINTF ++#define SECUREC_ENABLE_SNPRINTF 1 ++#endif ++#ifndef SECUREC_ENABLE_VSNPRINTF ++#define SECUREC_ENABLE_VSNPRINTF 1 ++#endif ++#ifndef SECUREC_ENABLE_SSCANF ++#define SECUREC_ENABLE_SSCANF 1 ++#endif ++#ifndef SECUREC_ENABLE_VSSCANF ++#define SECUREC_ENABLE_VSSCANF 1 ++#endif ++#ifndef SECUREC_ENABLE_SCANF ++#if SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_SCANF 1 ++#else ++#define SECUREC_ENABLE_SCANF 0 ++#endif ++#endif ++#ifndef SECUREC_ENABLE_VSCANF ++#if SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_VSCANF 1 ++#else ++#define SECUREC_ENABLE_VSCANF 0 ++#endif ++#endif ++ ++#ifndef SECUREC_ENABLE_FSCANF ++#if SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_FSCANF 1 ++#else ++#define SECUREC_ENABLE_FSCANF 0 ++#endif ++#endif ++#ifndef SECUREC_ENABLE_VFSCANF ++#if SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_VFSCANF 1 ++#else ++#define SECUREC_ENABLE_VFSCANF 0 ++#endif ++#endif ++ ++#ifndef SECUREC_ENABLE_STRTOK ++#define SECUREC_ENABLE_STRTOK 1 ++#endif ++#ifndef SECUREC_ENABLE_GETS ++#define SECUREC_ENABLE_GETS 1 ++#endif ++#endif /* SECUREC_USE_STD_SECURE_LIB */ ++ ++#if !SECUREC_ENABLE_SCANF_FILE ++#if SECUREC_ENABLE_FSCANF ++#undef SECUREC_ENABLE_FSCANF ++#define SECUREC_ENABLE_FSCANF 0 ++#endif ++#if SECUREC_ENABLE_VFSCANF ++#undef SECUREC_ENABLE_VFSCANF ++#define SECUREC_ENABLE_VFSCANF 0 ++#endif ++#if SECUREC_ENABLE_SCANF ++#undef SECUREC_ENABLE_SCANF ++#define SECUREC_ENABLE_SCANF 0 ++#endif ++#if SECUREC_ENABLE_FSCANF ++#undef SECUREC_ENABLE_FSCANF ++#define SECUREC_ENABLE_FSCANF 0 ++#endif ++ ++#endif ++ ++#if SECUREC_IN_KERNEL ++#include ++#include ++#else ++#ifndef SECUREC_HAVE_STDIO_H ++#define SECUREC_HAVE_STDIO_H 1 ++#endif ++#ifndef SECUREC_HAVE_STRING_H ++#define SECUREC_HAVE_STRING_H 1 ++#endif ++#ifndef SECUREC_HAVE_STDLIB_H ++#define SECUREC_HAVE_STDLIB_H 1 ++#endif ++#if SECUREC_HAVE_STDIO_H ++#include ++#endif ++#if SECUREC_HAVE_STRING_H ++#include ++#endif ++#if SECUREC_HAVE_STDLIB_H ++#include ++#endif ++#endif ++ ++/* ++ * If you need high performance, enable the SECUREC_WITH_PERFORMANCE_ADDONS macro, default is enable. ++ * The macro is automatically closed on the windows platform and linux kernel ++ */ ++#ifndef SECUREC_WITH_PERFORMANCE_ADDONS ++#if SECUREC_IN_KERNEL ++#define SECUREC_WITH_PERFORMANCE_ADDONS 0 ++#else ++#define SECUREC_WITH_PERFORMANCE_ADDONS 1 ++#endif ++#endif ++ ++/* If enable SECUREC_COMPATIBLE_WIN_FORMAT, the output format will be compatible to Windows. */ ++#if (defined(_WIN32) || defined(_WIN64) || defined(_MSC_VER)) && !defined(SECUREC_COMPATIBLE_LINUX_FORMAT) ++#ifndef SECUREC_COMPATIBLE_WIN_FORMAT ++#define SECUREC_COMPATIBLE_WIN_FORMAT ++#endif ++#endif ++ ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++/* On windows platform, can't use optimized function for there is no __builtin_constant_p like function */ ++/* If need optimized macro, can define this: define __builtin_constant_p(x) 0 */ ++#ifdef SECUREC_WITH_PERFORMANCE_ADDONS ++#undef SECUREC_WITH_PERFORMANCE_ADDONS ++#define SECUREC_WITH_PERFORMANCE_ADDONS 0 ++#endif ++#endif ++ ++#if defined(__VXWORKS__) || defined(__vxworks) || defined(__VXWORKS) || defined(_VXWORKS_PLATFORM_) || \ ++ defined(SECUREC_VXWORKS_VERSION_5_4) ++#ifndef SECUREC_VXWORKS_PLATFORM ++#define SECUREC_VXWORKS_PLATFORM ++#endif ++#endif ++ ++/* If enable SECUREC_COMPATIBLE_LINUX_FORMAT, the output format will be compatible to Linux. */ ++#if !defined(SECUREC_COMPATIBLE_WIN_FORMAT) && !defined(SECUREC_VXWORKS_PLATFORM) ++#ifndef SECUREC_COMPATIBLE_LINUX_FORMAT ++#define SECUREC_COMPATIBLE_LINUX_FORMAT ++#endif ++#endif ++ ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++#ifndef SECUREC_HAVE_STDDEF_H ++#define SECUREC_HAVE_STDDEF_H 1 ++#endif ++/* Some system may no stddef.h */ ++#if SECUREC_HAVE_STDDEF_H ++#if !SECUREC_IN_KERNEL ++#include ++#endif ++#endif ++#endif ++ ++/* ++ * Add the -DSECUREC_SUPPORT_FORMAT_WARNING=1 compiler option to supoort -Wformat=2. ++ * Default does not check the format is that the same data type in the actual code. ++ * In the product is different in the original data type definition of VxWorks and Linux. ++ */ ++#ifndef SECUREC_SUPPORT_FORMAT_WARNING ++#define SECUREC_SUPPORT_FORMAT_WARNING 0 ++#endif ++ ++#if SECUREC_SUPPORT_FORMAT_WARNING ++#define SECUREC_ATTRIBUTE(x, y) __attribute__((format(printf, (x), (y)))) ++#else ++#define SECUREC_ATTRIBUTE(x, y) ++#endif ++ ++/* ++ * Add the -DSECUREC_SUPPORT_BUILTIN_EXPECT=0 compiler option, if compiler can not support __builtin_expect. ++ */ ++#ifndef SECUREC_SUPPORT_BUILTIN_EXPECT ++#define SECUREC_SUPPORT_BUILTIN_EXPECT 1 ++#endif ++ ++#if SECUREC_SUPPORT_BUILTIN_EXPECT && defined(__GNUC__) && ((__GNUC__ > 3) || \ ++ (defined(__GNUC_MINOR__) && (__GNUC__ == 3 && __GNUC_MINOR__ > 3))) ++/* ++ * This is a built-in function that can be used without a declaration, if warning for declaration not found occurred, ++ * you can add -DSECUREC_NEED_BUILTIN_EXPECT_DECLARE to compiler options ++ */ ++#ifdef SECUREC_NEED_BUILTIN_EXPECT_DECLARE ++long __builtin_expect(long exp, long c); ++#endif ++ ++#define SECUREC_LIKELY(x) __builtin_expect(!!(x), 1) ++#define SECUREC_UNLIKELY(x) __builtin_expect(!!(x), 0) ++#else ++#define SECUREC_LIKELY(x) (x) ++#define SECUREC_UNLIKELY(x) (x) ++#endif ++ ++/* Define the max length of the string */ ++#ifndef SECUREC_STRING_MAX_LEN ++#define SECUREC_STRING_MAX_LEN 0x7fffffffUL ++#endif ++#define SECUREC_WCHAR_STRING_MAX_LEN (SECUREC_STRING_MAX_LEN / sizeof(wchar_t)) ++ ++/* Add SECUREC_MEM_MAX_LEN for memcpy and memmove */ ++#ifndef SECUREC_MEM_MAX_LEN ++#define SECUREC_MEM_MAX_LEN 0x7fffffffUL ++#endif ++#define SECUREC_WCHAR_MEM_MAX_LEN (SECUREC_MEM_MAX_LEN / sizeof(wchar_t)) ++ ++#if SECUREC_STRING_MAX_LEN > 0x7fffffffUL ++#error "max string is 2G" ++#endif ++ ++#if (defined(__GNUC__) && defined(__SIZEOF_POINTER__)) ++#if (__SIZEOF_POINTER__ != 4) && (__SIZEOF_POINTER__ != 8) ++#error "unsupported system" ++#endif ++#endif ++ ++#if defined(_WIN64) || defined(WIN64) || defined(__LP64__) || defined(_LP64) ++#define SECUREC_ON_64BITS ++#endif ++ ++#if (!defined(SECUREC_ON_64BITS) && defined(__GNUC__) && defined(__SIZEOF_POINTER__)) ++#if __SIZEOF_POINTER__ == 8 ++#define SECUREC_ON_64BITS ++#endif ++#endif ++ ++#if defined(__SVR4) || defined(__svr4__) ++#define SECUREC_ON_SOLARIS ++#endif ++ ++#if (defined(__hpux) || defined(_AIX) || defined(SECUREC_ON_SOLARIS)) ++#define SECUREC_ON_UNIX ++#endif ++ ++/* ++ * Codes should run under the macro SECUREC_COMPATIBLE_LINUX_FORMAT in unknown system on default, ++ * and strtold. ++ * The function strtold is referenced first at ISO9899:1999(C99), and some old compilers can ++ * not support these functions. Here provides a macro to open these functions: ++ * SECUREC_SUPPORT_STRTOLD -- If defined, strtold will be used ++ */ ++#ifndef SECUREC_SUPPORT_STRTOLD ++#define SECUREC_SUPPORT_STRTOLD 0 ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) ++#if defined(__USE_ISOC99) || \ ++ (defined(_AIX) && defined(_ISOC99_SOURCE)) || \ ++ (defined(__hpux) && defined(__ia64)) || \ ++ (defined(SECUREC_ON_SOLARIS) && (!defined(_STRICT_STDC) && !defined(__XOPEN_OR_POSIX)) || \ ++ defined(_STDC_C99) || defined(__EXTENSIONS__)) ++#undef SECUREC_SUPPORT_STRTOLD ++#define SECUREC_SUPPORT_STRTOLD 1 ++#endif ++#endif ++#if ((defined(SECUREC_WRLINUX_BELOW4) || defined(_WRLINUX_BELOW4_))) ++#undef SECUREC_SUPPORT_STRTOLD ++#define SECUREC_SUPPORT_STRTOLD 0 ++#endif ++#endif ++ ++#if SECUREC_WITH_PERFORMANCE_ADDONS ++ ++#ifndef SECUREC_TWO_MIN ++#define SECUREC_TWO_MIN(a, b) ((a) < (b) ? (a) : (b)) ++#endif ++ ++/* For strncpy_s performance optimization */ ++#define SECUREC_STRNCPY_SM(dest, destMax, src, count) \ ++ (((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ ++ (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ ++ (SECUREC_TWO_MIN((size_t)(count), strlen(src)) + 1) <= (size_t)(destMax)) ? \ ++ (((size_t)(count) < strlen(src)) ? (memcpy((dest), (src), (count)), *((char *)(dest) + (count)) = '\0', EOK) : \ ++ (memcpy((dest), (src), strlen(src) + 1), EOK)) : (strncpy_error((dest), (destMax), (src), (count)))) ++ ++#define SECUREC_STRCPY_SM(dest, destMax, src) \ ++ (((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ ++ (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ ++ (strlen(src) + 1) <= (size_t)(destMax)) ? (memcpy((dest), (src), strlen(src) + 1), EOK) : \ ++ (strcpy_error((dest), (destMax), (src)))) ++ ++/* For strcat_s performance optimization */ ++#if defined(__GNUC__) ++#define SECUREC_STRCAT_SM(dest, destMax, src) ({ \ ++ int catRet_ = EOK; \ ++ if ((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ ++ (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN)) { \ ++ char *catTmpDst_ = (char *)(dest); \ ++ size_t catRestSize_ = (destMax); \ ++ while (catRestSize_ > 0 && *catTmpDst_ != '\0') { \ ++ ++catTmpDst_; \ ++ --catRestSize_; \ ++ } \ ++ if (catRestSize_ == 0) { \ ++ catRet_ = EINVAL; \ ++ } else if ((strlen(src) + 1) <= catRestSize_) { \ ++ memcpy(catTmpDst_, (src), strlen(src) + 1); \ ++ catRet_ = EOK; \ ++ } else { \ ++ catRet_ = ERANGE; \ ++ } \ ++ if (catRet_ != EOK) { \ ++ catRet_ = strcat_s((dest), (destMax), (src)); \ ++ } \ ++ } else { \ ++ catRet_ = strcat_s((dest), (destMax), (src)); \ ++ } \ ++ catRet_; \ ++}) ++#else ++#define SECUREC_STRCAT_SM(dest, destMax, src) strcat_s((dest), (destMax), (src)) ++#endif ++ ++/* For strncat_s performance optimization */ ++#if defined(__GNUC__) ++#define SECUREC_STRNCAT_SM(dest, destMax, src, count) ({ \ ++ int ncatRet_ = EOK; \ ++ if ((void *)(dest) != NULL && (const void *)(src) != NULL && (size_t)(destMax) > 0 && \ ++ (((unsigned long long)(destMax) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN) && \ ++ (((unsigned long long)(count) & (unsigned long long)(-2)) < SECUREC_STRING_MAX_LEN)) { \ ++ char *ncatTmpDest_ = (char *)(dest); \ ++ size_t ncatRestSize_ = (size_t)(destMax); \ ++ while (ncatRestSize_ > 0 && *ncatTmpDest_ != '\0') { \ ++ ++ncatTmpDest_; \ ++ --ncatRestSize_; \ ++ } \ ++ if (ncatRestSize_ == 0) { \ ++ ncatRet_ = EINVAL; \ ++ } else if ((SECUREC_TWO_MIN((count), strlen(src)) + 1) <= ncatRestSize_) { \ ++ if ((size_t)(count) < strlen(src)) { \ ++ memcpy(ncatTmpDest_, (src), (count)); \ ++ *(ncatTmpDest_ + (count)) = '\0'; \ ++ } else { \ ++ memcpy(ncatTmpDest_, (src), strlen(src) + 1); \ ++ } \ ++ } else { \ ++ ncatRet_ = ERANGE; \ ++ } \ ++ if (ncatRet_ != EOK) { \ ++ ncatRet_ = strncat_s((dest), (destMax), (src), (count)); \ ++ } \ ++ } else { \ ++ ncatRet_ = strncat_s((dest), (destMax), (src), (count)); \ ++ } \ ++ ncatRet_; \ ++}) ++#else ++#define SECUREC_STRNCAT_SM(dest, destMax, src, count) strncat_s((dest), (destMax), (src), (count)) ++#endif ++ ++/* This macro do not check buffer overlap by default */ ++#define SECUREC_MEMCPY_SM(dest, destMax, src, count) \ ++ (!(((size_t)(destMax) == 0) || \ ++ (((unsigned long long)(destMax) & (unsigned long long)(-2)) > SECUREC_MEM_MAX_LEN) || \ ++ ((size_t)(count) > (size_t)(destMax)) || ((void *)(dest)) == NULL || ((const void *)(src) == NULL)) ? \ ++ (memcpy((dest), (src), (count)), EOK) : \ ++ (memcpy_s((dest), (destMax), (src), (count)))) ++ ++#define SECUREC_MEMSET_SM(dest, destMax, c, count) \ ++ (!((((unsigned long long)(destMax) & (unsigned long long)(-2)) > SECUREC_MEM_MAX_LEN) || \ ++ ((void *)(dest) == NULL) || ((size_t)(count) > (size_t)(destMax))) ? \ ++ (memset((dest), (c), (count)), EOK) : \ ++ (memset_s((dest), (destMax), (c), (count)))) ++ ++#endif ++#endif ++ +diff --git a/include/linux/vendor/peri_io.h b/include/linux/vendor/peri_io.h +new file mode 100644 +index 000000000000..6b0c8f255b2c +--- /dev/null ++++ b/include/linux/vendor/peri_io.h +@@ -0,0 +1,57 @@ ++/* ++ * Copyright (c) 2022-2022 Shenshu Technologies Co., Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#ifndef __PERIPH_IO_H ++#define __PERIPH_IO_H ++ ++#include ++#include ++ ++enum bsp_peri_type { ++ BSP_PERI_NONE = 0, ++ BSP_PERI_SDIO, ++ BSP_PERI_MMC, ++ BSP_PERI_USB, ++ BSP_PERI_SATA, ++ BSP_PERI_GMAC, ++ BSP_PERI_FMC, ++}; ++ ++unsigned long bsp_peri_lock(enum bsp_peri_type type); ++void bsp_peri_unlock(unsigned long flags, enum bsp_peri_type type); ++ ++static inline u32 bsp_peri_readl(const volatile void __iomem *addr, ++ enum bsp_peri_type type) ++{ ++ u32 val; ++ unsigned long flags; ++ flags = bsp_peri_lock(type); ++ val = readl(addr); ++ bsp_peri_unlock(flags, type); ++ return val; ++} ++ ++static inline void bsp_peri_writel(u32 val, volatile void __iomem *addr, ++ enum bsp_peri_type type) ++{ ++ unsigned long flags; ++ flags = bsp_peri_lock(type); ++ writel(val, addr); ++ bsp_peri_unlock(flags, type); ++} ++ ++#endif /* __PERIPH_IO_H */ +diff --git a/include/linux/vendor/sva_ext.h b/include/linux/vendor/sva_ext.h +new file mode 100644 +index 000000000000..130e45f0b3c9 +--- /dev/null ++++ b/include/linux/vendor/sva_ext.h +@@ -0,0 +1,93 @@ ++/* ++* ++* Copyright (c) 2020-2021 Shenshu Technologies Co., Ltd. ++* ++* This software is licensed under the terms of the GNU General Public ++* License version 2, as published by the Free Software Foundation, and ++* may be copied, distributed, and modified under those terms. ++* ++* This program is distributed in the hope that it will be useful, ++* but WITHOUT ANY WARRANTY; without even the implied warranty of ++* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++* GNU General Public License for more details. ++* ++*/ ++ ++#ifndef _SVA_EXTEND_H ++#define _SVA_EXTEND_H ++ ++#ifdef CONFIG_VENDOR_NPU ++ ++extern void iommu_sva_flush_iotlb_single(struct mm_struct *mm); ++ ++extern const char *iommu_sva_get_smmu_device_name(struct mm_struct *mm); ++ ++extern int arm_smmu_device_post_probe(const char *device_name); ++ ++extern int arm_smmu_device_resume(const char *device_name); ++ ++extern int arm_smmu_device_suspend(const char *device_name); ++ ++extern int arm_smmu_device_reset_ex(const char *device_name); ++ ++extern const char *arm_smmu_get_device_name(struct iommu_domain *domain); ++ ++extern int svm_flush_cache(struct mm_struct *mm, unsigned long addr, size_t size); ++ ++extern void svm_smmu_clk_live_enter(void); ++extern void svm_smmu_clk_live_exit(void); ++ ++#else ++static inline void iommu_sva_flush_iotlb_single(struct mm_struct *mm) ++{ ++ return; ++} ++ ++static inline const char *iommu_sva_get_smmu_device_name(struct mm_struct *mm) ++{ ++ return NULL; ++} ++ ++static inline int arm_smmu_device_post_probe(const char *device_name) ++{ ++ return -1; ++} ++ ++static inline int arm_smmu_device_resume(const char *device_name) ++{ ++ return -1; ++} ++ ++static inline int arm_smmu_device_suspend(const char *device_name) ++{ ++ return -1; ++} ++ ++static inline int arm_smmu_device_reset_ex(const char *device_name) ++{ ++ return -1; ++} ++ ++static const char *arm_smmu_get_device_name(struct iommu_domain *domain) ++{ ++ return NULL; ++} ++ ++static inline int svm_flush_cache(struct mm_struct *mm, unsigned long addr, size_t size) ++{ ++ return -1; ++} ++ ++static inline void svm_smmu_clk_live_enter(void) ++{ ++ return; ++} ++ ++static inline void svm_smmu_clk_live_exit(void) ++{ ++ return; ++} ++ ++#endif ++ ++#endif /* _SVA_EXTEND_H */ +diff --git a/include/uapi/linux/i2c-dev.h b/include/uapi/linux/i2c-dev.h +index 85f8047afcf2..3f50287f3289 100644 +--- a/include/uapi/linux/i2c-dev.h ++++ b/include/uapi/linux/i2c-dev.h +@@ -52,6 +52,8 @@ + #define I2C_PEC 0x0708 /* != 0 to use PEC with SMBus */ + #define I2C_SMBUS 0x0720 /* SMBus transfer */ + ++#define I2C_CONFIG_MUL_REG 0x070c ++#define I2C_CONFIG_FLAGS 0x070d + + /* This is the structure as used in the I2C_SMBUS ioctl call */ + struct i2c_smbus_ioctl_data { +diff --git a/include/uapi/linux/i2c.h b/include/uapi/linux/i2c.h +index f71a1751cacf..ff5eb36df35b 100644 +--- a/include/uapi/linux/i2c.h ++++ b/include/uapi/linux/i2c.h +@@ -81,6 +81,9 @@ struct i2c_msg { + #define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + #define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */ + #define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ ++#define I2C_M_16BIT_REG 0x0002 /* indicate reg bit-width is 16bit */ ++#define I2C_M_16BIT_DATA 0x0008 /* indicate data bit-width is 16bit */ ++#define I2C_M_DMA 0x0004 /* indicate use dma mode */ + __u16 len; /* msg length */ + __u8 *buf; /* pointer to msg data */ + }; +diff --git a/include/uapi/linux/usb/g_uvc.h b/include/uapi/linux/usb/g_uvc.h +index 652f169a019e..ce03ccc68e19 100644 +--- a/include/uapi/linux/usb/g_uvc.h ++++ b/include/uapi/linux/usb/g_uvc.h +@@ -34,6 +34,21 @@ struct uvc_event { + }; + }; + ++#if IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) ++struct uvc_pack { ++ uint64_t buf_vir_addr; ++ uint32_t buf_size; ++ uint64_t pack_vir_addr; ++ uint32_t pack_len; ++ void *private_data; ++ ++ void (*callback_func)(void *); ++ bool is_frame_end; ++}; ++ ++extern int uvc_recv_pack(struct uvc_pack *pack); ++#endif /* IS_ENABLED(CONFIG_MPP_TO_GADGET_UVC) */ ++ + #define UVCIOC_SEND_RESPONSE _IOW('U', 1, struct uvc_request_data) + + #endif /* __LINUX_USB_G_UVC_H */ +diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h +index bfdae12cdacf..5966a5b50419 100644 +--- a/include/uapi/linux/usb/video.h ++++ b/include/uapi/linux/usb/video.h +@@ -179,6 +179,36 @@ + #define UVC_CONTROL_CAP_AUTOUPDATE (1 << 3) + #define UVC_CONTROL_CAP_ASYNCHRONOUS (1 << 4) + ++/* 3.9.2.6 Color Matching Descriptor Values */ ++enum uvc_color_primaries_values { ++ UVC_COLOR_PRIMARIES_UNSPECIFIED, ++ UVC_COLOR_PRIMARIES_BT_709_SRGB, ++ UVC_COLOR_PRIMARIES_BT_470_2_M, ++ UVC_COLOR_PRIMARIES_BT_470_2_B_G, ++ UVC_COLOR_PRIMARIES_SMPTE_170M, ++ UVC_COLOR_PRIMARIES_SMPTE_240M, ++}; ++ ++enum uvc_transfer_characteristics_values { ++ UVC_TRANSFER_CHARACTERISTICS_UNSPECIFIED, ++ UVC_TRANSFER_CHARACTERISTICS_BT_709, ++ UVC_TRANSFER_CHARACTERISTICS_BT_470_2_M, ++ UVC_TRANSFER_CHARACTERISTICS_BT_470_2_B_G, ++ UVC_TRANSFER_CHARACTERISTICS_SMPTE_170M, ++ UVC_TRANSFER_CHARACTERISTICS_SMPTE_240M, ++ UVC_TRANSFER_CHARACTERISTICS_LINEAR, ++ UVC_TRANSFER_CHARACTERISTICS_SRGB, ++}; ++ ++enum uvc_matrix_coefficients { ++ UVC_MATRIX_COEFFICIENTS_UNSPECIFIED, ++ UVC_MATRIX_COEFFICIENTS_BT_709, ++ UVC_MATRIX_COEFFICIENTS_FCC, ++ UVC_MATRIX_COEFFICIENTS_BT_470_2_B_G, ++ UVC_MATRIX_COEFFICIENTS_SMPTE_170M, ++ UVC_MATRIX_COEFFICIENTS_SMPTE_240M, ++}; ++ + /* ------------------------------------------------------------------------ + * UVC structures + */ +@@ -342,6 +372,8 @@ struct UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) { \ + __u8 iExtension; \ + } __attribute__ ((packed)) + ++DECLARE_UVC_EXTENSION_UNIT_DESCRIPTOR(1,2); ++ + /* 3.8.2.2. Video Control Interrupt Endpoint Descriptor */ + struct uvc_control_endpoint_descriptor { + __u8 bLength; +@@ -567,5 +599,63 @@ struct UVC_FRAME_MJPEG(n) { \ + __le32 dwFrameInterval[n]; \ + } __attribute__ ((packed)) + ++/* 3.1.1 Frame Based Payload Video Format Descriptor */ ++struct uvc_frame_based_format_desc { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bFormatIndex; ++ __u8 bNumFrameDescriptors; ++ __u8 guidFormat[16]; ++ __u8 bBitsPerPixel; ++ __u8 bDefaultFrameIndex; ++ __u8 bAspectRatioX; ++ __u8 bAspectRatioY; ++ __u8 bmInterfaceFlags; ++ __u8 bCopyProtect; ++ __u8 bVariableSize; ++} __attribute__((__packed__)); ++ ++#define UVC_DT_FRAME_BASED_FORMAT_SIZE 28 ++ ++/* 3.1.2 Frame Based Payload Frame Descriptor */ ++struct uvc_frame_based_frame_desc { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDescriptorSubType; ++ __u8 bFrameIndex; ++ __u8 bmCapabilities; ++ __le16 wWidth; ++ __le16 wHeight; ++ __le32 dwMinBitRate; ++ __le32 dwMaxBitRate; ++ __le32 dwDefaultFrameInterval; ++ __u8 bFrameIntervalType; ++ __le32 dwBytesPerLine; ++ __le32 dwFrameInterval[]; ++} __attribute__((__packed__)); ++ ++#define UVC_DT_FRAME_BASED_FRAME_SIZE(n) (26+4*(n)) ++ ++#define UVC_FRAME_BASED(n) \ ++ uvc_frame_based_desc##n ++ ++#define DECLARE_UVC_FRAME_BASED(n) \ ++struct UVC_FRAME_BASED(n) { \ ++ __u8 bLength; \ ++ __u8 bDescriptorType; \ ++ __u8 bDescriptorSubType; \ ++ __u8 bFrameIndex; \ ++ __u8 bmCapabilities; \ ++ __le16 wWidth; \ ++ __le16 wHeight; \ ++ __le32 dwMinBitRate; \ ++ __le32 dwMaxBitRate; \ ++ __le32 dwDefaultFrameInterval; \ ++ __u8 bFrameIntervalType; \ ++ __le32 dwBytesPerLine; \ ++ __le32 dwFrameInterval[n]; \ ++} __attribute__ ((packed)) ++ + #endif /* __LINUX_USB_VIDEO_H */ + +diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h +index b28817c59fdf..0455da8fbacc 100644 +--- a/include/uapi/linux/videodev2.h ++++ b/include/uapi/linux/videodev2.h +@@ -705,6 +705,7 @@ struct v4l2_pix_format { + #define V4L2_PIX_FMT_HEVC v4l2_fourcc('H', 'E', 'V', 'C') /* HEVC aka H.265 */ + #define V4L2_PIX_FMT_FWHT v4l2_fourcc('F', 'W', 'H', 'T') /* Fast Walsh Hadamard Transform (vicodec) */ + #define V4L2_PIX_FMT_FWHT_STATELESS v4l2_fourcc('S', 'F', 'W', 'H') /* Stateless FWHT (vicodec) */ ++#define V4L2_PIX_FMT_H265 v4l2_fourcc('H', '2', '6', '5') /* H.265 aka HEVC */ + + /* Vendor-specific formats */ + #define V4L2_PIX_FMT_CPIA1 v4l2_fourcc('C', 'P', 'I', 'A') /* cpia1 YUV */ +diff --git a/kernel/Makefile b/kernel/Makefile +index 3ae3b70c46e8..45a3a6ec0ad0 100644 +--- a/kernel/Makefile ++++ b/kernel/Makefile +@@ -12,6 +12,8 @@ obj-y = fork.o exec_domain.o panic.o \ + notifier.o ksysfs.o cred.o reboot.o \ + async.o range.o smpboot.o ucount.o regset.o + ++obj-y += iprec.o ++ + obj-$(CONFIG_USERMODE_DRIVER) += usermode_driver.o + obj-$(CONFIG_MODULES) += kmod.o + obj-$(CONFIG_MULTIUSER) += groups.o +diff --git a/kernel/dma/contiguous.c b/kernel/dma/contiguous.c +index 16b95ff12e4d..bda1b952f9c7 100644 +--- a/kernel/dma/contiguous.c ++++ b/kernel/dma/contiguous.c +@@ -164,6 +164,11 @@ void __init dma_pernuma_cma_reserve(void) + * has been activated and all other subsystems have already allocated/reserved + * memory. + */ ++#ifdef CONFIG_ARCH_BSP ++#ifdef CONFIG_64BIT ++extern __init int declare_heap_memory(void); ++#endif ++#endif + void __init dma_contiguous_reserve(phys_addr_t limit) + { + phys_addr_t selected_size = 0; +@@ -173,6 +178,11 @@ void __init dma_contiguous_reserve(phys_addr_t limit) + + pr_debug("%s(limit %08lx)\n", __func__, (unsigned long)limit); + ++#ifdef CONFIG_ARCH_BSP ++#ifdef CONFIG_64BIT ++ declare_heap_memory(); ++#endif ++#endif + if (size_cmdline != -1) { + selected_size = size_cmdline; + selected_base = base_cmdline; +@@ -262,6 +272,9 @@ struct page *dma_alloc_from_contiguous(struct device *dev, size_t count, + + return cma_alloc(dev_get_cma_area(dev), count, align, no_warn); + } ++#ifdef CONFIG_ARCH_BSP ++EXPORT_SYMBOL(dma_alloc_from_contiguous); ++#endif + + /** + * dma_release_from_contiguous() - release allocated pages +@@ -278,6 +291,9 @@ bool dma_release_from_contiguous(struct device *dev, struct page *pages, + { + return cma_release(dev_get_cma_area(dev), pages, count); + } ++#ifdef CONFIG_ARCH_BSP ++EXPORT_SYMBOL(dma_release_from_contiguous); ++#endif + + static struct page *cma_alloc_aligned(struct cma *cma, size_t size, gfp_t gfp) + { +diff --git a/kernel/fork.c b/kernel/fork.c +index 2547c6a6e5b1..4faf2dd4cd33 100644 +--- a/kernel/fork.c ++++ b/kernel/fork.c +@@ -1038,6 +1038,13 @@ static void mm_init_uprobes_state(struct mm_struct *mm) + #endif + } + ++static void mm_init_pasid(struct mm_struct *mm) ++{ ++#ifdef CONFIG_IOMMU_SUPPORT ++ mm->pasid = INIT_PASID; ++#endif ++} ++ + static struct mm_struct *mm_init(struct mm_struct *mm, struct task_struct *p, + struct user_namespace *user_ns) + { +@@ -1063,6 +1070,7 @@ static struct mm_struct *mm_init(struct mm_struct *mm, struct task_struct *p, + mm_init_aio(mm); + mm_init_owner(mm, p); + mm_pasid_init(mm); ++ mm_init_pasid(mm); + RCU_INIT_POINTER(mm->exe_file, NULL); + mmu_notifier_subscriptions_init(mm); + init_tlb_flush_pending(mm); +diff --git a/kernel/iprec.c b/kernel/iprec.c +new file mode 100755 +index 000000000000..0650b335d6db +--- /dev/null ++++ b/kernel/iprec.c +@@ -0,0 +1,410 @@ ++/* ++ * iprec.c: Record any ip io transfer process to ++ * system memory. Reduce printk log latency ++ * or ftrace complexity. ++ * ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++ ++#define SEC_FOUR_DIGIT 10000 ++#define USEC_TO_MSEC 1000 ++#define TIME_STAMP_LEN 16 ++ ++static struct proc_dir_entry *iprec_proc; ++static int iprec_init = 0; ++static int iprec_proc_cnt = 0; ++static char tim[TIME_STAMP_LEN] = {0}; ++extern void iprec_inc(void); ++ ++static char **rec_pool = NULL; ++static int rec_lines = IPREC_DEFAULT_LINE; ++static int rec_delay = IPREC_DEFAULT_DLAY; ++static int rem_delay = -1; ++static int rec_lock = 0; ++static int rec_line = 0; ++static int rec_ovwr = 0; ++ ++ ++static spinlock_t rec_spinlock; ++ ++spinlock_t *iprec_spinlock(void) ++{ ++ return &rec_spinlock; ++} ++EXPORT_SYMBOL_GPL(iprec_spinlock); ++ ++void iprec_slock(void) ++{ ++ iprec("_SLOCK_"); ++ if (rec_delay == 0) ++ rec_lock = 1; ++ else ++ rem_delay = rec_delay; ++} ++EXPORT_SYMBOL_GPL(iprec_slock); ++ ++int iprec_glock(void) ++{ ++ return rec_lock; ++} ++EXPORT_SYMBOL_GPL(iprec_glock); ++ ++char *iprec_pool(void) ++{ ++ return (rec_pool[rec_line % rec_lines]); ++} ++EXPORT_SYMBOL_GPL(iprec_pool); ++ ++char *iprec_tm(void) ++{ ++ int ret; ++ struct timespec64 tv; ++ long s, ms, us; ++ ++ ktime_get_boottime_ts64(&tv); ++ ++ s = tv.tv_sec % SEC_FOUR_DIGIT; ++ ms = tv.tv_nsec / USEC_TO_MSEC / USEC_TO_MSEC; ++ us = tv.tv_nsec % (USEC_TO_MSEC * USEC_TO_MSEC) / USEC_TO_MSEC; ++ ++ ret = sprintf_s(tim, TIME_STAMP_LEN, "[%04ld.%03ld%03ld]", s, ms, us); ++ ++ if (ret < 0) { ++ pr_err("[%s line:%d] sprintf_s failed\n", __func__, __LINE__); ++ } ++ ++ return tim; ++} ++EXPORT_SYMBOL_GPL(iprec_tm); ++ ++void iprec_inc(void) ++{ ++ rec_line++; ++ rec_line %= rec_lines; ++ if (rec_line == 0) ++ rec_ovwr++; ++ ++ if (rec_delay) { ++ // check if lock is actived! ++ if (rem_delay > 0) { ++ rem_delay--; ++ } else if (rem_delay == 0) { /* set lock */ ++ rec_lock = 1; ++ rem_delay = -1; // lock is unactived! ++ } ++ } ++} ++EXPORT_SYMBOL_GPL(iprec_inc); ++ ++static void iprec_show(struct seq_file *s) ++{ ++ int i; ++ rec_lock = 1; ++ ++ seq_printf(s, "|__ ov: %d __|__ delay: %d __|\n\n", rec_ovwr, rec_delay); ++ ++ if (rec_ovwr == 0) { ++ for (i = 0; i < rec_line; i++) { ++ seq_printf(s, " %04d %s\n", (i + 1), rec_pool[i]); ++ } ++ } else { ++ for (i = rec_line; i < rec_lines; i++) { ++ seq_printf(s, " %04d %s\n", (i - rec_line + 1), rec_pool[i]); ++ } ++ ++ for (i = 0; i < rec_line; i++) { ++ seq_printf(s, " %04d %s\n", (i + rec_lines - rec_line + 1), ++ rec_pool[i]); ++ } ++ } ++ ++ seq_printf(s, "\n|__ ov: %d __|__ delay: %d __|\n", rec_ovwr, rec_delay); ++} ++ ++static void iprec_pool_free(char **pool) ++{ ++ int i; ++ ++ if (!pool) ++ return; ++ ++ for (i = 0; i < rec_lines; i++) { ++ if (pool[i]) ++ kfree(pool[i]); ++ } ++ kfree(pool); ++} ++ ++static char **iprec_pool_alloc(int lines) ++{ ++ int i; ++ char *mem = NULL; ++ char **pool = NULL; ++ ++ if (lines <= 0) ++ return NULL; ++ ++ pool = kmalloc(lines * sizeof(char *), GFP_KERNEL); ++ if (pool == NULL) { ++ pr_err("%s: no enough mem iprec %d\n", __func__, lines); ++ return NULL; ++ } ++ ++ for (i = 0; i < lines; i++) { ++ mem = kmalloc(IPREC_STR_LEN, GFP_KERNEL); ++ if (mem == NULL) ++ goto free_pool; ++ mem[0] = 0; ++ pool[i] = mem; ++ } ++ ++ return pool; ++ ++free_pool: ++ iprec_pool_free(pool); ++ ++ return NULL; ++} ++ ++static int iprec_dump_seq_show(struct seq_file *s, void *v) ++{ ++ iprec_show(s); ++ return 0; ++} ++ ++static int iprec_proc_dump_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, iprec_dump_seq_show, PDE_DATA(inode)); ++} ++ ++static const struct proc_ops iprec_dump_ops = { ++ .proc_open = iprec_proc_dump_open, ++ .proc_read = seq_read, ++ .proc_release = single_release, ++}; ++ ++static int iprec_line_seq_show(struct seq_file *s, void *v) ++{ ++ seq_printf(s, "%d (N x %dB)\n", rec_lines, IPREC_STR_LEN); ++ return 0; ++} ++ ++static int iprec_proc_line_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, iprec_line_seq_show, PDE_DATA(inode)); ++} ++ ++static ssize_t iprec_proc_line_write(struct file *file, ++ const char __user *buffer, size_t count, loff_t *pos) ++{ ++ int err; ++ unsigned long flags; ++ unsigned int val = 0; ++ char **pool = NULL; ++ ++ err = kstrtouint_from_user(buffer, count, 0, &val); ++ if (err) ++ return err; ++ ++ spin_lock_irqsave(iprec_spinlock(), flags); ++ ++ pool = iprec_pool_alloc(val); ++ if (pool) { ++ iprec_pool_free(rec_pool); ++ rec_pool = pool; ++ rec_lines = val; ++ rec_line = 0; // reset ++ } ++ spin_unlock_irqrestore(iprec_spinlock(), flags); ++ return count; ++} ++ ++static const struct proc_ops iprec_line_ops = { ++ .proc_open = iprec_proc_line_open, ++ .proc_read = seq_read, ++ .proc_write = iprec_proc_line_write, ++ .proc_release = single_release, ++}; ++ ++static int iprec_lock_seq_show(struct seq_file *s, void *v) ++{ ++ seq_printf(s, "%d\n", rec_lock); ++ return 0; ++} ++ ++static int iprec_proc_lock_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, iprec_lock_seq_show, PDE_DATA(inode)); ++} ++ ++static ssize_t iprec_proc_lock_write(struct file *file, ++ const char __user *buffer, size_t count, loff_t *pos) ++{ ++ int err; ++ unsigned int val = 0; ++ ++ err = kstrtouint_from_user(buffer, count, 0, &val); ++ if (err) ++ return err; ++ ++ if (val) { ++ iprec_slock(); ++ } else { ++ rec_lock = 0; ++ rem_delay = -1; ++ } ++ ++ return count; ++} ++ ++static const struct proc_ops iprec_lock_ops = { ++ .proc_open = iprec_proc_lock_open, ++ .proc_read = seq_read, ++ .proc_write = iprec_proc_lock_write, ++ .proc_release = single_release, ++}; ++ ++static int iprec_delay_seq_show(struct seq_file *s, void *v) ++{ ++ seq_printf(s, "%d\n", rec_delay); ++ return 0; ++} ++ ++static int iprec_proc_delay_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, iprec_delay_seq_show, PDE_DATA(inode)); ++} ++ ++static ssize_t iprec_proc_delay_write(struct file *file, ++ const char __user *buffer, size_t count, loff_t *pos) ++{ ++ int err; ++ unsigned int val = 0; ++ ++ err = kstrtouint_from_user(buffer, count, 0, &val); ++ if (err) ++ return err; ++ if (val) ++ rec_delay = (val < rec_lines) ? val : (rec_lines - 1); ++ ++ return count; ++} ++ ++static const struct proc_ops iprec_delay_ops = { ++ .proc_open = iprec_proc_delay_open, ++ .proc_read = seq_read, ++ .proc_write = iprec_proc_delay_write, ++ .proc_release = single_release, ++}; ++ ++static int iprec_lines__setup(char *line) ++{ ++ return kstrtouint(line, 10, &rec_lines); /* 10 decimal */ ++} ++__setup("iprec.line=", iprec_lines__setup); ++ ++static struct proc_dir_entry *iprec_create_proc_node(const char *name, ++ struct proc_dir_entry *proc_entry, const struct proc_ops *fileops ++ /* const struct file_operations *fileops */) ++{ ++ struct proc_dir_entry *ret = NULL; ++ ret = proc_create_data(name, 0, proc_entry, fileops, NULL); ++ if (ret == NULL) ++ pr_err("[iprec] failed to create proc file %s\n", name); ++ ++ return ret; ++} ++ ++static int __init iprec_proc_init(void) ++{ ++ char **pool = NULL; ++ struct proc_dir_entry *proc_entry = NULL; ++ ++ if (iprec_init == 0) { ++ proc_entry = proc_mkdir(IPREC, NULL); ++ if (proc_entry == NULL) { ++ pr_err("%s: failed to create proc file %s\n", __func__, IPREC); ++ return -ENOMEM; ++ } ++ iprec_proc = proc_entry; ++ ++ if (iprec_create_proc_node(IPREC_DUMP, iprec_proc, &iprec_dump_ops) == ++ NULL) { ++ pr_err("%s: failed to create proc file %s\n", __func__, IPREC_DUMP); ++ goto remove_entry; ++ } ++ ++ if (iprec_create_proc_node(IPREC_LINE, iprec_proc, &iprec_line_ops) == ++ NULL) { ++ pr_err("%s: failed to create proc file %s\n", __func__, IPREC_LINE); ++ goto remove_dump; ++ } ++ ++ if (iprec_create_proc_node(IPREC_LOCK, iprec_proc, &iprec_lock_ops) == ++ NULL) { ++ pr_err("%s: failed to create proc file %s\n", __func__, IPREC_LOCK); ++ goto remove_line; ++ } ++ ++ if (iprec_create_proc_node(IPREC_DLAY, iprec_proc, &iprec_delay_ops) == ++ NULL) { ++ pr_err("%s: failed to create proc file %s\n", __func__, IPREC_DLAY); ++ goto remove_lock; ++ } ++ ++ pool = iprec_pool_alloc(rec_lines); ++ if (pool == NULL) ++ goto remove_delay; ++ rec_pool = pool; ++ spin_lock_init(&rec_spinlock); ++ iprec_init = 1; ++ } ++ iprec_proc_cnt++; ++ return 0; ++ ++remove_delay: ++ remove_proc_entry(IPREC_DLAY, iprec_proc); ++remove_lock: ++ remove_proc_entry(IPREC_LOCK, iprec_proc); ++remove_line: ++ remove_proc_entry(IPREC_LINE, iprec_proc); ++remove_dump: ++ remove_proc_entry(IPREC_DUMP, iprec_proc); ++remove_entry: ++ remove_proc_entry(IPREC, NULL); ++ return -1; ++} ++ ++static void __exit iprec_proc_shutdown(void) ++{ ++ if (iprec_init) { ++ if (iprec_proc_cnt == 0) { ++ remove_proc_entry(IPREC_DUMP, iprec_proc); ++ remove_proc_entry(IPREC_DLAY, iprec_proc); ++ remove_proc_entry(IPREC_LINE, iprec_proc); ++ remove_proc_entry(IPREC_LOCK, iprec_proc); ++ remove_proc_entry(IPREC, NULL); ++ if (rec_pool) { ++ iprec_pool_free(rec_pool); ++ rec_pool = NULL; ++ } ++ iprec_proc = NULL; ++ iprec_init = 0; ++ } ++ iprec_proc_cnt--; ++ } ++ ++ return; ++} ++subsys_initcall(iprec_proc_init); ++module_exit(iprec_proc_shutdown); ++ ++MODULE_LICENSE("GPL"); +diff --git a/kernel/kallsyms.c b/kernel/kallsyms.c +index c6738525fe11..78078cb8d3cf 100644 +--- a/kernel/kallsyms.c ++++ b/kernel/kallsyms.c +@@ -176,6 +176,7 @@ unsigned long kallsyms_lookup_name(const char *name) + } + return module_kallsyms_lookup_name(name); + } ++EXPORT_SYMBOL(kallsyms_lookup_name); + + int kallsyms_on_each_symbol(int (*fn)(void *, const char *, struct module *, + unsigned long), +diff --git a/kernel/sched/core.c b/kernel/sched/core.c +index 974a41b87aa1..b7c0cf2d504f 100644 +--- a/kernel/sched/core.c ++++ b/kernel/sched/core.c +@@ -6597,6 +6597,7 @@ int sched_setscheduler(struct task_struct *p, int policy, + { + return _sched_setscheduler(p, policy, param, true); + } ++EXPORT_SYMBOL(sched_setscheduler); + + int sched_setattr(struct task_struct *p, const struct sched_attr *attr) + { +diff --git a/lib/Kconfig b/lib/Kconfig +index 36326864249d..eecd86d0133e 100644 +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -693,3 +693,7 @@ config GENERIC_LIB_UCMPDI2 + config PLDMFW + bool + default n ++ ++config LIB_PRINT ++ bool ++ default y +diff --git a/lib/Makefile b/lib/Makefile +index a803e1527c4b..c05d1bad49cc 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -354,3 +354,5 @@ obj-$(CONFIG_BITFIELD_KUNIT) += bitfield_kunit.o + obj-$(CONFIG_LIST_KUNIT_TEST) += list-test.o + obj-$(CONFIG_LINEAR_RANGES_TEST) += test_linear_ranges.o + obj-$(CONFIG_BITS_TEST) += test_bits.o ++ ++obj-$(CONFIG_LIB_PRINT) += securec/ +diff --git a/lib/securec/LICENSE b/lib/securec/LICENSE +new file mode 100644 +index 000000000000..42f2a83670c6 +--- /dev/null ++++ b/lib/securec/LICENSE +@@ -0,0 +1,124 @@ ++木兰宽松许可证， 第2版 ++ ++2020年1月 http://license.coscl.org.cn/MulanPSL2 ++ ++您对“软件”的复制、使用、修改及分发受木兰宽松许可证，第2版（“本许可证”）的如下条款的约束： ++ ++0. 定义 ++ ++“软件” 是指由“贡献”构成的许可在“本许可证”下的程序和相关文档的集合。 ++ ++“贡献” 是指由任一“贡献者”许可在“本许可证”下的受版权法保护的作品。 ++ ++“贡献者” 是指将受版权法保护的作品许可在“本许可证”下的自然人或“法人实体”。 ++ ++“法人实体” 是指提交贡献的机构及其“关联实体”。 ++ ++“关联实体” 是指，对“本许可证”下的行为方而言，控制、受控制或与其共同受控制的机构，此处的控制是指有受控方或共同受控方至少50%直接或间接的投票权、资金或其他有价证券。 ++ ++1. 授予版权许可 ++ ++每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的版权许可，您可以复制、使用、修改、分发其“贡献”，不论修改与否。 ++ ++2. 授予专利许可 ++ ++每个“贡献者”根据“本许可证”授予您永久性的、全球性的、免费的、非独占的、不可撤销的（根据本条规定撤销除外）专利许可，供您制造、委托制造、使用、许诺销售、销售、进口其“贡献”或以其他方式转移其“贡献”。前述专利许可仅限于“贡献者”现在或将来拥有或控制的其“贡献”本身或其“贡献”与许可“贡献”时的“软件”结合而将必然会侵犯的专利权利要求，不包括对“贡献”的修改或包含“贡献”的其他结合。如果您或您的“关联实体”直接或间接地，就“软件”或其中的“贡献”对任何人发起专利侵权诉讼（包括反诉或交叉诉讼）或其他专利维权行动，指控其侵犯专利权，则“本许可证”授予您对“软件”的专利许可自您提起诉讼或发起维权行动之日终止。 ++ ++3. 无商标许可 ++ ++“本许可证”不提供对“贡献者”的商品名称、商标、服务标志或产品名称的商标许可，但您为满足第4条规定的声明义务而必须使用除外。 ++ ++4. 分发限制 ++ ++您可以在任何媒介中将“软件”以源程序形式或可执行形式重新分发，不论修改与否，但您必须向接收者提供“本许可证”的副本，并保留“软件”中的版权、商标、专利及免责声明。 ++ ++5. 免责声明与责任限制 ++ ++“软件”及其中的“贡献”在提供时不带任何明示或默示的担保。在任何情况下，“贡献者”或版权所有者不对任何人因使用“软件”或其中的“贡献”而引发的任何直接或间接损失承担责任，不论因何种原因导致或者基于何种法律理论，即使其曾被建议有此种损失的可能性。 ++ ++6. 语言 ++ ++“本许可证”以中英文双语表述，中英文版本具有同等法律效力。如果中英文版本存在任何冲突不一致，以中文版为准。 ++ ++条款结束 ++ ++如何将木兰宽松许可证，第2版，应用到您的软件 ++ ++如果您希望将木兰宽松许可证，第2版，应用到您的新软件，为了方便接收者查阅，建议您完成如下三步： ++ ++1， 请您补充如下声明中的空白，包括软件名、软件的首次发表年份以及您作为版权人的名字； ++ ++2， 请您在软件包的一级目录下创建以“LICENSE”为名的文件，将整个许可证文本放入该文件中； ++ ++3， 请将如下声明文本放入每个源文件的头部注释中。 ++ ++Copyright (c) [Year] [name of copyright holder] ++[Software Name] is licensed under Mulan PSL v2. ++You can use this software according to the terms and conditions of the Mulan PSL v2. ++You may obtain a copy of Mulan PSL v2 at: ++ http://license.coscl.org.cn/MulanPSL2 ++THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++See the Mulan PSL v2 for more details. ++Mulan Permissive Software License,Version 2 ++Mulan Permissive Software License,Version 2 (Mulan PSL v2) ++ ++January 2020 http://license.coscl.org.cn/MulanPSL2 ++ ++Your reproduction, use, modification and distribution of the Software shall be subject to Mulan PSL v2 (this License) with the following terms and conditions: ++ ++0. Definition ++ ++Software means the program and related documents which are licensed under this License and comprise all Contribution(s). ++ ++Contribution means the copyrightable work licensed by a particular Contributor under this License. ++ ++Contributor means the Individual or Legal Entity who licenses its copyrightable work under this License. ++ ++Legal Entity means the entity making a Contribution and all its Affiliates. ++ ++Affiliates means entities that control, are controlled by, or are under common control with the acting entity under this License, 'control' means direct or indirect ownership of at least fifty percent (50%) of the voting power, capital or other securities of controlled or commonly controlled entity. ++ ++1. Grant of Copyright License ++ ++Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable copyright license to reproduce, use, modify, or distribute its Contribution, with modification or not. ++ ++2. Grant of Patent License ++ ++Subject to the terms and conditions of this License, each Contributor hereby grants to you a perpetual, worldwide, royalty-free, non-exclusive, irrevocable (except for revocation under this Section) patent license to make, have made, use, offer for sale, sell, import or otherwise transfer its Contribution, where such patent license is only limited to the patent claims owned or controlled by such Contributor now or in future which will be necessarily infringed by its Contribution alone, or by combination of the Contribution with the Software to which the Contribution was contributed. The patent license shall not apply to any modification of the Contribution, and any other combination which includes the Contribution. If you or your Affiliates directly or indirectly institute patent litigation (including a cross claim or counterclaim in a litigation) or other patent enforcement activities against any individual or entity by alleging that the Software or any Contribution in it infringes patents, then any patent license granted to you under this License for the Software shall terminate as of the date such litigation or activity is filed or taken. ++ ++3. No Trademark License ++ ++No trademark license is granted to use the trade names, trademarks, service marks, or product names of Contributor, except as required to fulfill notice requirements in section 4. ++ ++4. Distribution Restriction ++ ++You may distribute the Software in any medium with or without modification, whether in source or executable forms, provided that you provide recipients with a copy of this License and retain copyright, patent, trademark and disclaimer statements in the Software. ++ ++5. Disclaimer of Warranty and Limitation of Liability ++ ++THE SOFTWARE AND CONTRIBUTION IN IT ARE PROVIDED WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED. IN NO EVENT SHALL ANY CONTRIBUTOR OR COPYRIGHT HOLDER BE LIABLE TO YOU FOR ANY DAMAGES, INCLUDING, BUT NOT LIMITED TO ANY DIRECT, OR INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES ARISING FROM YOUR USE OR INABILITY TO USE THE SOFTWARE OR THE CONTRIBUTION IN IT, NO MATTER HOW IT'S CAUSED OR BASED ON WHICH LEGAL THEORY, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. ++ ++6. Language ++ ++THIS LICENSE IS WRITTEN IN BOTH CHINESE AND ENGLISH, AND THE CHINESE VERSION AND ENGLISH VERSION SHALL HAVE THE SAME LEGAL EFFECT. IN THE CASE OF DIVERGENCE BETWEEN THE CHINESE AND ENGLISH VERSIONS, THE CHINESE VERSION SHALL PREVAIL. ++ ++END OF THE TERMS AND CONDITIONS ++ ++How to Apply the Mulan Permissive Software License,Version 2 (Mulan PSL v2) to Your Software ++ ++To apply the Mulan PSL v2 to your work, for easy identification by recipients, you are suggested to complete following three steps: ++ ++Fill in the blanks in following statement, including insert your software name, the year of the first publication of your software, and your name identified as the copyright owner; ++Create a file named "LICENSE" which contains the whole context of this License in the first directory of your software package; ++Attach the statement to the appropriate annotated syntax at the beginning of each source file. ++Copyright (c) [Year] [name of copyright holder] ++[Software Name] is licensed under Mulan PSL v2. ++You can use this software according to the terms and conditions of the Mulan PSL v2. ++You may obtain a copy of Mulan PSL v2 at: ++ http://license.coscl.org.cn/MulanPSL2 ++THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++See the Mulan PSL v2 for more details. +\ No newline at end of file +diff --git a/lib/securec/Makefile b/lib/securec/Makefile +new file mode 100644 +index 000000000000..9d804337a01e +--- /dev/null ++++ b/lib/securec/Makefile +@@ -0,0 +1 @@ ++obj-y += src/ +diff --git a/lib/securec/README.en.md b/lib/securec/README.en.md +new file mode 100644 +index 000000000000..60c477fe8978 +--- /dev/null ++++ b/lib/securec/README.en.md +@@ -0,0 +1,59 @@ ++# libboundscheck ++ ++#### Description ++ ++- following the standard of C11 Annex K (bound-checking interfaces), functions of the common memory/string operation classes, such as memcpy_s, strcpy_s, are selected and implemented. ++ ++- other standard functions in C11 Annex K will be analyzed in the future and implemented in this organization if necessary. ++ ++- handles the release, update, and maintenance of bounds_checking_function. ++ ++#### Function List ++ ++- memcpy_s ++- wmemcpy_s ++- memmove_s ++- wmemmove_s ++- memset_s ++- strcpy_s ++- wcscpy_s ++- strncpy_s ++- wcsncpy_s ++- strcat_s ++- wcscat_s ++- strncat_s ++- wcsncat_s ++- strtok_s ++- wcstok_s ++- sprintf_s ++- swprintf_s ++- vsprintf_s ++- vswprintf_s ++- snprintf_s ++- vsnprintf_s ++- scanf_s ++- wscanf_s ++- vscanf_s ++- vwscanf_s ++- fscanf_s ++- fwscanf_s ++- vfscanf_s ++- vfwscanf_s ++- sscanf_s ++- swscanf_s ++- vsscanf_s ++- vswscanf_s ++- gets_s ++ ++ ++#### Build ++ ++``` ++CC=gcc make ++``` ++The generated Dynamic library libboundscheck.so is stored in the newly created directory lib. ++ ++#### How to use ++1. Copy the libboundscheck.so to the library file directory, for example: "/usr/local/lib/". ++ ++2. To use the libboundscheck, add the “-lboundscheck” parameters to the compiler, for example: “gcc -g -o test test.c -lboundscheck”. +\ No newline at end of file +diff --git a/lib/securec/README.md b/lib/securec/README.md +new file mode 100644 +index 000000000000..c16cbb17696c +--- /dev/null ++++ b/lib/securec/README.md +@@ -0,0 +1,56 @@ ++# libboundscheck ++ ++#### 介绍 ++- 遵循C11 Annex K (Bounds-checking interfaces)的标准，选取并实现了常见的内存/字符串操作类的函数，如memcpy_s、strcpy_s等函数。 ++- 未来将分析C11 Annex K中的其他标准函数，如果有必要，将在该组织中实现。 ++- 处理边界检查函数的版本发布、更新以及维护。 ++ ++#### 函数清单 ++ ++- memcpy_s ++- wmemcpy_s ++- memmove_s ++- wmemmove_s ++- memset_s ++- strcpy_s ++- wcscpy_s ++- strncpy_s ++- wcsncpy_s ++- strcat_s ++- wcscat_s ++- strncat_s ++- wcsncat_s ++- strtok_s ++- wcstok_s ++- sprintf_s ++- swprintf_s ++- vsprintf_s ++- vswprintf_s ++- snprintf_s ++- vsnprintf_s ++- scanf_s ++- wscanf_s ++- vscanf_s ++- vwscanf_s ++- fscanf_s ++- fwscanf_s ++- vfscanf_s ++- vfwscanf_s ++- sscanf_s ++- swscanf_s ++- vsscanf_s ++- vswscanf_s ++- gets_s ++ ++#### 构建方法 ++ ++运行命令 ++``` ++make CC=gcc ++``` ++生成的动态库libboundscheck.so存放在新创建的lib目录下。 ++ ++#### 使用方法 ++1. 将构建生成的动态库libboundscheck.so放到库文件目录下，例如："/usr/local/lib/"。 ++ ++2. 为使用libboundscheck，编译程序时需增加编译参数"-lboundscheck"，例如："gcc -g -o test test.c -lboundscheck"。 +\ No newline at end of file +diff --git a/lib/securec/src/Makefile b/lib/securec/src/Makefile +new file mode 100644 +index 000000000000..42554f880412 +--- /dev/null ++++ b/lib/securec/src/Makefile +@@ -0,0 +1,17 @@ ++obj-y += securecutil.o ++obj-y += strncpy_s.o ++obj-y += vsprintf_s.o ++obj-y += snprintf_s.o ++obj-y += memcpy_s.o ++obj-y += memmove_s.o ++obj-y += strcat_s.o ++obj-y += secureprintoutput_a.o ++obj-y += memset_s.o ++obj-y += strtok_s.o ++obj-y += sprintf_s.o ++obj-y += strncat_s.o ++obj-y += strcpy_s.o ++obj-y += vsnprintf_s.o ++obj-y += secureinput_a.o ++obj-y += vsscanf_s.o ++obj-y += sscanf_s.o +diff --git a/lib/securec/src/input.inl b/lib/securec/src/input.inl +new file mode 100644 +index 000000000000..5880d45df453 +--- /dev/null ++++ b/lib/securec/src/input.inl +@@ -0,0 +1,2229 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Used by secureinput_a.c and secureinput_w.c to include. ++ * This file provides a template function for ANSI and UNICODE compiling by ++ * different type definition. The functions of SecInputS or ++ * SecInputSW provides internal implementation for scanf family API, such as sscanf_s, fscanf_s. ++ * Create: 2014-02-25 ++ * Notes: The formatted input processing results of integers on different platforms are different. ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Performance-sensitive ++ * [reason] Always used in the performance critical path, ++ * and sufficient input validation is performed before calling ++ */ ++#ifndef INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 ++#define INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 ++ ++#if SECUREC_IN_KERNEL ++#if !defined(SECUREC_CTYPE_MACRO_ADAPT) ++#include ++#endif ++#else ++#if !defined(SECUREC_SYSAPI4VXWORKS) && !defined(SECUREC_CTYPE_MACRO_ADAPT) ++//#include ++#ifdef SECUREC_FOR_WCHAR ++//#include /* For iswspace */ ++#endif ++#endif ++#endif ++ ++#ifndef EOF ++#define EOF (-1) ++#endif ++ ++#define SECUREC_NUM_WIDTH_SHORT 0 ++#define SECUREC_NUM_WIDTH_INT 1 ++#define SECUREC_NUM_WIDTH_LONG 2 ++#define SECUREC_NUM_WIDTH_LONG_LONG 3 /* Also long double */ ++ ++#define SECUREC_BUFFERED_BLOK_SIZE 1024U ++ ++#if defined(SECUREC_VXWORKS_PLATFORM) && !defined(va_copy) && !defined(__va_copy) ++/* The name is the same as system macro. */ ++#define __va_copy(dest, src) do { \ ++ size_t destSize_ = (size_t)sizeof(dest); \ ++ size_t srcSize_ = (size_t)sizeof(src); \ ++ if (destSize_ != srcSize_) { \ ++ SECUREC_MEMCPY_WARP_OPT((dest), (src), sizeof(va_list)); \ ++ } else { \ ++ SECUREC_MEMCPY_WARP_OPT(&(dest), &(src), sizeof(va_list)); \ ++ } \ ++} SECUREC_WHILE_ZERO ++#endif ++ ++#define SECUREC_MULTI_BYTE_MAX_LEN 6 ++ ++/* Compatibility macro name cannot be modifie */ ++#ifndef UNALIGNED ++#if !(defined(_M_IA64)) && !(defined(_M_AMD64)) ++#define UNALIGNED ++#else ++#define UNALIGNED __unaligned ++#endif ++#endif ++ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++/* Max 64bit value is 0xffffffffffffffff */ ++#define SECUREC_MAX_64BITS_VALUE 18446744073709551615ULL ++#define SECUREC_MAX_64BITS_VALUE_DIV_TEN 1844674407370955161ULL ++#define SECUREC_MAX_64BITS_VALUE_CUT_LAST_DIGIT 18446744073709551610ULL ++#define SECUREC_MIN_64BITS_NEG_VALUE 9223372036854775808ULL ++#define SECUREC_MAX_64BITS_POS_VALUE 9223372036854775807ULL ++#define SECUREC_MIN_32BITS_NEG_VALUE 2147483648UL ++#define SECUREC_MAX_32BITS_POS_VALUE 2147483647UL ++#define SECUREC_MAX_32BITS_VALUE 4294967295UL ++#define SECUREC_MAX_32BITS_VALUE_INC 4294967296UL ++#define SECUREC_MAX_32BITS_VALUE_DIV_TEN 429496729UL ++#define SECUREC_LONG_BIT_NUM ((unsigned int)(sizeof(long) << 3U)) ++/* Use ULL to clean up cl6x compilation alerts */ ++#define SECUREC_MAX_LONG_POS_VALUE ((unsigned long)(1ULL << (SECUREC_LONG_BIT_NUM - 1)) - 1) ++#define SECUREC_MIN_LONG_NEG_VALUE ((unsigned long)(1ULL << (SECUREC_LONG_BIT_NUM - 1))) ++ ++/* Covert to long long to clean up cl6x compilation alerts */ ++#define SECUREC_LONG_HEX_BEYOND_MAX(number) (((unsigned long long)(number) >> (SECUREC_LONG_BIT_NUM - 4U)) > 0) ++#define SECUREC_LONG_OCTAL_BEYOND_MAX(number) (((unsigned long long)(number) >> (SECUREC_LONG_BIT_NUM - 3U)) > 0) ++ ++#define SECUREC_QWORD_HEX_BEYOND_MAX(number) (((number) >> (64U - 4U)) > 0) ++#define SECUREC_QWORD_OCTAL_BEYOND_MAX(number) (((number) >> (64U - 3U)) > 0) ++ ++#define SECUREC_LP64_BIT_WIDTH 64 ++#define SECUREC_LP32_BIT_WIDTH 32 ++ ++#define SECUREC_CONVERT_IS_SIGNED(conv) ((conv) == 'd' || (conv) == 'i') ++#endif ++ ++#define SECUREC_BRACE '{' /* [ to { */ ++#define SECUREC_FILED_WIDTH_ENOUGH(spec) ((spec)->widthSet == 0 || (spec)->width > 0) ++#define SECUREC_FILED_WIDTH_DEC(spec) do { \ ++ if ((spec)->widthSet != 0) { \ ++ --(spec)->width; \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++#ifdef SECUREC_FOR_WCHAR ++/* Bits for all wchar, size is 65536/8, only supports wide characters with a maximum length of two bytes */ ++#define SECUREC_BRACKET_TABLE_SIZE 8192 ++#define SECUREC_EOF WEOF ++#define SECUREC_MB_LEN 16 /* Max. # bytes in multibyte char ,see MB_LEN_MAX */ ++#else ++/* Bits for all char, size is 256/8 */ ++#define SECUREC_BRACKET_TABLE_SIZE 32 ++#define SECUREC_EOF EOF ++#endif ++ ++#if SECUREC_HAVE_WCHART ++#define SECUREC_ARRAY_WIDTH_IS_WRONG(spec) ((spec).arrayWidth == 0 || \ ++ ((spec).isWCharOrLong <= 0 && (spec).arrayWidth > SECUREC_STRING_MAX_LEN) || \ ++ ((spec).isWCharOrLong > 0 && (spec).arrayWidth > SECUREC_WCHAR_STRING_MAX_LEN)) ++#else ++#define SECUREC_ARRAY_WIDTH_IS_WRONG(spec) ((spec).arrayWidth == 0 || (spec).arrayWidth > SECUREC_STRING_MAX_LEN) ++#endif ++ ++#ifdef SECUREC_ON_64BITS ++/* Use 0xffffffffUL mask to pass integer as array length */ ++#define SECUREC_GET_ARRAYWIDTH(argList) (((size_t)va_arg((argList), size_t)) & 0xffffffffUL) ++#else /* !SECUREC_ON_64BITS */ ++#define SECUREC_GET_ARRAYWIDTH(argList) ((size_t)va_arg((argList), size_t)) ++#endif ++ ++typedef struct { ++#ifdef SECUREC_FOR_WCHAR ++ unsigned char *table; /* Default NULL */ ++#else ++ unsigned char table[SECUREC_BRACKET_TABLE_SIZE]; /* Array length is large enough in application scenarios */ ++#endif ++ unsigned char mask; /* Default 0 */ ++} SecBracketTable; ++ ++#ifdef SECUREC_FOR_WCHAR ++#define SECUREC_INIT_BRACKET_TABLE { NULL, 0 } ++#else ++#define SECUREC_INIT_BRACKET_TABLE { {0}, 0 } ++#endif ++ ++#if SECUREC_ENABLE_SCANF_FLOAT ++typedef struct { ++ size_t floatStrTotalLen; /* Initialization must be length of buffer in charater */ ++ size_t floatStrUsedLen; /* Store float string len */ ++ SecChar *floatStr; /* Initialization must point to buffer */ ++ SecChar *allocatedFloatStr; /* Initialization must be NULL to store alloced point */ ++ SecChar buffer[SECUREC_FLOAT_BUFSIZE + 1]; ++} SecFloatSpec; ++#endif ++ ++#define SECUREC_NUMBER_STATE_DEFAULT 0U ++#define SECUREC_NUMBER_STATE_STARTED 1U ++ ++typedef struct { ++ SecInt ch; /* Char read from input */ ++ int charCount; /* Number of characters processed */ ++ void *argPtr; /* Variable parameter pointer, point to the end of the string */ ++ size_t arrayWidth; /* Length of pointer Variable parameter, in charaters */ ++ SecUnsignedInt64 number64; /* Store input number64 value */ ++ unsigned long number; /* Store input number32 value */ ++ int numberWidth; /* 0 = SHORT, 1 = int, > 1 long or L_DOUBLE */ ++ int numberArgType; /* 1 for 64-bit integer, 0 otherwise. use it as decode function index */ ++ unsigned int negative; /* 0 is positive */ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ unsigned int beyondMax; /* Non-zero means beyond */ ++#endif ++ unsigned int numberState; /* Identifies whether to start processing numbers, 1 is can input number */ ++ int width; /* Width number in format */ ++ int widthSet; /* 0 is not set width in format */ ++ int convChr; /* Lowercase format conversion characters */ ++ int oriConvChr; /* Store original format conversion, convChr may change when parsing integers */ ++ signed char isWCharOrLong; /* -1/0 not wchar or long, 1 for wchar or long */ ++ unsigned char suppress; /* 0 is not have %* in format */ ++} SecScanSpec; ++ ++#ifdef SECUREC_FOR_WCHAR ++#define SECUREC_GETC fgetwc ++#define SECUREC_UN_GETC ungetwc ++/* Only supports wide characters with a maximum length of two bytes in format string */ ++#define SECUREC_BRACKET_CHAR_MASK 0xffffU ++#else ++#define SECUREC_GETC fgetc ++#define SECUREC_UN_GETC ungetc ++#define SECUREC_BRACKET_CHAR_MASK 0xffU ++#endif ++ ++#define SECUREC_CHAR_SIZE ((unsigned int)(sizeof(SecChar))) ++/* To avoid 648, mask high bit: 0x00ffffff 0x0000ffff or 0x00000000 */ ++#define SECUREC_CHAR_MASK_HIGH (((((((((unsigned int)(-1) >> SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ ++ SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ ++ SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) >> \ ++ SECUREC_CHAR_SIZE) >> SECUREC_CHAR_SIZE) ++ ++/* For char is 0xff, wcahr_t is 0xffff or 0xffffffff. */ ++#define SECUREC_CHAR_MASK (~((((((((((unsigned int)(-1) & SECUREC_CHAR_MASK_HIGH) << \ ++ SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ ++ SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ ++ SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE) << \ ++ SECUREC_CHAR_SIZE) << SECUREC_CHAR_SIZE)) ++ ++/* According wchar_t has multiple bytes, so use sizeof */ ++#define SECUREC_GET_CHAR(stream, outCh) do { \ ++ if ((stream)->count >= sizeof(SecChar)) { \ ++ *(outCh) = (SecInt)(SECUREC_CHAR_MASK & \ ++ (unsigned int)(int)(*((const SecChar *)(const void *)(stream)->cur))); \ ++ (stream)->cur += sizeof(SecChar); \ ++ (stream)->count -= sizeof(SecChar); \ ++ } else { \ ++ *(outCh) = SECUREC_EOF; \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++#define SECUREC_UN_GET_CHAR(stream) do { \ ++ if ((stream)->cur > (stream)->base) { \ ++ (stream)->cur -= sizeof(SecChar); \ ++ (stream)->count += sizeof(SecChar); \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++/* Convert wchar_t to int and then to unsigned int to keep data clearing warning */ ++#define SECUREC_TO_LOWERCASE(chr) ((int)((unsigned int)(int)(chr) | (unsigned int)('a' - 'A'))) ++ ++/* Record a flag for each bit */ ++#define SECUREC_BRACKET_INDEX(x) ((unsigned int)(x) >> 3U) ++#define SECUREC_BRACKET_VALUE(x) ((unsigned char)(1U << ((unsigned int)(x) & 7U))) ++#if SECUREC_IN_KERNEL ++#define SECUREC_CONVERT_IS_UNSIGNED(conv) ((conv) == 'x' || (conv) == 'o' || (conv) == 'u') ++#endif ++ ++/* ++ * Set char in %[xxx] into table, only supports wide characters with a maximum length of two bytes ++ */ ++SECUREC_INLINE void SecBracketSetBit(unsigned char *table, SecUnsignedChar ch) ++{ ++ unsigned int tableIndex = SECUREC_BRACKET_INDEX(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); ++ unsigned int tableValue = SECUREC_BRACKET_VALUE(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); ++ /* Do not use |= optimize this code, it will cause compiling warning */ ++ table[tableIndex] = (unsigned char)(table[tableIndex] | tableValue); ++} ++ ++SECUREC_INLINE void SecBracketSetBitRange(unsigned char *table, SecUnsignedChar startCh, SecUnsignedChar endCh) ++{ ++ SecUnsignedChar expCh; ++ /* %[a-z] %[a-a] Format %[a-\xff] end is 0xFF, condition (expCh <= endChar) cause dead loop */ ++ for (expCh = startCh; expCh < endCh; ++expCh) { ++ SecBracketSetBit(table, expCh); ++ } ++ SecBracketSetBit(table, endCh); ++} ++/* ++ * Determine whether the expression can be satisfied ++ */ ++SECUREC_INLINE int SecCanInputForBracket(int convChr, SecInt ch, const SecBracketTable *bracketTable) ++{ ++ unsigned int tableIndex = SECUREC_BRACKET_INDEX(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); ++ unsigned int tableValue = SECUREC_BRACKET_VALUE(((unsigned int)(int)ch & SECUREC_BRACKET_CHAR_MASK)); ++#ifdef SECUREC_FOR_WCHAR ++ if (((unsigned int)(int)ch & (~(SECUREC_BRACKET_CHAR_MASK))) != 0) { ++ /* The value of the wide character exceeds the size of two bytes */ ++ return 0; ++ } ++ return (int)(convChr == SECUREC_BRACE && ++ (((unsigned int)bracketTable->table[tableIndex] ^ (unsigned int)bracketTable->mask) & tableValue) != 0); ++#else ++ return (int)(convChr == SECUREC_BRACE && ++ (((unsigned int)bracketTable->table[tableIndex] ^ (unsigned int)bracketTable->mask) & tableValue) != 0); ++#endif ++} ++ ++/* ++ * String input ends when blank character is encountered ++ */ ++SECUREC_INLINE int SecCanInputString(int convChr, SecInt ch) ++{ ++ return (int)(convChr == 's' && ++ (!(ch >= SECUREC_CHAR('\t') && ch <= SECUREC_CHAR('\r')) && ch != SECUREC_CHAR(' '))); ++} ++ ++/* ++ * Can input a character when format is %c ++ */ ++SECUREC_INLINE int SecCanInputCharacter(int convChr) ++{ ++ return (int)(convChr == 'c'); ++} ++ ++/* ++ * Determine if it is a 64-bit pointer function ++ * Return 0 is not ,1 is 64bit pointer ++ */ ++SECUREC_INLINE int SecNumberArgType(size_t sizeOfVoidStar) ++{ ++ /* Point size is 4 or 8 , Under the 64 bit system, the value not 0 */ ++ /* To clear e778 */ ++ if ((sizeOfVoidStar & sizeof(SecInt64)) != 0) { ++ return 1; ++ } ++ return 0; ++} ++SECUREC_INLINE int SecIsDigit(SecInt ch); ++SECUREC_INLINE int SecIsXdigit(SecInt ch); ++SECUREC_INLINE int SecIsSpace(SecInt ch); ++SECUREC_INLINE SecInt SecSkipSpaceChar(SecFileStream *stream, int *counter); ++SECUREC_INLINE SecInt SecGetChar(SecFileStream *stream, int *counter); ++SECUREC_INLINE void SecUnGetChar(SecInt ch, SecFileStream *stream, int *counter); ++ ++#if SECUREC_ENABLE_SCANF_FLOAT ++ ++/* ++ * Convert a floating point string to a floating point number ++ */ ++SECUREC_INLINE int SecAssignNarrowFloat(const char *floatStr, const SecScanSpec *spec) ++{ ++ char *endPtr = NULL; ++ double d; ++#if SECUREC_SUPPORT_STRTOLD ++ if (spec->numberWidth == SECUREC_NUM_WIDTH_LONG_LONG) { ++ long double d2 = strtold(floatStr, &endPtr); ++ if (endPtr == floatStr) { ++ return -1; ++ } ++ *(long double UNALIGNED *)(spec->argPtr) = d2; ++ return 0; ++ } ++#endif ++ d = strtod(floatStr, &endPtr); ++ /* cannot detect if endPtr points to the end of floatStr,because strtod handles only two characters for 1.E */ ++ if (endPtr == floatStr) { ++ return -1; ++ } ++ if (spec->numberWidth > SECUREC_NUM_WIDTH_INT) { ++ *(double UNALIGNED *)(spec->argPtr) = (double)d; ++ } else { ++ *(float UNALIGNED *)(spec->argPtr) = (float)d; ++ } ++ return 0; ++} ++ ++#ifdef SECUREC_FOR_WCHAR ++/* ++ * Convert a floating point wchar string to a floating point number ++ * Success ret 0 ++ */ ++SECUREC_INLINE int SecAssignWideFloat(const SecFloatSpec *floatSpec, const SecScanSpec *spec) ++{ ++ int retVal; ++ /* Convert float string */ ++ size_t mbsLen; ++ size_t tempFloatStrLen = (size_t)(floatSpec->floatStrUsedLen + 1) * sizeof(wchar_t); ++ char *tempFloatStr = (char *)SECUREC_MALLOC(tempFloatStrLen); ++ if (tempFloatStr == NULL) { ++ return -1; ++ } ++ tempFloatStr[0] = '\0'; ++ SECUREC_MASK_MSVC_CRT_WARNING ++ mbsLen = wcstombs(tempFloatStr, floatSpec->floatStr, tempFloatStrLen - 1); ++ SECUREC_END_MASK_MSVC_CRT_WARNING ++ /* This condition must satisfy mbsLen is not -1 */ ++ if (mbsLen >= tempFloatStrLen) { ++ SECUREC_FREE(tempFloatStr); ++ return -1; ++ } ++ tempFloatStr[mbsLen] = '\0'; ++ retVal = SecAssignNarrowFloat(tempFloatStr, spec); ++ SECUREC_FREE(tempFloatStr); ++ return retVal; ++} ++#endif ++ ++SECUREC_INLINE int SecAssignFloat(const SecFloatSpec *floatSpec, const SecScanSpec *spec) ++{ ++#ifdef SECUREC_FOR_WCHAR ++ return SecAssignWideFloat(floatSpec, spec); ++#else ++ return SecAssignNarrowFloat(floatSpec->floatStr, spec); ++#endif ++} ++ ++/* ++ * Init SecFloatSpec before parse format ++ */ ++SECUREC_INLINE void SecInitFloatSpec(SecFloatSpec *floatSpec) ++{ ++ floatSpec->floatStr = floatSpec->buffer; ++ floatSpec->allocatedFloatStr = NULL; ++ floatSpec->floatStrTotalLen = sizeof(floatSpec->buffer) / sizeof(floatSpec->buffer[0]); ++ floatSpec->floatStrUsedLen = 0; ++} ++ ++SECUREC_INLINE void SecFreeFloatSpec(SecFloatSpec *floatSpec, int *doneCount) ++{ ++ /* 2014.3.6 add, clear the stack data */ ++ if (memset_s(floatSpec->buffer, sizeof(floatSpec->buffer), 0, sizeof(floatSpec->buffer)) != EOK) { ++ *doneCount = 0; /* This code just to meet the coding requirements */ ++ } ++ /* The pFloatStr can be alloced in SecExtendFloatLen function, clear and free it */ ++ if (floatSpec->allocatedFloatStr != NULL) { ++ size_t bufferSize = floatSpec->floatStrTotalLen * sizeof(SecChar); ++ if (memset_s(floatSpec->allocatedFloatStr, bufferSize, 0, bufferSize) != EOK) { ++ *doneCount = 0; /* This code just to meet the coding requirements */ ++ } ++ SECUREC_FREE(floatSpec->allocatedFloatStr); ++ floatSpec->allocatedFloatStr = NULL; ++ floatSpec->floatStr = NULL; ++ } ++} ++ ++/* ++ * Splice floating point string ++ * Return 0 OK ++ */ ++SECUREC_INLINE int SecExtendFloatLen(SecFloatSpec *floatSpec) ++{ ++ if (floatSpec->floatStrUsedLen >= floatSpec->floatStrTotalLen) { ++ /* Buffer size is len x sizeof(SecChar) */ ++ size_t oriSize = floatSpec->floatStrTotalLen * sizeof(SecChar); ++ /* Add one character to clear tool warning */ ++ size_t nextSize = (oriSize * 2) + sizeof(SecChar); /* Multiply 2 to extend buffer size */ ++ ++ /* Prevents integer overflow, the maximum length of SECUREC_MAX_WIDTH_LEN is enough */ ++ if (nextSize <= (size_t)SECUREC_MAX_WIDTH_LEN) { ++ void *nextBuffer = (void *)SECUREC_MALLOC(nextSize); ++ if (nextBuffer == NULL) { ++ return -1; ++ } ++ if (memcpy_s(nextBuffer, nextSize, floatSpec->floatStr, oriSize) != EOK) { ++ SECUREC_FREE(nextBuffer); /* This is a dead code, just to meet the coding requirements */ ++ return -1; ++ } ++ /* Clear old buffer memory */ ++ if (memset_s(floatSpec->floatStr, oriSize, 0, oriSize) != EOK) { ++ SECUREC_FREE(nextBuffer); /* This is a dead code, just to meet the coding requirements */ ++ return -1; ++ } ++ /* Free old allocated buffer */ ++ if (floatSpec->allocatedFloatStr != NULL) { ++ SECUREC_FREE(floatSpec->allocatedFloatStr); ++ } ++ floatSpec->allocatedFloatStr = (SecChar *)(nextBuffer); /* Use to clear free on stack warning */ ++ floatSpec->floatStr = (SecChar *)(nextBuffer); ++ floatSpec->floatStrTotalLen = nextSize / sizeof(SecChar); /* Get buffer total len in character */ ++ return 0; ++ } ++ return -1; /* Next size is beyond max */ ++ } ++ return 0; ++} ++ ++/* Do not use localeconv()->decimal_pointif onlay support '.' */ ++SECUREC_INLINE int SecIsFloatDecimal(SecChar ch) ++{ ++ return (int)(ch == SECUREC_CHAR('.')); ++} ++ ++SECUREC_INLINE int SecInputFloatSign(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) ++{ ++ if (!SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ return 0; ++ } ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ if (spec->ch == SECUREC_CHAR('+') || spec->ch == SECUREC_CHAR('-')) { ++ SECUREC_FILED_WIDTH_DEC(spec); /* Make sure the count after un get char is correct */ ++ if (spec->ch == SECUREC_CHAR('-')) { ++ floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('-'); ++ ++floatSpec->floatStrUsedLen; ++ if (SecExtendFloatLen(floatSpec) != 0) { ++ return -1; ++ } ++ } ++ } else { ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ } ++ return 0; ++} ++ ++SECUREC_INLINE int SecInputFloatDigit(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) ++{ ++ /* Now get integral part */ ++ while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ if (SecIsDigit(spec->ch) == 0) { ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ return 0; ++ } ++ SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ ++ spec->numberState = SECUREC_NUMBER_STATE_STARTED; ++ floatSpec->floatStr[floatSpec->floatStrUsedLen] = (SecChar)spec->ch; ++ ++floatSpec->floatStrUsedLen; ++ if (SecExtendFloatLen(floatSpec) != 0) { ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/* ++* Scan value of exponent. ++* Return 0 OK ++*/ ++SECUREC_INLINE int SecInputFloatE(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) ++{ ++ if (SecInputFloatSign(stream, spec, floatSpec) == -1) { ++ return -1; ++ } ++ if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ return 0; ++} ++ ++SECUREC_INLINE int SecInputFloatFractional(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) ++{ ++ if (SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ if (SecIsFloatDecimal((SecChar)spec->ch) == 0) { ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ return 0; ++ } ++ SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ ++ /* Now check for decimal */ ++ floatSpec->floatStr[floatSpec->floatStrUsedLen] = (SecChar)spec->ch; ++ ++floatSpec->floatStrUsedLen; ++ if (SecExtendFloatLen(floatSpec) != 0) { ++ return -1; ++ } ++ if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++SECUREC_INLINE int SecInputFloatExponent(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) ++{ ++ /* Now get exponent part */ ++ if (spec->numberState == SECUREC_NUMBER_STATE_STARTED && SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ if (spec->ch != SECUREC_CHAR('e') && spec->ch != SECUREC_CHAR('E')) { ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ return 0; ++ } ++ SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ ++ floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('e'); ++ ++floatSpec->floatStrUsedLen; ++ if (SecExtendFloatLen(floatSpec) != 0) { ++ return -1; ++ } ++ if (SecInputFloatE(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/* ++* Scan %f. ++* Return 0 OK ++*/ ++SECUREC_INLINE int SecInputFloat(SecFileStream *stream, SecScanSpec *spec, SecFloatSpec *floatSpec) ++{ ++ floatSpec->floatStrUsedLen = 0; ++ ++ /* The following code sequence is strict */ ++ if (SecInputFloatSign(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ if (SecInputFloatDigit(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ if (SecInputFloatFractional(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ if (SecInputFloatExponent(stream, spec, floatSpec) != 0) { ++ return -1; ++ } ++ ++ /* Make sure have a string terminator, buffer is large enough */ ++ floatSpec->floatStr[floatSpec->floatStrUsedLen] = SECUREC_CHAR('\0'); ++ if (spec->numberState == SECUREC_NUMBER_STATE_STARTED) { ++ return 0; ++ } ++ return -1; ++} ++#endif ++ ++#if (!defined(SECUREC_FOR_WCHAR) && SECUREC_HAVE_WCHART && SECUREC_HAVE_MBTOWC) || \ ++ (!defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION)) ++/* only multi-bytes string need isleadbyte() function */ ++SECUREC_INLINE int SecIsLeadByte(SecInt ch) ++{ ++ unsigned int c = (unsigned int)ch; ++#if !(defined(_MSC_VER) || defined(_INC_WCTYPE)) ++ return (int)(c & 0x80U); /* Use bitwise operation to check if the most significant bit is 1 */ ++#else ++ return (int)isleadbyte((int)(c & 0xffU)); /* Use bitwise operations to limit character values to valid ranges */ ++#endif ++} ++#endif ++ ++/* ++ * Parsing whether it is a wide character ++ */ ++SECUREC_INLINE void SecUpdateWcharFlagByType(SecUnsignedChar ch, SecScanSpec *spec) ++{ ++ if (spec->isWCharOrLong != 0) { ++ /* Wide character identifiers have been explicitly set by l or h flag */ ++ return; ++ } ++ ++ /* Set default flag */ ++#if defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ spec->isWCharOrLong = 1; /* On windows wide char version %c %s %[ is wide char */ ++#else ++ spec->isWCharOrLong = -1; /* On linux all version %c %s %[ is multi char */ ++#endif ++ ++ if (ch == SECUREC_CHAR('C') || ch == SECUREC_CHAR('S')) { ++#if defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ spec->isWCharOrLong = -1; /* On windows wide char version %C %S is multi char */ ++#else ++ spec->isWCharOrLong = 1; /* On linux all version %C %S is wide char */ ++#endif ++ } ++ ++ return; ++} ++/* ++ * Decode %l %ll ++ */ ++SECUREC_INLINE void SecDecodeScanQualifierL(const SecUnsignedChar **format, SecScanSpec *spec) ++{ ++ const SecUnsignedChar *fmt = *format; ++ if (*(fmt + 1) == SECUREC_CHAR('l')) { ++ spec->numberArgType = 1; ++ spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; ++ ++fmt; ++ } else { ++ spec->numberWidth = SECUREC_NUM_WIDTH_LONG; ++#if defined(SECUREC_ON_64BITS) && !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) ++ /* On window 64 system sizeof long is 32bit */ ++ spec->numberArgType = 1; ++#endif ++ spec->isWCharOrLong = 1; ++ } ++ *format = fmt; ++} ++ ++/* ++ * Decode %I %I43 %I64 %Id %Ii %Io ... ++ * Set finishFlag to 1 finish Flag ++ */ ++SECUREC_INLINE void SecDecodeScanQualifierI(const SecUnsignedChar **format, SecScanSpec *spec, int *finishFlag) ++{ ++ const SecUnsignedChar *fmt = *format; ++ if ((*(fmt + 1) == SECUREC_CHAR('6')) && ++ (*(fmt + 2) == SECUREC_CHAR('4'))) { /* Offset 2 for I64 */ ++ spec->numberArgType = 1; ++ *format = *format + 2; /* Add 2 to skip I64 point to '4' next loop will inc */ ++ } else if ((*(fmt + 1) == SECUREC_CHAR('3')) && ++ (*(fmt + 2) == SECUREC_CHAR('2'))) { /* Offset 2 for I32 */ ++ *format = *format + 2; /* Add 2 to skip I32 point to '2' next loop will inc */ ++ } else if ((*(fmt + 1) == SECUREC_CHAR('d')) || ++ (*(fmt + 1) == SECUREC_CHAR('i')) || ++ (*(fmt + 1) == SECUREC_CHAR('o')) || ++ (*(fmt + 1) == SECUREC_CHAR('x')) || ++ (*(fmt + 1) == SECUREC_CHAR('X'))) { ++ spec->numberArgType = SecNumberArgType(sizeof(void *)); ++ } else { ++ /* For %I */ ++ spec->numberArgType = SecNumberArgType(sizeof(void *)); ++ *finishFlag = 1; ++ } ++} ++ ++SECUREC_INLINE int SecDecodeScanWidth(const SecUnsignedChar **format, SecScanSpec *spec) ++{ ++ const SecUnsignedChar *fmt = *format; ++ while (SecIsDigit((SecInt)(int)(*fmt)) != 0) { ++ spec->widthSet = 1; ++ if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(spec->width)) { ++ return -1; ++ } ++ spec->width = (int)SECUREC_MUL_TEN((unsigned int)spec->width) + (unsigned char)(*fmt - SECUREC_CHAR('0')); ++ ++fmt; ++ } ++ *format = fmt; ++ return 0; ++} ++ ++/* ++ * Init default flags for each format. do not init ch this variable is context-dependent ++ */ ++SECUREC_INLINE void SecSetDefaultScanSpec(SecScanSpec *spec) ++{ ++ /* The ch and charCount member variables cannot be initialized here */ ++ spec->argPtr = NULL; ++ spec->arrayWidth = 0; ++ spec->number64 = 0; ++ spec->number = 0; ++ spec->numberWidth = SECUREC_NUM_WIDTH_INT; /* 0 = SHORT, 1 = int, > 1 long or L_DOUBLE */ ++ spec->numberArgType = 0; /* 1 for 64-bit integer, 0 otherwise */ ++ spec->width = 0; ++ spec->widthSet = 0; ++ spec->convChr = 0; ++ spec->oriConvChr = 0; ++ spec->isWCharOrLong = 0; ++ spec->suppress = 0; ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ spec->beyondMax = 0; ++#endif ++ spec->negative = 0; ++ spec->numberState = SECUREC_NUMBER_STATE_DEFAULT; ++} ++ ++/* ++ * Decode qualifier %I %L %h ... ++ * Set finishFlag to 1 finish Flag ++ */ ++SECUREC_INLINE void SecDecodeScanQualifier(const SecUnsignedChar **format, SecScanSpec *spec, int *finishFlag) ++{ ++ switch (**format) { ++ case SECUREC_CHAR('F'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('N'): ++ break; ++ case SECUREC_CHAR('h'): ++ --spec->numberWidth; /* The h for SHORT , hh for CHAR */ ++ spec->isWCharOrLong = -1; ++ break; ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++ case SECUREC_CHAR('j'): ++ spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; /* For intmax_t or uintmax_t */ ++ spec->numberArgType = 1; ++ break; ++ case SECUREC_CHAR('t'): /* fall-through */ /* FALLTHRU */ ++#endif ++#if SECUREC_IN_KERNEL ++ case SECUREC_CHAR('Z'): /* fall-through */ /* FALLTHRU */ ++#endif ++ case SECUREC_CHAR('z'): ++#ifdef SECUREC_ON_64BITS ++ spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; ++ spec->numberArgType = 1; ++#else ++ spec->numberWidth = SECUREC_NUM_WIDTH_LONG; ++#endif ++ break; ++ case SECUREC_CHAR('L'): /* For long double */ /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('q'): ++ spec->numberWidth = SECUREC_NUM_WIDTH_LONG_LONG; ++ spec->numberArgType = 1; ++ break; ++ case SECUREC_CHAR('l'): ++ SecDecodeScanQualifierL(format, spec); ++ break; ++ case SECUREC_CHAR('w'): ++ spec->isWCharOrLong = 1; ++ break; ++ case SECUREC_CHAR('*'): ++ spec->suppress = 1; ++ break; ++ case SECUREC_CHAR('I'): ++ SecDecodeScanQualifierI(format, spec, finishFlag); ++ break; ++ default: ++ *finishFlag = 1; ++ break; ++ } ++} ++/* ++ * Decode width and qualifier in format ++ */ ++SECUREC_INLINE int SecDecodeScanFlag(const SecUnsignedChar **format, SecScanSpec *spec) ++{ ++ const SecUnsignedChar *fmt = *format; ++ int finishFlag = 0; ++ ++ do { ++ ++fmt; /* First skip % , next seek fmt */ ++ /* May %*6d , so put it inside the loop */ ++ if (SecDecodeScanWidth(&fmt, spec) != 0) { ++ return -1; ++ } ++ SecDecodeScanQualifier(&fmt, spec, &finishFlag); ++ } while (finishFlag == 0); ++ *format = fmt; ++ return 0; ++} ++ ++/* ++ * Judging whether a zeroing buffer is needed according to different formats ++ */ ++SECUREC_INLINE int SecDecodeClearFormat(const SecUnsignedChar *format, int *convChr) ++{ ++ const SecUnsignedChar *fmt = format; ++ /* To lowercase */ ++ int ch = SECUREC_TO_LOWERCASE(*fmt); ++ if (!(ch == 'c' || ch == 's' || ch == SECUREC_BRACE)) { ++ return -1; /* First argument is not a string type */ ++ } ++ if (ch == SECUREC_BRACE) { ++#if !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) ++ if (*fmt == SECUREC_CHAR('{')) { ++ return -1; ++ } ++#endif ++ ++fmt; ++ if (*fmt == SECUREC_CHAR('^')) { ++ ++fmt; ++ } ++ if (*fmt == SECUREC_CHAR(']')) { ++ ++fmt; ++ } ++ while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR(']')) { ++ ++fmt; ++ } ++ if (*fmt == SECUREC_CHAR('\0')) { ++ return -1; /* Trunc'd format string */ ++ } ++ } ++ *convChr = ch; ++ return 0; ++} ++ ++/* ++ * Add L'\0' for wchar string , add '\0' for char string ++ */ ++SECUREC_INLINE void SecAddEndingZero(void *ptr, const SecScanSpec *spec) ++{ ++ if (spec->suppress == 0) { ++ *(char *)ptr = '\0'; ++#if SECUREC_HAVE_WCHART ++ if (spec->isWCharOrLong > 0) { ++ *(wchar_t UNALIGNED *)ptr = L'\0'; ++ } ++#endif ++ } ++} ++ ++SECUREC_INLINE void SecDecodeClearArg(SecScanSpec *spec, va_list argList) ++{ ++ va_list argListSave; /* Backup for argList value, this variable don't need initialized */ ++ (void)SECUREC_MEMSET_FUNC_OPT(&argListSave, 0, sizeof(va_list)); /* To clear e530 argListSave not initialized */ ++#if defined(va_copy) ++ va_copy(argListSave, argList); ++#elif defined(__va_copy) /* For vxworks */ ++ __va_copy(argListSave, argList); ++#else ++ argListSave = argList; ++#endif ++ spec->argPtr = (void *)va_arg(argListSave, void *); ++ /* Get the next argument, size of the array in characters */ ++ /* Use 0xffffffffUL mask to Support pass integer as array length */ ++ spec->arrayWidth = ((size_t)(va_arg(argListSave, size_t))) & 0xffffffffUL; ++ va_end(argListSave); ++ /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ (void)argListSave; ++} ++ ++#ifdef SECUREC_FOR_WCHAR ++/* ++ * Clean up the first %s %c buffer to zero for wchar version ++ */ ++void SecClearDestBufW(const wchar_t *buffer, const wchar_t *format, va_list argList) ++#else ++/* ++ * Clean up the first %s %c buffer to zero for char version ++ */ ++void SecClearDestBuf(const char *buffer, const char *format, va_list argList) ++#endif ++{ ++ SecScanSpec spec; ++ int convChr = 0; ++ const SecUnsignedChar *fmt = (const SecUnsignedChar *)format; ++ ++ /* Find first % */ ++ while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR('%')) { ++ ++fmt; ++ } ++ if (*fmt == SECUREC_CHAR('\0')) { ++ return; ++ } ++ ++ SecSetDefaultScanSpec(&spec); ++ if (SecDecodeScanFlag(&fmt, &spec) != 0) { ++ return; ++ } ++ ++ /* Update wchar flag for %S %C */ ++ SecUpdateWcharFlagByType(*fmt, &spec); ++ if (spec.suppress != 0) { ++ return; ++ } ++ ++ if (SecDecodeClearFormat(fmt, &convChr) != 0) { ++ return; ++ } ++ ++ if (*buffer != SECUREC_CHAR('\0') && convChr != 's') { ++ /* ++ * When buffer not empty just clear %s. ++ * Example call sscanf by argment of (" \n", "%s", s, sizeof(s)) ++ */ ++ return; ++ } ++ ++ SecDecodeClearArg(&spec, argList); ++ /* There is no need to judge the upper limit */ ++ if (spec.arrayWidth == 0 || spec.argPtr == NULL) { ++ return; ++ } ++ /* Clear one char */ ++ SecAddEndingZero(spec.argPtr, &spec); ++ return; ++} ++ ++/* ++ * Assign number to output buffer ++ */ ++SECUREC_INLINE void SecAssignNumber(const SecScanSpec *spec) ++{ ++ void *argPtr = spec->argPtr; ++ if (spec->numberArgType != 0) { ++#if defined(SECUREC_VXWORKS_PLATFORM) ++#if defined(SECUREC_VXWORKS_PLATFORM_COMP) ++ *(SecInt64 UNALIGNED *)argPtr = (SecInt64)(spec->number64); ++#else ++ /* Take number64 as unsigned number unsigned to int clear Compile warning */ ++ *(SecInt64 UNALIGNED *)argPtr = *(SecUnsignedInt64 *)(&(spec->number64)); ++#endif ++#else ++ /* Take number64 as unsigned number */ ++ *(SecInt64 UNALIGNED *)argPtr = (SecInt64)(spec->number64); ++#endif ++ return; ++ } ++ if (spec->numberWidth > SECUREC_NUM_WIDTH_INT) { ++ /* Take number as unsigned number */ ++ *(long UNALIGNED *)argPtr = (long)(spec->number); ++ } else if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { ++ *(int UNALIGNED *)argPtr = (int)(spec->number); ++ } else if (spec->numberWidth == SECUREC_NUM_WIDTH_SHORT) { ++ /* Take number as unsigned number */ ++ *(short UNALIGNED *)argPtr = (short)(spec->number); ++ } else { /* < 0 for hh format modifier */ ++ /* Take number as unsigned number */ ++ *(char UNALIGNED *)argPtr = (char)(spec->number); ++ } ++} ++ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++/* ++ * Judge the long bit width ++ */ ++SECUREC_INLINE int SecIsLongBitEqual(int bitNum) ++{ ++ return (int)((unsigned int)bitNum == SECUREC_LONG_BIT_NUM); ++} ++#endif ++ ++/* ++ * Convert hexadecimal characters to decimal value ++ */ ++SECUREC_INLINE int SecHexValueOfChar(SecInt ch) ++{ ++ /* Use isdigt Causing tool false alarms */ ++ return (int)((ch >= '0' && ch <= '9') ? ((unsigned char)ch - '0') : ++ ((((unsigned char)ch | (unsigned char)('a' - 'A')) - ('a')) + 10)); /* Adding 10 is to hex value */ ++} ++ ++/* ++ * Parse decimal character to integer for 32bit . ++ */ ++static void SecDecodeNumberDecimal(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ unsigned long decimalEdge = SECUREC_MAX_32BITS_VALUE_DIV_TEN; ++#ifdef SECUREC_ON_64BITS ++ if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { ++ decimalEdge = (unsigned long)SECUREC_MAX_64BITS_VALUE_DIV_TEN; ++ } ++#endif ++ if (spec->number > decimalEdge) { ++ spec->beyondMax = 1; ++ } ++#endif ++ spec->number = SECUREC_MUL_TEN(spec->number); ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (spec->number == SECUREC_MUL_TEN(decimalEdge)) { ++ /* This code is specially converted to unsigned long type for compatibility */ ++ SecUnsignedInt64 number64As = (unsigned long)SECUREC_MAX_64BITS_VALUE - spec->number; ++ if (number64As < (SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')) { ++ spec->beyondMax = 1; ++ } ++ } ++#endif ++ spec->number += ((unsigned long)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); ++} ++ ++/* ++ * Parse Hex character to integer for 32bit . ++ */ ++static void SecDecodeNumberHex(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (SECUREC_LONG_HEX_BEYOND_MAX(spec->number)) { ++ spec->beyondMax = 1; ++ } ++#endif ++ spec->number = SECUREC_MUL_SIXTEEN(spec->number); ++ spec->number += (unsigned long)(unsigned int)SecHexValueOfChar(spec->ch); ++} ++ ++/* ++ * Parse Octal character to integer for 32bit . ++ */ ++static void SecDecodeNumberOctal(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (SECUREC_LONG_OCTAL_BEYOND_MAX(spec->number)) { ++ spec->beyondMax = 1; ++ } ++#endif ++ spec->number = SECUREC_MUL_EIGHT(spec->number); ++ spec->number += ((unsigned long)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); ++} ++ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++/* Compatible with integer negative values other than int */ ++SECUREC_INLINE void SecFinishNumberNegativeOther(SecScanSpec *spec) ++{ ++ if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { ++ if (spec->number > SECUREC_MIN_LONG_NEG_VALUE) { ++ spec->number = SECUREC_MIN_LONG_NEG_VALUE; ++ } else { ++ spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ ++ } ++ if (spec->beyondMax != 0) { ++ if (spec->numberWidth < SECUREC_NUM_WIDTH_INT) { ++ spec->number = 0; ++ } ++ if (spec->numberWidth == SECUREC_NUM_WIDTH_LONG) { ++ spec->number = SECUREC_MIN_LONG_NEG_VALUE; ++ } ++ } ++ } else { /* For o, u, x, X, p */ ++ spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ ++ if (spec->beyondMax != 0) { ++ spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; ++ } ++ } ++} ++/* Compatible processing of integer negative numbers */ ++SECUREC_INLINE void SecFinishNumberNegativeInt(SecScanSpec *spec) ++{ ++ if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { ++#ifdef SECUREC_ON_64BITS ++ if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { ++ if ((spec->number > SECUREC_MIN_64BITS_NEG_VALUE)) { ++ spec->number = 0; ++ } else { ++ spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ ++ } ++ } ++#else ++ if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { ++ if ((spec->number > SECUREC_MIN_32BITS_NEG_VALUE)) { ++ spec->number = SECUREC_MIN_32BITS_NEG_VALUE; ++ } else { ++ spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ ++ } ++ } ++#endif ++ if (spec->beyondMax != 0) { ++#ifdef SECUREC_ON_64BITS ++ if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { ++ spec->number = 0; ++ } ++#else ++ if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { ++ spec->number = SECUREC_MIN_32BITS_NEG_VALUE; ++ } ++#endif ++ } ++ } else { /* For o, u, x, X ,p */ ++#ifdef SECUREC_ON_64BITS ++ if (spec->number > SECUREC_MAX_32BITS_VALUE_INC) { ++ spec->number = SECUREC_MAX_32BITS_VALUE; ++ } else { ++ spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ ++ } ++#else ++ spec->number = (unsigned int)(0U - (unsigned int)spec->number); /* Wrap with unsigned int numbers */ ++#endif ++ if (spec->beyondMax != 0) { ++ spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; ++ } ++ } ++} ++ ++/* Compatible with integer positive values other than int */ ++SECUREC_INLINE void SecFinishNumberPositiveOther(SecScanSpec *spec) ++{ ++ if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { ++ if (spec->number > SECUREC_MAX_LONG_POS_VALUE) { ++ spec->number = SECUREC_MAX_LONG_POS_VALUE; ++ } ++ if ((spec->beyondMax != 0 && spec->numberWidth < SECUREC_NUM_WIDTH_INT)) { ++ spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; ++ } ++ if (spec->beyondMax != 0 && spec->numberWidth == SECUREC_NUM_WIDTH_LONG) { ++ spec->number = SECUREC_MAX_LONG_POS_VALUE; ++ } ++ } else { ++ if (spec->beyondMax != 0) { ++ spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; ++ } ++ } ++} ++ ++/* Compatible processing of integer positive numbers */ ++SECUREC_INLINE void SecFinishNumberPositiveInt(SecScanSpec *spec) ++{ ++ if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { ++#ifdef SECUREC_ON_64BITS ++ if (SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { ++ if (spec->number > SECUREC_MAX_64BITS_POS_VALUE) { ++ spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; ++ } ++ } ++ if (spec->beyondMax != 0 && SecIsLongBitEqual(SECUREC_LP64_BIT_WIDTH) != 0) { ++ spec->number = (unsigned long)SECUREC_MAX_64BITS_VALUE; ++ } ++#else ++ if (SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { ++ if (spec->number > SECUREC_MAX_32BITS_POS_VALUE) { ++ spec->number = SECUREC_MAX_32BITS_POS_VALUE; ++ } ++ } ++ if (spec->beyondMax != 0 && SecIsLongBitEqual(SECUREC_LP32_BIT_WIDTH) != 0) { ++ spec->number = SECUREC_MAX_32BITS_POS_VALUE; ++ } ++#endif ++ } else { /* For o,u,x,X,p */ ++ if (spec->beyondMax != 0) { ++ spec->number = SECUREC_MAX_32BITS_VALUE; ++ } ++ } ++} ++ ++#endif ++ ++/* ++ * Parse decimal character to integer for 64bit . ++ */ ++static void SecDecodeNumber64Decimal(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (spec->number64 > SECUREC_MAX_64BITS_VALUE_DIV_TEN) { ++ spec->beyondMax = 1; ++ } ++#endif ++ spec->number64 = SECUREC_MUL_TEN(spec->number64); ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (spec->number64 == SECUREC_MAX_64BITS_VALUE_CUT_LAST_DIGIT) { ++ SecUnsignedInt64 number64As = (SecUnsignedInt64)SECUREC_MAX_64BITS_VALUE - spec->number64; ++ if (number64As < (SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')) { ++ spec->beyondMax = 1; ++ } ++ } ++#endif ++ spec->number64 += ((SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); ++} ++ ++/* ++ * Parse Hex character to integer for 64bit . ++ */ ++static void SecDecodeNumber64Hex(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (SECUREC_QWORD_HEX_BEYOND_MAX(spec->number64)) { ++ spec->beyondMax = 1; ++ } ++#endif ++ spec->number64 = SECUREC_MUL_SIXTEEN(spec->number64); ++ spec->number64 += (SecUnsignedInt64)(unsigned int)SecHexValueOfChar(spec->ch); ++} ++ ++/* ++ * Parse Octal character to integer for 64bit . ++ */ ++static void SecDecodeNumber64Octal(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (SECUREC_QWORD_OCTAL_BEYOND_MAX(spec->number64)) { ++ spec->beyondMax = 1; ++ } ++#endif ++ spec->number64 = SECUREC_MUL_EIGHT(spec->number64); ++ spec->number64 += ((SecUnsignedInt64)(SecUnsignedInt)spec->ch - (SecUnsignedInt)SECUREC_CHAR('0')); ++} ++ ++#define SECUREC_DECODE_NUMBER_FUNC_NUM 2 ++ ++/* ++ * Parse 64-bit integer formatted input, return 0 when ch is a number. ++ */ ++SECUREC_INLINE int SecDecodeNumber(SecScanSpec *spec) ++{ ++ /* Function name cannot add address symbol, causing 546 alarm */ ++ static void (* const secDecodeNumberHex[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { ++ SecDecodeNumberHex, SecDecodeNumber64Hex ++ }; ++ static void (* const secDecodeNumberOctal[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { ++ SecDecodeNumberOctal, SecDecodeNumber64Octal ++ }; ++ static void (* const secDecodeNumberDecimal[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { ++ SecDecodeNumberDecimal, SecDecodeNumber64Decimal ++ }; ++ if (spec->convChr == 'x' || spec->convChr == 'p') { ++ if (SecIsXdigit(spec->ch) != 0) { ++ (*secDecodeNumberHex[spec->numberArgType])(spec); ++ } else { ++ return -1; ++ } ++ return 0; ++ } ++ if (SecIsDigit(spec->ch) == 0) { ++ return -1; ++ } ++ if (spec->convChr == 'o') { ++ if (spec->ch < SECUREC_CHAR('8')) { /* Octal maximum limit '8' */ ++ (*secDecodeNumberOctal[spec->numberArgType])(spec); ++ } else { ++ return -1; ++ } ++ } else { /* The convChr is 'd' */ ++ (*secDecodeNumberDecimal[spec->numberArgType])(spec); ++ } ++ return 0; ++} ++ ++/* ++ * Complete the final 32-bit integer formatted input ++ */ ++static void SecFinishNumber(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (spec->negative != 0) { ++ if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { ++ SecFinishNumberNegativeInt(spec); ++ } else { ++ SecFinishNumberNegativeOther(spec); ++ } ++ } else { ++ if (spec->numberWidth == SECUREC_NUM_WIDTH_INT) { ++ SecFinishNumberPositiveInt(spec); ++ } else { ++ SecFinishNumberPositiveOther(spec); ++ } ++ } ++#else ++ if (spec->negative != 0) { ++#if defined(__hpux) ++ if (spec->oriConvChr != 'p') { ++ spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ ++ } ++#else ++ spec->number = (unsigned long)(0U - spec->number); /* Wrap with unsigned long numbers */ ++#endif ++ } ++#endif ++ return; ++} ++ ++/* ++ * Complete the final 64-bit integer formatted input ++ */ ++static void SecFinishNumber64(SecScanSpec *spec) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && !(defined(SECUREC_ON_UNIX))) ++ if (spec->negative != 0) { ++ if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { ++ if (spec->number64 > SECUREC_MIN_64BITS_NEG_VALUE) { ++ spec->number64 = SECUREC_MIN_64BITS_NEG_VALUE; ++ } else { ++ spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ ++ } ++ if (spec->beyondMax != 0) { ++ spec->number64 = SECUREC_MIN_64BITS_NEG_VALUE; ++ } ++ } else { /* For o, u, x, X, p */ ++ spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ ++ if (spec->beyondMax != 0) { ++ spec->number64 = SECUREC_MAX_64BITS_VALUE; ++ } ++ } ++ } else { ++ if (SECUREC_CONVERT_IS_SIGNED(spec->oriConvChr)) { ++ if (spec->number64 > SECUREC_MAX_64BITS_POS_VALUE) { ++ spec->number64 = SECUREC_MAX_64BITS_POS_VALUE; ++ } ++ if (spec->beyondMax != 0) { ++ spec->number64 = SECUREC_MAX_64BITS_POS_VALUE; ++ } ++ } else { ++ if (spec->beyondMax != 0) { ++ spec->number64 = SECUREC_MAX_64BITS_VALUE; ++ } ++ } ++ } ++#else ++ if (spec->negative != 0) { ++#if defined(__hpux) ++ if (spec->oriConvChr != 'p') { ++ spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ ++ } ++#else ++ spec->number64 = (SecUnsignedInt64)(0U - spec->number64); /* Wrap with unsigned int64 numbers */ ++#endif ++ } ++#endif ++ return; ++} ++ ++#if SECUREC_ENABLE_SCANF_FILE ++ ++/* ++ * Adjust the pointer position of the file stream ++ */ ++SECUREC_INLINE void SecSeekStream(SecFileStream *stream) ++{ ++ if (stream->count == 0) { ++ if (feof(stream->pf) != 0) { ++ /* File pointer at the end of file, don't need to seek back */ ++ stream->base[0] = '\0'; ++ return; ++ } ++ } ++ /* Seek to original position, for file read, but nothing to input */ ++ if (fseek(stream->pf, stream->oriFilePos, SEEK_SET) != 0) { ++ /* Seek failed, ignore it */ ++ stream->oriFilePos = 0; ++ return; ++ } ++ ++ if (stream->fileRealRead > 0) { /* Do not seek without input data */ ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ size_t residue = stream->fileRealRead % SECUREC_BUFFERED_BLOK_SIZE; ++ size_t loops; ++ for (loops = 0; loops < (stream->fileRealRead / SECUREC_BUFFERED_BLOK_SIZE); ++loops) { ++ if (fread(stream->base, (size_t)SECUREC_BUFFERED_BLOK_SIZE, (size_t)1, stream->pf) != (size_t)1) { ++ break; ++ } ++ } ++ if (residue != 0) { ++ long curFilePos; ++ if (fread(stream->base, residue, (size_t)1, stream->pf) != (size_t)1) { ++ return; ++ } ++ curFilePos = ftell(stream->pf); ++ if (curFilePos < stream->oriFilePos || ++ (size_t)(unsigned long)(curFilePos - stream->oriFilePos) < stream->fileRealRead) { ++ /* Try to remedy the problem */ ++ long adjustNum = (long)(stream->fileRealRead - (size_t)(unsigned long)(curFilePos - stream->oriFilePos)); ++ (void)fseek(stream->pf, adjustNum, SEEK_CUR); ++ } ++ } ++#else ++ /* Seek from oriFilePos. Regardless of the integer sign problem, call scanf will not read very large data */ ++ if (fseek(stream->pf, (long)stream->fileRealRead, SEEK_CUR) != 0) { ++ /* Seek failed, ignore it */ ++ stream->oriFilePos = 0; ++ return; ++ } ++#endif ++ } ++ return; ++} ++ ++/* ++ * Adjust the pointer position of the file stream and free memory ++ */ ++SECUREC_INLINE void SecAdjustStream(SecFileStream *stream) ++{ ++ if ((stream->flag & SECUREC_FILE_STREAM_FLAG) != 0 && stream->base != NULL) { ++ SecSeekStream(stream); ++ SECUREC_FREE(stream->base); ++ stream->base = NULL; ++ } ++ return; ++} ++#endif ++ ++SECUREC_INLINE void SecSkipSpaceFormat(const SecUnsignedChar **format) ++{ ++ const SecUnsignedChar *fmt = *format; ++ while (SecIsSpace((SecInt)(int)(*fmt)) != 0) { ++ ++fmt; ++ } ++ *format = fmt; ++} ++ ++#if !defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION) ++/* ++ * Handling multi-character characters ++ */ ++SECUREC_INLINE int SecDecodeLeadByte(SecScanSpec *spec, const SecUnsignedChar **format, SecFileStream *stream) ++{ ++#if SECUREC_HAVE_MBTOWC ++ const SecUnsignedChar *fmt = *format; ++ int ch1 = (int)spec->ch; ++ int ch2 = SecGetChar(stream, &(spec->charCount)); ++ spec->ch = (SecInt)ch2; ++ if (*fmt == SECUREC_CHAR('\0') || (int)(*fmt) != ch2) { ++ /* in console mode, ungetc twice may cause problem */ ++ SecUnGetChar(ch2, stream, &(spec->charCount)); ++ SecUnGetChar(ch1, stream, &(spec->charCount)); ++ return -1; ++ } ++ ++fmt; ++ if ((unsigned int)MB_CUR_MAX >= SECUREC_UTF8_BOM_HEADER_SIZE && ++ (((unsigned char)ch1 & SECUREC_UTF8_LEAD_1ST) == SECUREC_UTF8_LEAD_1ST) && ++ (((unsigned char)ch2 & SECUREC_UTF8_LEAD_2ND) == SECUREC_UTF8_LEAD_2ND)) { ++ /* This char is very likely to be a UTF-8 char */ ++ wchar_t tempWChar; ++ char temp[SECUREC_MULTI_BYTE_MAX_LEN]; ++ int ch3 = (int)SecGetChar(stream, &(spec->charCount)); ++ spec->ch = (SecInt)ch3; ++ if (*fmt == SECUREC_CHAR('\0') || (int)(*fmt) != ch3) { ++ SecUnGetChar(ch3, stream, &(spec->charCount)); ++ return -1; ++ } ++ temp[0] = (char)ch1; ++ temp[1] = (char)ch2; /* 1 index of second character */ ++ temp[2] = (char)ch3; /* 2 index of third character */ ++ temp[3] = '\0'; /* 3 of string terminator position */ ++ if (mbtowc(&tempWChar, temp, sizeof(temp)) > 0) { ++ /* Succeed */ ++ ++fmt; ++ --spec->charCount; ++ } else { ++ SecUnGetChar(ch3, stream, &(spec->charCount)); ++ } ++ } ++ --spec->charCount; /* Only count as one character read */ ++ *format = fmt; ++ return 0; ++#else ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ (void)format; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ return -1; ++#endif ++} ++ ++SECUREC_INLINE int SecFilterWcharInFormat(SecScanSpec *spec, const SecUnsignedChar **format, SecFileStream *stream) ++{ ++ if (SecIsLeadByte(spec->ch) != 0) { ++ if (SecDecodeLeadByte(spec, format, stream) != 0) { ++ return -1; ++ } ++ } ++ return 0; ++} ++#endif ++ ++/* ++ * Resolving sequence of characters from %[ format, format wile point to ']' ++ */ ++SECUREC_INLINE int SecSetupBracketTable(const SecUnsignedChar **format, SecBracketTable *bracketTable) ++{ ++ const SecUnsignedChar *fmt = *format; ++ SecUnsignedChar prevChar = 0; ++#if !(defined(SECUREC_COMPATIBLE_WIN_FORMAT)) ++ if (*fmt == SECUREC_CHAR('{')) { ++ return -1; ++ } ++#endif ++ /* For building "table" data */ ++ ++fmt; /* Skip [ */ ++ bracketTable->mask = 0; /* Set all bits to 0 */ ++ if (*fmt == SECUREC_CHAR('^')) { ++ ++fmt; ++ bracketTable->mask = (unsigned char)0xffU; /* Use 0xffU to set all bits to 1 */ ++ } ++ if (*fmt == SECUREC_CHAR(']')) { ++ prevChar = SECUREC_CHAR(']'); ++ ++fmt; ++ SecBracketSetBit(bracketTable->table, SECUREC_CHAR(']')); ++ } ++ while (*fmt != SECUREC_CHAR('\0') && *fmt != SECUREC_CHAR(']')) { ++ SecUnsignedChar expCh = *fmt; ++ ++fmt; ++ if (expCh != SECUREC_CHAR('-') || prevChar == 0 || *fmt == SECUREC_CHAR(']')) { ++ /* Normal character */ ++ prevChar = expCh; ++ SecBracketSetBit(bracketTable->table, expCh); ++ } else { ++ /* For %[a-z] */ ++ expCh = *fmt; /* Get end of range */ ++ ++fmt; ++ if (prevChar <= expCh) { /* %[a-z] %[a-a] */ ++ SecBracketSetBitRange(bracketTable->table, prevChar, expCh); ++ } else { ++ /* For %[z-a] */ ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ /* Swap start and end characters */ ++ SecBracketSetBitRange(bracketTable->table, expCh, prevChar); ++#else ++ SecBracketSetBit(bracketTable->table, SECUREC_CHAR('-')); ++ SecBracketSetBit(bracketTable->table, expCh); ++#endif ++ } ++ prevChar = 0; ++ } ++ } ++ *format = fmt; ++ return 0; ++} ++ ++#ifdef SECUREC_FOR_WCHAR ++SECUREC_INLINE int SecInputForWchar(SecScanSpec *spec) ++{ ++ void *endPtr = spec->argPtr; ++ if (spec->isWCharOrLong > 0) { ++ *(wchar_t UNALIGNED *)endPtr = (wchar_t)spec->ch; ++ endPtr = (wchar_t *)endPtr + 1; ++ --spec->arrayWidth; ++ } else { ++#if SECUREC_HAVE_WCTOMB ++ int temp; ++ char tmpBuf[SECUREC_MB_LEN + 1]; ++ SECUREC_MASK_MSVC_CRT_WARNING temp = wctomb(tmpBuf, (wchar_t)spec->ch); ++ SECUREC_END_MASK_MSVC_CRT_WARNING ++ if (temp <= 0 || (size_t)(unsigned int)temp > sizeof(tmpBuf)) { ++ /* If wctomb error, then ignore character */ ++ return 0; ++ } ++ if (((size_t)(unsigned int)temp) > spec->arrayWidth) { ++ return -1; ++ } ++ if (memcpy_s(endPtr, spec->arrayWidth, tmpBuf, (size_t)(unsigned int)temp) != EOK) { ++ return -1; ++ } ++ endPtr = (char *)endPtr + temp; ++ spec->arrayWidth -= (size_t)(unsigned int)temp; ++#else ++ return -1; ++#endif ++ } ++ spec->argPtr = endPtr; ++ return 0; ++} ++#endif ++ ++#ifndef SECUREC_FOR_WCHAR ++#if SECUREC_HAVE_WCHART ++SECUREC_INLINE wchar_t SecConvertInputCharToWchar(SecScanSpec *spec, SecFileStream *stream) ++{ ++ wchar_t tempWChar = L'?'; /* Set default char is ? */ ++#if SECUREC_HAVE_MBTOWC ++ char temp[SECUREC_MULTI_BYTE_MAX_LEN + 1]; ++ temp[0] = (char)spec->ch; ++ temp[1] = '\0'; ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ if (SecIsLeadByte(spec->ch) != 0) { ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ temp[1] = (char)spec->ch; ++ temp[2] = '\0'; /* 2 of string terminator position */ ++ } ++ if (mbtowc(&tempWChar, temp, sizeof(temp)) <= 0) { ++ /* No string termination error for tool */ ++ tempWChar = L'?'; ++ } ++#else ++ if (SecIsLeadByte(spec->ch) != 0) { ++ int convRes = 0; ++ int di = 1; ++ /* On Linux like system, the string is encoded in UTF-8 */ ++ while (convRes <= 0 && di < (int)MB_CUR_MAX && di < SECUREC_MULTI_BYTE_MAX_LEN) { ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ temp[di] = (char)spec->ch; ++ ++di; ++ temp[di] = '\0'; ++ convRes = mbtowc(&tempWChar, temp, sizeof(temp)); ++ } ++ if (convRes <= 0) { ++ tempWChar = L'?'; ++ } ++ } else { ++ if (mbtowc(&tempWChar, temp, sizeof(temp)) <= 0) { ++ tempWChar = L'?'; ++ } ++ } ++#endif ++#else ++ (void)spec; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++#endif /* SECUREC_HAVE_MBTOWC */ ++ ++ return tempWChar; ++} ++#endif /* SECUREC_HAVE_WCHART */ ++ ++SECUREC_INLINE int SecInputForChar(SecScanSpec *spec, SecFileStream *stream) ++{ ++ void *endPtr = spec->argPtr; ++ if (spec->isWCharOrLong > 0) { ++#if SECUREC_HAVE_WCHART ++ *(wchar_t UNALIGNED *)endPtr = SecConvertInputCharToWchar(spec, stream); ++ endPtr = (wchar_t *)endPtr + 1; ++ --spec->arrayWidth; ++#else ++ (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ return -1; ++#endif ++ } else { ++ *(char *)endPtr = (char)spec->ch; ++ endPtr = (char *)endPtr + 1; ++ --spec->arrayWidth; ++ } ++ spec->argPtr = endPtr; ++ return 0; ++} ++#endif ++ ++/* ++ * Scan digital part of %d %i %o %u %x %p. ++ * Return 0 OK ++ */ ++SECUREC_INLINE int SecInputNumberDigital(SecFileStream *stream, SecScanSpec *spec) ++{ ++ static void (* const secFinishNumber[SECUREC_DECODE_NUMBER_FUNC_NUM])(SecScanSpec *spec) = { ++ SecFinishNumber, SecFinishNumber64 ++ }; ++ while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ /* Decode ch to number */ ++ if (SecDecodeNumber(spec) != 0) { ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ break; ++ } ++ SECUREC_FILED_WIDTH_DEC(spec); /* Must be behind un get char, otherwise the logic is incorrect */ ++ spec->numberState = SECUREC_NUMBER_STATE_STARTED; ++ } ++ /* Handling integer negative numbers and beyond max */ ++ (*secFinishNumber[spec->numberArgType])(spec); ++ if (spec->numberState == SECUREC_NUMBER_STATE_STARTED) { ++ return 0; ++ } ++ return -1; ++} ++ ++/* ++ * Scan %d %i %o %u %x %p. ++ * Return 0 OK ++ */ ++SECUREC_INLINE int SecInputNumber(SecFileStream *stream, SecScanSpec *spec) ++{ ++ /* Character already read */ ++ if (spec->ch == SECUREC_CHAR('+') || spec->ch == SECUREC_CHAR('-')) { ++ if (spec->ch == SECUREC_CHAR('-')) { ++ spec->negative = 1; ++#if SECUREC_IN_KERNEL ++ /* In kernel Refuse to enter negative number */ ++ if (SECUREC_CONVERT_IS_UNSIGNED(spec->oriConvChr)) { ++ return -1; ++ } ++#endif ++ } ++ SECUREC_FILED_WIDTH_DEC(spec); /* Do not need to check width here, must be greater than 0 */ ++ spec->ch = SecGetChar(stream, &(spec->charCount)); /* Eat + or - */ ++ spec->ch = SecGetChar(stream, &(spec->charCount)); /* Get next character, used for the '0' judgments */ ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); /* Not sure if it was actually read, so push back */ ++ } ++ ++ if (spec->oriConvChr == 'i') { ++ spec->convChr = 'd'; /* The i could be d, o, or x, use d as default */ ++ } ++ ++ if (spec->ch == SECUREC_CHAR('0') && (spec->oriConvChr == 'x' || spec->oriConvChr == 'i') && ++ SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ /* Input string begin with 0, may be 0x123 0X123 0123 0x 01 0yy 09 0 0ab 00 */ ++ SECUREC_FILED_WIDTH_DEC(spec); ++ spec->ch = SecGetChar(stream, &(spec->charCount)); /* ch is '0' */ ++ ++ /* Read only '0' due to width limitation */ ++ if (!SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ /* The number or number64 in spec has been set 0 */ ++ return 0; ++ } ++ ++ spec->ch = SecGetChar(stream, &(spec->charCount)); /* Get next char to check x or X, do not dec width */ ++ if ((SecChar)spec->ch == SECUREC_CHAR('x') || (SecChar)spec->ch == SECUREC_CHAR('X')) { ++ spec->convChr = 'x'; ++ SECUREC_FILED_WIDTH_DEC(spec); /* Make incorrect width for x or X */ ++ } else { ++ if (spec->oriConvChr == 'i') { ++ spec->convChr = 'o'; ++ } ++ /* For "0y" "08" "01" "0a" ... ,push the 'y' '8' '1' 'a' back */ ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ /* Since 0 has been read, it indicates that a valid character has been read */ ++ spec->numberState = SECUREC_NUMBER_STATE_STARTED; ++ } ++ } ++ return SecInputNumberDigital(stream, spec); ++} ++ ++/* ++ * Scan %c %s %[ ++ * Return 0 OK ++ */ ++SECUREC_INLINE int SecInputString(SecFileStream *stream, SecScanSpec *spec, ++ const SecBracketTable *bracketTable, int *doneCount) ++{ ++ void *startPtr = spec->argPtr; ++ int suppressed = 0; ++ int errNoMem = 0; ++ ++ while (SECUREC_FILED_WIDTH_ENOUGH(spec)) { ++ SECUREC_FILED_WIDTH_DEC(spec); ++ spec->ch = SecGetChar(stream, &(spec->charCount)); ++ /* ++ * The char condition or string condition and bracket condition. ++ * Only supports wide characters with a maximum length of two bytes ++ */ ++ if (spec->ch != SECUREC_EOF && (SecCanInputCharacter(spec->convChr) != 0 || ++ SecCanInputString(spec->convChr, spec->ch) != 0 || ++ SecCanInputForBracket(spec->convChr, spec->ch, bracketTable) != 0)) { ++ if (spec->suppress != 0) { ++ /* Used to identify processed data for %*, use argPtr to identify will cause 613, so use suppressed */ ++ suppressed = 1; ++ continue; ++ } ++ /* Now suppress is not set */ ++ if (spec->arrayWidth == 0) { ++ errNoMem = 1; /* We have exhausted the user's buffer */ ++ break; ++ } ++#ifdef SECUREC_FOR_WCHAR ++ errNoMem = SecInputForWchar(spec); ++#else ++ errNoMem = SecInputForChar(spec, stream); ++#endif ++ if (errNoMem != 0) { ++ break; ++ } ++ } else { ++ SecUnGetChar(spec->ch, stream, &(spec->charCount)); ++ break; ++ } ++ } ++ ++ if (errNoMem != 0) { ++ /* In case of error, blank out the input buffer */ ++ SecAddEndingZero(startPtr, spec); ++ return -1; ++ } ++ if ((spec->suppress != 0 && suppressed == 0) || ++ (spec->suppress == 0 && startPtr == spec->argPtr)) { ++ /* No input was scanned */ ++ return -1; ++ } ++ if (spec->convChr != 'c') { ++ /* Add null-terminate for strings */ ++ SecAddEndingZero(spec->argPtr, spec); ++ } ++ if (spec->suppress == 0) { ++ *doneCount = *doneCount + 1; ++ } ++ return 0; ++} ++ ++#ifdef SECUREC_FOR_WCHAR ++/* ++ * Alloce buffer for wchar version of %[. ++ * Return 0 OK ++ */ ++SECUREC_INLINE int SecAllocBracketTable(SecBracketTable *bracketTable) ++{ ++ if (bracketTable->table == NULL) { ++ /* Table should be freed after use */ ++ bracketTable->table = (unsigned char *)SECUREC_MALLOC(SECUREC_BRACKET_TABLE_SIZE); ++ if (bracketTable->table == NULL) { ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/* ++ * Free buffer for wchar version of %[ ++ */ ++SECUREC_INLINE void SecFreeBracketTable(SecBracketTable *bracketTable) ++{ ++ if (bracketTable->table != NULL) { ++ SECUREC_FREE(bracketTable->table); ++ bracketTable->table = NULL; ++ } ++} ++#endif ++ ++#ifdef SECUREC_FOR_WCHAR ++/* ++ * Formatting input core functions for wchar version.Called by a function such as vswscanf_s ++ */ ++int SecInputSW(SecFileStream *stream, const wchar_t *cFormat, va_list argList) ++#else ++/* ++ * Formatting input core functions for char version.Called by a function such as vsscanf_s ++ */ ++int SecInputS(SecFileStream *stream, const char *cFormat, va_list argList) ++#endif ++{ ++ const SecUnsignedChar *format = (const SecUnsignedChar *)cFormat; ++ SecBracketTable bracketTable = SECUREC_INIT_BRACKET_TABLE; ++ SecScanSpec spec; ++ int doneCount = 0; ++ int formatError = 0; ++ int paraIsNull = 0; ++ int match = 0; /* When % is found , inc this value */ ++ int errRet = 0; ++#if SECUREC_ENABLE_SCANF_FLOAT ++ SecFloatSpec floatSpec; ++ SecInitFloatSpec(&floatSpec); ++#endif ++ spec.ch = 0; /* Need to initialize to 0 */ ++ spec.charCount = 0; /* Need to initialize to 0 */ ++ ++ /* Format must not NULL, use err < 1 to claer 845 */ ++ while (errRet < 1 && *format != SECUREC_CHAR('\0')) { ++ /* Skip space in format and space in input */ ++ if (SecIsSpace((SecInt)(int)(*format)) != 0) { ++ /* Read first no space char */ ++ spec.ch = SecSkipSpaceChar(stream, &(spec.charCount)); ++ /* Read the EOF cannot be returned directly here, because the case of " %n" needs to be handled */ ++ /* Put fist no space char backup. put EOF back is also OK, and to modify the character count */ ++ SecUnGetChar(spec.ch, stream, &(spec.charCount)); ++ SecSkipSpaceFormat(&format); ++ continue; ++ } ++ ++ if (*format != SECUREC_CHAR('%')) { ++ spec.ch = SecGetChar(stream, &(spec.charCount)); ++ if ((int)(*format) != (int)(spec.ch)) { ++ SecUnGetChar(spec.ch, stream, &(spec.charCount)); ++ break; ++ } ++ ++format; ++#if !defined(SECUREC_FOR_WCHAR) && defined(SECUREC_COMPATIBLE_VERSION) ++ if (SecFilterWcharInFormat(&spec, &format, stream) != 0) { ++ break; ++ } ++#endif ++ continue; ++ } ++ ++ /* Now *format is % */ ++ /* Set default value for each % */ ++ SecSetDefaultScanSpec(&spec); ++ if (SecDecodeScanFlag(&format, &spec) != 0) { ++ formatError = 1; ++ ++errRet; ++ continue; ++ } ++ if (!SECUREC_FILED_WIDTH_ENOUGH(&spec)) { ++ /* 0 width in format */ ++ ++errRet; ++ continue; ++ } ++ ++ /* Update wchar flag for %S %C */ ++ SecUpdateWcharFlagByType(*format, &spec); ++ ++ spec.convChr = SECUREC_TO_LOWERCASE(*format); ++ spec.oriConvChr = spec.convChr; /* convChr may be modified to handle integer logic */ ++ if (spec.convChr != 'n') { ++ if (spec.convChr != 'c' && spec.convChr != SECUREC_BRACE) { ++ spec.ch = SecSkipSpaceChar(stream, &(spec.charCount)); ++ } else { ++ spec.ch = SecGetChar(stream, &(spec.charCount)); ++ } ++ if (spec.ch == SECUREC_EOF) { ++ ++errRet; ++ continue; ++ } ++ } ++ ++ /* Now no 0 width in format and get one char from input */ ++ switch (spec.oriConvChr) { ++ case 'c': /* Also 'C' */ ++ if (spec.widthSet == 0) { ++ spec.widthSet = 1; ++ spec.width = 1; ++ } ++ /* fall-through */ /* FALLTHRU */ ++ case 's': /* Also 'S': */ ++ /* fall-through */ /* FALLTHRU */ ++ case SECUREC_BRACE: ++ /* Unset last char to stream */ ++ SecUnGetChar(spec.ch, stream, &(spec.charCount)); ++ /* Check dest buffer and size */ ++ if (spec.suppress == 0) { ++ spec.argPtr = (void *)va_arg(argList, void *); ++ if (spec.argPtr == NULL) { ++ paraIsNull = 1; ++ ++errRet; ++ continue; ++ } ++ /* Get the next argument, size of the array in characters */ ++ spec.arrayWidth = SECUREC_GET_ARRAYWIDTH(argList); ++ if (SECUREC_ARRAY_WIDTH_IS_WRONG(spec)) { ++ /* Do not clear buffer just go error */ ++ ++errRet; ++ continue; ++ } ++ /* One element is needed for '\0' for %s and %[ */ ++ if (spec.convChr != 'c') { ++ --spec.arrayWidth; ++ } ++ } else { ++ /* Set argPtr to NULL is necessary, in supress mode we don't use argPtr to store data */ ++ spec.argPtr = NULL; ++ } ++ ++ if (spec.convChr == SECUREC_BRACE) { ++ /* Malloc when first %[ is meet for wchar version */ ++#ifdef SECUREC_FOR_WCHAR ++ if (SecAllocBracketTable(&bracketTable) != 0) { ++ ++errRet; ++ continue; ++ } ++#endif ++ (void)SECUREC_MEMSET_FUNC_OPT(bracketTable.table, 0, (size_t)SECUREC_BRACKET_TABLE_SIZE); ++ if (SecSetupBracketTable(&format, &bracketTable) != 0) { ++ ++errRet; ++ continue; ++ } ++ ++ if (*format == SECUREC_CHAR('\0')) { ++ /* Default add string terminator */ ++ SecAddEndingZero(spec.argPtr, &spec); ++ ++errRet; ++ /* Truncated format */ ++ continue; ++ } ++ } ++ ++ /* Set completed. Now read string or character */ ++ if (SecInputString(stream, &spec, &bracketTable, &doneCount) != 0) { ++ ++errRet; ++ continue; ++ } ++ break; ++ case 'p': ++ /* Make %hp same as %p */ ++ spec.numberWidth = SECUREC_NUM_WIDTH_INT; ++#ifdef SECUREC_ON_64BITS ++ spec.numberArgType = 1; ++#endif ++ /* fall-through */ /* FALLTHRU */ ++ case 'o': /* fall-through */ /* FALLTHRU */ ++ case 'u': /* fall-through */ /* FALLTHRU */ ++ case 'd': /* fall-through */ /* FALLTHRU */ ++ case 'i': /* fall-through */ /* FALLTHRU */ ++ case 'x': ++ /* Unset last char to stream */ ++ SecUnGetChar(spec.ch, stream, &(spec.charCount)); ++ if (SecInputNumber(stream, &spec) != 0) { ++ ++errRet; ++ continue; ++ } ++ if (spec.suppress == 0) { ++ spec.argPtr = (void *)va_arg(argList, void *); ++ if (spec.argPtr == NULL) { ++ paraIsNull = 1; ++ ++errRet; ++ continue; ++ } ++ SecAssignNumber(&spec); ++ ++doneCount; ++ } ++ break; ++ case 'n': /* Char count */ ++ if (spec.suppress == 0) { ++ spec.argPtr = (void *)va_arg(argList, void *); ++ if (spec.argPtr == NULL) { ++ paraIsNull = 1; ++ ++errRet; ++ continue; ++ } ++ spec.number = (unsigned long)(unsigned int)(spec.charCount); ++ spec.numberArgType = 0; ++ SecAssignNumber(&spec); ++ } ++ break; ++ case 'e': /* fall-through */ /* FALLTHRU */ ++ case 'f': /* fall-through */ /* FALLTHRU */ ++ case 'g': /* Scan a float */ ++ /* Unset last char to stream */ ++ SecUnGetChar(spec.ch, stream, &(spec.charCount)); ++#if SECUREC_ENABLE_SCANF_FLOAT ++ if (SecInputFloat(stream, &spec, &floatSpec) != 0) { ++ ++errRet; ++ continue; ++ } ++ if (spec.suppress == 0) { ++ spec.argPtr = (void *)va_arg(argList, void *); ++ if (spec.argPtr == NULL) { ++ ++errRet; ++ paraIsNull = 1; ++ continue; ++ } ++ if (SecAssignFloat(&floatSpec, &spec) != 0) { ++ ++errRet; ++ continue; ++ } ++ ++doneCount; ++ } ++ break; ++#else /* SECUREC_ENABLE_SCANF_FLOAT */ ++ ++errRet; ++ continue; ++#endif ++ default: ++ if ((int)(*format) != (int)spec.ch) { ++ SecUnGetChar(spec.ch, stream, &(spec.charCount)); ++ formatError = 1; ++ ++errRet; ++ continue; ++ } else { ++ --match; /* Compensate for the self-increment of the following code */ ++ } ++ break; ++ } ++ ++match; ++ ++format; ++ } ++ ++#ifdef SECUREC_FOR_WCHAR ++ SecFreeBracketTable(&bracketTable); ++#endif ++ ++#if SECUREC_ENABLE_SCANF_FLOAT ++ SecFreeFloatSpec(&floatSpec, &doneCount); ++#endif ++ ++#if SECUREC_ENABLE_SCANF_FILE ++ SecAdjustStream(stream); ++#endif ++ ++ if (spec.ch == SECUREC_EOF) { ++ return ((doneCount != 0 || match != 0) ? doneCount : SECUREC_SCANF_EINVAL); ++ } ++ if (formatError != 0 || paraIsNull != 0) { ++ /* Invalid Input Format or parameter, but not meet EOF */ ++ return SECUREC_SCANF_ERROR_PARA; ++ } ++ return doneCount; ++} ++ ++#if SECUREC_ENABLE_SCANF_FILE ++/* ++ * Get char from stream use std function ++ */ ++SECUREC_INLINE SecInt SecGetCharFromStream(const SecFileStream *stream) ++{ ++ SecInt ch; ++ ch = SECUREC_GETC(stream->pf); ++ return ch; ++} ++ ++/* ++ * Try to read the BOM header, when meet a BOM head, discard it, then data is Aligned to base ++ */ ++SECUREC_INLINE void SecReadAndSkipBomHeader(SecFileStream *stream) ++{ ++ /* Use size_t type conversion to clean e747 */ ++ stream->count = fread(stream->base, (size_t)1, (size_t)SECUREC_BOM_HEADER_SIZE, stream->pf); ++ if (stream->count > SECUREC_BOM_HEADER_SIZE) { ++ stream->count = 0; ++ } ++ if (SECUREC_BEGIN_WITH_BOM(stream->base, stream->count)) { ++ /* It's BOM header, discard it */ ++ stream->count = 0; ++ } ++} ++ ++/* ++ * Get char from file stream or buffer ++ */ ++SECUREC_INLINE SecInt SecGetCharFromFile(SecFileStream *stream) ++{ ++ SecInt ch; ++ if (stream->count < sizeof(SecChar)) { ++ /* Load file to buffer */ ++ size_t len; ++ if (stream->base != NULL) { ++ /* Put the last unread data in the buffer head */ ++ for (len = 0; len < stream->count; ++len) { ++ stream->base[len] = stream->cur[len]; ++ } ++ } else { ++ stream->oriFilePos = ftell(stream->pf); /* Save original file read position */ ++ if (stream->oriFilePos == -1) { ++ /* It may be a pipe stream */ ++ stream->flag = SECUREC_PIPE_STREAM_FLAG; ++ return SecGetCharFromStream(stream); ++ } ++ /* Reserve the length of BOM head */ ++ stream->base = (char *)SECUREC_MALLOC(SECUREC_BUFFERED_BLOK_SIZE + ++ SECUREC_BOM_HEADER_SIZE + sizeof(SecChar)); /* To store '\0' and aligned to wide char */ ++ if (stream->base == NULL) { ++ return SECUREC_EOF; ++ } ++ /* First read file */ ++ if (stream->oriFilePos == 0) { ++ /* Make sure the data is aligned to base */ ++ SecReadAndSkipBomHeader(stream); ++ } ++ } ++ ++ /* Skip existing data and read data */ ++ len = fread(stream->base + stream->count, (size_t)1, (size_t)SECUREC_BUFFERED_BLOK_SIZE, stream->pf); ++ if (len > SECUREC_BUFFERED_BLOK_SIZE) { /* It won't happen, */ ++ len = 0; ++ } ++ stream->count += len; ++ stream->cur = stream->base; ++ stream->flag |= SECUREC_LOAD_FILE_TO_MEM_FLAG; ++ stream->base[stream->count] = '\0'; /* For tool Warning string null */ ++ } ++ ++ SECUREC_GET_CHAR(stream, &ch); ++ if (ch != SECUREC_EOF) { ++ stream->fileRealRead += sizeof(SecChar); ++ } ++ return ch; ++} ++#endif ++ ++/* ++ * Get char for wchar version ++ */ ++SECUREC_INLINE SecInt SecGetChar(SecFileStream *stream, int *counter) ++{ ++ *counter = *counter + 1; /* Always plus 1 */ ++ /* The main scenario is scanf str */ ++ if ((stream->flag & SECUREC_MEM_STR_FLAG) != 0) { ++ SecInt ch; ++ SECUREC_GET_CHAR(stream, &ch); ++ return ch; ++ } ++#if SECUREC_ENABLE_SCANF_FILE ++ if ((stream->flag & SECUREC_FILE_STREAM_FLAG) != 0) { ++ return SecGetCharFromFile(stream); ++ } ++ if ((stream->flag & SECUREC_PIPE_STREAM_FLAG) != 0) { ++ return SecGetCharFromStream(stream); ++ } ++#endif ++ return SECUREC_EOF; ++} ++ ++/* ++ * Unget Public realizatio char for wchar and char version ++ */ ++SECUREC_INLINE void SecUnGetCharImpl(SecInt ch, SecFileStream *stream) ++{ ++ if ((stream->flag & SECUREC_MEM_STR_FLAG) != 0) { ++ SECUREC_UN_GET_CHAR(stream); ++ return; ++ } ++#if SECUREC_ENABLE_SCANF_FILE ++ if ((stream->flag & SECUREC_LOAD_FILE_TO_MEM_FLAG) != 0) { ++ SECUREC_UN_GET_CHAR(stream); ++ if (stream->fileRealRead > 0) { ++ stream->fileRealRead -= sizeof(SecChar); ++ } ++ return; ++ } ++ if ((stream->flag & SECUREC_PIPE_STREAM_FLAG) != 0) { ++ (void)SECUREC_UN_GETC(ch, stream->pf); ++ return; ++ } ++#else ++ (void)ch; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++#endif ++} ++ ++/* ++ * Unget char for char version ++ */ ++SECUREC_INLINE void SecUnGetChar(SecInt ch, SecFileStream *stream, int *counter) ++{ ++ *counter = *counter - 1; /* Always mius 1 */ ++ if (ch != SECUREC_EOF) { ++ SecUnGetCharImpl(ch, stream); ++ } ++} ++ ++/* ++ * Skip space char by isspace ++ */ ++SECUREC_INLINE SecInt SecSkipSpaceChar(SecFileStream *stream, int *counter) ++{ ++ SecInt ch; ++ do { ++ ch = SecGetChar(stream, counter); ++ if (ch == SECUREC_EOF) { ++ break; ++ } ++ } while (SecIsSpace(ch) != 0); ++ return ch; ++} ++#endif /* INPUT_INL_5D13A042_DC3F_4ED9_A8D1_882811274C27 */ ++ +diff --git a/lib/securec/src/memcpy_s.c b/lib/securec/src/memcpy_s.c +new file mode 100644 +index 000000000000..a7fd48748e50 +--- /dev/null ++++ b/lib/securec/src/memcpy_s.c +@@ -0,0 +1,555 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: memcpy_s function ++ * Create: 2014-02-25 ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Portability ++ * [reason] Use unsafe function to implement security function to maintain platform compatibility. ++ * And sufficient input validation is performed before calling ++ */ ++ ++#include "securecutil.h" ++ ++#if SECUREC_WITH_PERFORMANCE_ADDONS ++#ifndef SECUREC_MEMCOPY_THRESHOLD_SIZE ++#define SECUREC_MEMCOPY_THRESHOLD_SIZE 64UL ++#endif ++ ++#define SECUREC_SMALL_MEM_COPY(dest, src, count) do { \ ++ if (SECUREC_ADDR_ALIGNED_8(dest) && SECUREC_ADDR_ALIGNED_8(src)) { \ ++ /* Use struct assignment */ \ ++ switch (count) { \ ++ case 1: \ ++ *(unsigned char *)(dest) = *(const unsigned char *)(src); \ ++ break; \ ++ case 2: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 2); \ ++ break; \ ++ case 3: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 3); \ ++ break; \ ++ case 4: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 4); \ ++ break; \ ++ case 5: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 5); \ ++ break; \ ++ case 6: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 6); \ ++ break; \ ++ case 7: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 7); \ ++ break; \ ++ case 8: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 8); \ ++ break; \ ++ case 9: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 9); \ ++ break; \ ++ case 10: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 10); \ ++ break; \ ++ case 11: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 11); \ ++ break; \ ++ case 12: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 12); \ ++ break; \ ++ case 13: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 13); \ ++ break; \ ++ case 14: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 14); \ ++ break; \ ++ case 15: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 15); \ ++ break; \ ++ case 16: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 16); \ ++ break; \ ++ case 17: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 17); \ ++ break; \ ++ case 18: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 18); \ ++ break; \ ++ case 19: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 19); \ ++ break; \ ++ case 20: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 20); \ ++ break; \ ++ case 21: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 21); \ ++ break; \ ++ case 22: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 22); \ ++ break; \ ++ case 23: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 23); \ ++ break; \ ++ case 24: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 24); \ ++ break; \ ++ case 25: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 25); \ ++ break; \ ++ case 26: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 26); \ ++ break; \ ++ case 27: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 27); \ ++ break; \ ++ case 28: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 28); \ ++ break; \ ++ case 29: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 29); \ ++ break; \ ++ case 30: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 30); \ ++ break; \ ++ case 31: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 31); \ ++ break; \ ++ case 32: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 32); \ ++ break; \ ++ case 33: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 33); \ ++ break; \ ++ case 34: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 34); \ ++ break; \ ++ case 35: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 35); \ ++ break; \ ++ case 36: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 36); \ ++ break; \ ++ case 37: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 37); \ ++ break; \ ++ case 38: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 38); \ ++ break; \ ++ case 39: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 39); \ ++ break; \ ++ case 40: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 40); \ ++ break; \ ++ case 41: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 41); \ ++ break; \ ++ case 42: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 42); \ ++ break; \ ++ case 43: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 43); \ ++ break; \ ++ case 44: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 44); \ ++ break; \ ++ case 45: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 45); \ ++ break; \ ++ case 46: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 46); \ ++ break; \ ++ case 47: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 47); \ ++ break; \ ++ case 48: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 48); \ ++ break; \ ++ case 49: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 49); \ ++ break; \ ++ case 50: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 50); \ ++ break; \ ++ case 51: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 51); \ ++ break; \ ++ case 52: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 52); \ ++ break; \ ++ case 53: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 53); \ ++ break; \ ++ case 54: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 54); \ ++ break; \ ++ case 55: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 55); \ ++ break; \ ++ case 56: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 56); \ ++ break; \ ++ case 57: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 57); \ ++ break; \ ++ case 58: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 58); \ ++ break; \ ++ case 59: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 59); \ ++ break; \ ++ case 60: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 60); \ ++ break; \ ++ case 61: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 61); \ ++ break; \ ++ case 62: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 62); \ ++ break; \ ++ case 63: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 63); \ ++ break; \ ++ case 64: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((dest), (src), 64); \ ++ break; \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } /* END switch */ \ ++ } else { \ ++ unsigned char *tmpDest_ = (unsigned char *)(dest); \ ++ const unsigned char *tmpSrc_ = (const unsigned char *)(src); \ ++ switch (count) { \ ++ case 64: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 63: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 62: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 61: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 60: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 59: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 58: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 57: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 56: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 55: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 54: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 53: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 52: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 51: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 50: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 49: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 48: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 47: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 46: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 45: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 44: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 43: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 42: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 41: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 40: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 39: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 38: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 37: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 36: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 35: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 34: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 33: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 32: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 31: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 30: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 29: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 28: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 27: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 26: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 25: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 24: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 23: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 22: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 21: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 20: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 19: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 18: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 17: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 16: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 15: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 14: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 13: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 12: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 11: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 10: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 9: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 8: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 7: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 6: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 5: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 4: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 3: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 2: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 1: \ ++ *(tmpDest_++) = *(tmpSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++/* ++ * Performance optimization ++ */ ++#define SECUREC_MEMCPY_OPT(dest, src, count) do { \ ++ if ((count) > SECUREC_MEMCOPY_THRESHOLD_SIZE) { \ ++ SECUREC_MEMCPY_WARP_OPT((dest), (src), (count)); \ ++ } else { \ ++ SECUREC_SMALL_MEM_COPY((dest), (src), (count)); \ ++ } \ ++} SECUREC_WHILE_ZERO ++#endif ++ ++/* ++ * Handling errors ++ */ ++SECUREC_INLINE errno_t SecMemcpyError(void *dest, size_t destMax, const void *src, size_t count) ++{ ++ if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("memcpy_s"); ++ return ERANGE; ++ } ++ if (dest == NULL || src == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("memcpy_s"); ++ if (dest != NULL) { ++ (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); ++ return EINVAL_AND_RESET; ++ } ++ return EINVAL; ++ } ++ if (count > destMax) { ++ (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); ++ SECUREC_ERROR_INVALID_RANGE("memcpy_s"); ++ return ERANGE_AND_RESET; ++ } ++ if (SECUREC_MEMORY_IS_OVERLAP(dest, src, count)) { ++ (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); ++ SECUREC_ERROR_BUFFER_OVERLAP("memcpy_s"); ++ return EOVERLAP_AND_RESET; ++ } ++ /* Count is 0 or dest equal src also ret EOK */ ++ return EOK; ++} ++ ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ /* ++ * The fread API in windows will call memcpy_s and pass 0xffffffff to destMax. ++ * To avoid the failure of fread, we don't check desMax limit. ++ */ ++#define SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count) (SECUREC_LIKELY((count) <= (destMax) && \ ++ (dest) != NULL && (src) != NULL && \ ++ (count) > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) ++#else ++#define SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count) (SECUREC_LIKELY((count) <= (destMax) && \ ++ (dest) != NULL && (src) != NULL && (destMax) <= SECUREC_MEM_MAX_LEN && \ ++ (count) > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) ++#endif ++ ++/* ++ * ++ * The memcpy_s function copies n characters from the object pointed to by src into the object pointed to by dest ++ * ++ * ++ * dest Destination buffer. ++ * destMax Size of the destination buffer. ++ * src Buffer to copy from. ++ * count Number of characters to copy ++ * ++ * ++ * dest buffer is updated. ++ * ++ * ++ * EOK Success ++ * EINVAL dest is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN ++ * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN ++ * ERANGE destMax > SECUREC_MEM_MAX_LEN or destMax is 0 ++ * ERANGE_AND_RESET count > destMax and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN ++ * and dest != NULL and src != NULL ++ * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and ++ * count <= destMax destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN and dest != NULL ++ * and src != NULL and dest != src ++ * ++ * if an error occurred, dest will be filled with 0. ++ * If the source and destination overlap, the behavior of memcpy_s is undefined. ++ * Use memmove_s to handle overlapping regions. ++ */ ++errno_t memcpy_s(void *dest, size_t destMax, const void *src, size_t count) ++{ ++ if (SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count)) { ++ SECUREC_MEMCPY_WARP_OPT(dest, src, count); ++ return EOK; ++ } ++ /* Meet some runtime violation, return error code */ ++ return SecMemcpyError(dest, destMax, src, count); ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(memcpy_s); ++#endif ++ ++#if SECUREC_WITH_PERFORMANCE_ADDONS ++/* ++ * Performance optimization ++ */ ++errno_t memcpy_sOptAsm(void *dest, size_t destMax, const void *src, size_t count) ++{ ++ if (SECUREC_MEMCPY_PARAM_OK(dest, destMax, src, count)) { ++ SECUREC_MEMCPY_OPT(dest, src, count); ++ return EOK; ++ } ++ /* Meet some runtime violation, return error code */ ++ return SecMemcpyError(dest, destMax, src, count); ++} ++ ++/* Trim judgement on "destMax <= SECUREC_MEM_MAX_LEN" */ ++errno_t memcpy_sOptTc(void *dest, size_t destMax, const void *src, size_t count) ++{ ++ if (SECUREC_LIKELY(count <= destMax && dest != NULL && src != NULL && \ ++ count > 0 && SECUREC_MEMORY_NO_OVERLAP((dest), (src), (count)))) { ++ SECUREC_MEMCPY_OPT(dest, src, count); ++ return EOK; ++ } ++ /* Meet some runtime violation, return error code */ ++ return SecMemcpyError(dest, destMax, src, count); ++} ++#endif ++ +diff --git a/lib/securec/src/memmove_s.c b/lib/securec/src/memmove_s.c +new file mode 100644 +index 000000000000..f231f05da966 +--- /dev/null ++++ b/lib/securec/src/memmove_s.c +@@ -0,0 +1,123 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: memmove_s function ++ * Create: 2014-02-25 ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Portability ++ * [reason] Use unsafe function to implement security function to maintain platform compatibility. ++ * And sufficient input validation is performed before calling ++ */ ++ ++#include "securecutil.h" ++ ++#ifdef SECUREC_NOT_CALL_LIBC_CORE_API ++/* ++ * Implementing memory data movement ++ */ ++SECUREC_INLINE void SecUtilMemmove(void *dst, const void *src, size_t count) ++{ ++ unsigned char *pDest = (unsigned char *)dst; ++ const unsigned char *pSrc = (const unsigned char *)src; ++ size_t maxCount = count; ++ ++ if (dst <= src || pDest >= (pSrc + maxCount)) { ++ /* ++ * Non-Overlapping Buffers ++ * Copy from lower addresses to higher addresses ++ */ ++ while (maxCount > 0) { ++ --maxCount; ++ *pDest = *pSrc; ++ ++pDest; ++ ++pSrc; ++ } ++ } else { ++ /* ++ * Overlapping Buffers ++ * Copy from higher addresses to lower addresses ++ */ ++ pDest = pDest + maxCount - 1; ++ pSrc = pSrc + maxCount - 1; ++ while (maxCount > 0) { ++ --maxCount; ++ *pDest = *pSrc; ++ --pDest; ++ --pSrc; ++ } ++ } ++} ++#endif ++ ++/* ++ * ++ * The memmove_s function copies count bytes of characters from src to dest. ++ * This function can be assigned correctly when memory overlaps. ++ * ++ * dest Destination object. ++ * destMax Size of the destination buffer. ++ * src Source object. ++ * count Number of characters to copy. ++ * ++ * ++ * dest buffer is updated. ++ * ++ * ++ * EOK Success ++ * EINVAL dest is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN ++ * EINVAL_AND_RESET dest != NULL and src is NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN ++ * ERANGE destMax > SECUREC_MEM_MAX_LEN or destMax is 0 ++ * ERANGE_AND_RESET count > destMax and dest != NULL and src != NULL and destMax != 0 ++ * and destMax <= SECUREC_MEM_MAX_LEN ++ * ++ * If an error occurred, dest will be filled with 0 when dest and destMax valid. ++ * If some regions of the source area and the destination overlap, memmove_s ++ * ensures that the original source bytes in the overlapping region are copied ++ * before being overwritten. ++ */ ++errno_t memmove_s(void *dest, size_t destMax, const void *src, size_t count) ++{ ++ if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("memmove_s"); ++ return ERANGE; ++ } ++ if (dest == NULL || src == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("memmove_s"); ++ if (dest != NULL) { ++ (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); ++ return EINVAL_AND_RESET; ++ } ++ return EINVAL; ++ } ++ if (count > destMax) { ++ (void)SECUREC_MEMSET_FUNC_OPT(dest, 0, destMax); ++ SECUREC_ERROR_INVALID_RANGE("memmove_s"); ++ return ERANGE_AND_RESET; ++ } ++ if (dest == src) { ++ return EOK; ++ } ++ ++ if (count > 0) { ++#ifdef SECUREC_NOT_CALL_LIBC_CORE_API ++ SecUtilMemmove(dest, src, count); ++#else ++ /* Use underlying memmove for performance consideration */ ++ (void)memmove(dest, src, count); ++#endif ++ } ++ return EOK; ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(memmove_s); ++#endif ++ +diff --git a/lib/securec/src/memset_s.c b/lib/securec/src/memset_s.c +new file mode 100644 +index 000000000000..d9a657fd326a +--- /dev/null ++++ b/lib/securec/src/memset_s.c +@@ -0,0 +1,510 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: memset_s function ++ * Create: 2014-02-25 ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Portability ++ * [reason] Use unsafe function to implement security function to maintain platform compatibility. ++ * And sufficient input validation is performed before calling ++ */ ++ ++#include "securecutil.h" ++ ++#define SECUREC_MEMSET_PARAM_OK(dest, destMax, count) (SECUREC_LIKELY((destMax) <= SECUREC_MEM_MAX_LEN && \ ++ (dest) != NULL && (count) <= (destMax))) ++ ++#if SECUREC_WITH_PERFORMANCE_ADDONS ++ ++/* Use union to clear strict-aliasing warning */ ++typedef union { ++ SecStrBuf32 buf32; ++ SecStrBuf31 buf31; ++ SecStrBuf30 buf30; ++ SecStrBuf29 buf29; ++ SecStrBuf28 buf28; ++ SecStrBuf27 buf27; ++ SecStrBuf26 buf26; ++ SecStrBuf25 buf25; ++ SecStrBuf24 buf24; ++ SecStrBuf23 buf23; ++ SecStrBuf22 buf22; ++ SecStrBuf21 buf21; ++ SecStrBuf20 buf20; ++ SecStrBuf19 buf19; ++ SecStrBuf18 buf18; ++ SecStrBuf17 buf17; ++ SecStrBuf16 buf16; ++ SecStrBuf15 buf15; ++ SecStrBuf14 buf14; ++ SecStrBuf13 buf13; ++ SecStrBuf12 buf12; ++ SecStrBuf11 buf11; ++ SecStrBuf10 buf10; ++ SecStrBuf9 buf9; ++ SecStrBuf8 buf8; ++ SecStrBuf7 buf7; ++ SecStrBuf6 buf6; ++ SecStrBuf5 buf5; ++ SecStrBuf4 buf4; ++ SecStrBuf3 buf3; ++ SecStrBuf2 buf2; ++} SecStrBuf32Union; ++/* C standard initializes the first member of the consortium. */ ++static const SecStrBuf32 g_allZero = {{ ++ 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, ++ 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, ++ 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, ++ 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U ++}}; ++static const SecStrBuf32 g_allFF = {{ ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF ++}}; ++ ++/* Clear conversion warning strict aliasing" */ ++SECUREC_INLINE const SecStrBuf32Union *SecStrictAliasingCast(const SecStrBuf32 *buf) ++{ ++ return (const SecStrBuf32Union *)buf; ++} ++ ++#ifndef SECUREC_MEMSET_THRESHOLD_SIZE ++#define SECUREC_MEMSET_THRESHOLD_SIZE 32UL ++#endif ++ ++#define SECUREC_UNALIGNED_SET(dest, c, count) do { \ ++ unsigned char *pDest_ = (unsigned char *)(dest); \ ++ switch (count) { \ ++ case 32: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 31: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 30: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 29: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 28: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 27: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 26: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 25: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 24: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 23: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 22: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 21: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 20: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 19: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 18: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 17: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 16: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 15: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 14: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 13: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 12: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 11: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 10: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 9: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 8: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 7: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 6: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 5: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 4: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 3: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 2: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 1: \ ++ *(pDest_++) = (unsigned char)(c); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++#define SECUREC_SET_VALUE_BY_STRUCT(dest, dataName, n) do { \ ++ *(SecStrBuf##n *)(dest) = *(const SecStrBuf##n *)(&((SecStrictAliasingCast(&(dataName)))->buf##n)); \ ++} SECUREC_WHILE_ZERO ++ ++#define SECUREC_ALIGNED_SET_OPT_ZERO_FF(dest, c, count) do { \ ++ switch (c) { \ ++ case 0: \ ++ switch (count) { \ ++ case 1: \ ++ *(unsigned char *)(dest) = (unsigned char)0; \ ++ break; \ ++ case 2: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 2); \ ++ break; \ ++ case 3: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 3); \ ++ break; \ ++ case 4: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 4); \ ++ break; \ ++ case 5: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 5); \ ++ break; \ ++ case 6: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 6); \ ++ break; \ ++ case 7: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 7); \ ++ break; \ ++ case 8: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 8); \ ++ break; \ ++ case 9: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 9); \ ++ break; \ ++ case 10: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 10); \ ++ break; \ ++ case 11: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 11); \ ++ break; \ ++ case 12: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 12); \ ++ break; \ ++ case 13: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 13); \ ++ break; \ ++ case 14: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 14); \ ++ break; \ ++ case 15: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 15); \ ++ break; \ ++ case 16: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 16); \ ++ break; \ ++ case 17: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 17); \ ++ break; \ ++ case 18: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 18); \ ++ break; \ ++ case 19: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 19); \ ++ break; \ ++ case 20: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 20); \ ++ break; \ ++ case 21: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 21); \ ++ break; \ ++ case 22: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 22); \ ++ break; \ ++ case 23: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 23); \ ++ break; \ ++ case 24: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 24); \ ++ break; \ ++ case 25: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 25); \ ++ break; \ ++ case 26: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 26); \ ++ break; \ ++ case 27: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 27); \ ++ break; \ ++ case 28: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 28); \ ++ break; \ ++ case 29: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 29); \ ++ break; \ ++ case 30: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 30); \ ++ break; \ ++ case 31: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 31); \ ++ break; \ ++ case 32: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allZero, 32); \ ++ break; \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } \ ++ break; \ ++ case 0xFF: \ ++ switch (count) { \ ++ case 1: \ ++ *(unsigned char *)(dest) = (unsigned char)0xffU; \ ++ break; \ ++ case 2: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 2); \ ++ break; \ ++ case 3: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 3); \ ++ break; \ ++ case 4: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 4); \ ++ break; \ ++ case 5: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 5); \ ++ break; \ ++ case 6: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 6); \ ++ break; \ ++ case 7: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 7); \ ++ break; \ ++ case 8: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 8); \ ++ break; \ ++ case 9: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 9); \ ++ break; \ ++ case 10: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 10); \ ++ break; \ ++ case 11: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 11); \ ++ break; \ ++ case 12: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 12); \ ++ break; \ ++ case 13: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 13); \ ++ break; \ ++ case 14: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 14); \ ++ break; \ ++ case 15: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 15); \ ++ break; \ ++ case 16: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 16); \ ++ break; \ ++ case 17: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 17); \ ++ break; \ ++ case 18: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 18); \ ++ break; \ ++ case 19: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 19); \ ++ break; \ ++ case 20: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 20); \ ++ break; \ ++ case 21: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 21); \ ++ break; \ ++ case 22: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 22); \ ++ break; \ ++ case 23: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 23); \ ++ break; \ ++ case 24: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 24); \ ++ break; \ ++ case 25: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 25); \ ++ break; \ ++ case 26: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 26); \ ++ break; \ ++ case 27: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 27); \ ++ break; \ ++ case 28: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 28); \ ++ break; \ ++ case 29: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 29); \ ++ break; \ ++ case 30: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 30); \ ++ break; \ ++ case 31: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 31); \ ++ break; \ ++ case 32: \ ++ SECUREC_SET_VALUE_BY_STRUCT((dest), g_allFF, 32); \ ++ break; \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } \ ++ break; \ ++ default: \ ++ SECUREC_UNALIGNED_SET((dest), (c), (count)); \ ++ break; \ ++ } /* END switch */ \ ++} SECUREC_WHILE_ZERO ++ ++#define SECUREC_SMALL_MEM_SET(dest, c, count) do { \ ++ if (SECUREC_ADDR_ALIGNED_8((dest))) { \ ++ SECUREC_ALIGNED_SET_OPT_ZERO_FF((dest), (c), (count)); \ ++ } else { \ ++ SECUREC_UNALIGNED_SET((dest), (c), (count)); \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++/* ++ * Performance optimization ++ */ ++#define SECUREC_MEMSET_OPT(dest, c, count) do { \ ++ if ((count) > SECUREC_MEMSET_THRESHOLD_SIZE) { \ ++ SECUREC_MEMSET_PREVENT_DSE((dest), (c), (count)); \ ++ } else { \ ++ SECUREC_SMALL_MEM_SET((dest), (c), (count)); \ ++ } \ ++} SECUREC_WHILE_ZERO ++#endif ++ ++/* ++ * Handling errors ++ */ ++SECUREC_INLINE errno_t SecMemsetError(void *dest, size_t destMax, int c) ++{ ++ /* Check destMax is 0 compatible with _sp macro */ ++ if (destMax == 0 || destMax > SECUREC_MEM_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("memset_s"); ++ return ERANGE; ++ } ++ if (dest == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("memset_s"); ++ return EINVAL; ++ } ++ SECUREC_MEMSET_PREVENT_DSE(dest, c, destMax); /* Set entire buffer to value c */ ++ SECUREC_ERROR_INVALID_RANGE("memset_s"); ++ return ERANGE_AND_RESET; ++} ++ ++/* ++ * ++ * The memset_s function copies the value of c (converted to an unsigned char) ++ * into each of the first count characters of the object pointed to by dest. ++ * ++ * ++ * dest Pointer to destination. ++ * destMax The size of the buffer. ++ * c Character to set. ++ * count Number of characters. ++ * ++ * ++ * dest buffer is updated. ++ * ++ * ++ * EOK Success ++ * EINVAL dest == NULL and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN ++ * ERANGE destMax > SECUREC_MEM_MAX_LEN or (destMax is 0 and count > destMax) ++ * ERANGE_AND_RESET count > destMax and destMax != 0 and destMax <= SECUREC_MEM_MAX_LEN and dest != NULL ++ * ++ * if return ERANGE_AND_RESET then fill dest to c ,fill length is destMax ++ */ ++errno_t memset_s(void *dest, size_t destMax, int c, size_t count) ++{ ++ if (SECUREC_MEMSET_PARAM_OK(dest, destMax, count)) { ++ SECUREC_MEMSET_PREVENT_DSE(dest, c, count); ++ return EOK; ++ } ++ /* Meet some runtime violation, return error code */ ++ return SecMemsetError(dest, destMax, c); ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(memset_s); ++#endif ++ ++#if SECUREC_WITH_PERFORMANCE_ADDONS ++/* ++ * Performance optimization ++ */ ++errno_t memset_sOptAsm(void *dest, size_t destMax, int c, size_t count) ++{ ++ if (SECUREC_MEMSET_PARAM_OK(dest, destMax, count)) { ++ SECUREC_MEMSET_OPT(dest, c, count); ++ return EOK; ++ } ++ /* Meet some runtime violation, return error code */ ++ return SecMemsetError(dest, destMax, c); ++} ++ ++/* ++ * Performance optimization, trim judgement on "destMax <= SECUREC_MEM_MAX_LEN" ++ */ ++errno_t memset_sOptTc(void *dest, size_t destMax, int c, size_t count) ++{ ++ if (SECUREC_LIKELY(count <= destMax && dest != NULL)) { ++ SECUREC_MEMSET_OPT(dest, c, count); ++ return EOK; ++ } ++ /* Meet some runtime violation, return error code */ ++ return SecMemsetError(dest, destMax, c); ++} ++#endif ++ +diff --git a/lib/securec/src/output.inl b/lib/securec/src/output.inl +new file mode 100644 +index 000000000000..9392efaaff1f +--- /dev/null ++++ b/lib/securec/src/output.inl +@@ -0,0 +1,1720 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Used by secureprintoutput_a.c and secureprintoutput_w.c to include. ++ * This file provides a template function for ANSI and UNICODE compiling ++ * by different type definition. The functions of SecOutputS or ++ * SecOutputSW provides internal implementation for printf family API, such as sprintf, swprintf_s. ++ * Create: 2014-02-25 ++ * Notes: see www.cplusplus.com/reference/cstdio/printf/ ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Portability ++ * [reason] Use unsafe function to implement security function to maintain platform compatibility. ++ * And sufficient input validation is performed before calling ++ */ ++#ifndef OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 ++#define OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 ++ ++#ifndef SECUREC_ENABLE_SPRINTF_LONG_DOUBLE ++/* Some compilers do not support long double */ ++#define SECUREC_ENABLE_SPRINTF_LONG_DOUBLE 1 ++#endif ++ ++#define SECUREC_NULL_STRING_SIZE 8 ++#define SECUREC_STATE_TABLE_SIZE 337 ++ ++#if defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS) ++#define SECUREC_DIV_QUOTIENT_OCTAL(val64) ((val64) >> 3ULL) ++#define SECUREC_DIV_RESIDUE_OCTAL(val64) ((val64) & 7ULL) ++ ++#define SECUREC_DIV_QUOTIENT_HEX(val64) ((val64) >> 4ULL) ++#define SECUREC_DIV_RESIDUE_HEX(val64) ((val64) & 0xfULL) ++#endif ++ ++#define SECUREC_RADIX_OCTAL 8U ++#define SECUREC_RADIX_DECIMAL 10U ++#define SECUREC_RADIX_HEX 16U ++#define SECUREC_PREFIX_LEN 2 ++/* Size include '+' and '\0' */ ++#define SECUREC_FLOAT_BUF_EXT 2 ++ ++/* Sign extend or Zero-extend */ ++#define SECUREC_GET_LONG_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ ++ (SecInt64)(long)va_arg(argList, long) : \ ++ (SecInt64)(unsigned long)va_arg(argList, long)) ++ ++/* Sign extend or Zero-extend */ ++#define SECUREC_GET_CHAR_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ ++ SecUpdateNegativeChar(&(attr), ((char)va_arg(argList, int))) : \ ++ (SecInt64)(unsigned char)va_arg(argList, int)) ++ ++/* Sign extend or Zero-extend */ ++#define SECUREC_GET_SHORT_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ ++ (SecInt64)(short)va_arg(argList, int) : \ ++ (SecInt64)(unsigned short)va_arg(argList, int)) ++ ++/* Sign extend or Zero-extend */ ++#define SECUREC_GET_INT_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ ++ (SecInt64)(int)va_arg(argList, int) : \ ++ (SecInt64)(unsigned int)va_arg(argList, int)) ++ ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++/* Sign extend or Zero-extend. No suitable macros were found to handle the branch */ ++#define SECUREC_GET_SIZE_FROM_ARG(attr) ((((attr).flags & SECUREC_FLAG_SIGNED) != 0) ? \ ++ ((SecIsSameSize(sizeof(size_t), sizeof(long)) != 0) ? (SecInt64)(long)va_arg(argList, long) : \ ++ ((SecIsSameSize(sizeof(size_t), sizeof(long long)) != 0) ? (SecInt64)(long long)va_arg(argList, long long) : \ ++ (SecInt64)(int)va_arg(argList, int))) : \ ++ (SecInt64)(size_t)va_arg(argList, size_t)) ++#endif ++ ++/* Format output buffer pointer and available size */ ++typedef struct { ++ int count; ++ SecChar *cur; ++} SecPrintfStream; ++ ++typedef union { ++ /* Integer formatting refers to the end of the buffer, plus 1 to prevent tool alarms */ ++ char str[SECUREC_BUFFER_SIZE + 1]; ++#if SECUREC_HAVE_WCHART ++ wchar_t wStr[SECUREC_WCHAR_BUFFER_SIZE]; /* Just for %lc */ ++#endif ++} SecBuffer; ++ ++typedef union { ++ char *str; /* Not a null terminated string */ ++#if SECUREC_HAVE_WCHART ++ wchar_t *wStr; ++#endif ++} SecFormatBuf; ++ ++typedef struct { ++ const char *digits; /* Point to the hexadecimal subset */ ++ SecFormatBuf text; /* Point to formatted string */ ++ int textLen; /* Length of the text */ ++ int textIsWide; /* Flag for text is wide chars ; 0 is not wide char */ ++ unsigned int radix; /* Use for output number , default set to 10 */ ++ unsigned int flags; ++ int fldWidth; ++ int precision; ++ int dynWidth; /* %* 1 width from variable parameter ;0 not */ ++ int dynPrecision; /* %.* 1 precision from variable parameter ;0 not */ ++ int padding; /* Padding len */ ++ int prefixLen; /* Length of prefix, 0 or 1 or 2 */ ++ SecChar prefix[SECUREC_PREFIX_LEN]; /* Prefix is 0 or 0x */ ++ SecBuffer buffer; ++} SecFormatAttr; ++ ++#if SECUREC_ENABLE_SPRINTF_FLOAT ++#ifdef SECUREC_STACK_SIZE_LESS_THAN_1K ++#define SECUREC_FMT_STR_LEN 8 ++#else ++#define SECUREC_FMT_STR_LEN 16 ++#endif ++typedef struct { ++ char buffer[SECUREC_FMT_STR_LEN]; ++ char *fmtStr; /* Initialization must point to buffer */ ++ char *allocatedFmtStr; /* Initialization must be NULL to store allocated point */ ++ char *floatBuffer; /* Use heap memory if the SecFormatAttr.buffer is not enough */ ++ int bufferSize; /* The size of floatBuffer */ ++} SecFloatAdapt; ++#endif ++ ++/* Use 20 to Align the data */ ++#define SECUREC_DIGITS_BUF_SIZE 20 ++/* The serial number of 'x' or 'X' is 16 */ ++#define SECUREC_NUMBER_OF_X 16 ++/* Some systems can not use pointers to point to string literals, but can use string arrays. */ ++/* For example, when handling code under uboot, there is a problem with the pointer */ ++static const char g_itoaUpperDigits[SECUREC_DIGITS_BUF_SIZE] = "0123456789ABCDEFX"; ++static const char g_itoaLowerDigits[SECUREC_DIGITS_BUF_SIZE] = "0123456789abcdefx"; ++ ++#if SECUREC_ENABLE_SPRINTF_FLOAT ++/* Call system sprintf to format float value */ ++SECUREC_INLINE int SecFormatFloat(char *strDest, const char *format, ...) ++{ ++ int ret; /* If initialization causes e838 */ ++ va_list argList; ++ ++ va_start(argList, format); ++ SECUREC_MASK_VSPRINTF_WARNING ++ ret = vsprintf(strDest, format, argList); ++ SECUREC_END_MASK_VSPRINTF_WARNING ++ va_end(argList); ++ (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ ++ return ret; ++} ++ ++#if defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && SECUREC_ENABLE_SPRINTF_LONG_DOUBLE ++/* Out put long double value to dest */ ++SECUREC_INLINE void SecFormatLongDouble(SecFormatAttr *attr, const SecFloatAdapt *floatAdapt, long double ldValue) ++{ ++ int fldWidth = (((attr->flags & SECUREC_FLAG_LEFT) != 0) ? (-attr->fldWidth) : attr->fldWidth); ++ if (attr->dynWidth != 0 && attr->dynPrecision != 0) { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, attr->precision, ldValue); ++ } else if (attr->dynWidth != 0) { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, ldValue); ++ } else if (attr->dynPrecision != 0) { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, attr->precision, ldValue); ++ } else { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, ldValue); ++ } ++ if (attr->textLen < 0 || attr->textLen >= floatAdapt->bufferSize) { ++ attr->textLen = 0; ++ } ++} ++#endif ++ ++/* Out put double value to dest */ ++SECUREC_INLINE void SecFormatDouble(SecFormatAttr *attr, const SecFloatAdapt *floatAdapt, double dValue) ++{ ++ int fldWidth = (((attr->flags & SECUREC_FLAG_LEFT) != 0) ? (-attr->fldWidth) : attr->fldWidth); ++ if (attr->dynWidth != 0 && attr->dynPrecision != 0) { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, attr->precision, dValue); ++ } else if (attr->dynWidth != 0) { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, fldWidth, dValue); ++ } else if (attr->dynPrecision != 0) { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, attr->precision, dValue); ++ } else { ++ attr->textLen = SecFormatFloat(attr->text.str, floatAdapt->fmtStr, dValue); ++ } ++ if (attr->textLen < 0 || attr->textLen >= floatAdapt->bufferSize) { ++ attr->textLen = 0; ++ } ++} ++#endif ++ ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++/* To clear e506 warning */ ++SECUREC_INLINE int SecIsSameSize(size_t sizeA, size_t sizeB) ++{ ++ return (int)(sizeA == sizeB); ++} ++#endif ++ ++#ifndef SECUREC_ON_64BITS ++/* ++ * Compiler Optimized Division 8. ++ * The text.str point to buffer end, must be Large enough ++ */ ++SECUREC_INLINE void SecNumber32ToOctalString(SecUnsignedInt32 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt32 val32 = number; ++ do { ++ --attr->text.str; ++ /* Just use lowerDigits for 0 - 9 */ ++ *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_OCTAL]; ++ val32 /= SECUREC_RADIX_OCTAL; ++ } while (val32 != 0); ++} ++ ++#ifdef _AIX ++/* ++ * Compiler Optimized Division 10. ++ * The text.str point to buffer end, must be Large enough ++ */ ++SECUREC_INLINE void SecNumber32ToDecString(SecUnsignedInt32 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt32 val32 = number; ++ do { ++ --attr->text.str; ++ /* Just use lowerDigits for 0 - 9 */ ++ *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_DECIMAL]; ++ val32 /= SECUREC_RADIX_DECIMAL; ++ } while (val32 != 0); ++} ++#endif ++/* ++ * Compiler Optimized Division 16. ++ * The text.str point to buffer end, must be Large enough ++ */ ++SECUREC_INLINE void SecNumber32ToHexString(SecUnsignedInt32 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt32 val32 = number; ++ do { ++ --attr->text.str; ++ *(attr->text.str) = attr->digits[val32 % SECUREC_RADIX_HEX]; ++ val32 /= SECUREC_RADIX_HEX; ++ } while (val32 != 0); ++} ++ ++#ifndef _AIX ++/* Use fast div 10 */ ++SECUREC_INLINE void SecNumber32ToDecStringFast(SecUnsignedInt32 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt32 val32 = number; ++ do { ++ SecUnsignedInt32 quotient; ++ SecUnsignedInt32 remain; ++ --attr->text.str; ++ *(attr->text.str) = g_itoaLowerDigits[val32 % SECUREC_RADIX_DECIMAL]; ++ quotient = (val32 >> 1U) + (val32 >> 2U); /* Fast div magic 2 */ ++ quotient = quotient + (quotient >> 4U); /* Fast div magic 4 */ ++ quotient = quotient + (quotient >> 8U); /* Fast div magic 8 */ ++ quotient = quotient + (quotient >> 16U); /* Fast div magic 16 */ ++ quotient = quotient >> 3U; /* Fast div magic 3 */ ++ remain = val32 - SECUREC_MUL_TEN(quotient); ++ val32 = (remain > 9U) ? (quotient + 1U) : quotient; /* Fast div magic 9 */ ++ } while (val32 != 0); ++} ++#endif ++ ++SECUREC_INLINE void SecNumber32ToString(SecUnsignedInt32 number, SecFormatAttr *attr) ++{ ++ switch (attr->radix) { ++ case SECUREC_RADIX_HEX: ++ SecNumber32ToHexString(number, attr); ++ break; ++ case SECUREC_RADIX_OCTAL: ++ SecNumber32ToOctalString(number, attr); ++ break; ++ case SECUREC_RADIX_DECIMAL: ++#ifdef _AIX ++ /* The compiler will optimize div 10 */ ++ SecNumber32ToDecString(number, attr); ++#else ++ SecNumber32ToDecStringFast(number, attr); ++#endif ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++} ++#endif ++ ++#if defined(SECUREC_USE_SPECIAL_DIV64) || (defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS)) ++/* ++ * This function just to clear warning, on sume vxworks compiler shift 32 bit make warnings ++ */ ++SECUREC_INLINE SecUnsignedInt64 SecU64Shr32(SecUnsignedInt64 number) ++{ ++ return (((number) >> 16U) >> 16U); /* Two shifts of 16 bits to realize shifts of 32 bits */ ++} ++/* ++ * Fast divide by 10 algorithm. ++ * Calculation divisor multiply 0xcccccccccccccccdULL, resultHi64 >> 3 as quotient ++ */ ++SECUREC_INLINE void SecU64Div10(SecUnsignedInt64 divisor, SecUnsignedInt64 *quotient, SecUnsignedInt32 *residue) ++{ ++ SecUnsignedInt64 mask = 0xffffffffULL; /* Use 0xffffffffULL as 32 bit mask */ ++ SecUnsignedInt64 magicHi = 0xccccccccULL; /* Fast divide 10 magic numbers high 32bit 0xccccccccULL */ ++ SecUnsignedInt64 magicLow = 0xcccccccdULL; /* Fast divide 10 magic numbers low 32bit 0xcccccccdULL */ ++ SecUnsignedInt64 divisorHi = (SecUnsignedInt64)(SecU64Shr32(divisor)); /* High 32 bit use */ ++ SecUnsignedInt64 divisorLow = (SecUnsignedInt64)(divisor & mask); /* Low 32 bit mask */ ++ SecUnsignedInt64 factorHi = divisorHi * magicHi; ++ SecUnsignedInt64 factorLow1 = divisorHi * magicLow; ++ SecUnsignedInt64 factorLow2 = divisorLow * magicHi; ++ SecUnsignedInt64 factorLow3 = divisorLow * magicLow; ++ SecUnsignedInt64 carry = (factorLow1 & mask) + (factorLow2 & mask) + SecU64Shr32(factorLow3); ++ SecUnsignedInt64 resultHi64 = factorHi + SecU64Shr32(factorLow1) + SecU64Shr32(factorLow2) + SecU64Shr32(carry); ++ ++ *quotient = resultHi64 >> 3U; /* Fast divide 10 magic numbers 3 */ ++ *residue = (SecUnsignedInt32)(divisor - ((*quotient) * 10)); /* Quotient mul 10 */ ++ return; ++} ++#if defined(SECUREC_VXWORKS_VERSION_5_4) && !defined(SECUREC_ON_64BITS) ++/* ++ * Divide function for VXWORKS ++ */ ++SECUREC_INLINE int SecU64Div32(SecUnsignedInt64 divisor, SecUnsignedInt32 radix, ++ SecUnsignedInt64 *quotient, SecUnsignedInt32 *residue) ++{ ++ switch (radix) { ++ case SECUREC_RADIX_DECIMAL: ++ SecU64Div10(divisor, quotient, residue); ++ break; ++ case SECUREC_RADIX_HEX: ++ *quotient = SECUREC_DIV_QUOTIENT_HEX(divisor); ++ *residue = (SecUnsignedInt32)SECUREC_DIV_RESIDUE_HEX(divisor); ++ break; ++ case SECUREC_RADIX_OCTAL: ++ *quotient = SECUREC_DIV_QUOTIENT_OCTAL(divisor); ++ *residue = (SecUnsignedInt32)SECUREC_DIV_RESIDUE_OCTAL(divisor); ++ break; ++ default: ++ return -1; /* This does not happen in the current file */ ++ } ++ return 0; ++} ++SECUREC_INLINE void SecNumber64ToStringSpecial(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt64 val64 = number; ++ do { ++ SecUnsignedInt32 digit = 0; /* Ascii value of digit */ ++ SecUnsignedInt64 quotient = 0; ++ if (SecU64Div32(val64, (SecUnsignedInt32)attr->radix, "ient, &digit) != 0) { ++ /* Just break, when enter this function, no error is returned */ ++ break; ++ } ++ --attr->text.str; ++ *(attr->text.str) = attr->digits[digit]; ++ val64 = quotient; ++ } while (val64 != 0); ++} ++#endif ++#endif ++ ++#if defined(SECUREC_ON_64BITS) || !defined(SECUREC_VXWORKS_VERSION_5_4) ++#if defined(SECUREC_USE_SPECIAL_DIV64) ++/* The compiler does not provide 64 bit division problems */ ++SECUREC_INLINE void SecNumber64ToDecString(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt64 val64 = number; ++ do { ++ SecUnsignedInt64 quotient = 0; ++ SecUnsignedInt32 digit = 0; ++ SecU64Div10(val64, "ient, &digit); ++ --attr->text.str; ++ /* Just use lowerDigits for 0 - 9 */ ++ *(attr->text.str) = g_itoaLowerDigits[digit]; ++ val64 = quotient; ++ } while (val64 != 0); ++} ++#else ++/* ++ * Compiler Optimized Division 10. ++ * The text.str point to buffer end, must be Large enough ++ */ ++SECUREC_INLINE void SecNumber64ToDecString(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt64 val64 = number; ++ do { ++ --attr->text.str; ++ /* Just use lowerDigits for 0 - 9 */ ++ *(attr->text.str) = g_itoaLowerDigits[val64 % SECUREC_RADIX_DECIMAL]; ++ val64 /= SECUREC_RADIX_DECIMAL; ++ } while (val64 != 0); ++} ++#endif ++ ++/* ++ * Compiler Optimized Division 8. ++ * The text.str point to buffer end, must be Large enough ++ */ ++SECUREC_INLINE void SecNumber64ToOctalString(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt64 val64 = number; ++ do { ++ --attr->text.str; ++ /* Just use lowerDigits for 0 - 9 */ ++ *(attr->text.str) = g_itoaLowerDigits[val64 % SECUREC_RADIX_OCTAL]; ++ val64 /= SECUREC_RADIX_OCTAL; ++ } while (val64 != 0); ++} ++/* ++ * Compiler Optimized Division 16. ++ * The text.str point to buffer end, must be Large enough ++ */ ++SECUREC_INLINE void SecNumber64ToHexString(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++ SecUnsignedInt64 val64 = number; ++ do { ++ --attr->text.str; ++ *(attr->text.str) = attr->digits[val64 % SECUREC_RADIX_HEX]; ++ val64 /= SECUREC_RADIX_HEX; ++ } while (val64 != 0); ++} ++ ++SECUREC_INLINE void SecNumber64ToString(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++ switch (attr->radix) { ++ /* The compiler will optimize div 10 */ ++ case SECUREC_RADIX_DECIMAL: ++ SecNumber64ToDecString(number, attr); ++ break; ++ case SECUREC_RADIX_OCTAL: ++ SecNumber64ToOctalString(number, attr); ++ break; ++ case SECUREC_RADIX_HEX: ++ SecNumber64ToHexString(number, attr); ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++} ++#endif ++ ++/* ++ * Converting integers to string ++ */ ++SECUREC_INLINE void SecNumberToString(SecUnsignedInt64 number, SecFormatAttr *attr) ++{ ++#ifdef SECUREC_ON_64BITS ++ SecNumber64ToString(number, attr); ++#else /* For 32 bits system */ ++ if (number <= 0xffffffffUL) { /* Use 0xffffffffUL to check if the value is in the 32-bit range */ ++ /* In most case, the value to be converted is small value */ ++ SecUnsignedInt32 n32Tmp = (SecUnsignedInt32)number; ++ SecNumber32ToString(n32Tmp, attr); ++ } else { ++ /* The value to be converted is greater than 4G */ ++#if defined(SECUREC_VXWORKS_VERSION_5_4) ++ SecNumber64ToStringSpecial(number, attr); ++#else ++ SecNumber64ToString(number, attr); ++#endif ++ } ++#endif ++} ++ ++SECUREC_INLINE int SecIsNumberNeedTo32Bit(const SecFormatAttr *attr) ++{ ++ return (int)(((attr->flags & SECUREC_FLAG_I64) == 0) && ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++ ((attr->flags & SECUREC_FLAG_INTMAX) == 0) && ++#endif ++#ifdef SECUREC_ON_64BITS ++ ((attr->flags & SECUREC_FLAG_PTRDIFF) == 0) && ++ ((attr->flags & SECUREC_FLAG_SIZE) == 0) && ++#if !defined(SECUREC_COMPATIBLE_WIN_FORMAT) /* on window 64 system sizeof long is 32bit */ ++ ((attr->flags & SECUREC_FLAG_LONG) == 0) && ++#endif ++#endif ++ ((attr->flags & SECUREC_FLAG_LONGLONG) == 0)); ++} ++ ++SECUREC_INLINE void SecNumberToBuffer(SecFormatAttr *attr, SecInt64 num64) ++{ ++ SecUnsignedInt64 number; ++ /* Check for negative; copy into number */ ++ if ((attr->flags & SECUREC_FLAG_SIGNED) != 0 && num64 < 0) { ++ number = (SecUnsignedInt64)(0 - (SecUnsignedInt64)num64); /* Wrap with unsigned int64 numbers */ ++ attr->flags |= SECUREC_FLAG_NEGATIVE; ++ } else { ++ number = (SecUnsignedInt64)num64; ++ } ++ if (SecIsNumberNeedTo32Bit(attr) != 0) { ++ number = (number & (SecUnsignedInt64)0xffffffffUL); /* Use 0xffffffff as 32 bit mask */ ++ } ++ ++ /* The text.str must be point to buffer.str, this pointer is used outside the function */ ++ attr->text.str = &attr->buffer.str[SECUREC_BUFFER_SIZE]; ++ ++ if (number == 0) { ++ /* Turn off hex prefix default, and textLen is zero */ ++ attr->prefixLen = 0; ++ attr->textLen = 0; ++ return; ++ } ++ ++ /* Convert integer to string. It must be invoked when number > 0, otherwise the following logic is incorrect */ ++ SecNumberToString(number, attr); ++ /* Compute length of number, text.str must be in buffer.str */ ++ attr->textLen = (int)(size_t)((char *)&attr->buffer.str[SECUREC_BUFFER_SIZE] - attr->text.str); ++} ++ ++/* ++ * Write one character to dest buffer ++ */ ++SECUREC_INLINE void SecWriteChar(SecPrintfStream *stream, SecChar ch, int *charsOut) ++{ ++ /* Count must be reduced first, In order to identify insufficient length */ ++ --stream->count; ++ if (stream->count >= 0) { ++ *(stream->cur) = ch; ++ ++stream->cur; ++ *charsOut = *charsOut + 1; ++ return; ++ } ++ /* No enough length */ ++ *charsOut = -1; ++} ++ ++/* ++* Write multiple identical characters. ++*/ ++SECUREC_INLINE void SecWriteMultiChar(SecPrintfStream *stream, SecChar ch, int num, int *charsOut) ++{ ++ int count; ++ for (count = num; count > 0; --count) { ++ --stream->count; /* count may be negative,indicating insufficient space */ ++ if (stream->count < 0) { ++ *charsOut = -1; ++ return; ++ } ++ *(stream->cur) = ch; ++ ++stream->cur; ++ } ++ *charsOut = *charsOut + num; ++} ++ ++/* ++* Write string function, where this function is called, make sure that len is greater than 0 ++*/ ++SECUREC_INLINE void SecWriteString(SecPrintfStream *stream, const SecChar *str, int len, int *charsOut) ++{ ++ const SecChar *tmp = str; ++ int count; ++ for (count = len; count > 0; --count) { ++ --stream->count; /* count may be negative,indicating insufficient space */ ++ if (stream->count < 0) { ++ *charsOut = -1; ++ return; ++ } ++ *(stream->cur) = *tmp; ++ ++stream->cur; ++ ++tmp; ++ } ++ *charsOut = *charsOut + len; ++} ++ ++/* Use loop copy char or wchar_t string */ ++SECUREC_INLINE void SecWriteStringByLoop(SecPrintfStream *stream, const SecChar *str, int len) ++{ ++ int i; ++ const SecChar *tmp = str; ++ for (i = 0; i < len; ++i) { ++ *stream->cur = *tmp; ++ ++stream->cur; ++ ++tmp; ++ } ++ stream->count -= len; ++} ++ ++SECUREC_INLINE void SecWriteStringOpt(SecPrintfStream *stream, const SecChar *str, int len) ++{ ++ if (len < 12) { /* Performance optimization for mobile number length 12 */ ++ SecWriteStringByLoop(stream, str, len); ++ } else { ++ size_t count = (size_t)(unsigned int)len * sizeof(SecChar); ++ SECUREC_MEMCPY_WARP_OPT(stream->cur, str, count); ++ stream->cur += len; ++ stream->count -= len; ++ } ++} ++ ++/* ++ * Return if buffer length is enough ++ * The count variable can be reduced to 0, and the external function complements the \0 terminator. ++ */ ++SECUREC_INLINE int SecIsStreamBufEnough(const SecPrintfStream *stream, int needLen) ++{ ++ return (int)(stream->count >= needLen); ++} ++ ++/* Write text string */ ++SECUREC_INLINE void SecWriteTextOpt(SecPrintfStream *stream, const SecChar *str, int len, int *charsOut) ++{ ++ if (SecIsStreamBufEnough(stream, len) != 0) { ++ SecWriteStringOpt(stream, str, len); ++ *charsOut += len; ++ } else { ++ SecWriteString(stream, str, len, charsOut); ++ } ++} ++ ++/* Write left padding */ ++SECUREC_INLINE void SecWriteLeftPadding(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ if ((attr->flags & (SECUREC_FLAG_LEFT | SECUREC_FLAG_LEADZERO)) == 0 && attr->padding > 0) { ++ /* Pad on left with blanks */ ++ SecWriteMultiChar(stream, SECUREC_CHAR(' '), attr->padding, charsOut); ++ } ++} ++ ++/* Write prefix */ ++SECUREC_INLINE void SecWritePrefix(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ if (attr->prefixLen > 0) { ++ SecWriteString(stream, attr->prefix, attr->prefixLen, charsOut); ++ } ++} ++ ++/* Write leading zeros */ ++SECUREC_INLINE void SecWriteLeadingZero(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ if ((attr->flags & SECUREC_FLAG_LEADZERO) != 0 && (attr->flags & SECUREC_FLAG_LEFT) == 0 && ++ attr->padding > 0) { ++ SecWriteMultiChar(stream, SECUREC_CHAR('0'), attr->padding, charsOut); ++ } ++} ++ ++/* Write right padding */ ++SECUREC_INLINE void SecWriteRightPadding(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ if (*charsOut >= 0 && (attr->flags & SECUREC_FLAG_LEFT) != 0 && attr->padding > 0) { ++ /* Pad on right with blanks */ ++ SecWriteMultiChar(stream, SECUREC_CHAR(' '), attr->padding, charsOut); ++ } ++} ++ ++#ifdef SECUREC_FOR_WCHAR ++#define SECUREC_TEXT_CHAR_PTR(text) ((text).wStr) ++#define SECUREC_NEED_CONVERT_TEXT(attr) ((attr)->textIsWide == 0) ++#if SECUREC_HAVE_MBTOWC ++#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) SecWriteTextAfterMbtowc((stream), (attr), (charsOut)) ++#else ++#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) (*(charsOut) = -1) ++#endif ++#else ++#define SECUREC_TEXT_CHAR_PTR(text) ((text).str) ++#define SECUREC_NEED_CONVERT_TEXT(attr) ((attr)->textIsWide != 0) ++#if SECUREC_HAVE_WCTOMB ++#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) SecWriteTextAfterWctomb((stream), (attr), (charsOut)) ++#else ++#define SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut) (*(charsOut) = -1) ++#endif ++#endif ++ ++#ifdef SECUREC_FOR_WCHAR ++#if SECUREC_HAVE_MBTOWC ++SECUREC_INLINE void SecWriteTextAfterMbtowc(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ const char *p = attr->text.str; ++ int count = attr->textLen; ++ while (count > 0) { ++ wchar_t wChar = L'\0'; ++ int retVal = mbtowc(&wChar, p, (size_t)MB_CUR_MAX); ++ if (retVal <= 0) { ++ *charsOut = -1; ++ break; ++ } ++ SecWriteChar(stream, wChar, charsOut); ++ if (*charsOut == -1) { ++ break; ++ } ++ p += retVal; ++ count -= retVal; ++ } ++} ++#endif ++#else /* Not SECUREC_FOR_WCHAR */ ++#if SECUREC_HAVE_WCTOMB ++SECUREC_INLINE void SecWriteTextAfterWctomb(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ const wchar_t *p = attr->text.wStr; ++ int count = attr->textLen; ++ while (count > 0) { ++ char tmpBuf[SECUREC_MB_LEN + 1]; ++ SECUREC_MASK_MSVC_CRT_WARNING ++ int retVal = wctomb(tmpBuf, *p); ++ SECUREC_END_MASK_MSVC_CRT_WARNING ++ if (retVal <= 0) { ++ *charsOut = -1; ++ break; ++ } ++ SecWriteString(stream, tmpBuf, retVal, charsOut); ++ if (*charsOut == -1) { ++ break; ++ } ++ --count; ++ ++p; ++ } ++} ++#endif ++#endif ++ ++#if SECUREC_ENABLE_SPRINTF_FLOAT ++/* ++ * Write text of float ++ * Using independent functions to optimize the expansion of inline functions by the compiler ++ */ ++SECUREC_INLINE void SecWriteFloatText(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++#ifdef SECUREC_FOR_WCHAR ++#if SECUREC_HAVE_MBTOWC ++ SecWriteTextAfterMbtowc(stream, attr, charsOut); ++#else ++ *charsOut = -1; ++ (void)stream; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ (void)attr; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++#endif ++#else /* Not SECUREC_FOR_WCHAR */ ++ SecWriteString(stream, attr->text.str, attr->textLen, charsOut); ++#endif ++} ++#endif ++ ++/* Write text of integer or string ... */ ++SECUREC_INLINE void SecWriteText(SecPrintfStream *stream, const SecFormatAttr *attr, int *charsOut) ++{ ++ if (SECUREC_NEED_CONVERT_TEXT(attr)) { ++ SECUREC_WRITE_TEXT_AFTER_CONVERT(stream, attr, charsOut); ++ } else { ++ SecWriteTextOpt(stream, SECUREC_TEXT_CHAR_PTR(attr->text), attr->textLen, charsOut); ++ } ++} ++ ++#define SECUREC_FMT_STATE_OFFSET 256 ++ ++SECUREC_INLINE SecFmtState SecDecodeState(SecChar ch, SecFmtState lastState) ++{ ++ static const unsigned char stateTable[SECUREC_STATE_TABLE_SIZE] = { ++ /* ++ * Type ++ * 0: nospecial meaning; ++ * 1: '%' ++ * 2: '.' ++ * 3: '*' ++ * 4: '0' ++ * 5: '1' ... '9' ++ * 6: ' ', '+', '-', '#' ++ * 7: 'h', 'l', 'L', 'w' , 'N', 'z', 'q', 't', 'j' ++ * 8: 'd', 'o', 'u', 'i', 'x', 'X', 'e', 'f', 'g', 'E', 'F', 'G', 's', 'c', '[', 'p' ++ */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x06, 0x00, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03, 0x06, 0x00, 0x06, 0x02, 0x00, ++ 0x04, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x08, 0x08, 0x00, 0x07, 0x00, 0x00, 0x07, 0x00, 0x07, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x07, 0x08, 0x07, 0x00, 0x07, 0x00, 0x00, 0x08, ++ 0x08, 0x07, 0x00, 0x08, 0x07, 0x08, 0x00, 0x07, 0x08, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, ++ /* Fill zero for normal char 128 byte for 0x80 - 0xff */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ /* ++ * State ++ * 0: normal ++ * 1: percent ++ * 2: flag ++ * 3: width ++ * 4: dot ++ * 5: precis ++ * 6: size ++ * 7: type ++ * 8: invalid ++ */ ++ 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x01, 0x00, 0x08, 0x08, 0x08, 0x08, 0x08, ++ 0x01, 0x00, 0x00, 0x04, 0x04, 0x04, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x03, 0x03, 0x08, 0x05, ++ 0x08, 0x08, 0x00, 0x00, 0x00, 0x02, 0x02, 0x03, 0x05, 0x05, 0x08, 0x00, 0x00, 0x00, 0x03, 0x03, ++ 0x03, 0x05, 0x05, 0x08, 0x00, 0x00, 0x00, 0x02, 0x02, 0x02, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, ++ 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x00, ++ 0x00 ++ }; ++ ++#ifdef SECUREC_FOR_WCHAR ++ /* Convert to unsigned char to clear gcc 4.3.4 warning */ ++ unsigned char fmtType = (unsigned char)((((unsigned int)(int)(ch)) <= (unsigned int)(int)(L'~')) ? \ ++ (stateTable[(unsigned char)(ch)]) : 0); ++ return (SecFmtState)(stateTable[fmtType * ((unsigned char)STAT_INVALID + 1) + ++ (unsigned char)(lastState) + SECUREC_FMT_STATE_OFFSET]); ++#else ++ unsigned char fmtType = stateTable[(unsigned char)(ch)]; ++ return (SecFmtState)(stateTable[fmtType * ((unsigned char)STAT_INVALID + 1) + ++ (unsigned char)(lastState) + SECUREC_FMT_STATE_OFFSET]); ++#endif ++} ++ ++SECUREC_INLINE void SecDecodeFlags(SecChar ch, SecFormatAttr *attr) ++{ ++ switch (ch) { ++ case SECUREC_CHAR(' '): ++ attr->flags |= SECUREC_FLAG_SIGN_SPACE; ++ break; ++ case SECUREC_CHAR('+'): ++ attr->flags |= SECUREC_FLAG_SIGN; ++ break; ++ case SECUREC_CHAR('-'): ++ attr->flags |= SECUREC_FLAG_LEFT; ++ break; ++ case SECUREC_CHAR('0'): ++ attr->flags |= SECUREC_FLAG_LEADZERO; /* Add zero th the front */ ++ break; ++ case SECUREC_CHAR('#'): ++ attr->flags |= SECUREC_FLAG_ALTERNATE; /* Output %x with 0x */ ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ return; ++} ++ ++/* ++ * Decoded size identifier in format string to Reduce the number of lines of function code ++ */ ++SECUREC_INLINE int SecDecodeSizeI(SecFormatAttr *attr, const SecChar **format) ++{ ++#ifdef SECUREC_ON_64BITS ++ attr->flags |= SECUREC_FLAG_I64; /* %I to INT64 */ ++#endif ++ if ((**format == SECUREC_CHAR('6')) && (*((*format) + 1) == SECUREC_CHAR('4'))) { ++ (*format) += 2; /* Add 2 to skip I64 */ ++ attr->flags |= SECUREC_FLAG_I64; /* %I64 to INT64 */ ++ } else if ((**format == SECUREC_CHAR('3')) && (*((*format) + 1) == SECUREC_CHAR('2'))) { ++ (*format) += 2; /* Add 2 to skip I32 */ ++ attr->flags &= ~SECUREC_FLAG_I64; /* %I64 to INT32 */ ++ } else if ((**format == SECUREC_CHAR('d')) || (**format == SECUREC_CHAR('i')) || ++ (**format == SECUREC_CHAR('o')) || (**format == SECUREC_CHAR('u')) || ++ (**format == SECUREC_CHAR('x')) || (**format == SECUREC_CHAR('X'))) { ++ /* Do nothing */ ++ } else { ++ /* Compatibility code for "%I" just print I */ ++ return -1; ++ } ++ return 0; ++} ++ ++/* ++ * Decoded size identifier in format string, and skip format to next charater ++ */ ++SECUREC_INLINE int SecDecodeSize(SecChar ch, SecFormatAttr *attr, const SecChar **format) ++{ ++ switch (ch) { ++ case SECUREC_CHAR('l'): ++ if (**format == SECUREC_CHAR('l')) { ++ *format = *format + 1; ++ attr->flags |= SECUREC_FLAG_LONGLONG; /* For long long */ ++ } else { ++ attr->flags |= SECUREC_FLAG_LONG; /* For long int or wchar_t */ ++ } ++ break; ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++ case SECUREC_CHAR('z'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('Z'): ++ attr->flags |= SECUREC_FLAG_SIZE; ++ break; ++ case SECUREC_CHAR('j'): ++ attr->flags |= SECUREC_FLAG_INTMAX; ++ break; ++#endif ++ case SECUREC_CHAR('t'): ++ attr->flags |= SECUREC_FLAG_PTRDIFF; ++ break; ++ case SECUREC_CHAR('q'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('L'): ++ attr->flags |= (SECUREC_FLAG_LONGLONG | SECUREC_FLAG_LONG_DOUBLE); ++ break; ++ case SECUREC_CHAR('I'): ++ if (SecDecodeSizeI(attr, format) != 0) { ++ /* Compatibility code for "%I" just print I */ ++ return -1; ++ } ++ break; ++ case SECUREC_CHAR('h'): ++ if (**format == SECUREC_CHAR('h')) { ++ *format = *format + 1; ++ attr->flags |= SECUREC_FLAG_CHAR; /* For char */ ++ } else { ++ attr->flags |= SECUREC_FLAG_SHORT; /* For short int */ ++ } ++ break; ++ case SECUREC_CHAR('w'): ++ attr->flags |= SECUREC_FLAG_WIDECHAR; /* For wide char */ ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++ return 0; ++} ++ ++/* ++ * Decoded char type identifier ++ */ ++SECUREC_INLINE void SecDecodeTypeC(SecFormatAttr *attr, unsigned int c) ++{ ++ attr->textLen = 1; /* Only 1 wide character */ ++ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) && !(defined(__hpux)) && !(defined(SECUREC_ON_SOLARIS)) ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++#endif ++ ++#ifdef SECUREC_FOR_WCHAR ++ if ((attr->flags & SECUREC_FLAG_SHORT) != 0) { ++ /* Get multibyte character from argument */ ++ attr->buffer.str[0] = (char)c; ++ attr->text.str = attr->buffer.str; ++ attr->textIsWide = 0; ++ } else { ++ attr->buffer.wStr[0] = (wchar_t)c; ++ attr->text.wStr = attr->buffer.wStr; ++ attr->textIsWide = 1; ++ } ++#else /* Not SECUREC_FOR_WCHAR */ ++ if ((attr->flags & (SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) != 0) { ++#if SECUREC_HAVE_WCHART ++ attr->buffer.wStr[0] = (wchar_t)c; ++ attr->text.wStr = attr->buffer.wStr; ++ attr->textIsWide = 1; ++#else ++ attr->textLen = 0; /* Ignore unsupported characters */ ++ attr->fldWidth = 0; /* No paddings */ ++#endif ++ } else { ++ /* Get multibyte character from argument */ ++ attr->buffer.str[0] = (char)c; ++ attr->text.str = attr->buffer.str; ++ attr->textIsWide = 0; ++ } ++#endif ++} ++ ++#ifdef SECUREC_FOR_WCHAR ++#define SECUREC_IS_NARROW_STRING(attr) (((attr)->flags & SECUREC_FLAG_SHORT) != 0) ++#else ++#define SECUREC_IS_NARROW_STRING(attr) (((attr)->flags & (SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) == 0) ++#endif ++ ++SECUREC_INLINE void SecDecodeTypeSchar(SecFormatAttr *attr) ++{ ++ size_t textLen; ++ if (attr->text.str == NULL) { ++ /* ++ * Literal string to print null ptr, define it as array rather than const text area ++ * To avoid gcc warning with pointing const text with variable ++ */ ++ static char strNullString[SECUREC_NULL_STRING_SIZE] = "(null)"; ++ attr->text.str = strNullString; ++ } ++ if (attr->precision == -1) { ++ /* Precision NOT assigned */ ++ /* The strlen performance is high when the string length is greater than 32 */ ++ textLen = strlen(attr->text.str); ++ if (textLen > SECUREC_STRING_MAX_LEN) { ++ textLen = 0; ++ } ++ } else { ++ /* Precision assigned */ ++ SECUREC_CALC_STR_LEN(attr->text.str, (size_t)(unsigned int)attr->precision, &textLen); ++ } ++ attr->textLen = (int)textLen; ++} ++ ++SECUREC_INLINE void SecDecodeTypeSwchar(SecFormatAttr *attr) ++{ ++#if SECUREC_HAVE_WCHART ++ size_t textLen; ++ attr->textIsWide = 1; ++ if (attr->text.wStr == NULL) { ++ /* ++ * Literal string to print null ptr, define it as array rather than const text area ++ * To avoid gcc warning with pointing const text with variable ++ */ ++ static wchar_t wStrNullString[SECUREC_NULL_STRING_SIZE] = { L'(', L'n', L'u', L'l', L'l', L')', L'\0', L'\0' }; ++ attr->text.wStr = wStrNullString; ++ } ++ /* The textLen in wchar_t,when precision is -1, it is unlimited */ ++ SECUREC_CALC_WSTR_LEN(attr->text.wStr, (size_t)(unsigned int)attr->precision, &textLen); ++ if (textLen > SECUREC_WCHAR_STRING_MAX_LEN) { ++ textLen = 0; ++ } ++ attr->textLen = (int)textLen; ++#else ++ attr->textLen = 0; ++#endif ++} ++ ++/* ++ * Decoded string identifier ++ */ ++SECUREC_INLINE void SecDecodeTypeS(SecFormatAttr *attr, char *argPtr) ++{ ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT)) ++#if (!defined(SECUREC_ON_UNIX)) ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++#endif ++#if (defined(SECUREC_FOR_WCHAR)) ++ if ((attr->flags & SECUREC_FLAG_LONG) == 0) { ++ attr->flags |= SECUREC_FLAG_SHORT; ++ } ++#endif ++#endif ++ attr->text.str = argPtr; ++ if (SECUREC_IS_NARROW_STRING(attr)) { ++ /* The textLen now contains length in multibyte chars */ ++ SecDecodeTypeSchar(attr); ++ } else { ++ /* The textLen now contains length in wide chars */ ++ SecDecodeTypeSwchar(attr); ++ } ++} ++ ++/* ++ * Check precision in format ++ */ ++SECUREC_INLINE int SecDecodePrecision(SecChar ch, SecFormatAttr *attr) ++{ ++ if (attr->dynPrecision == 0) { ++ /* Add digit to current precision */ ++ if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(attr->precision)) { ++ return -1; ++ } ++ attr->precision = (int)SECUREC_MUL_TEN((unsigned int)attr->precision) + ++ (unsigned char)(ch - SECUREC_CHAR('0')); ++ } else { ++ if (attr->precision < 0) { ++ attr->precision = -1; ++ } ++ if (attr->precision > SECUREC_MAX_WIDTH_LEN) { ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/* ++ * Check width in format ++ */ ++SECUREC_INLINE int SecDecodeWidth(SecChar ch, SecFormatAttr *attr, SecFmtState lastState) ++{ ++ if (attr->dynWidth == 0) { ++ if (lastState != STAT_WIDTH) { ++ attr->fldWidth = 0; ++ } ++ if (SECUREC_MUL_TEN_ADD_BEYOND_MAX(attr->fldWidth)) { ++ return -1; ++ } ++ attr->fldWidth = (int)SECUREC_MUL_TEN((unsigned int)attr->fldWidth) + ++ (unsigned char)(ch - SECUREC_CHAR('0')); ++ } else { ++ if (attr->fldWidth < 0) { ++ attr->flags |= SECUREC_FLAG_LEFT; ++ attr->fldWidth = (-attr->fldWidth); ++ } ++ if (attr->fldWidth > SECUREC_MAX_WIDTH_LEN) { ++ return -1; ++ } ++ } ++ return 0; ++} ++ ++/* ++ * The sprintf_s function processes the wide character as a parameter for %C ++ * The swprintf_s function processes the multiple character as a parameter for %C ++ */ ++SECUREC_INLINE void SecUpdateWcharFlags(SecFormatAttr *attr) ++{ ++ if ((attr->flags & (SECUREC_FLAG_SHORT | SECUREC_FLAG_LONG | SECUREC_FLAG_WIDECHAR)) == 0) { ++#ifdef SECUREC_FOR_WCHAR ++ attr->flags |= SECUREC_FLAG_SHORT; ++#else ++ attr->flags |= SECUREC_FLAG_WIDECHAR; ++#endif ++ } ++} ++/* ++ * When encountering %S, current just same as %C ++ */ ++SECUREC_INLINE void SecUpdateWstringFlags(SecFormatAttr *attr) ++{ ++ SecUpdateWcharFlags(attr); ++} ++ ++#if SECUREC_IN_KERNEL ++SECUREC_INLINE void SecUpdatePointFlagsForKernel(SecFormatAttr *attr) ++{ ++ /* Width is not set */ ++ if (attr->fldWidth <= 0) { ++ attr->flags |= SECUREC_FLAG_LEADZERO; ++ attr->fldWidth = 2 * sizeof(void *); /* 2 x byte number is the length of hex */ ++ } ++ if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { ++ /* Alternate form means '0x' prefix */ ++ attr->prefix[0] = SECUREC_CHAR('0'); ++ attr->prefix[1] = SECUREC_CHAR('x'); ++ attr->prefixLen = SECUREC_PREFIX_LEN; ++ } ++ attr->flags |= SECUREC_FLAG_LONG; /* Converting a long */ ++} ++#endif ++ ++SECUREC_INLINE void SecUpdatePointFlags(SecFormatAttr *attr) ++{ ++ attr->flags |= SECUREC_FLAG_POINTER; ++#if SECUREC_IN_KERNEL ++ SecUpdatePointFlagsForKernel(attr); ++#else ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) || defined(SECUREC_VXWORKS_PLATFORM)) && (!defined(SECUREC_ON_UNIX)) ++#if defined(SECUREC_VXWORKS_PLATFORM) ++ attr->precision = 1; ++#else ++ attr->precision = 0; ++#endif ++ attr->flags |= SECUREC_FLAG_ALTERNATE; /* "0x" is not default prefix in UNIX */ ++ attr->digits = g_itoaLowerDigits; ++#else /* On unix or win */ ++#if defined(_AIX) || defined(SECUREC_ON_SOLARIS) ++ attr->precision = 1; ++#else ++ attr->precision = 2 * sizeof(void *); /* 2 x byte number is the length of hex */ ++#endif ++#if defined(SECUREC_ON_UNIX) ++ attr->digits = g_itoaLowerDigits; ++#else ++ attr->digits = g_itoaUpperDigits; ++#endif ++#endif ++ ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++#endif ++ ++#ifdef SECUREC_ON_64BITS ++ attr->flags |= SECUREC_FLAG_I64; /* Converting an int64 */ ++#else ++ attr->flags |= SECUREC_FLAG_LONG; /* Converting a long */ ++#endif ++ /* Set up for %#p on different system */ ++ if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { ++ /* Alternate form means '0x' prefix */ ++ attr->prefix[0] = SECUREC_CHAR('0'); ++#if (defined(SECUREC_COMPATIBLE_LINUX_FORMAT) || defined(SECUREC_VXWORKS_PLATFORM)) ++ attr->prefix[1] = SECUREC_CHAR('x'); ++#else ++ attr->prefix[1] = (SecChar)(attr->digits[SECUREC_NUMBER_OF_X]); ++#endif ++#if defined(_AIX) || defined(SECUREC_ON_SOLARIS) ++ attr->prefixLen = 0; ++#else ++ attr->prefixLen = SECUREC_PREFIX_LEN; ++#endif ++ } ++#endif ++} ++ ++SECUREC_INLINE void SecUpdateXpxFlags(SecFormatAttr *attr, SecChar ch) ++{ ++ /* Use unsigned lower hex output for 'x' */ ++ attr->digits = g_itoaLowerDigits; ++ attr->radix = SECUREC_RADIX_HEX; ++ switch (ch) { ++ case SECUREC_CHAR('p'): ++ /* Print a pointer */ ++ SecUpdatePointFlags(attr); ++ break; ++ case SECUREC_CHAR('X'): /* fall-through */ /* FALLTHRU */ ++ /* Unsigned upper hex output */ ++ attr->digits = g_itoaUpperDigits; ++ /* fall-through */ /* FALLTHRU */ ++ default: ++ /* For %#x or %#X */ ++ if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { ++ /* Alternate form means '0x' prefix */ ++ attr->prefix[0] = SECUREC_CHAR('0'); ++ attr->prefix[1] = (SecChar)(attr->digits[SECUREC_NUMBER_OF_X]); ++ attr->prefixLen = SECUREC_PREFIX_LEN; ++ } ++ break; ++ } ++} ++ ++SECUREC_INLINE void SecUpdateOudiFlags(SecFormatAttr *attr, SecChar ch) ++{ ++ /* Do not set digits here */ ++ switch (ch) { ++ case SECUREC_CHAR('i'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('d'): /* fall-through */ /* FALLTHRU */ ++ /* For signed decimal output */ ++ attr->flags |= SECUREC_FLAG_SIGNED; ++ /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('u'): ++ attr->radix = SECUREC_RADIX_DECIMAL; ++ attr->digits = g_itoaLowerDigits; ++ break; ++ case SECUREC_CHAR('o'): ++ /* For unsigned octal output */ ++ attr->radix = SECUREC_RADIX_OCTAL; ++ attr->digits = g_itoaLowerDigits; ++ if ((attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { ++ /* Alternate form means force a leading 0 */ ++ attr->flags |= SECUREC_FLAG_FORCE_OCTAL; ++ } ++ break; ++ default: ++ /* Do nothing */ ++ break; ++ } ++} ++ ++#if SECUREC_ENABLE_SPRINTF_FLOAT ++SECUREC_INLINE void SecFreeFloatBuffer(SecFloatAdapt *floatAdapt) ++{ ++ if (floatAdapt->floatBuffer != NULL) { ++ SECUREC_FREE(floatAdapt->floatBuffer); ++ } ++ if (floatAdapt->allocatedFmtStr != NULL) { ++ SECUREC_FREE(floatAdapt->allocatedFmtStr); ++ } ++ floatAdapt->floatBuffer = NULL; ++ floatAdapt->allocatedFmtStr = NULL; ++ floatAdapt->fmtStr = NULL; ++ floatAdapt->bufferSize = 0; ++} ++ ++SECUREC_INLINE void SecSeekToFrontPercent(const SecChar **format) ++{ ++ const SecChar *fmt = *format; ++ while (*fmt != SECUREC_CHAR('%')) { /* Must meet '%' */ ++ --fmt; ++ } ++ *format = fmt; ++} ++ ++/* Init float format, return 0 is OK */ ++SECUREC_INLINE int SecInitFloatFmt(SecFloatAdapt *floatFmt, const SecChar *format) ++{ ++ const SecChar *fmt = format - 2; /* Sub 2 to the position before 'f' or 'g' */ ++ int fmtStrLen; ++ int i; ++ ++ SecSeekToFrontPercent(&fmt); ++ /* Now fmt point to '%' */ ++ fmtStrLen = (int)(size_t)(format - fmt) + 1; /* With ending terminator */ ++ if (fmtStrLen > (int)sizeof(floatFmt->buffer)) { ++ /* When buffer is NOT enough, alloc a new buffer */ ++ floatFmt->allocatedFmtStr = (char *)SECUREC_MALLOC((size_t)((unsigned int)fmtStrLen)); ++ if (floatFmt->allocatedFmtStr == NULL) { ++ return -1; ++ } ++ floatFmt->fmtStr = floatFmt->allocatedFmtStr; ++ } else { ++ floatFmt->fmtStr = floatFmt->buffer; ++ floatFmt->allocatedFmtStr = NULL; /* Must set to NULL, later code free memory based on this identity */ ++ } ++ ++ for (i = 0; i < fmtStrLen - 1; ++i) { ++ /* Convert wchar to char */ ++ floatFmt->fmtStr[i] = (char)(fmt[i]); /* Copy the format string */ ++ } ++ floatFmt->fmtStr[fmtStrLen - 1] = '\0'; ++ ++ return 0; ++} ++ ++/* Init float buffer and format, return 0 is OK */ ++SECUREC_INLINE int SecInitFloatBuffer(SecFloatAdapt *floatAdapt, const SecChar *format, SecFormatAttr *attr) ++{ ++ floatAdapt->allocatedFmtStr = NULL; ++ floatAdapt->fmtStr = NULL; ++ floatAdapt->floatBuffer = NULL; ++ /* Compute the precision value */ ++ if (attr->precision < 0) { ++ attr->precision = SECUREC_FLOAT_DEFAULT_PRECISION; ++ } ++ /* ++ * Calc buffer size to store double value ++ * The maximum length of SECUREC_MAX_WIDTH_LEN is enough ++ */ ++ if ((attr->flags & SECUREC_FLAG_LONG_DOUBLE) != 0) { ++ if (attr->precision > (SECUREC_MAX_WIDTH_LEN - SECUREC_FLOAT_BUFSIZE_LB)) { ++ return -1; ++ } ++ /* Long double needs to meet the basic print length */ ++ floatAdapt->bufferSize = SECUREC_FLOAT_BUFSIZE_LB + attr->precision + SECUREC_FLOAT_BUF_EXT; ++ } else { ++ if (attr->precision > (SECUREC_MAX_WIDTH_LEN - SECUREC_FLOAT_BUFSIZE)) { ++ return -1; ++ } ++ /* Double needs to meet the basic print length */ ++ floatAdapt->bufferSize = SECUREC_FLOAT_BUFSIZE + attr->precision + SECUREC_FLOAT_BUF_EXT; ++ } ++ if (attr->fldWidth > floatAdapt->bufferSize) { ++ floatAdapt->bufferSize = attr->fldWidth + SECUREC_FLOAT_BUF_EXT; ++ } ++ ++ if (floatAdapt->bufferSize > SECUREC_BUFFER_SIZE) { ++ /* The current value of SECUREC_BUFFER_SIZE could not store the formatted float string */ ++ floatAdapt->floatBuffer = (char *)SECUREC_MALLOC(((size_t)(unsigned int)floatAdapt->bufferSize)); ++ if (floatAdapt->floatBuffer == NULL) { ++ return -1; ++ } ++ attr->text.str = floatAdapt->floatBuffer; ++ } else { ++ attr->text.str = attr->buffer.str; /* Output buffer for float string with default size */ ++ } ++ ++ if (SecInitFloatFmt(floatAdapt, format) != 0) { ++ if (floatAdapt->floatBuffer != NULL) { ++ SECUREC_FREE(floatAdapt->floatBuffer); ++ floatAdapt->floatBuffer = NULL; ++ } ++ return -1; ++ } ++ return 0; ++} ++#endif ++ ++SECUREC_INLINE SecInt64 SecUpdateNegativeChar(SecFormatAttr *attr, char ch) ++{ ++ SecInt64 num64 = ch; /* Sign extend */ ++ if (num64 >= 128) { /* 128 on some platform, char is always unsigned */ ++ unsigned char tmp = (unsigned char)(~((unsigned char)ch)); ++ num64 = tmp + 1; ++ attr->flags |= SECUREC_FLAG_NEGATIVE; ++ } ++ return num64; ++} ++ ++/* ++ * If the precision is not satisfied, zero is added before the string ++ */ ++SECUREC_INLINE void SecNumberSatisfyPrecision(SecFormatAttr *attr) ++{ ++ int precision; ++ if (attr->precision < 0) { ++ precision = 1; /* Default precision 1 */ ++ } else { ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++#else ++ if ((attr->flags & SECUREC_FLAG_POINTER) == 0) { ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++ } ++#endif ++ if (attr->precision > SECUREC_MAX_PRECISION) { ++ attr->precision = SECUREC_MAX_PRECISION; ++ } ++ precision = attr->precision; ++ } ++ while (attr->textLen < precision) { ++ --attr->text.str; ++ *(attr->text.str) = '0'; ++ ++attr->textLen; ++ } ++} ++ ++/* ++ * Add leading zero for %#o ++ */ ++SECUREC_INLINE void SecNumberForceOctal(SecFormatAttr *attr) ++{ ++ /* Force a leading zero if FORCEOCTAL flag set */ ++ if ((attr->flags & SECUREC_FLAG_FORCE_OCTAL) != 0 && ++ (attr->textLen == 0 || attr->text.str[0] != '0')) { ++ --attr->text.str; ++ *(attr->text.str) = '0'; ++ ++attr->textLen; ++ } ++} ++ ++SECUREC_INLINE void SecUpdateSignedNumberPrefix(SecFormatAttr *attr) ++{ ++ if ((attr->flags & SECUREC_FLAG_SIGNED) == 0) { ++ return; ++ } ++ if ((attr->flags & SECUREC_FLAG_NEGATIVE) != 0) { ++ /* Prefix is '-' */ ++ attr->prefix[0] = SECUREC_CHAR('-'); ++ attr->prefixLen = 1; ++ return; ++ } ++ if ((attr->flags & SECUREC_FLAG_SIGN) != 0) { ++ /* Prefix is '+' */ ++ attr->prefix[0] = SECUREC_CHAR('+'); ++ attr->prefixLen = 1; ++ return; ++ } ++ if ((attr->flags & SECUREC_FLAG_SIGN_SPACE) != 0) { ++ /* Prefix is ' ' */ ++ attr->prefix[0] = SECUREC_CHAR(' '); ++ attr->prefixLen = 1; ++ return; ++ } ++ return; ++} ++ ++SECUREC_INLINE void SecNumberCompatZero(SecFormatAttr *attr) ++{ ++#if SECUREC_IN_KERNEL ++ if ((attr->flags & SECUREC_FLAG_POINTER) != 0) { ++ static char strNullPointer[SECUREC_NULL_STRING_SIZE] = "(null)"; ++ attr->text.str = strNullPointer; ++ attr->textLen = 6; /* Length of (null) is 6 */ ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++ attr->prefixLen = 0; ++ if (attr->precision >= 0 && attr->precision < attr->textLen) { ++ attr->textLen = attr->precision; ++ } ++ } ++ if ((attr->flags & SECUREC_FLAG_POINTER) == 0 && attr->radix == SECUREC_RADIX_HEX && ++ (attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { ++ /* Add 0x prefix for %x or %X, the prefix string has been set before */ ++ attr->prefixLen = SECUREC_PREFIX_LEN; ++ } ++#elif defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && (!defined(SECUREC_ON_UNIX)) ++ if ((attr->flags & SECUREC_FLAG_POINTER) != 0) { ++ static char strNullPointer[SECUREC_NULL_STRING_SIZE] = "(nil)"; ++ attr->text.str = strNullPointer; ++ attr->textLen = 5; /* Length of (nil) is 5 */ ++ attr->flags &= ~SECUREC_FLAG_LEADZERO; ++ } ++#elif defined(SECUREC_VXWORKS_PLATFORM) || defined(__hpux) ++ if ((attr->flags & SECUREC_FLAG_POINTER) != 0 && (attr->flags & SECUREC_FLAG_ALTERNATE) != 0) { ++ /* Add 0x prefix for %p, the prefix string has been set before */ ++ attr->prefixLen = SECUREC_PREFIX_LEN; ++ } ++#endif ++ (void)attr; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++} ++ ++/* ++ * Formatting output core function ++ */ ++SECUREC_INLINE int SecOutput(SecPrintfStream *stream, const SecChar *cFormat, va_list argList) ++{ ++ const SecChar *format = cFormat; ++ int charsOut; /* Characters written */ ++ int noOutput = 0; /* Must be initialized or compiler alerts */ ++ SecFmtState state; ++ SecFormatAttr formatAttr; ++ ++ formatAttr.flags = 0; ++ formatAttr.textIsWide = 0; /* Flag for buffer contains wide chars */ ++ formatAttr.fldWidth = 0; ++ formatAttr.precision = 0; ++ formatAttr.dynWidth = 0; ++ formatAttr.dynPrecision = 0; ++ formatAttr.digits = g_itoaUpperDigits; ++ formatAttr.radix = SECUREC_RADIX_DECIMAL; ++ formatAttr.padding = 0; ++ formatAttr.textLen = 0; ++ formatAttr.text.str = NULL; ++ formatAttr.prefixLen = 0; ++ formatAttr.prefix[0] = SECUREC_CHAR('\0'); ++ formatAttr.prefix[1] = SECUREC_CHAR('\0'); ++ charsOut = 0; ++ state = STAT_NORMAL; /* Starting state */ ++ ++ /* Loop each format character */ ++ while (*format != SECUREC_CHAR('\0') && charsOut >= 0) { ++ SecFmtState lastState = state; ++ SecChar ch = *format; /* Currently read character */ ++ ++format; ++ state = SecDecodeState(ch, lastState); ++ switch (state) { ++ case STAT_NORMAL: ++ SecWriteChar(stream, ch, &charsOut); ++ continue; ++ case STAT_PERCENT: ++ /* Set default values */ ++ noOutput = 0; ++ formatAttr.prefixLen = 0; ++ formatAttr.textLen = 0; ++ formatAttr.flags = 0; ++ formatAttr.fldWidth = 0; ++ formatAttr.precision = -1; ++ formatAttr.textIsWide = 0; ++ formatAttr.dynWidth = 0; ++ formatAttr.dynPrecision = 0; ++ break; ++ case STAT_FLAG: ++ /* Set flag based on which flag character */ ++ SecDecodeFlags(ch, &formatAttr); ++ break; ++ case STAT_WIDTH: ++ /* Update width value */ ++ if (ch == SECUREC_CHAR('*')) { ++ /* get width from arg list */ ++ formatAttr.fldWidth = (int)va_arg(argList, int); ++ formatAttr.dynWidth = 1; ++ } ++ if (SecDecodeWidth(ch, &formatAttr, lastState) != 0) { ++ return -1; ++ } ++ break; ++ case STAT_DOT: ++ formatAttr.precision = 0; ++ break; ++ case STAT_PRECIS: ++ /* Update precision value */ ++ if (ch == SECUREC_CHAR('*')) { ++ /* Get precision from arg list */ ++ formatAttr.precision = (int)va_arg(argList, int); ++ formatAttr.dynPrecision = 1; ++ } ++ if (SecDecodePrecision(ch, &formatAttr) != 0) { ++ return -1; ++ } ++ break; ++ case STAT_SIZE: ++ /* Read a size specifier, set the formatAttr.flags based on it, and skip format to next character */ ++ if (SecDecodeSize(ch, &formatAttr, &format) != 0) { ++ /* Compatibility code for "%I" just print I */ ++ SecWriteChar(stream, ch, &charsOut); ++ state = STAT_NORMAL; ++ continue; ++ } ++ break; ++ case STAT_TYPE: ++ switch (ch) { ++ case SECUREC_CHAR('C'): /* Wide char */ ++ SecUpdateWcharFlags(&formatAttr); ++ /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('c'): { ++ unsigned int cValue = (unsigned int)va_arg(argList, int); ++ SecDecodeTypeC(&formatAttr, cValue); ++ break; ++ } ++ case SECUREC_CHAR('S'): /* Wide char string */ ++ SecUpdateWstringFlags(&formatAttr); ++ /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('s'): { ++ char *argPtr = (char *)va_arg(argList, char *); ++ SecDecodeTypeS(&formatAttr, argPtr); ++ break; ++ } ++ case SECUREC_CHAR('G'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('g'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('E'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('F'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('e'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('f'): { ++#if SECUREC_ENABLE_SPRINTF_FLOAT ++ /* Add following code to call system sprintf API for float number */ ++ SecFloatAdapt floatAdapt; ++ noOutput = 1; /* It's no more data needs to be written */ ++ ++ /* Now format is pointer to the next character of 'f' */ ++ if (SecInitFloatBuffer(&floatAdapt, format, &formatAttr) != 0) { ++ break; ++ } ++ ++ if ((formatAttr.flags & SECUREC_FLAG_LONG_DOUBLE) != 0) { ++#if defined(SECUREC_COMPATIBLE_LINUX_FORMAT) && SECUREC_ENABLE_SPRINTF_LONG_DOUBLE ++ long double tmp = (long double)va_arg(argList, long double); ++ SecFormatLongDouble(&formatAttr, &floatAdapt, tmp); ++#else ++ double tmp = (double)va_arg(argList, double); ++ SecFormatDouble(&formatAttr, &floatAdapt, tmp); ++#endif ++ } else { ++ double tmp = (double)va_arg(argList, double); ++ SecFormatDouble(&formatAttr, &floatAdapt, tmp); ++ } ++ ++ /* Only need write formatted float string */ ++ SecWriteFloatText(stream, &formatAttr, &charsOut); ++ SecFreeFloatBuffer(&floatAdapt); ++ break; ++#else ++ return -1; ++#endif ++ } ++ case SECUREC_CHAR('X'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('p'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('x'): /* fall-through */ /* FALLTHRU */ ++ SecUpdateXpxFlags(&formatAttr, ch); ++ /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('i'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('d'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('u'): /* fall-through */ /* FALLTHRU */ ++ case SECUREC_CHAR('o'): { ++ SecInt64 num64; ++ SecUpdateOudiFlags(&formatAttr, ch); ++ /* Read argument into variable num64. Be careful, depend on the order of judgment */ ++ if ((formatAttr.flags & SECUREC_FLAG_I64) != 0 || ++ (formatAttr.flags & SECUREC_FLAG_LONGLONG) != 0) { ++ num64 = (SecInt64)va_arg(argList, SecInt64); /* Maximum Bit Width sign bit unchanged */ ++ } else if ((formatAttr.flags & SECUREC_FLAG_LONG) != 0) { ++ num64 = SECUREC_GET_LONG_FROM_ARG(formatAttr); ++ } else if ((formatAttr.flags & SECUREC_FLAG_CHAR) != 0) { ++ num64 = SECUREC_GET_CHAR_FROM_ARG(formatAttr); ++ } else if ((formatAttr.flags & SECUREC_FLAG_SHORT) != 0) { ++ num64 = SECUREC_GET_SHORT_FROM_ARG(formatAttr); ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++ } else if ((formatAttr.flags & SECUREC_FLAG_PTRDIFF) != 0) { ++ num64 = (ptrdiff_t)va_arg(argList, ptrdiff_t); /* Sign extend */ ++ } else if ((formatAttr.flags & SECUREC_FLAG_SIZE) != 0) { ++ num64 = SECUREC_GET_SIZE_FROM_ARG(formatAttr); ++ } else if ((formatAttr.flags & SECUREC_FLAG_INTMAX) != 0) { ++ num64 = (SecInt64)va_arg(argList, SecInt64); ++#endif ++ } else { ++ num64 = SECUREC_GET_INT_FROM_ARG(formatAttr); ++ } ++ ++ /* The order of the following calls must be correct */ ++ SecNumberToBuffer(&formatAttr, num64); ++ SecNumberSatisfyPrecision(&formatAttr); ++ SecNumberForceOctal(&formatAttr); ++ SecUpdateSignedNumberPrefix(&formatAttr); ++ if (num64 == 0) { ++ SecNumberCompatZero(&formatAttr); ++ } ++ break; ++ } ++ default: ++ /* Do nothing */ ++ break; ++ } ++ ++ if (noOutput == 0) { ++ /* Calculate amount of padding */ ++ formatAttr.padding = (formatAttr.fldWidth - formatAttr.textLen) - formatAttr.prefixLen; ++ ++ /* Put out the padding, prefix, and text, in the correct order */ ++ SecWriteLeftPadding(stream, &formatAttr, &charsOut); ++ SecWritePrefix(stream, &formatAttr, &charsOut); ++ SecWriteLeadingZero(stream, &formatAttr, &charsOut); ++ SecWriteText(stream, &formatAttr, &charsOut); ++ SecWriteRightPadding(stream, &formatAttr, &charsOut); ++ } ++ break; ++ case STAT_INVALID: /* fall-through */ /* FALLTHRU */ ++ default: ++ return -1; /* Input format is wrong(STAT_INVALID), directly return */ ++ } ++ } ++ ++ if (state != STAT_NORMAL && state != STAT_TYPE) { ++ return -1; ++ } ++ ++ return charsOut; /* The number of characters written */ ++} ++ ++/* ++ * Output one zero character zero into the SecPrintfStream structure ++ * If there is not enough space, make sure f->count is less than 0 ++ */ ++SECUREC_INLINE int SecPutZeroChar(SecPrintfStream *stream) ++{ ++ --stream->count; ++ if (stream->count >= 0) { ++ *(stream->cur) = SECUREC_CHAR('\0'); ++ ++stream->cur; ++ return 0; ++ } ++ return -1; ++} ++ ++/* ++ * Multi character formatted output implementation ++ */ ++#ifdef SECUREC_FOR_WCHAR ++int SecVswprintfImpl(wchar_t *string, size_t count, const wchar_t *format, va_list argList) ++#else ++int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList) ++#endif ++{ ++ SecPrintfStream stream; ++ int retVal; ++ ++ stream.count = (int)count; /* The count include \0 character, must be greater than zero */ ++ stream.cur = string; ++ ++ retVal = SecOutput(&stream, format, argList); ++ if (retVal >= 0) { ++ if (SecPutZeroChar(&stream) == 0) { ++ return retVal; ++ } ++ } ++ if (stream.count < 0) { ++ /* The buffer was too small, then truncate */ ++ string[count - 1] = SECUREC_CHAR('\0'); ++ return SECUREC_PRINTF_TRUNCATE; ++ } ++ string[0] = SECUREC_CHAR('\0'); /* Empty the dest string */ ++ return -1; ++} ++#endif /* OUTPUT_INL_2B263E9C_43D8_44BB_B17A_6D2033DECEE5 */ ++ +diff --git a/lib/securec/src/scanf_s.c b/lib/securec/src/scanf_s.c +new file mode 100644 +index 000000000000..dc575714e516 +--- /dev/null ++++ b/lib/securec/src/scanf_s.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: scanf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "linux/securec.h" ++ ++/* ++ * ++ * The scanf_s function is equivalent to fscanf_s with the argument stdin interposed before the arguments to scanf_s ++ * The scanf_s function reads data from the standard input stream stdin and ++ * writes the data into the location that's given by argument. Each argument ++ * must be a pointer to a variable of a type that corresponds to a type specifier ++ * in format. If copying occurs between strings that overlap, the behavior is ++ * undefined. ++ * ++ * ++ * format Format control string. ++ * ... Optional arguments. ++ * ++ * ++ * ... The converted value stored in user assigned address ++ * ++ * ++ * Returns the number of fields successfully converted and assigned; ++ * the return value does not include fields that were read but not assigned. ++ * A return value of 0 indicates that no fields were assigned. ++ * return -1 if an error occurs. ++ */ ++int scanf_s(const char *format, ...) ++{ ++ int ret; /* If initialization causes e838 */ ++ va_list argList; ++ ++ va_start(argList, format); ++ ret = vscanf_s(format, argList); ++ va_end(argList); ++ (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ ++ return ret; ++} ++ +diff --git a/lib/securec/src/secinput.h b/lib/securec/src/secinput.h +new file mode 100644 +index 000000000000..176ee05d96d4 +--- /dev/null ++++ b/lib/securec/src/secinput.h +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Define macro, data struct, and declare function prototype, ++ * which is used by input.inl, secureinput_a.c and secureinput_w.c. ++ * Create: 2014-02-25 ++ */ ++ ++#ifndef SEC_INPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C ++#define SEC_INPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C ++#include "securecutil.h" ++ ++#define SECUREC_SCANF_EINVAL (-1) ++#define SECUREC_SCANF_ERROR_PARA (-2) ++ ++/* For internal stream flag */ ++#define SECUREC_MEM_STR_FLAG 0x01U ++#define SECUREC_FILE_STREAM_FLAG 0x02U ++#define SECUREC_PIPE_STREAM_FLAG 0x04U ++#define SECUREC_LOAD_FILE_TO_MEM_FLAG 0x08U ++ ++#define SECUREC_UCS_BOM_HEADER_SIZE 2U ++#define SECUREC_UCS_BOM_HEADER_BE_1ST 0xfeU ++#define SECUREC_UCS_BOM_HEADER_BE_2ST 0xffU ++#define SECUREC_UCS_BOM_HEADER_LE_1ST 0xffU ++#define SECUREC_UCS_BOM_HEADER_LE_2ST 0xfeU ++#define SECUREC_UTF8_BOM_HEADER_SIZE 3U ++#define SECUREC_UTF8_BOM_HEADER_1ST 0xefU ++#define SECUREC_UTF8_BOM_HEADER_2ND 0xbbU ++#define SECUREC_UTF8_BOM_HEADER_3RD 0xbfU ++#define SECUREC_UTF8_LEAD_1ST 0xe0U ++#define SECUREC_UTF8_LEAD_2ND 0x80U ++ ++#define SECUREC_BEGIN_WITH_UCS_BOM(s, len) ((len) == SECUREC_UCS_BOM_HEADER_SIZE && \ ++ (((unsigned char)((s)[0]) == SECUREC_UCS_BOM_HEADER_LE_1ST && \ ++ (unsigned char)((s)[1]) == SECUREC_UCS_BOM_HEADER_LE_2ST) || \ ++ ((unsigned char)((s)[0]) == SECUREC_UCS_BOM_HEADER_BE_1ST && \ ++ (unsigned char)((s)[1]) == SECUREC_UCS_BOM_HEADER_BE_2ST))) ++ ++#define SECUREC_BEGIN_WITH_UTF8_BOM(s, len) ((len) == SECUREC_UTF8_BOM_HEADER_SIZE && \ ++ (unsigned char)((s)[0]) == SECUREC_UTF8_BOM_HEADER_1ST && \ ++ (unsigned char)((s)[1]) == SECUREC_UTF8_BOM_HEADER_2ND && \ ++ (unsigned char)((s)[2]) == SECUREC_UTF8_BOM_HEADER_3RD) ++ ++#ifdef SECUREC_FOR_WCHAR ++#define SECUREC_BOM_HEADER_SIZE SECUREC_UCS_BOM_HEADER_SIZE ++#define SECUREC_BEGIN_WITH_BOM(s, len) SECUREC_BEGIN_WITH_UCS_BOM((s), (len)) ++#else ++#define SECUREC_BOM_HEADER_SIZE SECUREC_UTF8_BOM_HEADER_SIZE ++#define SECUREC_BEGIN_WITH_BOM(s, len) SECUREC_BEGIN_WITH_UTF8_BOM((s), (len)) ++#endif ++ ++typedef struct { ++ unsigned int flag; /* Mark the properties of input stream */ ++ char *base; /* The pointer to the header of buffered string */ ++ const char *cur; /* The pointer to next read position */ ++ size_t count; /* The size of buffered string in bytes */ ++#if SECUREC_ENABLE_SCANF_FILE ++ FILE *pf; /* The file pointer */ ++ size_t fileRealRead; ++ long oriFilePos; /* The original position of file offset when fscanf is called */ ++#endif ++} SecFileStream; ++ ++#if SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_FILE_STREAM_INIT_FILE(stream, fp) do { \ ++ (stream)->pf = (fp); \ ++ (stream)->fileRealRead = 0; \ ++ (stream)->oriFilePos = 0; \ ++} SECUREC_WHILE_ZERO ++#else ++/* Disable file */ ++#define SECUREC_FILE_STREAM_INIT_FILE(stream, fp) ++#endif ++ ++/* This initialization for eliminating redundant initialization. */ ++#define SECUREC_FILE_STREAM_FROM_STRING(stream, buf, cnt) do { \ ++ (stream)->flag = SECUREC_MEM_STR_FLAG; \ ++ (stream)->base = NULL; \ ++ (stream)->cur = (buf); \ ++ (stream)->count = (cnt); \ ++ SECUREC_FILE_STREAM_INIT_FILE((stream), NULL); \ ++} SECUREC_WHILE_ZERO ++ ++/* This initialization for eliminating redundant initialization. */ ++#define SECUREC_FILE_STREAM_FROM_FILE(stream, fp) do { \ ++ (stream)->flag = SECUREC_FILE_STREAM_FLAG; \ ++ (stream)->base = NULL; \ ++ (stream)->cur = NULL; \ ++ (stream)->count = 0; \ ++ SECUREC_FILE_STREAM_INIT_FILE((stream), (fp)); \ ++} SECUREC_WHILE_ZERO ++ ++/* This initialization for eliminating redundant initialization. */ ++#define SECUREC_FILE_STREAM_FROM_STDIN(stream) do { \ ++ (stream)->flag = SECUREC_PIPE_STREAM_FLAG; \ ++ (stream)->base = NULL; \ ++ (stream)->cur = NULL; \ ++ (stream)->count = 0; \ ++ SECUREC_FILE_STREAM_INIT_FILE((stream), SECUREC_STREAM_STDIN); \ ++} SECUREC_WHILE_ZERO ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++int SecInputS(SecFileStream *stream, const char *cFormat, va_list argList); ++void SecClearDestBuf(const char *buffer, const char *format, va_list argList); ++#ifdef SECUREC_FOR_WCHAR ++int SecInputSW(SecFileStream *stream, const wchar_t *cFormat, va_list argList); ++void SecClearDestBufW(const wchar_t *buffer, const wchar_t *format, va_list argList); ++#endif ++ ++/* 20150105 For software and hardware decoupling,such as UMG */ ++#ifdef SECUREC_SYSAPI4VXWORKS ++#ifdef feof ++#undef feof ++#endif ++extern int feof(FILE *stream); ++#endif ++ ++#if defined(SECUREC_SYSAPI4VXWORKS) || defined(SECUREC_CTYPE_MACRO_ADAPT) ++#ifndef isspace ++#define isspace(c) (((c) == ' ') || ((c) == '\t') || ((c) == '\r') || ((c) == '\n')) ++#endif ++#ifndef iswspace ++#define iswspace(c) (((c) == L' ') || ((c) == L'\t') || ((c) == L'\r') || ((c) == L'\n')) ++#endif ++#ifndef isascii ++#define isascii(c) (((unsigned char)(c)) <= 0x7f) ++#endif ++#ifndef isupper ++#define isupper(c) ((c) >= 'A' && (c) <= 'Z') ++#endif ++#ifndef islower ++#define islower(c) ((c) >= 'a' && (c) <= 'z') ++#endif ++#ifndef isalpha ++#define isalpha(c) (isupper(c) || (islower(c))) ++#endif ++#ifndef isdigit ++#define isdigit(c) ((c) >= '0' && (c) <= '9') ++#endif ++#ifndef isxupper ++#define isxupper(c) ((c) >= 'A' && (c) <= 'F') ++#endif ++#ifndef isxlower ++#define isxlower(c) ((c) >= 'a' && (c) <= 'f') ++#endif ++#ifndef isxdigit ++#define isxdigit(c) (isdigit(c) || isxupper(c) || isxlower(c)) ++#endif ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++/* Reserved file operation macro interface, s is FILE *, i is fileno zero. */ ++#ifndef SECUREC_LOCK_FILE ++#define SECUREC_LOCK_FILE(s) ++#endif ++ ++#ifndef SECUREC_UNLOCK_FILE ++#define SECUREC_UNLOCK_FILE(s) ++#endif ++ ++#ifndef SECUREC_LOCK_STDIN ++#define SECUREC_LOCK_STDIN(i, s) ++#endif ++ ++#ifndef SECUREC_UNLOCK_STDIN ++#define SECUREC_UNLOCK_STDIN(i, s) ++#endif ++#endif ++ +diff --git a/lib/securec/src/securecutil.c b/lib/securec/src/securecutil.c +new file mode 100644 +index 000000000000..7518eb300b2e +--- /dev/null ++++ b/lib/securec/src/securecutil.c +@@ -0,0 +1,81 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Provides internal functions used by this library, such as memory ++ * copy and memory move. Besides, include some helper function for ++ * printf family API, such as SecVsnprintfImpl ++ * Create: 2014-02-25 ++ */ ++ ++/* Avoid duplicate header files,not include securecutil.h */ ++#include "securecutil.h" ++ ++#if defined(ANDROID) && !defined(SECUREC_CLOSE_ANDROID_HANDLE) && (SECUREC_HAVE_WCTOMB || SECUREC_HAVE_MBTOWC) ++#include ++#if SECUREC_HAVE_WCTOMB ++/* ++ * Convert wide characters to narrow multi-bytes ++ */ ++int wctomb(char *s, wchar_t wc) ++{ ++ return (int)wcrtomb(s, wc, NULL); ++} ++#endif ++ ++#if SECUREC_HAVE_MBTOWC ++/* ++ * Converting narrow multi-byte characters to wide characters ++ * mbrtowc returns -1 or -2 upon failure, unlike mbtowc, which only returns -1 ++ * When the return value is less than zero, we treat it as a failure ++ */ ++int mbtowc(wchar_t *pwc, const char *s, size_t n) ++{ ++ return (int)mbrtowc(pwc, s, n, NULL); ++} ++#endif ++#endif ++ ++/* The V100R001C01 version num is 0x5 (High 8 bits) */ ++#define SECUREC_C_VERSION 0x500U ++#define SECUREC_SPC_VERSION 0xbU ++#define SECUREC_VERSION_STR "V100R001C01SPC011B003" ++ ++/* ++ * Get version string and version number. ++ * The rules for version number are as follows: ++ * 1) SPC verNumber<->verStr like: ++ * 0x201<->C01 ++ * 0x202<->C01SPC001 Redefine numbers after this version ++ * 0x502<->C01SPC002 ++ * 0x503<->C01SPC003 ++ * ... ++ * 0X50a<->SPC010 ++ * 0X50b<->SPC011 ++ * ... ++ * 0x700<->C02 ++ * 0x701<->C01SPC001 ++ * 0x702<->C02SPC002 ++ * ... ++ * 2) CP verNumber<->verStr like: ++ * 0X601<->CP0001 ++ * 0X602<->CP0002 ++ * ... ++ */ ++const char *GetHwSecureCVersion(unsigned short *verNumber) ++{ ++ if (verNumber != NULL) { ++ *verNumber = (unsigned short)(SECUREC_C_VERSION | SECUREC_SPC_VERSION); ++ } ++ return SECUREC_VERSION_STR; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(GetHwSecureCVersion); ++#endif ++ +diff --git a/lib/securec/src/securecutil.h b/lib/securec/src/securecutil.h +new file mode 100644 +index 000000000000..35112a248658 +--- /dev/null ++++ b/lib/securec/src/securecutil.h +@@ -0,0 +1,574 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Define macro, data struct, and declare internal used function prototype, ++ * which is used by secure functions. ++ * Create: 2014-02-25 ++ */ ++ ++#ifndef SECURECUTIL_H_46C86578_F8FF_4E49_8E64_9B175241761F ++#define SECURECUTIL_H_46C86578_F8FF_4E49_8E64_9B175241761F ++#include "linux/securec.h" ++ ++#if (defined(_MSC_VER)) && (_MSC_VER >= 1400) ++/* Shield compilation alerts using discarded functions and Constant expression to maximize code compatibility */ ++#define SECUREC_MASK_MSVC_CRT_WARNING __pragma(warning(push)) \ ++ __pragma(warning(disable : 4996 4127)) ++#define SECUREC_END_MASK_MSVC_CRT_WARNING __pragma(warning(pop)) ++#else ++#define SECUREC_MASK_MSVC_CRT_WARNING ++#define SECUREC_END_MASK_MSVC_CRT_WARNING ++#endif ++#define SECUREC_WHILE_ZERO SECUREC_MASK_MSVC_CRT_WARNING while (0) SECUREC_END_MASK_MSVC_CRT_WARNING ++ ++/* Automatically identify the platform that supports strnlen function, and use this function to improve performance */ ++#ifndef SECUREC_HAVE_STRNLEN ++#if (defined(_XOPEN_SOURCE) && _XOPEN_SOURCE >= 700) || (defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE >= 200809L) ++#if SECUREC_IN_KERNEL ++#define SECUREC_HAVE_STRNLEN 0 ++#else ++#if defined(__GLIBC__) && __GLIBC__ >= 2 && defined(__GLIBC_MINOR__) && __GLIBC_MINOR__ >= 10 ++#define SECUREC_HAVE_STRNLEN 1 ++#else ++#define SECUREC_HAVE_STRNLEN 0 ++#endif ++#endif ++#else ++#define SECUREC_HAVE_STRNLEN 0 ++#endif ++#endif ++ ++#if SECUREC_IN_KERNEL ++/* In kernel disable functions */ ++#ifndef SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_SCANF_FILE 0 ++#endif ++#ifndef SECUREC_ENABLE_SCANF_FLOAT ++#define SECUREC_ENABLE_SCANF_FLOAT 0 ++#endif ++#ifndef SECUREC_ENABLE_SPRINTF_FLOAT ++#define SECUREC_ENABLE_SPRINTF_FLOAT 0 ++#endif ++#ifndef SECUREC_HAVE_MBTOWC ++#define SECUREC_HAVE_MBTOWC 0 ++#endif ++#ifndef SECUREC_HAVE_WCTOMB ++#define SECUREC_HAVE_WCTOMB 0 ++#endif ++#ifndef SECUREC_HAVE_WCHART ++#define SECUREC_HAVE_WCHART 0 ++#endif ++#else /* Not in kernel */ ++/* Systems that do not support file, can define this macro to 0. */ ++#ifndef SECUREC_ENABLE_SCANF_FILE ++#define SECUREC_ENABLE_SCANF_FILE 1 ++#endif ++#ifndef SECUREC_ENABLE_SCANF_FLOAT ++#define SECUREC_ENABLE_SCANF_FLOAT 0 ++#endif ++/* Systems that do not support float, can define this macro to 0. */ ++#ifndef SECUREC_ENABLE_SPRINTF_FLOAT ++#define SECUREC_ENABLE_SPRINTF_FLOAT 1 ++#endif ++#ifndef SECUREC_HAVE_MBTOWC ++#define SECUREC_HAVE_MBTOWC 0 ++#endif ++#ifndef SECUREC_HAVE_WCTOMB ++#define SECUREC_HAVE_WCTOMB 0 ++#endif ++#ifndef SECUREC_HAVE_WCHART ++#define SECUREC_HAVE_WCHART 1 ++#endif ++#endif ++ ++#ifndef SECUREC_ENABLE_INLINE ++#define SECUREC_ENABLE_INLINE 0 ++#endif ++ ++#ifndef SECUREC_INLINE ++#if SECUREC_ENABLE_INLINE ++#define SECUREC_INLINE static inline ++#else ++#define SECUREC_INLINE static ++#endif ++#endif ++ ++#ifndef SECUREC_WARP_OUTPUT ++#if SECUREC_IN_KERNEL ++#define SECUREC_WARP_OUTPUT 1 ++#else ++#define SECUREC_WARP_OUTPUT 0 ++#endif ++#endif ++ ++#ifndef SECUREC_STREAM_STDIN ++#define SECUREC_STREAM_STDIN stdin ++#endif ++ ++#define SECUREC_MUL_SIXTEEN(x) ((x) << 4U) ++#define SECUREC_MUL_EIGHT(x) ((x) << 3U) ++#define SECUREC_MUL_TEN(x) ((((x) << 2U) + (x)) << 1U) ++/* Limited format input and output width, use signed integer */ ++#define SECUREC_MAX_WIDTH_LEN_DIV_TEN 21474836 ++#define SECUREC_MAX_WIDTH_LEN (SECUREC_MAX_WIDTH_LEN_DIV_TEN * 10) ++/* Is the x multiplied by 10 greater than */ ++#define SECUREC_MUL_TEN_ADD_BEYOND_MAX(x) (((x) > SECUREC_MAX_WIDTH_LEN_DIV_TEN)) ++ ++#define SECUREC_FLOAT_BUFSIZE (309 + 40) /* Max length of double value */ ++#define SECUREC_FLOAT_BUFSIZE_LB (4932 + 40) /* Max length of long double value */ ++#define SECUREC_FLOAT_DEFAULT_PRECISION 6 ++ ++/* This macro does not handle pointer equality or integer overflow */ ++#define SECUREC_MEMORY_NO_OVERLAP(dest, src, count) \ ++ (((src) < (dest) && ((const char *)(src) + (count)) <= (char *)(dest)) || \ ++ ((dest) < (src) && ((char *)(dest) + (count)) <= (const char *)(src))) ++ ++#define SECUREC_MEMORY_IS_OVERLAP(dest, src, count) \ ++ (((src) < (dest) && ((const char *)(src) + (count)) > (char *)(dest)) || \ ++ ((dest) < (src) && ((char *)(dest) + (count)) > (const char *)(src))) ++ ++/* ++ * Check whether the strings overlap, len is the length of the string not include terminator ++ * Length is related to data type char or wchar , do not force conversion of types ++ */ ++#define SECUREC_STRING_NO_OVERLAP(dest, src, len) \ ++ (((src) < (dest) && ((src) + (len)) < (dest)) || \ ++ ((dest) < (src) && ((dest) + (len)) < (src))) ++ ++/* ++ * Check whether the strings overlap for strcpy wcscpy function, dest len and src Len are not include terminator ++ * Length is related to data type char or wchar , do not force conversion of types ++ */ ++#define SECUREC_STRING_IS_OVERLAP(dest, src, len) \ ++ (((src) < (dest) && ((src) + (len)) >= (dest)) || \ ++ ((dest) < (src) && ((dest) + (len)) >= (src))) ++ ++/* ++ * Check whether the strings overlap for strcat wcscat function, dest len and src Len are not include terminator ++ * Length is related to data type char or wchar , do not force conversion of types ++ */ ++#define SECUREC_CAT_STRING_IS_OVERLAP(dest, destLen, src, srcLen) \ ++ (((dest) < (src) && ((dest) + (destLen) + (srcLen)) >= (src)) || \ ++ ((src) < (dest) && ((src) + (srcLen)) >= (dest))) ++ ++#if SECUREC_HAVE_STRNLEN ++#define SECUREC_CALC_STR_LEN(str, maxLen, outLen) do { \ ++ *(outLen) = strnlen((str), (maxLen)); \ ++} SECUREC_WHILE_ZERO ++#define SECUREC_CALC_STR_LEN_OPT(str, maxLen, outLen) do { \ ++ if ((maxLen) > 8) { \ ++ /* Optimization or len less then 8 */ \ ++ if (*((str) + 0) == '\0') { \ ++ *(outLen) = 0; \ ++ } else if (*((str) + 1) == '\0') { \ ++ *(outLen) = 1; \ ++ } else if (*((str) + 2) == '\0') { \ ++ *(outLen) = 2; \ ++ } else if (*((str) + 3) == '\0') { \ ++ *(outLen) = 3; \ ++ } else if (*((str) + 4) == '\0') { \ ++ *(outLen) = 4; \ ++ } else if (*((str) + 5) == '\0') { \ ++ *(outLen) = 5; \ ++ } else if (*((str) + 6) == '\0') { \ ++ *(outLen) = 6; \ ++ } else if (*((str) + 7) == '\0') { \ ++ *(outLen) = 7; \ ++ } else if (*((str) + 8) == '\0') { \ ++ /* Optimization with a length of 8 */ \ ++ *(outLen) = 8; \ ++ } else { \ ++ /* The offset is 8 because the performance of 8 byte alignment is high */ \ ++ *(outLen) = 8 + strnlen((str) + 8, (maxLen) - 8); \ ++ } \ ++ } else { \ ++ SECUREC_CALC_STR_LEN((str), (maxLen), (outLen)); \ ++ } \ ++} SECUREC_WHILE_ZERO ++#else ++#define SECUREC_CALC_STR_LEN(str, maxLen, outLen) do { \ ++ const char *strEnd_ = (const char *)(str); \ ++ size_t availableSize_ = (size_t)(maxLen); \ ++ while (availableSize_ > 0 && *strEnd_ != '\0') { \ ++ --availableSize_; \ ++ ++strEnd_; \ ++ } \ ++ *(outLen) = (size_t)(strEnd_ - (str)); \ ++} SECUREC_WHILE_ZERO ++#define SECUREC_CALC_STR_LEN_OPT SECUREC_CALC_STR_LEN ++#endif ++ ++#define SECUREC_CALC_WSTR_LEN(str, maxLen, outLen) do { \ ++ const wchar_t *strEnd_ = (const wchar_t *)(str); \ ++ size_t len_ = 0; \ ++ while (len_ < (maxLen) && *strEnd_ != L'\0') { \ ++ ++len_; \ ++ ++strEnd_; \ ++ } \ ++ *(outLen) = len_; \ ++} SECUREC_WHILE_ZERO ++ ++/* ++ * Performance optimization, product may disable inline function. ++ * Using function pointer for MEMSET to prevent compiler optimization when cleaning up memory. ++ */ ++#ifdef SECUREC_USE_ASM ++#define SECUREC_MEMSET_FUNC_OPT memset_opt ++#define SECUREC_MEMCPY_FUNC_OPT memcpy_opt ++#else ++#define SECUREC_MEMSET_FUNC_OPT memset ++#define SECUREC_MEMCPY_FUNC_OPT memcpy ++#endif ++ ++#define SECUREC_MEMCPY_WARP_OPT(dest, src, count) (void)SECUREC_MEMCPY_FUNC_OPT((dest), (src), (count)) ++ ++#ifndef SECUREC_MEMSET_BARRIER ++#if defined(__GNUC__) ++/* Can be turned off for scenarios that do not use memory barrier */ ++#define SECUREC_MEMSET_BARRIER 1 ++#else ++#define SECUREC_MEMSET_BARRIER 0 ++#endif ++#endif ++ ++#ifndef SECUREC_MEMSET_INDIRECT_USE ++/* Can be turned off for scenarios that do not allow pointer calls */ ++#define SECUREC_MEMSET_INDIRECT_USE 1 ++#endif ++ ++#if SECUREC_MEMSET_BARRIER ++#define SECUREC_MEMORY_BARRIER(dest) __asm__ __volatile__("": : "r"(dest) : "memory") ++#else ++#define SECUREC_MEMORY_BARRIER(dest) ++#endif ++ ++#if SECUREC_MEMSET_BARRIER ++#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) do { \ ++ (void)SECUREC_MEMSET_FUNC_OPT(dest, value, count); \ ++ SECUREC_MEMORY_BARRIER(dest); \ ++} SECUREC_WHILE_ZERO ++#elif SECUREC_MEMSET_INDIRECT_USE ++#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) do { \ ++ void *(* const volatile fn_)(void *s_, int c_, size_t n_) = SECUREC_MEMSET_FUNC_OPT; \ ++ (void)(*fn_)((dest), (value), (count)); \ ++} SECUREC_WHILE_ZERO ++#else ++#define SECUREC_MEMSET_PREVENT_DSE(dest, value, count) (void)SECUREC_MEMSET_FUNC_OPT((dest), (value), (count)) ++#endif ++ ++#ifdef SECUREC_FORMAT_OUTPUT_INPUT ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) || defined(__ARMCC_VERSION) ++typedef __int64 SecInt64; ++typedef unsigned __int64 SecUnsignedInt64; ++#if defined(__ARMCC_VERSION) ++typedef unsigned int SecUnsignedInt32; ++#else ++typedef unsigned __int32 SecUnsignedInt32; ++#endif ++#else ++typedef unsigned int SecUnsignedInt32; ++typedef long long SecInt64; ++typedef unsigned long long SecUnsignedInt64; ++#endif ++ ++#ifdef SECUREC_FOR_WCHAR ++#if 1//defined(SECUREC_VXWORKS_PLATFORM) && !defined(__WINT_TYPE__) ++typedef wchar_t wint_t; ++#endif ++#ifndef WEOF ++#define WEOF ((wchar_t)(-1)) ++#endif ++#define SECUREC_CHAR(x) L ## x ++typedef wchar_t SecChar; ++typedef wchar_t SecUnsignedChar; ++typedef wint_t SecInt; ++typedef wint_t SecUnsignedInt; ++#else /* no SECUREC_FOR_WCHAR */ ++#define SECUREC_CHAR(x) (x) ++typedef char SecChar; ++typedef unsigned char SecUnsignedChar; ++typedef int SecInt; ++typedef unsigned int SecUnsignedInt; ++#endif ++#endif ++ ++/* ++ * Determine whether the address is 8-byte aligned ++ * Some systems do not have uintptr_t type, so use NULL to clear tool alarm 507 ++ */ ++#define SECUREC_ADDR_ALIGNED_8(addr) ((((size_t)(addr)) & 7U) == 0) /* Use 7 to check aligned 8 */ ++ ++/* ++ * If you define the memory allocation function, you need to define the function prototype. ++ * You can define this macro as a header file. ++ */ ++#if defined(SECUREC_MALLOC_PROTOTYPE) ++SECUREC_MALLOC_PROTOTYPE ++#endif ++ ++#ifndef SECUREC_MALLOC ++#define SECUREC_MALLOC(x) malloc((size_t)(x)) ++#endif ++ ++#ifndef SECUREC_FREE ++#define SECUREC_FREE(x) free((void *)(x)) ++#endif ++ ++/* Improve performance with struct assignment, buf1 is not defined to avoid tool false positive */ ++#define SECUREC_COPY_VALUE_BY_STRUCT(dest, src, n) do { \ ++ *(SecStrBuf##n *)(void *)(dest) = *(const SecStrBuf##n *)(const void *)(src); \ ++} SECUREC_WHILE_ZERO ++ ++typedef struct { ++ unsigned char buf[2]; /* Performance optimization code structure assignment length 2 bytes */ ++} SecStrBuf2; ++typedef struct { ++ unsigned char buf[3]; /* Performance optimization code structure assignment length 3 bytes */ ++} SecStrBuf3; ++typedef struct { ++ unsigned char buf[4]; /* Performance optimization code structure assignment length 4 bytes */ ++} SecStrBuf4; ++typedef struct { ++ unsigned char buf[5]; /* Performance optimization code structure assignment length 5 bytes */ ++} SecStrBuf5; ++typedef struct { ++ unsigned char buf[6]; /* Performance optimization code structure assignment length 6 bytes */ ++} SecStrBuf6; ++typedef struct { ++ unsigned char buf[7]; /* Performance optimization code structure assignment length 7 bytes */ ++} SecStrBuf7; ++typedef struct { ++ unsigned char buf[8]; /* Performance optimization code structure assignment length 8 bytes */ ++} SecStrBuf8; ++typedef struct { ++ unsigned char buf[9]; /* Performance optimization code structure assignment length 9 bytes */ ++} SecStrBuf9; ++typedef struct { ++ unsigned char buf[10]; /* Performance optimization code structure assignment length 10 bytes */ ++} SecStrBuf10; ++typedef struct { ++ unsigned char buf[11]; /* Performance optimization code structure assignment length 11 bytes */ ++} SecStrBuf11; ++typedef struct { ++ unsigned char buf[12]; /* Performance optimization code structure assignment length 12 bytes */ ++} SecStrBuf12; ++typedef struct { ++ unsigned char buf[13]; /* Performance optimization code structure assignment length 13 bytes */ ++} SecStrBuf13; ++typedef struct { ++ unsigned char buf[14]; /* Performance optimization code structure assignment length 14 bytes */ ++} SecStrBuf14; ++typedef struct { ++ unsigned char buf[15]; /* Performance optimization code structure assignment length 15 bytes */ ++} SecStrBuf15; ++typedef struct { ++ unsigned char buf[16]; /* Performance optimization code structure assignment length 16 bytes */ ++} SecStrBuf16; ++typedef struct { ++ unsigned char buf[17]; /* Performance optimization code structure assignment length 17 bytes */ ++} SecStrBuf17; ++typedef struct { ++ unsigned char buf[18]; /* Performance optimization code structure assignment length 18 bytes */ ++} SecStrBuf18; ++typedef struct { ++ unsigned char buf[19]; /* Performance optimization code structure assignment length 19 bytes */ ++} SecStrBuf19; ++typedef struct { ++ unsigned char buf[20]; /* Performance optimization code structure assignment length 20 bytes */ ++} SecStrBuf20; ++typedef struct { ++ unsigned char buf[21]; /* Performance optimization code structure assignment length 21 bytes */ ++} SecStrBuf21; ++typedef struct { ++ unsigned char buf[22]; /* Performance optimization code structure assignment length 22 bytes */ ++} SecStrBuf22; ++typedef struct { ++ unsigned char buf[23]; /* Performance optimization code structure assignment length 23 bytes */ ++} SecStrBuf23; ++typedef struct { ++ unsigned char buf[24]; /* Performance optimization code structure assignment length 24 bytes */ ++} SecStrBuf24; ++typedef struct { ++ unsigned char buf[25]; /* Performance optimization code structure assignment length 25 bytes */ ++} SecStrBuf25; ++typedef struct { ++ unsigned char buf[26]; /* Performance optimization code structure assignment length 26 bytes */ ++} SecStrBuf26; ++typedef struct { ++ unsigned char buf[27]; /* Performance optimization code structure assignment length 27 bytes */ ++} SecStrBuf27; ++typedef struct { ++ unsigned char buf[28]; /* Performance optimization code structure assignment length 28 bytes */ ++} SecStrBuf28; ++typedef struct { ++ unsigned char buf[29]; /* Performance optimization code structure assignment length 29 bytes */ ++} SecStrBuf29; ++typedef struct { ++ unsigned char buf[30]; /* Performance optimization code structure assignment length 30 bytes */ ++} SecStrBuf30; ++typedef struct { ++ unsigned char buf[31]; /* Performance optimization code structure assignment length 31 bytes */ ++} SecStrBuf31; ++typedef struct { ++ unsigned char buf[32]; /* Performance optimization code structure assignment length 32 bytes */ ++} SecStrBuf32; ++typedef struct { ++ unsigned char buf[33]; /* Performance optimization code structure assignment length 33 bytes */ ++} SecStrBuf33; ++typedef struct { ++ unsigned char buf[34]; /* Performance optimization code structure assignment length 34 bytes */ ++} SecStrBuf34; ++typedef struct { ++ unsigned char buf[35]; /* Performance optimization code structure assignment length 35 bytes */ ++} SecStrBuf35; ++typedef struct { ++ unsigned char buf[36]; /* Performance optimization code structure assignment length 36 bytes */ ++} SecStrBuf36; ++typedef struct { ++ unsigned char buf[37]; /* Performance optimization code structure assignment length 37 bytes */ ++} SecStrBuf37; ++typedef struct { ++ unsigned char buf[38]; /* Performance optimization code structure assignment length 38 bytes */ ++} SecStrBuf38; ++typedef struct { ++ unsigned char buf[39]; /* Performance optimization code structure assignment length 39 bytes */ ++} SecStrBuf39; ++typedef struct { ++ unsigned char buf[40]; /* Performance optimization code structure assignment length 40 bytes */ ++} SecStrBuf40; ++typedef struct { ++ unsigned char buf[41]; /* Performance optimization code structure assignment length 41 bytes */ ++} SecStrBuf41; ++typedef struct { ++ unsigned char buf[42]; /* Performance optimization code structure assignment length 42 bytes */ ++} SecStrBuf42; ++typedef struct { ++ unsigned char buf[43]; /* Performance optimization code structure assignment length 43 bytes */ ++} SecStrBuf43; ++typedef struct { ++ unsigned char buf[44]; /* Performance optimization code structure assignment length 44 bytes */ ++} SecStrBuf44; ++typedef struct { ++ unsigned char buf[45]; /* Performance optimization code structure assignment length 45 bytes */ ++} SecStrBuf45; ++typedef struct { ++ unsigned char buf[46]; /* Performance optimization code structure assignment length 46 bytes */ ++} SecStrBuf46; ++typedef struct { ++ unsigned char buf[47]; /* Performance optimization code structure assignment length 47 bytes */ ++} SecStrBuf47; ++typedef struct { ++ unsigned char buf[48]; /* Performance optimization code structure assignment length 48 bytes */ ++} SecStrBuf48; ++typedef struct { ++ unsigned char buf[49]; /* Performance optimization code structure assignment length 49 bytes */ ++} SecStrBuf49; ++typedef struct { ++ unsigned char buf[50]; /* Performance optimization code structure assignment length 50 bytes */ ++} SecStrBuf50; ++typedef struct { ++ unsigned char buf[51]; /* Performance optimization code structure assignment length 51 bytes */ ++} SecStrBuf51; ++typedef struct { ++ unsigned char buf[52]; /* Performance optimization code structure assignment length 52 bytes */ ++} SecStrBuf52; ++typedef struct { ++ unsigned char buf[53]; /* Performance optimization code structure assignment length 53 bytes */ ++} SecStrBuf53; ++typedef struct { ++ unsigned char buf[54]; /* Performance optimization code structure assignment length 54 bytes */ ++} SecStrBuf54; ++typedef struct { ++ unsigned char buf[55]; /* Performance optimization code structure assignment length 55 bytes */ ++} SecStrBuf55; ++typedef struct { ++ unsigned char buf[56]; /* Performance optimization code structure assignment length 56 bytes */ ++} SecStrBuf56; ++typedef struct { ++ unsigned char buf[57]; /* Performance optimization code structure assignment length 57 bytes */ ++} SecStrBuf57; ++typedef struct { ++ unsigned char buf[58]; /* Performance optimization code structure assignment length 58 bytes */ ++} SecStrBuf58; ++typedef struct { ++ unsigned char buf[59]; /* Performance optimization code structure assignment length 59 bytes */ ++} SecStrBuf59; ++typedef struct { ++ unsigned char buf[60]; /* Performance optimization code structure assignment length 60 bytes */ ++} SecStrBuf60; ++typedef struct { ++ unsigned char buf[61]; /* Performance optimization code structure assignment length 61 bytes */ ++} SecStrBuf61; ++typedef struct { ++ unsigned char buf[62]; /* Performance optimization code structure assignment length 62 bytes */ ++} SecStrBuf62; ++typedef struct { ++ unsigned char buf[63]; /* Performance optimization code structure assignment length 63 bytes */ ++} SecStrBuf63; ++typedef struct { ++ unsigned char buf[64]; /* Performance optimization code structure assignment length 64 bytes */ ++} SecStrBuf64; ++ ++/* ++ * User can change the error handler by modify the following definition, ++ * such as logging the detail error in file. ++ */ ++#if defined(_DEBUG) || defined(DEBUG) ++#if defined(SECUREC_ERROR_HANDLER_BY_ASSERT) ++#define SECUREC_ERROR_INVALID_PARAMTER(msg) assert(msg "invalid argument" == NULL) ++#define SECUREC_ERROR_INVALID_RANGE(msg) assert(msg "invalid dest buffer size" == NULL) ++#define SECUREC_ERROR_BUFFER_OVERLAP(msg) assert(msg "buffer overlap" == NULL) ++#elif defined(SECUREC_ERROR_HANDLER_BY_PRINTF) ++#if SECUREC_IN_KERNEL ++#define SECUREC_ERROR_INVALID_PARAMTER(msg) printk("%s invalid argument\n", msg) ++#define SECUREC_ERROR_INVALID_RANGE(msg) printk("%s invalid dest buffer size\n", msg) ++#define SECUREC_ERROR_BUFFER_OVERLAP(msg) printk("%s buffer overlap\n", msg) ++#else ++#define SECUREC_ERROR_INVALID_PARAMTER(msg) printf("%s invalid argument\n", msg) ++#define SECUREC_ERROR_INVALID_RANGE(msg) printf("%s invalid dest buffer size\n", msg) ++#define SECUREC_ERROR_BUFFER_OVERLAP(msg) printf("%s buffer overlap\n", msg) ++#endif ++#elif defined(SECUREC_ERROR_HANDLER_BY_FILE_LOG) ++#define SECUREC_ERROR_INVALID_PARAMTER(msg) LogSecureCRuntimeError(msg " EINVAL\n") ++#define SECUREC_ERROR_INVALID_RANGE(msg) LogSecureCRuntimeError(msg " ERANGE\n") ++#define SECUREC_ERROR_BUFFER_OVERLAP(msg) LogSecureCRuntimeError(msg " EOVERLAP\n") ++#endif ++#endif ++ ++/* Default handler is none */ ++#ifndef SECUREC_ERROR_INVALID_PARAMTER ++#define SECUREC_ERROR_INVALID_PARAMTER(msg) ++#endif ++#ifndef SECUREC_ERROR_INVALID_RANGE ++#define SECUREC_ERROR_INVALID_RANGE(msg) ++#endif ++#ifndef SECUREC_ERROR_BUFFER_OVERLAP ++#define SECUREC_ERROR_BUFFER_OVERLAP(msg) ++#endif ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* Assembly language memory copy and memory set for X86 or MIPS ... */ ++#ifdef SECUREC_USE_ASM ++void *memcpy_opt(void *dest, const void *src, size_t n); ++void *memset_opt(void *s, int c, size_t n); ++#endif ++ ++#if defined(SECUREC_ERROR_HANDLER_BY_FILE_LOG) ++void LogSecureCRuntimeError(const char *errDetail); ++#endif ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++#endif ++ +diff --git a/lib/securec/src/secureinput_a.c b/lib/securec/src/secureinput_a.c +new file mode 100644 +index 000000000000..e79868f45eff +--- /dev/null ++++ b/lib/securec/src/secureinput_a.c +@@ -0,0 +1,38 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: By defining data type for ANSI string and including "input.inl", ++ * this file generates real underlying function used by scanf family API. ++ * Create: 2014-02-25 ++ */ ++ ++#define SECUREC_FORMAT_OUTPUT_INPUT 1 ++#ifdef SECUREC_FOR_WCHAR ++#undef SECUREC_FOR_WCHAR ++#endif ++ ++#include "secinput.h" ++ ++#include "input.inl" ++ ++SECUREC_INLINE int SecIsDigit(SecInt ch) ++{ ++ /* SecInt to unsigned char clear 571, use bit mask to clear negative return of ch */ ++ return isdigit((int)((unsigned int)(unsigned char)(ch) & 0xffU)); ++} ++SECUREC_INLINE int SecIsXdigit(SecInt ch) ++{ ++ return isxdigit((int)((unsigned int)(unsigned char)(ch) & 0xffU)); ++} ++SECUREC_INLINE int SecIsSpace(SecInt ch) ++{ ++ return isspace((int)((unsigned int)(unsigned char)(ch) & 0xffU)); ++} ++ +diff --git a/lib/securec/src/secureprintoutput.h b/lib/securec/src/secureprintoutput.h +new file mode 100644 +index 000000000000..a00b10dfffab +--- /dev/null ++++ b/lib/securec/src/secureprintoutput.h +@@ -0,0 +1,146 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: Define macro, enum, data struct, and declare internal used function ++ * prototype, which is used by output.inl, secureprintoutput_w.c and ++ * secureprintoutput_a.c. ++ * Create: 2014-02-25 ++ */ ++ ++#ifndef SECUREPRINTOUTPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C ++#define SECUREPRINTOUTPUT_H_E950DA2C_902F_4B15_BECD_948E99090D9C ++#include "securecutil.h" ++ ++/* Shield compilation alerts about using sprintf without format attribute to format float value. */ ++#ifndef SECUREC_HANDLE_WFORMAT ++#define SECUREC_HANDLE_WFORMAT 1 ++#endif ++ ++#if SECUREC_HANDLE_WFORMAT && defined(__GNUC__) && ((__GNUC__ >= 5) || \ ++ (defined(__GNUC_MINOR__) && (__GNUC__ == 4 && __GNUC_MINOR__ > 7))) ++#if defined(__clang__) ++#define SECUREC_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic push") \ ++ _Pragma("GCC diagnostic ignored \"-Wformat-nonliteral\"") ++#else ++#define SECUREC_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic push") \ ++ _Pragma("GCC diagnostic ignored \"-Wformat-nonliteral\"") \ ++ _Pragma("GCC diagnostic ignored \"-Wmissing-format-attribute\"") \ ++ _Pragma("GCC diagnostic ignored \"-Wsuggest-attribute=format\"") ++#endif ++#define SECUREC_END_MASK_WFORMAT_WARNING _Pragma("GCC diagnostic pop") ++#else ++#define SECUREC_MASK_WFORMAT_WARNING ++#define SECUREC_END_MASK_WFORMAT_WARNING ++#endif ++ ++#define SECUREC_MASK_VSPRINTF_WARNING SECUREC_MASK_WFORMAT_WARNING \ ++ SECUREC_MASK_MSVC_CRT_WARNING ++ ++#define SECUREC_END_MASK_VSPRINTF_WARNING SECUREC_END_MASK_WFORMAT_WARNING \ ++ SECUREC_END_MASK_MSVC_CRT_WARNING ++ ++/* ++ * Flag definitions. ++ * Using macros instead of enumerations is because some of the enumerated types under the compiler are 16bit. ++ */ ++#define SECUREC_FLAG_SIGN 0x00001U ++#define SECUREC_FLAG_SIGN_SPACE 0x00002U ++#define SECUREC_FLAG_LEFT 0x00004U ++#define SECUREC_FLAG_LEADZERO 0x00008U ++#define SECUREC_FLAG_LONG 0x00010U ++#define SECUREC_FLAG_SHORT 0x00020U ++#define SECUREC_FLAG_SIGNED 0x00040U ++#define SECUREC_FLAG_ALTERNATE 0x00080U ++#define SECUREC_FLAG_NEGATIVE 0x00100U ++#define SECUREC_FLAG_FORCE_OCTAL 0x00200U ++#define SECUREC_FLAG_LONG_DOUBLE 0x00400U ++#define SECUREC_FLAG_WIDECHAR 0x00800U ++#define SECUREC_FLAG_LONGLONG 0x01000U ++#define SECUREC_FLAG_CHAR 0x02000U ++#define SECUREC_FLAG_POINTER 0x04000U ++#define SECUREC_FLAG_I64 0x08000U ++#define SECUREC_FLAG_PTRDIFF 0x10000U ++#define SECUREC_FLAG_SIZE 0x20000U ++#ifdef SECUREC_COMPATIBLE_LINUX_FORMAT ++#define SECUREC_FLAG_INTMAX 0x40000U ++#endif ++ ++/* State definitions. Identify the status of the current format */ ++typedef enum { ++ STAT_NORMAL, ++ STAT_PERCENT, ++ STAT_FLAG, ++ STAT_WIDTH, ++ STAT_DOT, ++ STAT_PRECIS, ++ STAT_SIZE, ++ STAT_TYPE, ++ STAT_INVALID ++} SecFmtState; ++ ++#ifndef SECUREC_BUFFER_SIZE ++#if SECUREC_IN_KERNEL ++#define SECUREC_BUFFER_SIZE 32 ++#elif defined(SECUREC_STACK_SIZE_LESS_THAN_1K) ++/* ++ * SECUREC BUFFER SIZE Can not be less than 23 ++ * The length of the octal representation of 64-bit integers with zero lead ++ */ ++#define SECUREC_BUFFER_SIZE 256 ++#else ++#define SECUREC_BUFFER_SIZE 512 ++#endif ++#endif ++#if SECUREC_BUFFER_SIZE < 23 ++#error SECUREC_BUFFER_SIZE Can not be less than 23 ++#endif ++/* Buffer size for wchar, use 4 to make the compiler aligns as 8 bytes as possible */ ++#define SECUREC_WCHAR_BUFFER_SIZE 4 ++ ++#define SECUREC_MAX_PRECISION SECUREC_BUFFER_SIZE ++/* Max. # bytes in multibyte char,see MB_LEN_MAX */ ++#define SECUREC_MB_LEN 16 ++/* The return value of the internal function, which is returned when truncated */ ++#define SECUREC_PRINTF_TRUNCATE (-2) ++ ++#define SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, maxLimit) \ ++ ((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) ++ ++#define SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, maxLimit) do { \ ++ if ((strDest) != NULL && (destMax) > 0 && (destMax) <= (maxLimit)) { \ ++ *(strDest) = '\0'; \ ++ } \ ++} SECUREC_WHILE_ZERO ++ ++#ifdef SECUREC_COMPATIBLE_WIN_FORMAT ++#define SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, maxLimit) \ ++ (((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) || \ ++ ((count) > (SECUREC_STRING_MAX_LEN - 1) && (count) != (size_t)(-1))) ++ ++#else ++#define SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, maxLimit) \ ++ (((format) == NULL || (strDest) == NULL || (destMax) == 0 || (destMax) > (maxLimit)) || \ ++ ((count) > (SECUREC_STRING_MAX_LEN - 1))) ++#endif ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++#ifdef SECUREC_FOR_WCHAR ++int SecVswprintfImpl(wchar_t *string, size_t count, const wchar_t *format, va_list argList); ++#else ++int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList); ++#endif ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ +diff --git a/lib/securec/src/secureprintoutput_a.c b/lib/securec/src/secureprintoutput_a.c +new file mode 100644 +index 000000000000..b2b4b6a65cfa +--- /dev/null ++++ b/lib/securec/src/secureprintoutput_a.c +@@ -0,0 +1,112 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: By defining corresponding macro for ANSI string and including "output.inl", ++ * this file generates real underlying function used by printf family API. ++ * Create: 2014-02-25 ++ */ ++ ++#define SECUREC_FORMAT_OUTPUT_INPUT 1 ++ ++#ifdef SECUREC_FOR_WCHAR ++#undef SECUREC_FOR_WCHAR ++#endif ++ ++#include "secureprintoutput.h" ++#if SECUREC_WARP_OUTPUT ++#define SECUREC_FORMAT_FLAG_TABLE_SIZE 128 ++SECUREC_INLINE const char *SecSkipKnownFlags(const char *format) ++{ ++ static const unsigned char flagTable[SECUREC_FORMAT_FLAG_TABLE_SIZE] = { ++ /* ++ * Known flag is "0123456789 +-#hlLwZzjqt*I$" ++ */ ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x01, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x01, 0x00, 0x00, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00, 0x00, 0x00, ++ 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00 ++ }; ++ const char *fmt = format; ++ while (*fmt != '\0') { ++ char fmtChar = *fmt; ++ if ((unsigned char)fmtChar > 0x7f) { /* 0x7f is upper limit of format char value */ ++ break; ++ } ++ if (flagTable[(unsigned char)fmtChar] == 0) { ++ break; ++ } ++ ++fmt; ++ } ++ return fmt; ++} ++ ++SECUREC_INLINE int SecFormatContainN(const char *format) ++{ ++ const char *fmt = format; ++ while (*fmt != '\0') { ++ ++fmt; ++ /* Skip normal char */ ++ if (*(fmt - 1) != '%') { ++ continue; ++ } ++ /* Meet %% */ ++ if (*fmt == '%') { ++ ++fmt; /* Point to the character after the %. Correct handling %%xx */ ++ continue; ++ } ++ /* Now parse %..., fmt point to the character after the % */ ++ fmt = SecSkipKnownFlags(fmt); ++ if (*fmt == 'n') { ++ return 1; ++ } ++ } ++ return 0; ++} ++/* ++ * Multi character formatted output implementation, the count include \0 character, must be greater than zero ++ */ ++int SecVsnprintfImpl(char *string, size_t count, const char *format, va_list argList) ++{ ++ int retVal; ++ if (SecFormatContainN(format) != 0) { ++ string[0] = '\0'; ++ return -1; ++ } ++ SECUREC_MASK_VSPRINTF_WARNING ++ retVal = vsnprintf(string, count, format, argList); ++ SECUREC_END_MASK_VSPRINTF_WARNING ++ if (retVal >= (int)count) { /* The size_t to int is ok, count max is SECUREC_STRING_MAX_LEN */ ++ /* The buffer was too small; we return truncation */ ++ string[count - 1] = '\0'; ++ return SECUREC_PRINTF_TRUNCATE; ++ } ++ if (retVal < 0) { ++ string[0] = '\0'; /* Empty the dest strDest */ ++ return -1; ++ } ++ return retVal; ++} ++#else ++#if SECUREC_IN_KERNEL ++#include ++#endif ++ ++#ifndef EOF ++#define EOF (-1) ++#endif ++ ++#include "output.inl" ++ ++#endif ++ +diff --git a/lib/securec/src/snprintf_s.c b/lib/securec/src/snprintf_s.c +new file mode 100644 +index 000000000000..ec18328e3b27 +--- /dev/null ++++ b/lib/securec/src/snprintf_s.c +@@ -0,0 +1,110 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: snprintf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "linux/securec.h" ++ ++#if SECUREC_ENABLE_SNPRINTF ++/* ++ * ++ * The snprintf_s function is equivalent to the snprintf function ++ * except for the parameter destMax/count and the explicit runtime-constraints violation ++ * The snprintf_s function formats and stores count or fewer characters in ++ * strDest and appends a terminating null. Each argument (if any) is converted ++ * and output according to the corresponding format specification in format. ++ * The formatting is consistent with the printf family of functions; If copying ++ * occurs between strings that overlap, the behavior is undefined. ++ * ++ * ++ * strDest Storage location for the output. ++ * destMax The size of the storage location for output. Size ++ * in bytes for snprintf_s or size in words for snwprintf_s. ++ * count Maximum number of character to store. ++ * format Format-control string. ++ * ... Optional arguments. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * return the number of characters written, not including the terminating null ++ * return -1 if an error occurs. ++ * return -1 if count < destMax and the output string has been truncated ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ * ++ */ ++int snprintf_s(char *strDest, size_t destMax, size_t count, const char *format, ...) ++{ ++ int ret; /* If initialization causes e838 */ ++ va_list argList; ++ ++ va_start(argList, format); ++ ret = vsnprintf_s(strDest, destMax, count, format, argList); ++ va_end(argList); ++ (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ ++ return ret; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(snprintf_s); ++#endif ++#endif ++ ++#if SECUREC_SNPRINTF_TRUNCATED ++/* ++ * ++ * The snprintf_truncated_s function is equivalent to the snprintf function ++ * except for the parameter destMax/count and the explicit runtime-constraints violation ++ * The snprintf_truncated_s function formats and stores count or fewer characters in ++ * strDest and appends a terminating null. Each argument (if any) is converted ++ * and output according to the corresponding format specification in format. ++ * The formatting is consistent with the printf family of functions; If copying ++ * occurs between strings that overlap, the behavior is undefined. ++ * ++ * ++ * strDest Storage location for the output. ++ * destMax The size of the storage location for output. Size ++ * in bytes for snprintf_truncated_s or size in words for snwprintf_s. ++ * format Format-control string. ++ * ... Optional arguments. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * return the number of characters written, not including the terminating null ++ * return -1 if an error occurs. ++ * return destMax-1 if output string has been truncated ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ * ++ */ ++int snprintf_truncated_s(char *strDest, size_t destMax, const char *format, ...) ++{ ++ int ret; /* If initialization causes e838 */ ++ va_list argList; ++ ++ va_start(argList, format); ++ ret = vsnprintf_truncated_s(strDest, destMax, format, argList); ++ va_end(argList); ++ (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ ++ return ret; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(snprintf_truncated_s); ++#endif ++ ++#endif ++ +diff --git a/lib/securec/src/sprintf_s.c b/lib/securec/src/sprintf_s.c +new file mode 100644 +index 000000000000..1f25f83990ad +--- /dev/null ++++ b/lib/securec/src/sprintf_s.c +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: sprintf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "linux/securec.h" ++ ++/* ++ * ++ * The sprintf_s function is equivalent to the sprintf function ++ * except for the parameter destMax and the explicit runtime-constraints violation ++ * The sprintf_s function formats and stores a series of characters and values ++ * in strDest. Each argument (if any) is converted and output according to ++ * the corresponding format specification in format. The format consists of ++ * ordinary characters and has the same form and function as the format argument ++ * for printf. A null character is appended after the last character written. ++ * If copying occurs between strings that overlap, the behavior is undefined. ++ * ++ * ++ * strDest Storage location for output. ++ * destMax Maximum number of characters to store. ++ * format Format-control string. ++ * ... Optional arguments ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * return the number of bytes stored in strDest, not counting the terminating null character. ++ * return -1 if an error occurred. ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++int sprintf_s(char *strDest, size_t destMax, const char *format, ...) ++{ ++ int ret; /* If initialization causes e838 */ ++ va_list argList; ++ ++ va_start(argList, format); ++ ret = vsprintf_s(strDest, destMax, format, argList); ++ va_end(argList); ++ (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ ++ return ret; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(sprintf_s); ++#endif ++ +diff --git a/lib/securec/src/sscanf_s.c b/lib/securec/src/sscanf_s.c +new file mode 100644 +index 000000000000..a8141ed25a6e +--- /dev/null ++++ b/lib/securec/src/sscanf_s.c +@@ -0,0 +1,58 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: sscanf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "linux/securec.h" ++ ++/* ++ * ++ * The sscanf_s function is equivalent to fscanf_s, ++ * except that input is obtained from a string (specified by the argument buffer) rather than from a stream ++ * The sscanf function reads data from buffer into the location given by each ++ * argument. Every argument must be a pointer to a variable with a type that ++ * corresponds to a type specifier in format. The format argument controls the ++ * interpretation of the input fields and has the same form and function as ++ * the format argument for the scanf function. ++ * If copying takes place between strings that overlap, the behavior is undefined. ++ * ++ * ++ * buffer Stored data. ++ * format Format control string, see Format Specifications. ++ * ... Optional arguments. ++ * ++ * ++ * ... The converted value stored in user assigned address ++ * ++ * ++ * Each of these functions returns the number of fields successfully converted ++ * and assigned; the return value does not include fields that were read but ++ * not assigned. ++ * A return value of 0 indicates that no fields were assigned. ++ * return -1 if an error occurs. ++ */ ++int sscanf_s(const char *buffer, const char *format, ...) ++{ ++ int ret; /* If initialization causes e838 */ ++ va_list argList; ++ ++ va_start(argList, format); ++ ret = vsscanf_s(buffer, format, argList); ++ va_end(argList); ++ (void)argList; /* To clear e438 last value assigned not used , the compiler will optimize this code */ ++ ++ return ret; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(sscanf_s); ++#endif ++ +diff --git a/lib/securec/src/strcat_s.c b/lib/securec/src/strcat_s.c +new file mode 100644 +index 000000000000..f835e7bc90a6 +--- /dev/null ++++ b/lib/securec/src/strcat_s.c +@@ -0,0 +1,101 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: strcat_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "securecutil.h" ++ ++/* ++ * Befor this function, the basic parameter checking has been done ++ */ ++SECUREC_INLINE errno_t SecDoCat(char *strDest, size_t destMax, const char *strSrc) ++{ ++ size_t destLen; ++ size_t srcLen; ++ size_t maxSrcLen; ++ SECUREC_CALC_STR_LEN(strDest, destMax, &destLen); ++ /* Only optimize strSrc, do not apply this function to strDest */ ++ maxSrcLen = destMax - destLen; ++ SECUREC_CALC_STR_LEN_OPT(strSrc, maxSrcLen, &srcLen); ++ ++ if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { ++ strDest[0] = '\0'; ++ if (strDest + destLen <= strSrc && destLen == destMax) { ++ SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); ++ return EINVAL_AND_RESET; ++ } ++ SECUREC_ERROR_BUFFER_OVERLAP("strcat_s"); ++ return EOVERLAP_AND_RESET; ++ } ++ if (srcLen + destLen >= destMax || strDest == strSrc) { ++ strDest[0] = '\0'; ++ if (destLen == destMax) { ++ SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); ++ return EINVAL_AND_RESET; ++ } ++ SECUREC_ERROR_INVALID_RANGE("strcat_s"); ++ return ERANGE_AND_RESET; ++ } ++ SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen + 1); /* Single character length include \0 */ ++ return EOK; ++} ++ ++/* ++ * ++ * The strcat_s function appends a copy of the string pointed to by strSrc (including the terminating null character) ++ * to the end of the string pointed to by strDest. ++ * The initial character of strSrc overwrites the terminating null character of strDest. ++ * strcat_s will return EOVERLAP_AND_RESET if the source and destination strings overlap. ++ * ++ * Note that the second parameter is the total size of the buffer, not the ++ * remaining size. ++ * ++ * ++ * strDest Null-terminated destination string buffer. ++ * destMax Size of the destination string buffer. ++ * strSrc Null-terminated source string buffer. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * EOK Success ++ * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN ++ * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid) or ++ * (strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN) ++ * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN ++ * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap ++ * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++errno_t strcat_s(char *strDest, size_t destMax, const char *strSrc) ++{ ++ if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("strcat_s"); ++ return ERANGE; ++ } ++ if (strDest == NULL || strSrc == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("strcat_s"); ++ if (strDest != NULL) { ++ strDest[0] = '\0'; ++ return EINVAL_AND_RESET; ++ } ++ return EINVAL; ++ } ++ return SecDoCat(strDest, destMax, strSrc); ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(strcat_s); ++#endif ++ +diff --git a/lib/securec/src/strcpy_s.c b/lib/securec/src/strcpy_s.c +new file mode 100644 +index 000000000000..ca1b2ddb1f44 +--- /dev/null ++++ b/lib/securec/src/strcpy_s.c +@@ -0,0 +1,353 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: strcpy_s function ++ * Create: 2014-02-25 ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Performance-sensitive ++ * [reason] Always used in the performance critical path, ++ * and sufficient input validation is performed before calling ++ */ ++ ++#include "securecutil.h" ++ ++#ifndef SECUREC_STRCPY_WITH_PERFORMANCE ++#define SECUREC_STRCPY_WITH_PERFORMANCE 1 ++#endif ++ ++#define SECUREC_STRCPY_PARAM_OK(strDest, destMax, strSrc) ((destMax) > 0 && \ ++ (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && (strDest) != (strSrc)) ++ ++#if (!SECUREC_IN_KERNEL) && SECUREC_STRCPY_WITH_PERFORMANCE ++#ifndef SECUREC_STRCOPY_THRESHOLD_SIZE ++#define SECUREC_STRCOPY_THRESHOLD_SIZE 32UL ++#endif ++/* The purpose of converting to void is to clean up the alarm */ ++#define SECUREC_SMALL_STR_COPY(strDest, strSrc, lenWithTerm) do { \ ++ if (SECUREC_ADDR_ALIGNED_8(strDest) && SECUREC_ADDR_ALIGNED_8(strSrc)) { \ ++ /* Use struct assignment */ \ ++ switch (lenWithTerm) { \ ++ case 1: \ ++ *(strDest) = *(strSrc); \ ++ break; \ ++ case 2: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 2); \ ++ break; \ ++ case 3: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 3); \ ++ break; \ ++ case 4: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 4); \ ++ break; \ ++ case 5: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 5); \ ++ break; \ ++ case 6: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 6); \ ++ break; \ ++ case 7: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 7); \ ++ break; \ ++ case 8: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 8); \ ++ break; \ ++ case 9: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 9); \ ++ break; \ ++ case 10: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 10); \ ++ break; \ ++ case 11: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 11); \ ++ break; \ ++ case 12: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 12); \ ++ break; \ ++ case 13: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 13); \ ++ break; \ ++ case 14: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 14); \ ++ break; \ ++ case 15: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 15); \ ++ break; \ ++ case 16: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 16); \ ++ break; \ ++ case 17: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 17); \ ++ break; \ ++ case 18: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 18); \ ++ break; \ ++ case 19: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 19); \ ++ break; \ ++ case 20: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 20); \ ++ break; \ ++ case 21: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 21); \ ++ break; \ ++ case 22: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 22); \ ++ break; \ ++ case 23: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 23); \ ++ break; \ ++ case 24: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 24); \ ++ break; \ ++ case 25: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 25); \ ++ break; \ ++ case 26: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 26); \ ++ break; \ ++ case 27: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 27); \ ++ break; \ ++ case 28: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 28); \ ++ break; \ ++ case 29: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 29); \ ++ break; \ ++ case 30: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 30); \ ++ break; \ ++ case 31: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 31); \ ++ break; \ ++ case 32: \ ++ SECUREC_COPY_VALUE_BY_STRUCT((strDest), (strSrc), 32); \ ++ break; \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } /* END switch */ \ ++ } else { \ ++ char *tmpStrDest_ = (char *)(strDest); \ ++ const char *tmpStrSrc_ = (const char *)(strSrc); \ ++ switch (lenWithTerm) { \ ++ case 32: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 31: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 30: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 29: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 28: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 27: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 26: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 25: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 24: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 23: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 22: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 21: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 20: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 19: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 18: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 17: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 16: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 15: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 14: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 13: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 12: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 11: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 10: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 9: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 8: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 7: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 6: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 5: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 4: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 3: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 2: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ case 1: \ ++ *(tmpStrDest_++) = *(tmpStrSrc_++); \ ++ /* fall-through */ /* FALLTHRU */ \ ++ default: \ ++ /* Do nothing */ \ ++ break; \ ++ } \ ++ } \ ++} SECUREC_WHILE_ZERO ++#endif ++ ++#if SECUREC_IN_KERNEL || (!SECUREC_STRCPY_WITH_PERFORMANCE) ++#define SECUREC_STRCPY_OPT(dest, src, lenWithTerm) SECUREC_MEMCPY_WARP_OPT((dest), (src), (lenWithTerm)) ++#else ++/* ++ * Performance optimization. lenWithTerm include '\0' ++ */ ++#define SECUREC_STRCPY_OPT(dest, src, lenWithTerm) do { \ ++ if ((lenWithTerm) > SECUREC_STRCOPY_THRESHOLD_SIZE) { \ ++ SECUREC_MEMCPY_WARP_OPT((dest), (src), (lenWithTerm)); \ ++ } else { \ ++ SECUREC_SMALL_STR_COPY((dest), (src), (lenWithTerm)); \ ++ } \ ++} SECUREC_WHILE_ZERO ++#endif ++ ++/* ++ * Check Src Range ++ */ ++SECUREC_INLINE errno_t CheckSrcRange(char *strDest, size_t destMax, const char *strSrc) ++{ ++ size_t tmpDestMax = destMax; ++ const char *tmpSrc = strSrc; ++ /* Use destMax as boundary checker and destMax must be greater than zero */ ++ while (*tmpSrc != '\0' && tmpDestMax > 0) { ++ ++tmpSrc; ++ --tmpDestMax; ++ } ++ if (tmpDestMax == 0) { ++ strDest[0] = '\0'; ++ SECUREC_ERROR_INVALID_RANGE("strcpy_s"); ++ return ERANGE_AND_RESET; ++ } ++ return EOK; ++} ++ ++/* ++ * Handling errors ++ */ ++errno_t strcpy_error(char *strDest, size_t destMax, const char *strSrc) ++{ ++ if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("strcpy_s"); ++ return ERANGE; ++ } ++ if (strDest == NULL || strSrc == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("strcpy_s"); ++ if (strDest != NULL) { ++ strDest[0] = '\0'; ++ return EINVAL_AND_RESET; ++ } ++ return EINVAL; ++ } ++ return CheckSrcRange(strDest, destMax, strSrc); ++} ++ ++/* ++ * ++ * The strcpy_s function copies the string pointed to strSrc ++ * (including the terminating null character) into the array pointed to by strDest ++ * The destination string must be large enough to hold the source string, ++ * including the terminating null character. strcpy_s will return EOVERLAP_AND_RESET ++ * if the source and destination strings overlap. ++ * ++ * ++ * strDest Location of destination string buffer ++ * destMax Size of the destination string buffer. ++ * strSrc Null-terminated source string buffer. ++ * ++ * ++ * strDest is updated. ++ * ++ * ++ * EOK Success ++ * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN ++ * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN ++ * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN ++ * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap ++ * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++errno_t strcpy_s(char *strDest, size_t destMax, const char *strSrc) ++{ ++ if (SECUREC_STRCPY_PARAM_OK(strDest, destMax, strSrc)) { ++ size_t srcStrLen; ++ SECUREC_CALC_STR_LEN(strSrc, destMax, &srcStrLen); ++ ++srcStrLen; /* The length include '\0' */ ++ ++ if (srcStrLen <= destMax) { ++ /* Use mem overlap check include '\0' */ ++ if (SECUREC_MEMORY_NO_OVERLAP(strDest, strSrc, srcStrLen)) { ++ /* Performance optimization srcStrLen include '\0' */ ++ SECUREC_STRCPY_OPT(strDest, strSrc, srcStrLen); ++ return EOK; ++ } else { ++ strDest[0] = '\0'; ++ SECUREC_ERROR_BUFFER_OVERLAP("strcpy_s"); ++ return EOVERLAP_AND_RESET; ++ } ++ } ++ } ++ return strcpy_error(strDest, destMax, strSrc); ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(strcpy_s); ++#endif ++ +diff --git a/lib/securec/src/strncat_s.c b/lib/securec/src/strncat_s.c +new file mode 100644 +index 000000000000..6686d2994a64 +--- /dev/null ++++ b/lib/securec/src/strncat_s.c +@@ -0,0 +1,119 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: strncat_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "securecutil.h" ++ ++/* ++ * Befor this function, the basic parameter checking has been done ++ */ ++SECUREC_INLINE errno_t SecDoCatLimit(char *strDest, size_t destMax, const char *strSrc, size_t count) ++{ ++ size_t destLen; ++ size_t srcLen; ++ SECUREC_CALC_STR_LEN(strDest, destMax, &destLen); ++ /* ++ * The strSrc is no longer optimized. The reason is that when count is small, ++ * the efficiency of strnlen is higher than that of self realization. ++ */ ++ SECUREC_CALC_STR_LEN(strSrc, count, &srcLen); ++ ++ if (SECUREC_CAT_STRING_IS_OVERLAP(strDest, destLen, strSrc, srcLen)) { ++ strDest[0] = '\0'; ++ if (strDest + destLen <= strSrc && destLen == destMax) { ++ SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); ++ return EINVAL_AND_RESET; ++ } ++ SECUREC_ERROR_BUFFER_OVERLAP("strncat_s"); ++ return EOVERLAP_AND_RESET; ++ } ++ if (srcLen + destLen >= destMax || strDest == strSrc) { ++ strDest[0] = '\0'; ++ if (destLen == destMax) { ++ SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); ++ return EINVAL_AND_RESET; ++ } ++ SECUREC_ERROR_INVALID_RANGE("strncat_s"); ++ return ERANGE_AND_RESET; ++ } ++ SECUREC_MEMCPY_WARP_OPT(strDest + destLen, strSrc, srcLen); /* No terminator */ ++ *(strDest + destLen + srcLen) = '\0'; ++ return EOK; ++} ++ ++/* ++ * ++ * The strncat_s function appends not more than n successive characters ++ * (not including the terminating null character) ++ * from the array pointed to by strSrc to the end of the string pointed to by strDest ++ * The strncat_s function try to append the first D characters of strSrc to ++ * the end of strDest, where D is the lesser of count and the length of strSrc. ++ * If appending those D characters will fit within strDest (whose size is given ++ * as destMax) and still leave room for a null terminator, then those characters ++ * are appended, starting at the original terminating null of strDest, and a ++ * new terminating null is appended; otherwise, strDest[0] is set to the null ++ * character. ++ * ++ * ++ * strDest Null-terminated destination string. ++ * destMax Size of the destination buffer. ++ * strSrc Null-terminated source string. ++ * count Number of character to append, or truncate. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * EOK Success ++ * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN ++ * EINVAL_AND_RESET (strDest unterminated and all other parameters are valid)or ++ * (strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN) ++ * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN ++ * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap ++ * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++errno_t strncat_s(char *strDest, size_t destMax, const char *strSrc, size_t count) ++{ ++ if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("strncat_s"); ++ return ERANGE; ++ } ++ ++ if (strDest == NULL || strSrc == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("strncat_s"); ++ if (strDest != NULL) { ++ strDest[0] = '\0'; ++ return EINVAL_AND_RESET; ++ } ++ return EINVAL; ++ } ++ if (count > SECUREC_STRING_MAX_LEN) { ++#ifdef SECUREC_COMPATIBLE_WIN_FORMAT ++ if (count == (size_t)(-1)) { ++ /* Windows internal functions may pass in -1 when calling this function */ ++ return SecDoCatLimit(strDest, destMax, strSrc, destMax); ++ } ++#endif ++ strDest[0] = '\0'; ++ SECUREC_ERROR_INVALID_RANGE("strncat_s"); ++ return ERANGE_AND_RESET; ++ } ++ return SecDoCatLimit(strDest, destMax, strSrc, count); ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(strncat_s); ++#endif ++ +diff --git a/lib/securec/src/strncpy_s.c b/lib/securec/src/strncpy_s.c +new file mode 100644 +index 000000000000..5f4c5b709ff9 +--- /dev/null ++++ b/lib/securec/src/strncpy_s.c +@@ -0,0 +1,145 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: strncpy_s function ++ * Create: 2014-02-25 ++ */ ++/* ++ * [Standardize-exceptions] Use unsafe function: Performance-sensitive ++ * [reason] Always used in the performance critical path, ++ * and sufficient input validation is performed before calling ++ */ ++ ++#include "securecutil.h" ++ ++#if defined(SECUREC_COMPATIBLE_WIN_FORMAT) ++#define SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count) \ ++ (((destMax) > 0 && (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && \ ++ ((count) <= SECUREC_STRING_MAX_LEN || (count) == ((size_t)(-1))) && (count) > 0)) ++#else ++#define SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count) \ ++ (((destMax) > 0 && (destMax) <= SECUREC_STRING_MAX_LEN && (strDest) != NULL && (strSrc) != NULL && \ ++ (count) <= SECUREC_STRING_MAX_LEN && (count) > 0)) ++#endif ++ ++/* ++ * Check Src Count Range ++ */ ++SECUREC_INLINE errno_t CheckSrcCountRange(char *strDest, size_t destMax, const char *strSrc, size_t count) ++{ ++ size_t tmpDestMax = destMax; ++ size_t tmpCount = count; ++ const char *endPos = strSrc; ++ ++ /* Use destMax and count as boundary checker and destMax must be greater than zero */ ++ while (*(endPos) != '\0' && tmpDestMax > 0 && tmpCount > 0) { ++ ++endPos; ++ --tmpCount; ++ --tmpDestMax; ++ } ++ if (tmpDestMax == 0) { ++ strDest[0] = '\0'; ++ SECUREC_ERROR_INVALID_RANGE("strncpy_s"); ++ return ERANGE_AND_RESET; ++ } ++ return EOK; ++} ++ ++/* ++ * Handling errors, when dest equal src return EOK ++ */ ++errno_t strncpy_error(char *strDest, size_t destMax, const char *strSrc, size_t count) ++{ ++ if (destMax == 0 || destMax > SECUREC_STRING_MAX_LEN) { ++ SECUREC_ERROR_INVALID_RANGE("strncpy_s"); ++ return ERANGE; ++ } ++ if (strDest == NULL || strSrc == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("strncpy_s"); ++ if (strDest != NULL) { ++ strDest[0] = '\0'; ++ return EINVAL_AND_RESET; ++ } ++ return EINVAL; ++ } ++ if (count > SECUREC_STRING_MAX_LEN) { ++ strDest[0] = '\0'; /* Clear dest string */ ++ SECUREC_ERROR_INVALID_RANGE("strncpy_s"); ++ return ERANGE_AND_RESET; ++ } ++ if (count == 0) { ++ strDest[0] = '\0'; ++ return EOK; ++ } ++ return CheckSrcCountRange(strDest, destMax, strSrc, count); ++} ++ ++/* ++ * ++ * The strncpy_s function copies not more than n successive characters (not including the terminating null character) ++ * from the array pointed to by strSrc to the array pointed to by strDest. ++ * ++ * ++ * strDest Destination string. ++ * destMax The size of the destination string, in characters. ++ * strSrc Source string. ++ * count Number of characters to be copied. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * EOK Success ++ * EINVAL strDest is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN ++ * EINVAL_AND_RESET strDest != NULL and strSrc is NULL and destMax != 0 and destMax <= SECUREC_STRING_MAX_LEN ++ * ERANGE destMax is 0 and destMax > SECUREC_STRING_MAX_LEN ++ * ERANGE_AND_RESET strDest have not enough space and all other parameters are valid and not overlap ++ * EOVERLAP_AND_RESET dest buffer and source buffer are overlapped and all parameters are valid ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++errno_t strncpy_s(char *strDest, size_t destMax, const char *strSrc, size_t count) ++{ ++ if (SECUREC_STRNCPY_PARAM_OK(strDest, destMax, strSrc, count)) { ++ size_t minCpLen; /* Use it to store the maxi length limit */ ++ if (count < destMax) { ++ SECUREC_CALC_STR_LEN(strSrc, count, &minCpLen); /* No ending terminator */ ++ } else { ++ size_t tmpCount = destMax; ++#ifdef SECUREC_COMPATIBLE_WIN_FORMAT ++ if (count == ((size_t)(-1))) { ++ tmpCount = destMax - 1; ++ } ++#endif ++ SECUREC_CALC_STR_LEN(strSrc, tmpCount, &minCpLen); /* No ending terminator */ ++ if (minCpLen == destMax) { ++ strDest[0] = '\0'; ++ SECUREC_ERROR_INVALID_RANGE("strncpy_s"); ++ return ERANGE_AND_RESET; ++ } ++ } ++ if (SECUREC_STRING_NO_OVERLAP(strDest, strSrc, minCpLen) || strDest == strSrc) { ++ /* Not overlap */ ++ SECUREC_MEMCPY_WARP_OPT(strDest, strSrc, minCpLen); /* Copy string without terminator */ ++ strDest[minCpLen] = '\0'; ++ return EOK; ++ } else { ++ strDest[0] = '\0'; ++ SECUREC_ERROR_BUFFER_OVERLAP("strncpy_s"); ++ return EOVERLAP_AND_RESET; ++ } ++ } ++ return strncpy_error(strDest, destMax, strSrc, count); ++} ++ ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(strncpy_s); ++#endif ++ +diff --git a/lib/securec/src/strtok_s.c b/lib/securec/src/strtok_s.c +new file mode 100644 +index 000000000000..cd5dcd2cdfa0 +--- /dev/null ++++ b/lib/securec/src/strtok_s.c +@@ -0,0 +1,116 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: strtok_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "securecutil.h" ++ ++SECUREC_INLINE int SecIsInDelimit(char ch, const char *strDelimit) ++{ ++ const char *ctl = strDelimit; ++ while (*ctl != '\0' && *ctl != ch) { ++ ++ctl; ++ } ++ return (int)(*ctl != '\0'); ++} ++ ++/* ++ * Find beginning of token (skip over leading delimiters). ++ * Note that there is no token if this loop sets string to point to the terminal null. ++ */ ++SECUREC_INLINE char *SecFindBegin(char *strToken, const char *strDelimit) ++{ ++ char *token = strToken; ++ while (*token != '\0') { ++ if (SecIsInDelimit(*token, strDelimit) != 0) { ++ ++token; ++ continue; ++ } ++ /* Don't find any delimiter in string header, break the loop */ ++ break; ++ } ++ return token; ++} ++ ++/* ++ * Find rest of token ++ */ ++SECUREC_INLINE char *SecFindRest(char *strToken, const char *strDelimit) ++{ ++ /* Find the rest of the token. If it is not the end of the string, put a null there */ ++ char *token = strToken; ++ while (*token != '\0') { ++ if (SecIsInDelimit(*token, strDelimit) != 0) { ++ /* Find a delimiter, set string terminator */ ++ *token = '\0'; ++ ++token; ++ break; ++ } ++ ++token; ++ } ++ return token; ++} ++ ++/* ++ * Find the final position pointer ++ */ ++SECUREC_INLINE char *SecUpdateToken(char *strToken, const char *strDelimit, char **context) ++{ ++ /* Point to updated position. Record string position for next search in the context */ ++ *context = SecFindRest(strToken, strDelimit); ++ /* Determine if a token has been found. */ ++ if (*context == strToken) { ++ return NULL; ++ } ++ return strToken; ++} ++ ++/* ++ * ++ * The strtok_s function parses a string into a sequence of strToken, ++ * replace all characters in strToken string that match to strDelimit set with 0. ++ * On the first call to strtok_s the string to be parsed should be specified in strToken. ++ * In each subsequent call that should parse the same string, strToken should be NULL ++ * ++ * strToken String containing token or tokens. ++ * strDelimit Set of delimiter characters. ++ * context Used to store position information between calls ++ * to strtok_s ++ * ++ * context is updated ++ * ++ * On the first call returns the address of the first non \0 character, otherwise NULL is returned. ++ * In subsequent calls, the strtoken is set to NULL, and the context set is the same as the previous call, ++ * return NULL if the *context string length is equal 0, otherwise return *context. ++ */ ++char *strtok_s(char *strToken, const char *strDelimit, char **context) ++{ ++ char *orgToken = strToken; ++ /* Validate delimiter and string context */ ++ if (context == NULL || strDelimit == NULL) { ++ return NULL; ++ } ++ /* Valid input string and string pointer from where to search */ ++ if (orgToken == NULL && *context == NULL) { ++ return NULL; ++ } ++ /* If string is null, continue searching from previous string position stored in context */ ++ if (orgToken == NULL) { ++ orgToken = *context; ++ } ++ orgToken = SecFindBegin(orgToken, strDelimit); ++ return SecUpdateToken(orgToken, strDelimit, context); ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(strtok_s); ++#endif ++ +diff --git a/lib/securec/src/vscanf_s.c b/lib/securec/src/vscanf_s.c +new file mode 100644 +index 000000000000..61480a69722f +--- /dev/null ++++ b/lib/securec/src/vscanf_s.c +@@ -0,0 +1,63 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: vscanf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "secinput.h" ++ ++/* ++ * ++ * The vscanf_s function is equivalent to scanf_s, with the variable argument list replaced by argList, ++ * The vscanf_s function reads data from the standard input stream stdin and ++ * writes the data into the location that's given by argument. Each argument ++ * must be a pointer to a variable of a type that corresponds to a type specifier ++ * in format. If copying occurs between strings that overlap, the behavior is ++ * undefined. ++ * ++ * ++ * format Format control string. ++ * argList pointer to list of arguments ++ * ++ * ++ * argList the converted value stored in user assigned address ++ * ++ * ++ * Returns the number of fields successfully converted and assigned; ++ * the return value does not include fields that were read but not assigned. ++ * A return value of 0 indicates that no fields were assigned. ++ * return -1 if an error occurs. ++ */ ++int vscanf_s(const char *format, va_list argList) ++{ ++ int retVal; /* If initialization causes e838 */ ++ SecFileStream fStr; ++ SECUREC_FILE_STREAM_FROM_STDIN(&fStr); ++ /* ++ * The "va_list" has different definition on different platform, so we can't use argList == NULL ++ * To determine it's invalid. If you has fixed platform, you can check some fields to validate it, ++ * such as "argList == NULL" or argList.xxx != NULL or *(size_t *)&argList != 0. ++ */ ++ if (format == NULL || fStr.pf == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("vscanf_s"); ++ return SECUREC_SCANF_EINVAL; ++ } ++ ++ SECUREC_LOCK_STDIN(0, fStr.pf); ++ retVal = SecInputS(&fStr, format, argList); ++ SECUREC_UNLOCK_STDIN(0, fStr.pf); ++ if (retVal < 0) { ++ SECUREC_ERROR_INVALID_PARAMTER("vscanf_s"); ++ return SECUREC_SCANF_EINVAL; ++ } ++ return retVal; ++} ++ +diff --git a/lib/securec/src/vsnprintf_s.c b/lib/securec/src/vsnprintf_s.c +new file mode 100644 +index 000000000000..35caaa2206a3 +--- /dev/null ++++ b/lib/securec/src/vsnprintf_s.c +@@ -0,0 +1,138 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: vsnprintf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "secureprintoutput.h" ++ ++#if SECUREC_ENABLE_VSNPRINTF ++/* ++ * ++ * The vsnprintf_s function is equivalent to the vsnprintf function ++ * except for the parameter destMax/count and the explicit runtime-constraints violation ++ * The vsnprintf_s function takes a pointer to an argument list, then formats ++ * and writes up to count characters of the given data to the memory pointed ++ * to by strDest and appends a terminating null. ++ * ++ * ++ * strDest Storage location for the output. ++ * destMax The size of the strDest for output. ++ * count Maximum number of character to write(not including ++ * the terminating NULL) ++ * format Format-control string. ++ * argList pointer to list of arguments. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * return the number of characters written, not including the terminating null ++ * return -1 if an error occurs. ++ * return -1 if count < destMax and the output string has been truncated ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++int vsnprintf_s(char *strDest, size_t destMax, size_t count, const char *format, va_list argList) ++{ ++ int retVal; ++ ++ if (SECUREC_VSNPRINTF_PARAM_ERROR(format, strDest, destMax, count, SECUREC_STRING_MAX_LEN)) { ++ SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); ++ SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_s"); ++ return -1; ++ } ++ ++ if (destMax > count) { ++ retVal = SecVsnprintfImpl(strDest, count + 1, format, argList); ++ if (retVal == SECUREC_PRINTF_TRUNCATE) { /* To keep dest buffer not destroyed 2014.2.18 */ ++ /* The string has been truncated, return -1 */ ++ return -1; /* To skip error handler, return strlen(strDest) or -1 */ ++ } ++ } else { ++ retVal = SecVsnprintfImpl(strDest, destMax, format, argList); ++#ifdef SECUREC_COMPATIBLE_WIN_FORMAT ++ if (retVal == SECUREC_PRINTF_TRUNCATE && count == (size_t)(-1)) { ++ return -1; ++ } ++#endif ++ } ++ ++ if (retVal < 0) { ++ strDest[0] = '\0'; /* Empty the dest strDest */ ++ if (retVal == SECUREC_PRINTF_TRUNCATE) { ++ /* Buffer too small */ ++ SECUREC_ERROR_INVALID_RANGE("vsnprintf_s"); ++ } ++ SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_s"); ++ return -1; ++ } ++ ++ return retVal; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(vsnprintf_s); ++#endif ++#endif ++ ++#if SECUREC_SNPRINTF_TRUNCATED ++/* ++ * ++ * The vsnprintf_truncated_s function is equivalent to the vsnprintf function ++ * except for the parameter destMax/count and the explicit runtime-constraints violation ++ * The vsnprintf_truncated_s function takes a pointer to an argument list, then formats ++ * and writes up to count characters of the given data to the memory pointed ++ * to by strDest and appends a terminating null. ++ * ++ * ++ * strDest Storage location for the output. ++ * destMax The size of the strDest for output. ++ * the terminating NULL) ++ * format Format-control string. ++ * argList pointer to list of arguments. ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * return the number of characters written, not including the terminating null ++ * return -1 if an error occurs. ++ * return destMax-1 if output string has been truncated ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++int vsnprintf_truncated_s(char *strDest, size_t destMax, const char *format, va_list argList) ++{ ++ int retVal; ++ ++ if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_STRING_MAX_LEN)) { ++ SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); ++ SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_truncated_s"); ++ return -1; ++ } ++ ++ retVal = SecVsnprintfImpl(strDest, destMax, format, argList); ++ if (retVal < 0) { ++ if (retVal == SECUREC_PRINTF_TRUNCATE) { ++ return (int)(destMax - 1); /* To skip error handler, return strlen(strDest) */ ++ } ++ strDest[0] = '\0'; /* Empty the dest strDest */ ++ SECUREC_ERROR_INVALID_PARAMTER("vsnprintf_truncated_s"); ++ return -1; ++ } ++ ++ return retVal; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(vsnprintf_truncated_s); ++#endif ++#endif ++ +diff --git a/lib/securec/src/vsprintf_s.c b/lib/securec/src/vsprintf_s.c +new file mode 100644 +index 000000000000..f50fa4a9802f +--- /dev/null ++++ b/lib/securec/src/vsprintf_s.c +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: vsprintf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "secureprintoutput.h" ++ ++/* ++ * ++ * The vsprintf_s function is equivalent to the vsprintf function ++ * except for the parameter destMax and the explicit runtime-constraints violation ++ * The vsprintf_s function takes a pointer to an argument list, and then formats ++ * and writes the given data to the memory pointed to by strDest. ++ * The function differ from the non-secure versions only in that the secure ++ * versions support positional parameters. ++ * ++ * ++ * strDest Storage location for the output. ++ * destMax Size of strDest ++ * format Format specification. ++ * argList pointer to list of arguments ++ * ++ * ++ * strDest is updated ++ * ++ * ++ * return the number of characters written, not including the terminating null character, ++ * return -1 if an error occurs. ++ * ++ * If there is a runtime-constraint violation, strDest[0] will be set to the '\0' when strDest and destMax valid ++ */ ++int vsprintf_s(char *strDest, size_t destMax, const char *format, va_list argList) ++{ ++ int retVal; /* If initialization causes e838 */ ++ ++ if (SECUREC_VSPRINTF_PARAM_ERROR(format, strDest, destMax, SECUREC_STRING_MAX_LEN)) { ++ SECUREC_VSPRINTF_CLEAR_DEST(strDest, destMax, SECUREC_STRING_MAX_LEN); ++ SECUREC_ERROR_INVALID_PARAMTER("vsprintf_s"); ++ return -1; ++ } ++ ++ retVal = SecVsnprintfImpl(strDest, destMax, format, argList); ++ if (retVal < 0) { ++ strDest[0] = '\0'; ++ if (retVal == SECUREC_PRINTF_TRUNCATE) { ++ /* Buffer is too small */ ++ SECUREC_ERROR_INVALID_RANGE("vsprintf_s"); ++ } ++ SECUREC_ERROR_INVALID_PARAMTER("vsprintf_s"); ++ return -1; ++ } ++ ++ return retVal; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(vsprintf_s); ++#endif ++ +diff --git a/lib/securec/src/vsscanf_s.c b/lib/securec/src/vsscanf_s.c +new file mode 100644 +index 000000000000..a19abe2b93da +--- /dev/null ++++ b/lib/securec/src/vsscanf_s.c +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (c) Huawei Technologies Co., Ltd. 2014-2021. All rights reserved. ++ * Licensed under Mulan PSL v2. ++ * You can use this software according to the terms and conditions of the Mulan PSL v2. ++ * You may obtain a copy of Mulan PSL v2 at: ++ * http://license.coscl.org.cn/MulanPSL2 ++ * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, ++ * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, ++ * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. ++ * See the Mulan PSL v2 for more details. ++ * Description: vsscanf_s function ++ * Create: 2014-02-25 ++ */ ++ ++#include "secinput.h" ++#if defined(SECUREC_VXWORKS_PLATFORM) && !SECUREC_IN_KERNEL && \ ++ (!defined(SECUREC_SYSAPI4VXWORKS) && !defined(SECUREC_CTYPE_MACRO_ADAPT)) ++#include ++#endif ++ ++/* ++ * ++ * vsscanf_s ++ * ++ * ++ * ++ * The vsscanf_s function is equivalent to sscanf_s, with the variable argument list replaced by argList ++ * The vsscanf_s function reads data from buffer into the location given by ++ * each argument. Every argument must be a pointer to a variable with a type ++ * that corresponds to a type specifier in format. The format argument controls ++ * the interpretation of the input fields and has the same form and function ++ * as the format argument for the scanf function. ++ * If copying takes place between strings that overlap, the behavior is undefined. ++ * ++ * ++ * buffer Stored data ++ * format Format control string, see Format Specifications. ++ * argList pointer to list of arguments ++ * ++ * ++ * argList the converted value stored in user assigned address ++ * ++ * ++ * Each of these functions returns the number of fields successfully converted ++ * and assigned; the return value does not include fields that were read but ++ * not assigned. A return value of 0 indicates that no fields were assigned. ++ * return -1 if an error occurs. ++ */ ++int vsscanf_s(const char *buffer, const char *format, va_list argList) ++{ ++ size_t count; /* If initialization causes e838 */ ++ int retVal; ++ SecFileStream fStr; ++ ++ /* Validation section */ ++ if (buffer == NULL || format == NULL) { ++ SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); ++ return SECUREC_SCANF_EINVAL; ++ } ++ count = strlen(buffer); ++ if (count == 0 || count > SECUREC_STRING_MAX_LEN) { ++ SecClearDestBuf(buffer, format, argList); ++ SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); ++ return SECUREC_SCANF_EINVAL; ++ } ++#if defined(SECUREC_VXWORKS_PLATFORM) && !SECUREC_IN_KERNEL ++ /* ++ * On vxworks platform when buffer is white string, will set first %s argument to zero.Like following usage: ++ * " \v\f\t\r\n", "%s", str, strSize ++ * Do not check all character, just first and last character then consider it is white string ++ */ ++ if (isspace((int)(unsigned char)buffer[0]) != 0 && isspace((int)(unsigned char)buffer[count - 1]) != 0) { ++ SecClearDestBuf(buffer, format, argList); ++ } ++#endif ++ SECUREC_FILE_STREAM_FROM_STRING(&fStr, buffer, count); ++ retVal = SecInputS(&fStr, format, argList); ++ if (retVal < 0) { ++ SECUREC_ERROR_INVALID_PARAMTER("vsscanf_s"); ++ return SECUREC_SCANF_EINVAL; ++ } ++ return retVal; ++} ++#if SECUREC_EXPORT_KERNEL_SYMBOL ++EXPORT_SYMBOL(vsscanf_s); ++#endif ++ +-- +2.25.1 + diff --git a/hi-vision/patch/readcap_vendor_id.patch b/hi-vision/patch/readcap_vendor_id.patch new file mode 100644 index 0000000000000000000000000000000000000000..3c3072e854a4438784c7f840543b14b91513840c --- /dev/null +++ b/hi-vision/patch/readcap_vendor_id.patch @@ -0,0 +1,117 @@ +diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c +index 3e5563308..2f9d647dd 100644 +--- a/drivers/usb/serial/option.c ++++ b/drivers/usb/serial/option.c +@@ -597,6 +597,9 @@ static void option_instat_callback(struct urb *urb); + #define SIERRA_VENDOR_ID 0x1199 + #define SIERRA_PRODUCT_EM9191 0x90d3 + ++/* TD tech products*/ ++#define TDTECH_VENDOR_ID 0x3466 ++ + /* Device flags */ + + /* Highest interface number which can be used with NCTRL() and RSVD() */ +@@ -2216,6 +2219,102 @@ static const struct usb_device_id option_ids[] = { + { USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x01, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x02, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x03, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x04, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x05, 0x1D) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x03) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x06) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x0A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x0B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x0E) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x10) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x12) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x13) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x14) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x15) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x18) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x19) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1A) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1B) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1C) }, ++ { USB_VENDOR_AND_INTERFACE_INFO(TDTECH_VENDOR_ID, 0xff, 0x06, 0x1D) }, + { } /* Terminating entry */ + }; + MODULE_DEVICE_TABLE(usb, option_ids); diff --git "a/hi-vision/\346\274\224\347\244\272\346\225\210\346\236\234\350\247\206\351\242\221/b\347\253\231\351\223\276\346\216\245.txt" "b/hi-vision/\346\274\224\347\244\272\346\225\210\346\236\234\350\247\206\351\242\221/b\347\253\231\351\223\276\346\216\245.txt" new file mode 100644 index 0000000000000000000000000000000000000000..e4c479095dd0716edfc5f5b5f9ebced1402311b1 --- /dev/null +++ "b/hi-vision/\346\274\224\347\244\272\346\225\210\346\236\234\350\247\206\351\242\221/b\347\253\231\351\223\276\346\216\245.txt" @@ -0,0 +1 @@ +Ÿ5GͼʾƵ https://www.bilibili.com/video/BV1qbSeYRE3S/?share_source=copy_web&vd_source=608b745de955c7e332c07754734deea4 \ No newline at end of file diff --git "a/\347\206\212\346\235\276\346\236\227 24b970443 \347\273\223\351\241\271\346\212\245\345\221\212.md" "b/\347\206\212\346\235\276\346\236\227 24b970443 \347\273\223\351\241\271\346\212\245\345\221\212.md" new file mode 100644 index 0000000000000000000000000000000000000000..2e8bd29b8dc3202b00ab04231ec4ea02825de41b --- /dev/null +++ "b/\347\206\212\346\235\276\346\236\227 24b970443 \347\273\223\351\241\271\346\212\245\345\221\212.md" @@ -0,0 +1,84 @@ +

项目信息

++ 项目名称： 基于 openEuler Embedded 的 RedCap 5G 图传案例开发 ++ 方案描述：基于海欧派和RedCap模组，提供海欧派的5G通信解决方案，开发5G通信端到端图传样例代码，以推动 5G 技术在嵌入式领域的应用。 ++ 时间规划： + - 2024.07.01 - 2024.07.15：硬件系统搭建 + * 配置硬件环境，搭建项目所需的开发环境。 + * 进行openEuler Embedded的系统移植，以确保系统能在嵌入式设备上稳定运行。 + * 进行项目需求分析，制定详细的技术方案。 + - 2024.07.16 - 2024.07.31：RedCap技术的研究与初步集成 + * 深入研究RedCap技术的原理和实现方式，探索其在5G图传中的应用。 + * 初步将RedCap技术集成到openEuler Embedded系统中，确保其与系统的兼容性。 + * 完成RedCap集成的初步测试，确保能够进行低复杂度、低成本的视频传输。 + - 2024.08.01 - 2024.09.15：5G图传案例开发 + * 开发5G图传的各个环节，包括视频采集、编码、传输、解码和显示。 + * 完成数据的采集与编码，确保视频数据能够在5G网络环境下进行高效传输。 + * 对5G图传案例进行功能测试，确保案例能够在openEuler Embedded系统上稳定运行。 + - 2024.09.16 - 2024.09.30：项目整体测试与性能优化 + * 对整个项目进行综合测试，确保5G图传案例的各个环节在openEuler Embedded系统上能够高效、稳定地运行。 + * 对系统性能进行进一步的优化，确保视频传输在5G网络环境下的高带宽和低延迟特性。 + * 完成项目报告的编写，为后续5G图传技术的深入研究和产品开发提供实践经验和技术积累。 + +

项目总结

++ 已完成工作： + - 硬件系统搭建与环境配置： 我们已经配置了所需的硬件环境，包括海欧派和RedCap模组的安装与连接，和Ubuntu虚拟机上交叉编译环境的搭建。 + - 搭建支持RTMP和HLS的服务器，用于传输图片。 + - 使用海鸥派和RedCap通过RTMP协议和HLS协议实现端到端的传输图片。 + - 使用海鸥派和RedCap通过RTMP协议和FFmpeg实现端到端实时视频传输，480P帧率稳定在20FPS。 ++ 遇到的问题及解决方案： + - 在尝试通过执行 `./dial.sh` 脚本使RedCap模块连接外网时，我们遇到了无法连接的问题。通过执行 `route` 指令查看系统的默认网关设置，我们发现了一个192.168.10.1的网关，这个网关是属于电脑以太网的，与我们想要使用的RedCap网络设置冲突。为了解决这一问题，我们使用命令 `route del default gw 192.168.10.1` 删除了该默认网关，之后RedCap模块成功连接到外网。 + - 在Ubuntu系统上搭建交叉编译环境支持openEuler Embedded和RedCap模块开发时，遇到软件依赖和库版本不兼容问题。我们尝试通过Ubuntu包管理系统安装依赖未果，因版本冲突和缺失。转而手动下载源码并编译所需库和工具，搭建成功。 + - 使用 `ffmpeg` 命令在海鸥派上无法解析域名，我们原本使用RTMP服务器的域名作为上传URL地址，但显示报错rtmp fail to resolve hostname，经过查阅，可能是ffmpeg版本问题，将域名换为IP地址后解决该问题。 + - 使用 `ffplay`命令接收视频时，出现延迟超过10秒的情况，我们尝试不使用缓存区， `-fflags nobuffer`命令，延时显著减少，但这样会导致视频卡顿。我们通过修改ffmpeg参数，调整服务器配置和接收数据流的缓存大小，最终实现低延迟的20帧流畅视频传输。 ++ 测试用例 + - 见项目报告 ++ 后续工作安排 + - 继续优化帧率，尽可能达到稳定30FPS。 + - 提高视频的质量，达到720P甚至1080P + - 提高稳定性，模拟各种网络环境，评估系统对网络波动的适应性和恢复能力。 + - 把该功能用于图像识别的视频传输，在未来的竞赛和项目中能够使用。 + +备注：没有相关issue + +

Project Information

++ **Project Name**: Development of RedCap 5G Image Transmission Case Based on openEuler Embedded ++ **Project Description**: Utilizing HiHope and RedCap modules to provide a 5G communication solution with HiHope, this project aims to develop end-to-end sample code for image transmission via 5G communications, thereby promoting the application of 5G technology in the embedded domain. ++ **Timeline**: ++ **2024.07.01 - 2024.07.15: Hardware System Setup** + - Set up the hardware environment and develop the necessary environment for the project. + - Perform system porting of openEuler Embedded to ensure stable operation on embedded devices. + - Conduct project requirement analysis and formulate a detailed technical plan. ++ **2024.07.16 - 2024.07.31: Research and Preliminary Integration of RedCap Technology** + - Deeply research the principles and implementation methods of RedCap technology and explore its application in 5G image transmission. + - Initially integrate RedCap technology into the openEuler Embedded system to ensure compatibility with the system. + - Complete preliminary testing of RedCap integration, ensuring low-complexity, cost-effective video transmission. ++ **2024.08.01 - 2024.09.15: Development of 5G Image Transmission Case** + - Develop various components of 5G image transmission, including video capture, encoding, transmission, decoding, and display. + - Complete data collection and encoding to ensure efficient video data transmission over the 5G network. + - Perform functional testing of the 5G image transmission case to ensure stable operation on the openEuler Embedded system. ++ **2024.09.16 - 2024.09.30: Overall Project Testing and Performance Optimization** + - Conduct comprehensive testing of the project to ensure efficient and stable operation of all components of the 5G image transmission case on the openEuler Embedded system. + - Further optimize system performance to ensure high bandwidth and low latency in video transmission over the 5G network. + - Complete the writing of the project report to provide practical experience and technical accumulation for further research and product development in 5G image transmission technology. + +

Project Summary

++ **Completed Work:** + - Hardware System Setup and Environment Configuration: We have configured the required hardware environment, including installation and connection of HiHope and RedCap modules, and set up a cross-compilation environment on an Ubuntu virtual machine. + - Built a server supporting RTMP and HLS for image transmission. + - Implemented end-to-end image transmission using HiHope and RedCap through RTMP and HLS protocols. + - Realized end-to-end real-time video transmission using HiHope and RedCap through RTMP protocol and FFmpeg, with a stable frame rate of 20FPS at 480P. ++ **Encountered Issues and Solutions:** + - During attempts to connect the RedCap module to the internet via the ./dial.sh script, we faced connection issues. By executing the route command to inspect the system's default gateway settings, we discovered a gateway at 192.168.10.1, which belongs to the computer's ethernet and conflicted with the RedCap network settings we intended to use. To resolve this issue, we used the command route del default gw 192.168.10.1 to remove this default gateway, after which the RedCap module successfully connected to the internet. + - While setting up a cross-compilation environment on Ubuntu system to support openEuler Embedded and RedCap module development, we encountered issues with software dependencies and library version incompatibilities. Attempts to install dependencies through Ubuntu's package management system were unsuccessful due to version conflicts and absences. We resorted to manually downloading the source code and compiling the necessary libraries and tools, which led to a successful setup. + - Using the ffmpeg command on HiHope, we could not resolve domain names. Originally, we used the domain name of the RTMP server as the upload URL address, but encountered errors stating 'rtmp fail to resolve hostname.' After research, it was likely due to an FFmpeg version issue. We resolved this by switching the domain name to an IP address. + - When receiving video using the ffplay command, we experienced delays exceeding 10 seconds. We tried using the -fflags nobuffer command to reduce buffering, which significantly reduced the delay but caused video stuttering. By adjusting FFmpeg parameters, modifying server settings, and tweaking the data stream's buffer size, we achieved low-latency, smooth video transmission at 20 frames per second. ++ **Test Cases:** + - See Project Report ++ **Future Work:** + - Continue optimizing frame rate to achieve a stable 30FPS. + - Improve video quality to reach 720P or even 1080P. + - Enhance stability, simulate various network environments, and assess the system's adaptability and recovery capabilities against network fluctuations. + - Utilize this functionality for video transmission in image recognition, enabling its use in future competitions and projects. + +Note: No related issues. + diff --git "a/\347\206\212\346\235\276\346\236\227 24b970443 \347\273\223\351\241\271\346\212\245\345\221\212.pdf" "b/\347\206\212\346\235\276\346\236\227 24b970443 \347\273\223\351\241\271\346\212\245\345\221\212.pdf" new file mode 100644 index 0000000000000000000000000000000000000000..9dcf52720a5450d44e6454e7f9e25e15f572920a Binary files /dev/null and "b/\347\206\212\346\235\276\346\236\227 24b970443 \347\273\223\351\241\271\346\212\245\345\221\212.pdf" differ