diff --git a/arch/arm64/core/CMakeLists.txt b/arch/arm64/core/CMakeLists.txt index 8aad9586dd343492a8d12408c164ea596bc1884b..e973edc333643f5b82820e5b4157db1864fbd92a 100644 --- a/arch/arm64/core/CMakeLists.txt +++ b/arch/arm64/core/CMakeLists.txt @@ -33,5 +33,3 @@ zephyr_cc_option_ifdef(CONFIG_USERSPACE -mno-outline-atomics) add_subdirectory_ifdef(CONFIG_SOC_XENVM xen) add_subdirectory_ifdef(CONFIG_ZVM virtualization) - -add_subdirectory_ifdef(CONFIG_NS16650_EARLYPRINT_DEBUG rk3568) diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig index 215670ba9e9bc404ed7cb9b3563dddbd39610b59..6d767e852da186f604ed66f3cfacf23345223d60 100644 --- a/arch/arm64/core/Kconfig +++ b/arch/arm64/core/Kconfig @@ -7,10 +7,10 @@ config CPU_CORTEX_A bool select CPU_CORTEX select HAS_FLASH_LOAD_OFFSET -# select SCHED_IPI_SUPPORTED if SMP - select CPU_HAS_FPU - imply FPU - imply FPU_SHARING + select SCHED_IPI_SUPPORTED if SMP +# select CPU_HAS_FPU @TODO: add fpu support +# imply FPU +# imply FPU_SHARING help This option signifies the use of a CPU of the Cortex-A family. diff --git a/arch/arm64/core/mmu.c b/arch/arm64/core/mmu.c index 6d71b1b0a48b9b044b9e259bd503c3ea7f77537a..693bed5113b45ec4ee885b750e4b2984c7798c38 100644 --- a/arch/arm64/core/mmu.c +++ b/arch/arm64/core/mmu.c @@ -21,9 +21,7 @@ #include #include #include -#include #include "mmu.h" -#include LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); @@ -825,7 +823,7 @@ void z_arm64_mm_init(bool is_primary_core) __ASSERT(CONFIG_MMU_PAGE_SIZE == KB(4), "Only 4K page size is supported\n"); -#if defined(CONFIG_HAS_ARM_VHE_EXTN) +#if defined(CONFIG_ZVM) && defined(CONFIG_HAS_ARM_VHE_EXTN) __ASSERT(GET_EL(read_currentel()) == MODE_EL2, "Exception level not EL2, MMU not enabled!\n"); diff --git a/arch/arm64/core/prep_c.c b/arch/arm64/core/prep_c.c index f7b2cb4cfe1630a39832b81eca9fc4a1643adad3..2c3e04cf0881ea23b252b671d2ae400389b69289 100644 --- a/arch/arm64/core/prep_c.c +++ b/arch/arm64/core/prep_c.c @@ -16,7 +16,6 @@ #include #include -#include __weak void z_arm64_mm_init(bool is_primary_core) { } @@ -44,11 +43,6 @@ static inline void z_arm64_bss_zero(void) */ void z_arm64_prep_c(void) { - /* init uart for output, for rk3568 */ -#if defined(CONFIG_SOC_RK3568) && defined(CONFIG_NS16650_EARLYPRINT_DEBUG) - tpl_main(); -#endif - /* Initialize tpidrro_el0 with our struct _cpu instance address */ write_tpidrro_el0((uintptr_t)&_kernel.cpus[0]); #if defined(CONFIG_HAS_ARM_VHE_EXTN) && defined(CONFIG_ZVM) diff --git a/arch/arm64/core/reset.S b/arch/arm64/core/reset.S index 8c43920e829907a2829c55379848bad35cb393e6..7e26d246a861345063f28182fe6127be0e471a05 100644 --- a/arch/arm64/core/reset.S +++ b/arch/arm64/core/reset.S @@ -135,9 +135,6 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) mov x1, x1, lsr #0x08 cmp x1, #0 bne 1f -#endif -#if defined(CONFIG_SOC_RK3568) - mov x1, x1, lsr #0x08 #endif cmp x2, #-1 beq primary_core @@ -146,7 +143,6 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) msr SPsel, #1 switch_el x13, 15f, 16f, 18f 18: - nop 16: mov_imm x13, (SCTLR_EL2_RES1) msr sctlr_el2, x13 @@ -161,7 +157,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start) isb mov_imm x13, (SPSR_MODE_EL1H | DAIF_FIQ_BIT) msr spsr_el1, x13 - + isb #endif /* loop until our turn comes */ @@ -206,7 +202,6 @@ switch_el: 2: /* TODO: The init order may be change */ #if defined(CONFIG_ZVM) && defined(CONFIG_HAS_ARM_VHE_EXTN) - /* EL2 VHE mode init */ bl z_arm64_el2_vhe_init #else bl z_arm64_el2_init diff --git a/arch/arm64/core/reset.c b/arch/arm64/core/reset.c index 7a09bde11b9ccc64b5ff6b81354b8e9a407f6633..ad779e303ecd68ff9d1199f898abfd0e64ba2b3b 100644 --- a/arch/arm64/core/reset.c +++ b/arch/arm64/core/reset.c @@ -6,7 +6,6 @@ #include #include -#include #include "boot.h" #include @@ -139,60 +138,6 @@ void z_arm64_el2_init(void) reg |= HCR_RW_BIT; /* EL1 Execution state is AArch64 */ write_hcr_el2(reg); -#if defined(CONFIG_HAS_ARM_VHE_EXTN) - reg = read_id_aa64mmfr1_el1(); - if(ASM_UBFX(8, 4, reg)){ - reg |= HCR_VHE_FLAGS; - }else{ - /* Enable EL1 physical timer and clear vitrtual offset */ - reg = 0x03; - write_cnthctl_el2(reg); - reg |= HCR_NVHE_FLAGS; - } - write_hcr_el2(reg); - zero_sysreg(cntvoff_el2); - -#if defined(CONFIG_GIC_V3) - reg = read_id_aa64pfr0_el1(); - reg = ASM_UBFX(24, 4, reg); - if(reg){ - __asm__ volatile( - "mrs x0, s3_4_c12_c9_5 \n" - "orr x0, x0, #0x01 \n" - "orr x0, x0, #0x08 \n" - "msr s3_4_c12_c9_5, x0 \n" - "isb \n" - "mrs x0, s3_4_c12_c9_5 \n" - "tbz x0, #0, 99f \n" - "msr s3_4_c12_c11_0, xzr \n " - "99: \n" - ); - } -#endif - - /* Get identification information for the PE from midr_el1, - Set it to vpidr_el2 to info virtualization process id*/ - reg = read_midr_el1(); - write_vpidr_el2(reg); - /* Get an additional PE identification mechanism in multiprocessor system - and info virtualization process id */ - reg = read_mpidr_el1(); - write_vmpidr_el2(reg); - - /* Disable CP15 trapping to EL2 of EL1 accesses to the System register */ - zero_sysreg(hstr_el2); - /* Debug related init */ - zero_sysreg(mdcr_el2); - /* Stage-2 translation base register init*/ - zero_sysreg(vttbr_el2); - - /* Set Exception type to EL1h, spsr_el2 hold the process state when exception happen */ - reg = INIT_PSTATE_EL1 | SPSR_DAIF_MASK; - write_spsr_el2(reg); - isb(); - -#endif - reg = 0U; /* RES0 */ reg |= CPTR_EL2_RES1; /* RES1 */ reg &= ~(CPTR_TFP_BIT | /* Do not trap SVE, SIMD and FP */ @@ -297,9 +242,6 @@ void z_arm64_el2_vhe_init(void) /* Debug related init */ zero_sysreg(mdcr_el2); - /*init memory implemention information */ -// zero_sysreg(lorc_el1); - /* Stage-2 translation base register init*/ zero_sysreg(vttbr_el2); diff --git a/arch/arm64/core/rk3568/debug_uart.S b/arch/arm64/core/rk3568/debug_uart.S deleted file mode 100755 index 560d4c3ff892d7ae141967408fa9d1b9f161d06e..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/debug_uart.S +++ /dev/null @@ -1,274 +0,0 @@ -#include -#include -#include -#include -#include -#include "../core/macro_priv.inc" - - -_ASM_FILE_PROLOGUE - -GDATA(BootromContex) - .align 10 - .zero 8*64 - .align 10 - -GTEXT(safe_print_debug) -SECTION_FUNC(TEXT, safe_print_debug) - - //ldr x0, =BootromContex - //ldr x0, [sp] - sub sp, sp, #0x0100 //256 byte - stp x0, x1, [sp, #16 * 0] - stp x2, x3, [sp, #16 * 1] - stp x4, x5, [sp, #16 * 2] - stp x6, x7, [sp, #16 * 3] - stp x8, x9, [sp, #16 * 4] - stp x10, x11, [sp, #16 * 5] - stp x12, x13, [sp, #16 * 6] - stp x14, x15, [sp, #16 * 7] - stp x16, x17, [sp, #16 * 8] - stp x18, x19, [sp, #16 * 9] - stp x20, x21, [sp, #16 * 10] - stp x22, x23, [sp, #16 * 11] - stp x24, x25, [sp, #16 * 12] - stp x26, x27, [sp, #16 * 13] - stp x28, x29, [sp, #16 * 14] - stp x30, xzr, [sp, #16 * 15] - - bl early_print_debug - - ldp x0, x1, [sp, #16 * 0] - ldp x2, x3, [sp, #16 * 1] - ldp x4, x5, [sp, #16 * 2] - ldp x6, x7, [sp, #16 * 3] - ldp x8, x9, [sp, #16 * 4] - ldp x10, x11, [sp, #16 * 5] - ldp x12, x13, [sp, #16 * 6] - ldp x14, x15, [sp, #16 * 7] - ldp x16, x17, [sp, #16 * 8] - ldp x18, x19, [sp, #16 * 9] - ldp x20, x21, [sp, #16 * 10] - ldp x22, x23, [sp, #16 * 11] - ldp x24, x25, [sp, #16 * 12] - ldp x26, x27, [sp, #16 * 13] - ldp x28, x29, [sp, #16 * 14] - ldp x30, xzr, [sp, #16 * 15] - add sp, sp, #0x0100 - - ret - -GTEXT(safe_print_debug_regs) -SECTION_FUNC(TEXT, safe_print_debug_regs) - - //ldr x0, =BootromContex - //ldr x0, [sp] - sub sp, sp, #0x0100 //256 byte - stp x0, x1, [sp, #16 * 0] - stp x2, x3, [sp, #16 * 1] - stp x4, x5, [sp, #16 * 2] - stp x6, x7, [sp, #16 * 3] - stp x8, x9, [sp, #16 * 4] - stp x10, x11, [sp, #16 * 5] - stp x12, x13, [sp, #16 * 6] - stp x14, x15, [sp, #16 * 7] - stp x16, x17, [sp, #16 * 8] - stp x18, x19, [sp, #16 * 9] - stp x20, x21, [sp, #16 * 10] - stp x22, x23, [sp, #16 * 11] - stp x24, x25, [sp, #16 * 12] - stp x26, x27, [sp, #16 * 13] - stp x28, x29, [sp, #16 * 14] - stp x30, xzr, [sp, #16 * 15] - - bl early_print_debug - - ldp x0, x1, [sp, #16 * 0] - ldp x2, x3, [sp, #16 * 1] - ldp x4, x5, [sp, #16 * 2] - ldp x6, x7, [sp, #16 * 3] - ldp x8, x9, [sp, #16 * 4] - ldp x10, x11, [sp, #16 * 5] - ldp x12, x13, [sp, #16 * 6] - ldp x14, x15, [sp, #16 * 7] - ldp x16, x17, [sp, #16 * 8] - ldp x18, x19, [sp, #16 * 9] - ldp x20, x21, [sp, #16 * 10] - ldp x22, x23, [sp, #16 * 11] - ldp x24, x25, [sp, #16 * 12] - ldp x26, x27, [sp, #16 * 13] - ldp x28, x29, [sp, #16 * 14] - ldp x30, xzr, [sp, #16 * 15] - add sp, sp, #0x0100 - - ret - - -GTEXT(safe_print_debug_smp) -SECTION_FUNC(TEXT, safe_print_debug_smp) - - //ldr x0, =BootromContex - //ldr x0, [sp] - sub sp, sp, #0x0100 //256 byte - stp x0, x1, [sp, #16 * 0] - stp x2, x3, [sp, #16 * 1] - stp x4, x5, [sp, #16 * 2] - stp x6, x7, [sp, #16 * 3] - stp x8, x9, [sp, #16 * 4] - stp x10, x11, [sp, #16 * 5] - stp x12, x13, [sp, #16 * 6] - stp x14, x15, [sp, #16 * 7] - stp x16, x17, [sp, #16 * 8] - stp x18, x19, [sp, #16 * 9] - stp x20, x21, [sp, #16 * 10] - stp x22, x23, [sp, #16 * 11] - stp x24, x25, [sp, #16 * 12] - stp x26, x27, [sp, #16 * 13] - stp x28, x29, [sp, #16 * 14] - stp x30, xzr, [sp, #16 * 15] - - bl asm_register_print_smp - - ldp x0, x1, [sp, #16 * 0] - ldp x2, x3, [sp, #16 * 1] - ldp x4, x5, [sp, #16 * 2] - ldp x6, x7, [sp, #16 * 3] - ldp x8, x9, [sp, #16 * 4] - ldp x10, x11, [sp, #16 * 5] - ldp x12, x13, [sp, #16 * 6] - ldp x14, x15, [sp, #16 * 7] - ldp x16, x17, [sp, #16 * 8] - ldp x18, x19, [sp, #16 * 9] - ldp x20, x21, [sp, #16 * 10] - ldp x22, x23, [sp, #16 * 11] - ldp x24, x25, [sp, #16 * 12] - ldp x26, x27, [sp, #16 * 13] - ldp x28, x29, [sp, #16 * 14] - ldp x30, xzr, [sp, #16 * 15] - add sp, sp, #0x0100 - - ret - - - -GTEXT(setjmp) -SECTION_FUNC(TEXT, setjmp) - /* 保存上下文 */ - stp x19, x20, [x0,#0] - stp x21, x22, [x0,#16] - stp x23, x24, [x0,#32] - stp x25, x26, [x0,#48] - stp x27, x28, [x0,#64] - stp x29, x30, [x0,#80] - mov x2, sp - str x2, [x0, #96] - mov x0, #0 - ret - -GTEXT(longjmp) -SECTION_FUNC(TEXT, longjmp) - ldp x19, x20, [x0,#0] - ldp x21, x22, [x0,#16] - ldp x23, x24, [x0,#32] - ldp x25, x26, [x0,#48] - ldp x27, x28, [x0,#64] - ldp x29, x30, [x0,#80] - ldr x2, [x0,#96] - mov sp, x2 - /* 恢复上下文, 第二个参数做返回值，如果第二个参数是0就加1返回1 */ - adds x0, xzr, x1 - csinc x0, x0, xzr, ne - /* invalid icache for cortex a35 */ - //branch_if_a35_core x1, __asm_invalidate_icache_all - ret - - -// Define some constants -.equ UART_BASE, 0xfdcc0000 // Base address of uart port -.equ UART_THR, 0x00 // Transmit holding register offset -.equ UART_LSR, 0x14 // Line status register offset - - -GTEXT(uart_putc) -SECTION_FUNC(TEXT, uart_putc) - ldr x1, =UART_BASE // Load base address of uart port to x1 - ldrb w2, [x0], #1 // Load a byte from string to w2 and increment x0 by 1 - cbz w2, uart_putc_done // If w2 is zero, branch to putc_done -uart_putc_loop: - ldrb w3, [x1, UART_LSR] // Load line status register to w3 - tbz w3, #5, uart_putc_loop // If transmit holding register empty bit is not set, loop - strb w2, [x1, UART_THR] // Store w2 to transmit holding register - b uart_putc // Branch to putc -uart_putc_done: - ret // Return from subroutine - -GTEXT(uart_putn) -SECTION_FUNC(TEXT, uart_putn) - mov x1, #10 // Load 10 to x1 as the base of decimal system - mov x2, sp // Load stack pointer to x2 as the buffer pointer -uart_putn_loop: - udiv x3, x0, x1 // Divide x0 by x1 and store the quotient in x3 - msub x4, x3, x1, x0 // Multiply x3 by x1 and subtract from x0 and store the remainder in x4 - add x4, x4, #'0' // Add '0' to x4 to convert it to a character - strb w4, [x2], #-1 // Store w4 to the buffer and decrement x2 by 1 - cbz x3, uart_putn_done // If x3 is zero, branch to putn_done - mov x0, x3 // Move x3 to x0 as the new number to output - b uart_putn_loop // Branch to putn_loop -uart_putn_done: - add x0, x2, #1 // Add 1 to x2 and store it in x0 as the string pointer - bl uart_putc // Branch with link to putc subroutine - ret // Return from subroutine - - -GTEXT(asm_safe_uart_output) -SECTION_FUNC(TEXT, asm_safe_uart_output) - - stp x29,x28,[sp,#-16]!// Store x29 and x28 pair on the stack and decrement sp by 16 - stp x27,x26,[sp,#-16]!// Store x27 and x26 pair on the stack and decrement sp by 16 - stp x25,x24,[sp,#-16]!// Store x25 and x24 pair on the stack and decrement sp by 16 - stp x23,x22,[sp,#-16]!// Store x23 and x22 pair on the stack and decrement sp by 16 - stp x21,x20,[sp,#-16]!// Store x21 and x20 pair on the stack and decrement sp by 16 - stp x19,x18,[sp,#-16]!// Store x19 and x18 pair on the stack and decrement sp by 16 - stp x17,x16,[sp,#-16]!// Store x19 and x18 pair on the stack and decrement sp by 16 - stp x15,x14,[sp,#-16]!// Store x15 and x14 pair on the stack and decrement sp by 16 - stp x13,x12,[sp,#-16]!// Store x13 and x12 pair on the stack and decrement sp by 16 - stp x11,x10,[sp,#-16]!// Store x11 and x10 pair on the stack and decrement sp by 16 - stp x9,x8,[sp,#-16]!// Store x9 and x8 pair on the stack and decrement sp by 16 - stp x7,x6,[sp,#-16]!// Store x7 and x6 pair on the stack and decrement sp by 16 - stp x5,x4,[sp,#-16]!// Store x5 and x4 pair on the stack and decrement sp by 16 - stp x3,x2,[sp,#-16]!// Store x3 and x2 pair on the stack and decrement sp by 16 - stp x1,x0,[sp,#-16]!// Store x1 and x0 pair on the stack and decrement sp by 16 - mrs x0, elr_el1 // Move exception link register to x0 - mrs x1, spsr_el1 // Move saved program status register to x1 - stp x0,x1,[sp,#-16]!// Store x0 and x1 pair on the stack and decrement sp by 16 - mov x0, lr - mov x1, sp - stp x0,x1,[sp,#-16]!// Store x0 and x1 pair on the stack and decrement sp by 16 - - mov x0, #12345 // Load a number to output to x0 - bl uart_putn // Branch with link to putn subroutine - - ldp x0,x1,[sp],#16 // Load x0 and x1 pair from the stack and increment sp by 16 - mov lr, x0 // Move x0 to exception link register - mov sp, x1 // Move x1 to saved program status register - ldp x0,x1,[sp],#16 // Load x0 and x1 pair from the stack and increment sp by 16 - msr elr_el1, x0 // Move x0 to exception link register - msr spsr_el1, x1 // Move x1 to saved program status register - ldp x1,x0,[sp],#16 // Load x1 and x0 pair from the stack and increment sp by 16 - ldp x3,x2,[sp],#16 // Load x3 and x2 pair from the stack and increment sp by 16 - ldp x5,x4,[sp],#16 // Load x5 and x4 pair from the stack and increment sp by 16 - ldp x7,x6,[sp],#16 // Load x7 and x6 pair from the stack and increment sp by 16 - ldp x9,x8,[sp],#16 // Load x9 and x8 pair from the stack and increment sp by 16 - ldp x11,x10,[sp],#16 // Load x11 and - ldp x13,x12,[sp],#16 // Load x11 and - ldp x15,x14,[sp],#16 // Load x11 and - ldp x17,x16,[sp],#16 // Load x11 and - ldp x19,x18,[sp],#16 // Load x19 and x18 pair from the stack and increment sp by 16 - ldp x21,x20,[sp],#16 // Load x21 and x20 pair from the stack and increment sp by 16 - ldp x23,x22,[sp],#16 // Load x23 and x22 pair from the stack and increment sp by 16 - ldp x25,x24,[sp],#16 // Load x25 and x24 pair from the stack and increment sp by 16 - ldp x27,x26,[sp],#16 // Load x27 and x26 pair from the stack and increment sp by 16 - ldp x29,x28,[sp],#16 // Load x29 and x28 pair from the stack and increment sp by 16 - - ret - diff --git a/arch/arm64/core/rk3568/debug_uart.c b/arch/arm64/core/rk3568/debug_uart.c deleted file mode 100755 index b64b1f3d53e53260faac8c81a26b4d0efb4a40cb..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/debug_uart.c +++ /dev/null @@ -1,351 +0,0 @@ -#include "rk3568_common.h" -#include "include/mm.h" -#include -#include -#include "stdarg.h" -#include - -#define MY_GET_EL(mode) (((mode) >> 0x02) & 0x03) -#define SYS_GRF 0xFDC60000 -#define GRF_IOFUNC_SEL3 0x030C -#define PMU_GRF 0xfdc20000 -#define GRF_GPIO0D_IOMUX_L 0x0018 -#define CONFIG_DEBUG_UART_BASE 0xFE660000 -#define CONFIG_DEBUG_UART_CLOCK 24000000 -#define CONFIG_BAUDRATE 1500000 -#define MAX_NUMBER_BYTES 64 - -#define IRAM_START_ADDR 0xfdcc0000 -#define BROM_BOOTSOURCE_ID_ADDR (IRAM_START_ADDR + 0x10) -#define CONFIG_ROCKCHIP_BOOT_MODE_REG 0xfdc20200 // 0xfdc20000 + 0x200 (PMU_GRF + PMU_GRF_OS_REG0) -#define BROMA_GOTO_NEXT 0 -#define BROMA_RELOAD_ME 1 -#define reg_per 13 - -uint64_t debug_print_reg[10000]; -int count_offset=2; -K_KERNEL_STACK_DEFINE(earlyprint_stack, PRINTK_STACK_SIZE); -extern u8 BootromContex; -u32 boot_mode, boot_dvid; -u32 bootrom_action; -const unsigned char hex_tab[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'a', 'b', 'c', 'd', 'e', 'f'}; - -void save_boot_params_ret(void); -int setjmp(u8* ctx); -void longjmp(u8* ctx, int ret); -void printascii(const char *str); -int debug_earlyprint(const char *fmt, ...); - - -static inline unsigned int get_current_el(void) -{ - return MY_GET_EL(read_currentel()); -} - -static void ns16650_putc(int ch) -{ - if (ch == '\n') ns16650_putc('\r'); - - struct NS16550 *com_port; - - com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - - while (!(serial_din(&com_port->lsr) & 0x20)) - ; - serial_dout(&com_port->thr, ch); -} - - -int save_boot_params(void) -{ - int tmp = setjmp(&BootromContex); // setjmp 首次返回0， 当在别的地方调用 longjmp(brom_ctx, 整数n) 时 setjmp 会再次从这里开始往运行，返回的 tmp 值为 整数n！ - - if(0 == tmp) - { - // contex saved in setjmp(&BootromContex) & return 0; - - boot_mode = readl(CONFIG_ROCKCHIP_BOOT_MODE_REG); - boot_dvid = readl(BROM_BOOTSOURCE_ID_ADDR); - bootrom_action = BROMA_GOTO_NEXT; - - save_boot_params_ret(); // 不让这个函数结束，实际就是从 rk3568tpl_start.S 中的 save_boot_params_ret 处接着往下运行 - }else{ - printascii("longjpm ok.\r\n"); - - return bootrom_action; - } - // 这里开始的代码，不会被执行！因为根本不会运行到这里！ - return 2; -} - -void back_to_bootrom(int exitCode) -{ - bootrom_action = exitCode; - - longjmp(&BootromContex, 888888); -} - - -void uart_init() -{ - // IOMUX 配置，将UART2对应的GPIO引脚选用为 uart2 mux0 功能 - //*((u32 *)(SYS_GRF + GRF_IOFUNC_SEL3)) = 0x0C000000; - rk_clrsetreg(SYS_GRF + GRF_IOFUNC_SEL3, 0x0C00, 0x0000); - - // GPIO0_D0 做 uart2 mux0 的 rx 线， GPIO0_D1 做 uart2 mux0 的 tx 线 - //*((u32 *)(PMU_GRF + GRF_GPIO0D_IOMUX_L)) = 0x00770011; - rk_clrsetreg(PMU_GRF + GRF_GPIO0D_IOMUX_L, 0x0077, 0x0011); - - // 时钟频率与波特率换算？？ - int baud_divisor = DIV_ROUND_CLOSEST(CONFIG_DEBUG_UART_CLOCK, 16 * CONFIG_BAUDRATE); - - - struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE; - serial_dout(&com_port->ier, (1 << 6)); - serial_dout(&com_port->mcr, 0x03); - serial_dout(&com_port->fcr, 0x07); - - serial_dout(&com_port->lcr, 0x80 | 0x03); - serial_dout(&com_port->dll, baud_divisor & 0xff); - serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff); - serial_dout(&com_port->lcr, 0x03); - -} - -static int outc(int c) -{ - ns16650_putc(c); - return 0; -} - -static int outs (const char *s) -{ - while (*s != '\0') - ns16650_putc(*s++); - return 0; -} - -static int out_num(long n, int base, char lead, int maxwidth) -{ - unsigned long m = 0; - char buf[MAX_NUMBER_BYTES], *s = buf + sizeof(buf); - int count = 0, i = 0; - - *--s = '\0'; - - if (n < 0) - m = -n; - else - m = n; - - do - { - *--s = hex_tab[m % base]; - count++; - } - while ((m /= base) != 0); - - if( maxwidth && count < maxwidth) - { - for (i = maxwidth - count; i; i--) - *--s = lead; - } - - if (n < 0) - *--s = '-'; - - return outs(s); -} - -/*ref: int vdebug_earlyprint(const char *format, va_list ap); */ -static int my_vdebug_earlyprint(const char *fmt, va_list ap) -{ - char lead = ' '; - int maxwidth = 0; - - for(; *fmt != '\0'; fmt++) - { - if (*fmt != '%') - { - outc(*fmt); - continue; - } - lead = ' '; - maxwidth = 0; - - //format : %08d, %8d,%d,%u,%x,%f,%c,%s - fmt++; - if(*fmt == '0') - { - lead = '0'; - fmt++; - } - - while(*fmt >= '0' && *fmt <= '9') - { - maxwidth *= 10; - maxwidth += (*fmt - '0'); - fmt++; - } - - switch (*fmt) - { - case 'd': - out_num(va_arg(ap, int), 10, lead, maxwidth); - break; - case 'o': - out_num(va_arg(ap, unsigned int), 8, lead, maxwidth); - break; - case 'u': - out_num(va_arg(ap, unsigned int), 10, lead, maxwidth); - break; - case 'x': - out_num(va_arg(ap, unsigned int), 16, lead, maxwidth); - break; - case 'c': - outc(va_arg(ap, int )); - break; - case 's': - outs(va_arg(ap, char *)); - break; - - default: - outc(*fmt); - break; - } - } - return 0; -} - -int debug_earlyprint(const char *fmt, ...) -{ - va_list ap; - va_start(ap, fmt); - my_vdebug_earlyprint(fmt, ap); - va_end(ap); - return 0; -} - - -void printascii(const char *str) -{ - while (*str) ns16650_putc(*str++); -} - - -static void asm_register_print(void) -{ - - switch(get_current_el()){ - case 2: { - debug_earlyprint("sctlr_el2:\t 0x%08x-%08x,\t spsr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_sctlr_el2()>>32),read_sctlr_el2(), (unsigned long)(read_spsr_el2()>>32), read_spsr_el2()); - debug_earlyprint("mair_el2:\t 0x%08x-%08x,\t tcr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_mair_el2()>>32),read_mair_el2(), (unsigned long)(read_tcr_el2()>>32),read_tcr_el2()); - debug_earlyprint("vtcr_el2:\t 0x%08x-%08x,\t vttbr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_vtcr_el2()>>32), read_vtcr_el2(), (unsigned long)(read_vttbr_el2()>>32), read_vttbr_el2()); - debug_earlyprint("tpidr_el2:\t 0x%08x-%08x,\t ttbr0_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_tpidr_el2()>>32), read_tpidr_el2(), (unsigned long)(read_ttbr0_el2()>>32), read_ttbr0_el2()); - debug_earlyprint("vbar_el2:\t 0x%08x-%08x,\t mpidr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_vbar_el2()>>32), read_vbar_el2(), (unsigned long)(read_mpidr_el1()>>32), read_mpidr_el1()); - debug_earlyprint("cptr_el2:\t 0x%08x-%08x,\t hcr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_cptr_el2()>>32), read_cptr_el2(), (unsigned long)(read_hcr_el2()>>32), read_hcr_el2()); - debug_earlyprint("esr_el2:\t 0x%08x-%08x,\t elr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_esr_el2()>>32), read_esr_el2(), (unsigned long)(read_elr_el2()>>32),read_elr_el2()); - } - case 1: { - debug_earlyprint("sctlr_el1:\t 0x%08x-%08x,\t spsr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_sctlr_el1()>>32),read_sctlr_el1(), (unsigned long)(read_spsr_el1()>>32),read_spsr_el1()); - debug_earlyprint("mair_el1:\t 0x%08x-%08x,\t tcr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_mair_el1()>>32),read_mair_el1(), (unsigned long)(read_tcr_el1()>>32),read_tcr_el1()); - debug_earlyprint("ttbr0_el1:\t 0x%08x-%08x,\t ttbr1_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_ttbr0_el1()>>32),read_ttbr0_el1(), (unsigned long)(read_ttbr1_el1()>>32),read_ttbr1_el1()); - debug_earlyprint("mpidr_el1:\t 0x%08x-%08x,\t cpacr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_mpidr_el1()>>32),read_mpidr_el1(), (unsigned long)(read_cpacr_el1()>>32),read_cpacr_el1()); - debug_earlyprint("esr_el1:\t 0x%08x-%08x,\t elr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_esr_el1()>>32),read_esr_el1(), (unsigned long)(read_elr_el1()>>32),read_elr_el1()); - debug_earlyprint("isr_el1:\t 0x%08x-%08x,\t \r\n", (unsigned long)(read_isr_el1()>>32),read_isr_el1()); - break; - } - default: - printascii("Wrong exception mode! \n"); - break; - } - return; -} - -void asm_register_print_smp(unsigned long long reg0, unsigned long long reg1) -{ - unsigned long reg0_1, reg1_1; - - reg0_1 = reg0 >> 32; - reg1_1 = reg1 >> 32; - printk("x0: 0x%08x-%08x , x1: 0x%08x-%08x \r\n", reg0_1, reg0, reg1_1, reg1); - - switch(get_current_el()){ - case 2: { - printk("sctlr_el2:\t 0x%08x-%08x,\t spsr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_sctlr_el2()>>32),read_sctlr_el2(), (unsigned long)(read_spsr_el2()>>32), read_spsr_el2()); - printk("mair_el2:\t 0x%08x-%08x,\t tcr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_mair_el2()>>32),read_mair_el2(), (unsigned long)(read_tcr_el2()>>32),read_tcr_el2()); - printk("vtcr_el2:\t 0x%08x-%08x,\t vttbr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_vtcr_el2()>>32), read_vtcr_el2(), (unsigned long)(read_vttbr_el2()>>32), read_vttbr_el2()); - printk("tpidr_el2:\t 0x%08x-%08x,\t ttbr0_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_tpidr_el2()>>32), read_tpidr_el2(), (unsigned long)(read_ttbr0_el2()>>32), read_ttbr0_el2()); - printk("vbar_el2:\t 0x%08x-%08x,\t mpidr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_vbar_el2()>>32), read_vbar_el2(), (unsigned long)(read_mpidr_el1()>>32), read_mpidr_el1()); - printk("cptr_el2:\t 0x%08x-%08x,\t hcr_el2:\t 0x%08x-%08x \r\n", (unsigned long)(read_cptr_el2()>>32), read_cptr_el2(), (unsigned long)(read_hcr_el2()>>32), read_hcr_el2()); - printk("esr_el2:\t 0x%08x-%08x\r\n", (unsigned long)(read_esr_el2()>>32), read_esr_el2()); - } - case 1: { - printk("sctlr_el1:\t 0x%08x-%08x,\t spsr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_sctlr_el1()>>32),read_sctlr_el1(), (unsigned long)(read_spsr_el1()>>32),read_spsr_el1()); - printk("mair_el1:\t 0x%08x-%08x,\t tcr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_mair_el1()>>32),read_mair_el1(), (unsigned long)(read_tcr_el1()>>32),read_tcr_el1()); - printk("ttbr0_el1:\t 0x%08x-%08x,\t ttbr1_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_ttbr0_el1()>>32),read_ttbr0_el1(), (unsigned long)(read_ttbr1_el1()>>32),read_ttbr1_el1()); - printk("mpidr_el1:\t 0x%08x-%08x,\t cpacr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_mpidr_el1()>>32),read_mpidr_el1(), (unsigned long)(read_cpacr_el1()>>32),read_cpacr_el1()); - printk("esr_el1:\t 0x%08x-%08x,\t elr_el1:\t 0x%08x-%08x \r\n", (unsigned long)(read_esr_el1()>>32),read_esr_el1(), (unsigned long)(read_elr_el1()>>32),read_elr_el1()); - printk("isr_el1:\t 0x%08lx-%08llx,\t tpidrro_el0:\t 0x%08lx-%08llx\r\n", (unsigned long)(read_isr_el1()>>32),read_isr_el1(), - (unsigned long)(read_tpidrro_el0()>>32),read_tpidrro_el0()); - break; - } - default: - printascii("Wrong exception mode! \n"); - break; - } - return; -} - -static void show_boot_mode(void) -{ - printascii("**********************************"); - printascii("\n## Booting on uboot......"); - printascii("\n## Earlyprintk init successful!"); - switch(get_current_el()){ - case 2: { - printascii("\n## Boot system on EL2 mode!\n"); - break; - } - case 1: { - printascii("\n## Boot system on EL1 mode!\n"); - break; - } - default: - printascii("Boot Wrong mode! \n"); - break; - } - return; -} - -void early_print_debug(unsigned long long reg1, unsigned long long reg2) -{ - unsigned long reg1_1, reg2_1; - - reg1_1 = reg1 >> 32; - reg2_1 = reg2 >> 32; - debug_earlyprint("x0: 0x%08x-%08x , x1: 0x%08x-%08x \r\n", reg1_1, reg1, reg2_1, reg2); -// asm_register_print(); - return; -} - -void show_print_debug_delay(void) -{ - int j; - while(count_offset>0){ - for(j=count_offset-reg_per; j>32),debug_print_reg[j], j+1+reg_per-count_offset,(unsigned long)(debug_print_reg[j+1]>>32), debug_print_reg[j+1]); - } - debug_earlyprint("---------------------------------------\n"); - count_offset -= reg_per; - } -} - -int tpl_main(void) -{ - uart_init(); - show_boot_mode(); - - return 0; -} diff --git a/arch/arm64/core/rk3568/include/mini_uart.h b/arch/arm64/core/rk3568/include/mini_uart.h deleted file mode 100755 index d3bd2dc4ab8da126e0b05fe1a81c60aaea0a1f61..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/include/mini_uart.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _MINI_UART_H -#define _MINI_UART_H - -void uart_init ( void ); -char uart_recv ( void ); -void uart_send ( char c ); -void uart_send_string(char* str); - -#endif /*_MINI_UART_H */ diff --git a/arch/arm64/core/rk3568/include/mm.h b/arch/arm64/core/rk3568/include/mm.h deleted file mode 100755 index 4cd3c5ed551230d8cc35c1e51ff9422c3e95a3de..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/include/mm.h +++ /dev/null @@ -1,82 +0,0 @@ -#ifndef _MM_H -#define _MM_H - -#define VA_START 0x40000000 -#define DEVICE_BASE 0x40000000 - -#define PHYS_MEMORY_SIZE 0x40000000 - -#define PAGE_SHIFT 12 -#define TABLE_SHIFT 9 -#define SECTION_SHIFT (PAGE_SHIFT + TABLE_SHIFT) - -#define PAGE_SIZE (1 << PAGE_SHIFT) -#define SECTION_SIZE (1 << SECTION_SHIFT) - -#define LOW_MEMORY (2 * SECTION_SIZE) -#define HIGH_MEMORY DEVICE_BASE - -#define PAGING_MEMORY (HIGH_MEMORY - LOW_MEMORY) -#define PAGING_PAGES (PAGING_MEMORY/PAGE_SIZE) - -#define PTRS_PER_TABLE (1 << TABLE_SHIFT) - -#define PGD_SHIFT PAGE_SHIFT + 3*TABLE_SHIFT -#define PUD_SHIFT PAGE_SHIFT + 2*TABLE_SHIFT -#define PMD_SHIFT PAGE_SHIFT + TABLE_SHIFT - -#define PG_DIR_SIZE (3 * PAGE_SIZE) - -/*******************************************/ - -#define SCTLR_RESERVED (3 << 28) | (3 << 22) | (1 << 20) | (1 << 11) -#define SCTLR_EE_LITTLE_ENDIAN (0 << 25) -#define SCTLR_EOE_LITTLE_ENDIAN (0 << 24) -#define SCTLR_I_CACHE_DISABLED (0 << 12) -#define SCTLR_D_CACHE_DISABLED (0 << 2) -#define SCTLR_MMU_DISABLED (0 << 0) -#define SCTLR_MMU_ENABLED (1 << 0) - -#define SCTLR_VALUE_MMU_DISABLED (SCTLR_RESERVED | SCTLR_EE_LITTLE_ENDIAN | SCTLR_I_CACHE_DISABLED | SCTLR_D_CACHE_DISABLED | SCTLR_MMU_DISABLED) - - -#define HCR_VALUE HCR_RW - - -/* AArch64 SPSR bits */ -#define PSR_F_BIT 0x00000040 -#define PSR_I_BIT 0x00000080 -#define PSR_A_BIT 0x00000100 -#define PSR_D_BIT 0x00000200 -#define PSR_SSBS_BIT 0x00001000 -#define PSR_PAN_BIT 0x00400000 -#define PSR_UAO_BIT 0x00800000 -#define PSR_DIT_BIT 0x01000000 -#define PSR_V_BIT 0x10000000 -#define PSR_C_BIT 0x20000000 -#define PSR_Z_BIT 0x40000000 -#define PSR_N_BIT 0x80000000 - -/* - * PSR bits - */ -#define PSR_MODE_EL0t 0x00000000 -#define PSR_MODE_EL1t 0x00000004 -#define PSR_MODE_EL1h 0x00000005 -#define PSR_MODE_EL2t 0x00000008 -#define PSR_MODE_EL2h 0x00000009 -#define PSR_MODE_EL3t 0x0000000c -#define PSR_MODE_EL3h 0x0000000d -#define PSR_MODE_MASK 0x0000000f - - -/*******************************************/ -#ifndef __ASSEMBLER__ - -void memzero(unsigned long src, unsigned long n); - -#endif - -#define PRINTK_STACK_SIZE 0x4000 - -#endif /*_MM_H */ diff --git a/arch/arm64/core/rk3568/include/utils.h b/arch/arm64/core/rk3568/include/utils.h deleted file mode 100755 index a23ae37a77b6c8d010782050335b9fb89ee1ddd9..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/include/utils.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _BOOT_H -#define _BOOT_H - -extern void delay ( unsigned long); -extern void put32 ( unsigned long, unsigned int ); -extern unsigned int get32 ( unsigned long ); - -#endif /*_BOOT_H */ diff --git a/arch/arm64/core/rk3568/readme.rst b/arch/arm64/core/rk3568/readme.rst deleted file mode 100755 index 7199160e01c4efc0cd863a03e9c0657ded807c84..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/readme.rst +++ /dev/null @@ -1,15 +0,0 @@ -rk3568 ns16550 uart test -==================================== - -串口测试工具 ---------- - -rk3568目录下的代码用作测试rk3568板卡，使用ns16650工具来对板卡进行调试。 - -配置项 -~~~~~~~~~ -CONFIG_NS16650_EARLYPRINT_DEBUG=y - - -注：串口工具在程序正常运行的时候需要关闭，不然会引起中断风暴（原因未知）。 - diff --git a/arch/arm64/core/rk3568/rk3568_common.h b/arch/arm64/core/rk3568/rk3568_common.h deleted file mode 100755 index d6fd67a6c7952b0b2e7827e01601ba3eb7583161..0000000000000000000000000000000000000000 --- a/arch/arm64/core/rk3568/rk3568_common.h +++ /dev/null @@ -1,109 +0,0 @@ -#ifndef __CONFIG_RK3568_COMMON_H -#define __CONFIG_RK3568_COMMON_H - - -typedef unsigned long size_t; - -typedef signed char s8; -typedef unsigned char u8; - -typedef signed short s16; -typedef unsigned short u16; - -typedef signed int s32; -typedef unsigned int u32; - -typedef signed long long s64; -typedef unsigned long long u64; - -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) -#define __arch_getq(a) (*(volatile unsigned long long *)(a)) - -#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) -#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v)) - -#define mb() dsb() -#define __iormb() dmb() -#define __iowmb() dmb() - -#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) -#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) -#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) -#define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) - -#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; }) -#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; }) -#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; }) -#define writeq(v,c) ({ u64 __v = v; __iowmb(); __arch_putq(__v,c); __v; }) - -#define rk_clrsetreg(addr, clr, set) writel(((clr) | (set)) << 16 | (set), addr) -#define rk_clrreg(addr, clr) writel((clr) << 16, addr) -#define rk_setreg(addr, set) writel((set) << 16 | (set), addr) - -#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) - -#define check_member(structure, member, offset) _Static_assert( \ - offsetof(struct structure, member) == offset, \ - "`struct " #structure "` offset for `" #member "` is not " #offset) - -#define DIV_ROUND_CLOSEST(x, divisor)( \ -{ \ - __typeof__(x) __x = x; \ - __typeof__(divisor) __d = divisor; \ - (((__typeof__(x))-1) > 0 || \ - ((__typeof__(divisor))-1) > 0 || (__x) > 0) ? \ - (((__x) + ((__d) / 2)) / (__d)) : \ - (((__x) - ((__d) / 2)) / (__d)); \ -} \ -) - -#define CONFIG_SYS_NS16550_REG_SIZE (-1) - -#define UART_REG(x) \ - unsigned char x; - //unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; - -struct NS16550 { - UART_REG(rbr); /* 0 */ - UART_REG(ier); /* 1 */ - UART_REG(fcr); /* 2 */ - UART_REG(lcr); /* 3 */ - UART_REG(mcr); /* 4 */ - UART_REG(lsr); /* 5 */ - UART_REG(msr); /* 6 */ - UART_REG(spr); /* 7 */ - UART_REG(mdr1); /* 8 */ - UART_REG(reg9); /* 9 */ - UART_REG(regA); /* A */ - UART_REG(regB); /* B */ - UART_REG(regC); /* C */ - UART_REG(regD); /* D */ - UART_REG(regE); /* E */ - UART_REG(uasr); /* F */ - UART_REG(scr); /* 10*/ - UART_REG(ssr); /* 11*/ - // struct ns16550_platdata *plat; -}; - -#define CONFIG_DEBUG_UART_SHIFT 2 - -#define serial_dout(reg, value) \ - writel(value, (char *)com_port + \ - ((char *)reg - (char *)com_port) * \ - (1 << CONFIG_DEBUG_UART_SHIFT) ) -#define serial_din(reg) \ - readl((char *)com_port + \ - ((char *)reg - (char *)com_port) * \ - (1 << CONFIG_DEBUG_UART_SHIFT)) - -#define thr rbr -#define iir fcr -#define dll rbr -#define dlm ier -/************************** GIC ***************************/ - -#endif diff --git a/arch/arm64/core/smp.c b/arch/arm64/core/smp.c index 083af2d88fbb8d2dd706ed8ef6e6083b5a97e18b..6d2fbf08590add60b283605d20f679a4865804d9 100644 --- a/arch/arm64/core/smp.c +++ b/arch/arm64/core/smp.c @@ -110,7 +110,6 @@ void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz, return; } -// sys_cache_data_all(K_CACHE_INVD); sctlr_reg = SCTLR_C_BIT | read_sctlr_el1(); write_sctlr_el1(sctlr_reg); isb(); @@ -129,7 +128,8 @@ void z_arm64_secondary_start(void) int cpu_num = arm64_cpu_boot_params.cpu_num; arch_cpustart_t fn; void *arg; - + /* Warning: DO NOT USE prink() IN SMP, WHICH WILL CAUSE BOOT ERROR + printk("Ready to init arm64_secondary_start\n "); */ __ASSERT(arm64_cpu_boot_params.mpid == MPIDR_TO_CORE(GET_MPIDR()), ""); /* Initialize tpidrro_el0 with our struct _cpu instance address */ @@ -152,10 +152,6 @@ void z_arm64_secondary_start(void) #endif #endif -#if defined(CONFIG_SOC_RK3568) && defined(CONFIG_NS16650_EARLYPRINT_DEBUG) - printascii("Init secondary core successful! \r\n"); -#endif - fn = arm64_cpu_boot_params.fn; arg = arm64_cpu_boot_params.arg; dsb(); diff --git a/arch/arm64/core/switch.S b/arch/arm64/core/switch.S index 186814cfb05385a0471a9318b3c7f3fc8c0a4d10..e60411f395a9dd75e94ae5380dbd0e2a72aad667 100644 --- a/arch/arm64/core/switch.S +++ b/arch/arm64/core/switch.S @@ -203,12 +203,7 @@ context_switch: ldp x0, x1, [sp, ___esf_t_x0_x1_OFFSET] /* Switch thread */ bl z_arm64_context_switch -#if defined(CONFIG_SOC_RK3568) && defined(CONFIG_NS16650_EARLYPRINT_DEBUG) && defined(RK3568_ASM_PRINTK) - stp x0, x1, [sp, #-16]! - mov x0, #0x215 - bl safe_print_debug - ldp x0, x1, [sp], #16 -#endif + b z_arm64_exit_exc inv: diff --git a/arch/arm64/core/vector_table.S b/arch/arm64/core/vector_table.S index 1fc87357c89e2fbe597c8c6de29be76733c1db5c..df872f76b6412ee2c58a269247b731a06461fb5d 100644 --- a/arch/arm64/core/vector_table.S +++ b/arch/arm64/core/vector_table.S @@ -220,13 +220,6 @@ GTEXT(z_arm64_exit_exc_fpu_done) z_arm64_exit_exc_fpu_done: #endif -#if defined(CONFIG_SOC_RK35681) && defined(CONFIG_NS16650_EARLYPRINT_DEBUG) && defined(RK3568_ASM_PRINTK) - stp x0, x1, [sp, #-16]! - mrs x0, elr_el1 - bl safe_print_debug - ldp x0, x1, [sp], #16 -#endif - ldp x0, x1, [sp, ___esf_t_spsr_elr_OFFSET] msr spsr_el1, x0 msr elr_el1, x1 diff --git a/arch/arm64/core/virtualization/arm.c b/arch/arm64/core/virtualization/arm.c index 930635448bc52c562131a07df4e5290eecdbdbd7..8918bd1ac876cc6088fe934c1057189572819ecd 100644 --- a/arch/arm64/core/virtualization/arm.c +++ b/arch/arm64/core/virtualization/arm.c @@ -241,7 +241,7 @@ int arch_vcpu_init(struct vcpu *vcpu) vcpu_arch->vcpu_sys_register_loaded = false; /* init vm_arch here */ - vm_arch->vtcr_el2 = (0x20 | BIT(6) | BIT(8) | BIT(10) | BIT(12) | BIT(13)); + vm_arch->vtcr_el2 = (0x20 | BIT(6) | BIT(8) | BIT(10) | BIT(12) | BIT(13) | BIT(31)); vm_arch->vttbr = (vcpu->vm->vmid | vm_arch->vm_pgd_base); arch_vcpu_common_regs_init(vcpu); @@ -274,6 +274,7 @@ int arch_vcpu_init(struct vcpu *vcpu) int zvm_arch_init(void *op) { + ARG_UNUSED(op); int ret = 0; /* Is hyp、vhe available? */ @@ -285,7 +286,7 @@ int zvm_arch_init(void *op) return -ENOVDEV; } - ret = zvm_arch_vtimer_init(op); + ret = zvm_arch_vtimer_init(); if(ret) { ZVM_LOG_ERR("Vtimer subsystem do not supported! \n"); return ret; diff --git a/arch/arm64/core/virtualization/hyp_entry.S b/arch/arm64/core/virtualization/hyp_entry.S index 0aade7e7af659dc92ef8e4b401ad34df8c9af688..6e76752832ca2b6034e56118eb65cfa99edec523 100644 --- a/arch/arm64/core/virtualization/hyp_entry.S +++ b/arch/arm64/core/virtualization/hyp_entry.S @@ -175,5 +175,6 @@ vm_isr_in_sync: ldp x25, x26, [x1, #_zvm_vcpu_ctxt_arch_regs_to_callee_saved_x25_x26] ldp x27, x28, [x1, #_zvm_vcpu_ctxt_arch_regs_to_callee_saved_x27_x28] + isb ldp x0, x1, [sp], #16 ret diff --git a/arch/arm64/core/virtualization/hyp_vector.S b/arch/arm64/core/virtualization/hyp_vector.S index 13e43f3fc86452efb9ad604627c4ab5757b6bb39..90ee36f258a3587b5e9e4877729f397356d11439 100644 --- a/arch/arm64/core/virtualization/hyp_vector.S +++ b/arch/arm64/core/virtualization/hyp_vector.S @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm64/core/virtualization/mm.c b/arch/arm64/core/virtualization/mm.c index b79173a22099c97db03196d8798ee5dc6ccc26e0..4cd7bef6432a4699aa00658545cf1c66fc5fc02e 100644 --- a/arch/arm64/core/virtualization/mm.c +++ b/arch/arm64/core/virtualization/mm.c @@ -63,7 +63,6 @@ static uint64_t get_vm_region_desc(uint32_t attrs) desc |= (attrs & MT_S2_ACCESS_OFF) ? 0 : S2_PTE_BLOCK_DESC_AF; mem_type = MT_S2_TYPE(attrs); - desc |= S2_PTE_BLOCK_DESC_MEMTYPE(mem_type); switch (mem_type) { case MT_S2_DEVICE_nGnRnE: @@ -73,16 +72,27 @@ static uint64_t get_vm_region_desc(uint32_t attrs) /* Map device memory as execute-never */ desc |= S2_PTE_BLOCK_DESC_PU_XN; break; + case MT_S2_NORMAL_WT: case MT_S2_NORMAL_NC: case MT_S2_NORMAL: /* Make Normal RW memory as execute */ - if ( (attrs & (MT_S2_R | MT_S2_W)) ) + if ( (attrs & (MT_S2_R | MT_S2_W)) ) { desc |= S2_PTE_BLOCK_DESC_NO_XN; + } - if (mem_type == MT_NORMAL) + if (mem_type == MT_NORMAL) { desc |= S2_PTE_BLOCK_DESC_INNER_SHARE; - else + } + else { desc |= S2_PTE_BLOCK_DESC_OUTER_SHARE; + } + /** + * When VM thread use atomic operation, stage-2 attributes must be + * Normal memory, Outer Write-Back Cacheable & Inner Write-Back + * Cacheable. + */ + desc |= (S2_PTE_BLOCK_DESC_O_WB_CACHE | S2_PTE_BLOCK_DESC_I_WB_CACHE); + break; } return desc; diff --git a/arch/arm64/core/virtualization/switch.c b/arch/arm64/core/virtualization/switch.c index a5a56a289d98c53801d2069f24b383134058b92a..c98df13753fb3ea5fb966722e4d87d37188d7de7 100644 --- a/arch/arm64/core/virtualization/switch.c +++ b/arch/arm64/core/virtualization/switch.c @@ -104,10 +104,28 @@ void get_zvm_host_context(void) ); } +static inline void print_list_register(void) +{ + ZVM_LOG_INFO("\n -------List register:------- \n"); + + if(read_sysreg(ICH_LR0_EL2)){ + ZVM_LOG_INFO("ICH_LR0_EL2: %08llx \n", read_sysreg(ICH_LR0_EL2)); + } + if(read_sysreg(ICH_LR1_EL2)){ + ZVM_LOG_INFO("ICH_LR1_EL2: %08llx \n", read_sysreg(ICH_LR1_EL2)); + } + if(read_sysreg(ICH_LR2_EL2)){ + ZVM_LOG_INFO("ICH_LR2_EL2: %08llx \n", read_sysreg(ICH_LR2_EL2)); + } + if(read_sysreg(ICH_LR3_EL2)){ + ZVM_LOG_INFO("ICH_LR3_EL2: %08llx \n", read_sysreg(ICH_LR3_EL2)); + } +} + int arch_vcpu_run(struct vcpu *vcpu) { int ret; - uint16_t exit_type; + uint16_t exit_type = 0; /* mask all interrupt here to disable interrupt */ vm_disable_daif(); diff --git a/arch/arm64/core/virtualization/sysreg.c b/arch/arm64/core/virtualization/sysreg.c index d4f0d5d6933bd860b923cd75a8e4f4f86c422de4..30b7078ca60f9f8aaf8f6c3bce953893ba4c75ab 100644 --- a/arch/arm64/core/virtualization/sysreg.c +++ b/arch/arm64/core/virtualization/sysreg.c @@ -92,12 +92,15 @@ void switch_to_guest_sysreg(struct vcpu *vcpu) /* load stage-2 pgd for vm */ write_vtcr_el2(vcpu->vm->arch->vtcr_el2); write_vttbr_el2(vcpu->vm->arch->vttbr); + isb(); /* enable hyperviosr trap */ write_hcr_el2(vcpu->arch->hcr_el2); reg_val = read_cpacr_el1(); + reg_val |= CPACR_EL1_TTA; reg_val &= ~CPACR_EL1_ZEN; - reg_val = (CPACR_EL1_TTA | CPTR_EL2_TAM | CPACR_EL1_FPEN_NOTRAP); + reg_val |= CPTR_EL2_TAM; + reg_val |= CPACR_EL1_FPEN_NOTRAP; write_cpacr_el1(reg_val); write_vbar_el2((uint64_t)_hyp_vector_table); @@ -111,7 +114,6 @@ void switch_to_guest_sysreg(struct vcpu *vcpu) reg_val &= ~(0x02); write_sysreg(reg_val, ICC_CTLR_EL1); - write_mdscr_el1(gcontext->sys_regs[VCPU_MDSCR_EL1]); } void switch_to_host_sysreg(struct vcpu *vcpu) @@ -130,8 +132,6 @@ void switch_to_host_sysreg(struct vcpu *vcpu) reg_val |= (0x02); write_sysreg(reg_val, ICC_CTLR_EL1); - gcontext->sys_regs[VCPU_MDSCR_EL1] = read_mdscr_el1(); - /* disable hyperviosr trap */ if (vcpu->arch->hcr_el2 & HCR_VSE_BIT) { vcpu->arch->hcr_el2 = read_hcr_el2(); @@ -142,6 +142,7 @@ void switch_to_host_sysreg(struct vcpu *vcpu) /* save vm's stage-2 pgd */ vcpu->vm->arch->vtcr_el2 = read_vtcr_el2(); vcpu->vm->arch->vttbr = read_vttbr_el2(); + isb(); /* load host context */ write_mdscr_el1(hcontext->sys_regs[VCPU_MDSCR_EL1]); diff --git a/arch/arm64/core/virtualization/trap_handler.c b/arch/arm64/core/virtualization/trap_handler.c index a638dd196469de4e408bacb55fe3d38fc61fcad0..825c19235a1917416410506cbd7db17d9276321f 100644 --- a/arch/arm64/core/virtualization/trap_handler.c +++ b/arch/arm64/core/virtualization/trap_handler.c @@ -51,7 +51,7 @@ static int handle_ftrans_desc(int iss_dfsc, uint64_t pa_addr, if(ret){ reg_value = find_index_reg(reg_index, regs); *reg_value = 0xfefefefefefefefe; - ZVM_LOG_INFO("VM's mem abort addr: 0x%llx ! \n", pa_addr); + ZVM_LOG_WARN("VM's mem abort addr: 0x%llx ! \n", pa_addr); /** * if the device is allocated, whether it can be emulated * by virtIO? @@ -73,7 +73,7 @@ static int handle_faccess_desc(int iss_dfsc, uint64_t pa_addr, uint64_t addr = pa_addr, *reg_value; iss_isv = dabt->isv; - + if (!iss_isv) { ZVM_LOG_WARN("Instruction syndrome not valid\n"); return -EFAULT; @@ -222,6 +222,8 @@ static int cpu_system_msr_mrs_sync(arch_commom_regs_t *arch_ctxt, uint64_t esr_e static int cpu_inst_abort_low_sync(arch_commom_regs_t *arch_ctxt, uint64_t esr_elx) { + uint64_t ipa_ddr; + ipa_ddr = get_fault_ipa(read_hpfar_el2(), read_far_el2()); ARG_UNUSED(arch_ctxt); ARG_UNUSED(esr_elx); return 0; diff --git a/arch/arm64/core/virtualization/vtimer.c b/arch/arm64/core/virtualization/vtimer.c index d34f3ab0a2c0ce0cddfd909905fb6c1bbd187cab..ed11689d38c5b7583aa2389c5e1c487767329b8a 100644 --- a/arch/arm64/core/virtualization/vtimer.c +++ b/arch/arm64/core/virtualization/vtimer.c @@ -288,10 +288,38 @@ int arch_vcpu_timer_init(struct vcpu *vcpu) return 0; } +static void zvm_virt_vtimer_init(void) +{ + uint64_t cntv_ctl; + + IRQ_CONNECT(ARM_ARCH_VIRT_VTIMER_IRQ, ARM_ARCH_VIRT_VTIMER_PRIO, + arm_arch_virt_vtimer_compare_isr, NULL, ARM_ARCH_VIRT_VTIMER_FLAGS); + /* disable vtimer for vm */ +#if defined(CONFIG_HAS_ARM_VHE_EXTN) + cntv_ctl = read_cntv_ctl_el02(); + cntv_ctl &= ~CNTV_CTL_ENABLE_BIT; + write_cntv_ctl_el02(cntv_ctl); +#endif +} + +static void zvm_virt_ptimer_init(void) +{ + uint64_t cntp_ctl; + + IRQ_CONNECT(ARM_ARCH_VIRT_PTIMER_IRQ, ARM_ARCH_VIRT_PTIMER_PRIO, + arm_arch_virt_ptimer_compare_isr, NULL, ARM_ARCH_VIRT_PTIMER_FLAGS); + /* disable ptimer for vm */ +#if defined(CONFIG_HAS_ARM_VHE_EXTN) + cntp_ctl = read_cntp_ctl_el02(); + cntp_ctl &= ~CNTP_CTL_ENABLE_BIT; + write_cntp_ctl_el02(cntp_ctl); +#endif +} + /** * @brief Get virtual timer irq number, it should be done when ZVM init. */ -int zvm_arch_vtimer_init() +int zvm_arch_vtimer_init(void) { /* get vtimer irq */ zvm_global_vtimer_info.virt_irq = ARM_ARCH_VIRT_VTIMER_IRQ; @@ -307,11 +335,8 @@ int zvm_arch_vtimer_init() return -EVIRQ; } - IRQ_CONNECT(ARM_ARCH_VIRT_VTIMER_IRQ, ARM_ARCH_VIRT_VTIMER_PRIO, - arm_arch_virt_vtimer_compare_isr, NULL, ARM_ARCH_VIRT_VTIMER_FLAGS); - - IRQ_CONNECT(ARM_ARCH_VIRT_PTIMER_IRQ, ARM_ARCH_VIRT_PTIMER_PRIO, - arm_arch_virt_ptimer_compare_isr, NULL, ARM_ARCH_VIRT_PTIMER_FLAGS); + zvm_virt_vtimer_init(); + zvm_virt_ptimer_init(); return 0; } diff --git a/auto_zvm.sh b/auto_zvm.sh index da05a9f41aa4dfb82ffcec058eb157d60a8bf0b4..14ae37f6a3364a40b968d802c891fceb9395288b 100755 --- a/auto_zvm.sh +++ b/auto_zvm.sh @@ -31,8 +31,8 @@ if [ "$OPS" = "$ops_build" ]; then -DARMFVP_BL1_FILE=$(pwd)/zvm_config/fvp_platform/hub/bl1.bin \ -DARMFVP_FIP_FILE=$(pwd)/zvm_config/fvp_platform/hub/fip.bin elif [ "$PLAT" = "$plat_rk3568" ]; then - west build -b roc_rk3568_pc samples/_zvm - cp build/zephyr/zvm_host.bin /home/xiong/tftp_server + west build -b roc_rk3568_pc_smp samples/_zvm + cp build/zephyr/zvm_host.bin ../../tftp_ser else echo "Error arguments for this auto.sh! \n Please input command like: ./auto_build.sh build qemu. " fi diff --git a/boards/arm64/qemu_cortex_max/qemu_cortex_max_defconfig b/boards/arm64/qemu_cortex_max/qemu_cortex_max_defconfig index 86f4f56747229270a28fd3e63db413eebceb7fca..bbe7535c80b71526f62753dba38b77f60129898d 100644 --- a/boards/arm64/qemu_cortex_max/qemu_cortex_max_defconfig +++ b/boards/arm64/qemu_cortex_max/qemu_cortex_max_defconfig @@ -3,16 +3,11 @@ CONFIG_BOARD_QEMU_CORTEX_MAX=y CONFIG_ARM_ARCH_TIMER=y CONFIG_QEMU_ICOUNT=n -CONFIG_ARMV8_A_NS=y CONFIG_CACHE_MANAGEMENT=y # Enable UART driver CONFIG_SERIAL=y -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - # Enable serial port CONFIG_UART_PL011=y CONFIG_UART_PL011_PORT0=y diff --git a/boards/arm64/qemu_cortex_max/qemu_cortex_max_smp_defconfig b/boards/arm64/qemu_cortex_max/qemu_cortex_max_smp_defconfig index 8730237ccc51be65ed7fce7bafd1b9f62c927777..93df268fc44aaab1b5038204e09bb005cf37b065 100644 --- a/boards/arm64/qemu_cortex_max/qemu_cortex_max_smp_defconfig +++ b/boards/arm64/qemu_cortex_max/qemu_cortex_max_smp_defconfig @@ -8,10 +8,10 @@ CONFIG_QEMU_ICOUNT=n # SMP support CONFIG_SMP=y +CONFIG_ARMV8_A_NS=y CONFIG_MP_NUM_CPUS=4 CONFIG_CACHE_MANAGEMENT=y CONFIG_TIMEOUT_64BIT=y -CONFIG_ARMV8_A_NS=y # PSCI is supported CONFIG_PM_CPU_OPS=y @@ -27,17 +27,3 @@ CONFIG_UART_PL011=y CONFIG_UART_PL011_PORT0=y #CONFIG_UART_PL011_PORT1=y CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Threads stacks -CONFIG_ISR_STACK_SIZE=16384 -CONFIG_IDLE_STACK_SIZE=8192 -CONFIG_MAIN_STACK_SIZE=8192 -CONFIG_SHELL_STACK_SIZE=65536 -CONFIG_THREAD_STACK_INFO=y - -# make more table for host's pgd -CONFIG_MAX_XLAT_TABLES=16 diff --git a/arch/arm64/core/rk3568/CMakeLists.txt b/boards/arm64/roc_rk3568_pc/CMakeLists.txt old mode 100755 new mode 100644 similarity index 33% rename from arch/arm64/core/rk3568/CMakeLists.txt rename to boards/arm64/roc_rk3568_pc/CMakeLists.txt index bbb88487db351693c6f753e4a48c2c441f39ba45..9881313609aae2c16a19dae665af4268bd54431d --- a/arch/arm64/core/rk3568/CMakeLists.txt +++ b/boards/arm64/roc_rk3568_pc/CMakeLists.txt @@ -1,9 +1 @@ # SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources( - debug_uart.c - debug_uart.S -) - diff --git a/boards/arm64/roc_rk3568_pc/Kconfig.board b/boards/arm64/roc_rk3568_pc/Kconfig.board index 22f5da5f2c5527f806939d8c2ab29ff0b534c1ac..97844de31fd4475e2be6923cbebd2e540a1a006d 100644 --- a/boards/arm64/roc_rk3568_pc/Kconfig.board +++ b/boards/arm64/roc_rk3568_pc/Kconfig.board @@ -1,17 +1,8 @@ -# Copyright 2021 HNU +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 config BOARD_ROC_RK3568_PC bool "Rockchip ROC-RK3568-PC" depends on SOC_SERIES_RK3568 - select SOC_PART_NUMBER_ROCRK3568PC select ARM64 - -config NS16650_EARLYPRINT_DEBUG - bool "RK3568's Early Print Function" - default n - depends on BOARD_ROC_RK3568_PC - help - For debug hardware system, there must be a early printk mechanism to - output the system info, which is usefull for development. In rk3568 - borads, this print function using ns16650 to debug hardware. diff --git a/boards/arm64/roc_rk3568_pc/Kconfig.defconfig b/boards/arm64/roc_rk3568_pc/Kconfig.defconfig index 4617c31e32c9993bd7d1bae84b6218a68a72a69d..9ad4f73bd2b02c8adfc007dbfc696d11250dfda1 100644 --- a/boards/arm64/roc_rk3568_pc/Kconfig.defconfig +++ b/boards/arm64/roc_rk3568_pc/Kconfig.defconfig @@ -1,4 +1,5 @@ -# Copyright 2020 HNU +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 if BOARD_ROC_RK3568_PC diff --git a/boards/arm64/roc_rk3568_pc/board.cmake b/boards/arm64/roc_rk3568_pc/board.cmake new file mode 100644 index 0000000000000000000000000000000000000000..9881313609aae2c16a19dae665af4268bd54431d --- /dev/null +++ b/boards/arm64/roc_rk3568_pc/board.cmake @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm64/roc_rk3568_pc/doc/index.rst b/boards/arm64/roc_rk3568_pc/doc/index.rst index 245d246fb3b27a0ef15da1e83f3fb10ae6b6b073..ae999409545d760d43e897915ab76a9f1a52ed0e 100644 --- a/boards/arm64/roc_rk3568_pc/doc/index.rst +++ b/boards/arm64/roc_rk3568_pc/doc/index.rst @@ -1,4 +1,142 @@ -# SPDX-License-Identifier: Apache-2.0 +.. _roc_rk3568_pc: +Firefly ROC-RK3568-PC (Quad-core Cortex-A55) +############################################ -This is RK3568 file for simple try! \ No newline at end of file +Overview +******** + +The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2 +and SATA3.0 interfaces enables expansion with large hard drives. +Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission. +Control Port can be connected with RS485/RS232 devices. + +RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture, +has frequency up to 2.0GHz. Zephyr OS is ported to run on it. + + +- Board features: + + - RAM: 4GB LPDDR4 + - Storage: + + - 32GB eMMC + - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD) + - TF-Card Slot + - Wireless: + + - Supports WiFi 6 (802.11 AX) + - Supports BT5.0 + - USB: + + - One USB 3.0 + - Two USB 2.0 + - One Type-C + - Ethernet + - M.2 PCIe3.0 (Expand with NVMe SSD) + - LEDs: + + - 1x Power status LED + - Debug + + - UART debug ports for board + + +Supported Features +================== + +The Zephyr roc_rk3568_pc board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 2.0 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2. + +Programming and Debugging +************************* + +Use U-Boot to load the zephyr.bin to the memory and kick it: + +.. code-block:: console + + tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3568_pc + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build bc695c6df5eb *** + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 0 on roc_rk3568_pc! + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 0 on roc_rk3568_pc! + + +roc_rk3568_pc_smp support, use this configuration to run Zephyr smp applications and subsys tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3568_pc_smp + :goals: run + +This will build an image with the shell_module sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build bc695c6df5eb *** + I/TC: Secondary CPU 1 initializing + I/TC: Secondary CPU 1 switching to normal world boot + I/TC: Secondary CPU 2 initializing + I/TC: Secondary CPU 2 switching to normal world boot + I/TC: Secondary CPU 3 initializing + I/TC: Secondary CPU 3 switching to normal world boot + Secondary CPU core 1 (MPID:0x100) is up + Secondary CPU core 2 (MPID:0x200) is up + Secondary CPU core 3 (MPID:0x300) is up + + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 1 on roc_rk3568_pc! + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 1 on roc_rk3568_pc! + +References +========== + +More information can refer to Firefly official website: +`Firefly website`_. + +.. _Firefly website: + https://en.t-firefly.com/product/industry/rocrk3568pc.html?theme=pc diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts index 883a93e76d09425382cf9f4aacc94728cd30936c..d90fbd9eb51cb08003a9fa7516c98da0c8b852d8 100644 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts +++ b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts @@ -1,24 +1,37 @@ /* - * Copyright 2022 HNU - * + * Copyright 2022 HNU-ESNL + * Copyright 2022 openEuler SIG-Zephyr * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; -#include +#include #include / { - model = "Rockchip ROCRK3568PC"; + model = "Firefly ROC-RK3568-PC"; compatible = "rockchip,rk3568"; + aliases { - serial2 = &uart0; + serial2 = &uart2; + }; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &sram0; }; + + sram0: memory@10000000 { + device_type = "memory"; + compatible = "mmio-sram"; + reg = <0x0 0x10000000 0x0 DT_SIZE_M(512)>; + }; + }; -/* debug */ -&uart0 { - status = "okay"; +&uart2 { + status = "okay"; current-speed = <1500000>; }; diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml index 69ab912688073d577a2241d93f2ba20f5cc61bcf..8414416b0064f655546fd86374574c8602284833 100644 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml +++ b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml @@ -1,12 +1,13 @@ identifier: roc_rk3568_pc -name: Rockchip roc rk3568 pc +name: Rockchip ROC RK3568 PC type: mcu arch: arm64 toolchain: - zephyr - cross-compile -ram: 256 +ram: 256 testing: + default: true ignore_tags: - net - bluetooth diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig index 8b0ca4d18a5ab50122a2bb9442f25404d21b2f6b..6d1d36ca6aa8f2fd46c185310c2eee698d5bae84 100644 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig +++ b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig @@ -1,29 +1,23 @@ +# Copyright 2021 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 # Platform Configuration CONFIG_SOC_SERIES_RK3568=y CONFIG_SOC_RK3568=y CONFIG_BOARD_ROC_RK3568_PC=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_CLOCK_CONTROL=y # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_NS16550=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_NS16650_EARLYPRINT_DEBUG=n -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# SMP support -CONFIG_SMP=y +# ARMv8 NS world with cache management CONFIG_ARMV8_A_NS=y -CONFIG_MP_NUM_CPUS=4 -CONFIG_TIMEOUT_64BIT=y CONFIG_CACHE_MANAGEMENT=y -CONFIG_PM=y -CONFIG_PM_CPU_OPS=y -CONFIG_PM_CPU_OPS_PSCI=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_CLOCK_CONTROL=y + +# SMP support +CONFIG_SMP=n diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts new file mode 100644 index 0000000000000000000000000000000000000000..41d10fb440279cdea7fe790e1b144949608c6c5e --- /dev/null +++ b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts @@ -0,0 +1,8 @@ +/* + * Copyright 2022 HNU-ESNL + * Copyright 2022 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "roc_rk3568_pc.dts" diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml new file mode 100644 index 0000000000000000000000000000000000000000..abc5dddabda43926e02f7825cb74e40c68f2ba1e --- /dev/null +++ b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml @@ -0,0 +1,15 @@ +identifier: roc_rk3568_pc_smp +name: Rockchip ROC RK3568 PC SMP +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..0f99d24cf0f7220f092fbc84b59fc49ac0c4c27d --- /dev/null +++ b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_SOC_SERIES_RK3568=y +CONFIG_SOC_RK3568=y +CONFIG_BOARD_ROC_RK3568_PC=y + +# SMP support +CONFIG_SMP=y +CONFIG_ARMV8_A_NS=y +CONFIG_MP_NUM_CPUS=4 +CONFIG_TIMEOUT_64BIT=y +CONFIG_CACHE_MANAGEMENT=y + +# PSCI is supported +CONFIG_PM=y +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y + +# Enable Timer and Sys clock +CONFIG_ARM_ARCH_TIMER=y +CONFIG_CLOCK_CONTROL=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +CONFIG_KERNEL_VM_SIZE=0x3200000 + +# System control register +CONFIG_SYSCON=y + +# clock controller +CONFIG_CLOCK_CONTROL_RK3568=y \ No newline at end of file diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index ec94e8072159cdc016c789f4ab72d0cbc77aa9c1..abb87947f7ee6624f08b133796cd92dd5b129e56 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -19,7 +19,8 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF clock_cont zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clock_calibration.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RCAR_CPG_MSSR clock_control_rcar_cpg_mssr.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c) -zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RK3568_CRU clock_control_rk3568_cru.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RK3568 clock_control_rk3568_cru.c + clock_control_rk3568_pmucru.c) if(CONFIG_CLOCK_CONTROL_STM32_CUBE) if(CONFIG_SOC_SERIES_STM32MP1X) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index b68d1f14e6c6d41d1639065e57d6d4ee51cc3f15..dac48095746d871101a124a9215d872aaadf2681 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -60,4 +60,6 @@ source "drivers/clock_control/Kconfig.rcar" source "drivers/clock_control/Kconfig.xec" +source "drivers/clock_control/Kconfig.rk3568" + endif # CLOCK_CONTROL diff --git a/drivers/clock_control/Kconfig.rk3568 b/drivers/clock_control/Kconfig.rk3568 new file mode 100644 index 0000000000000000000000000000000000000000..887078786db414a80075ca2f8d419358e279aea0 --- /dev/null +++ b/drivers/clock_control/Kconfig.rk3568 @@ -0,0 +1,7 @@ +# Copyright (c) 2023, HNU-ESNL +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_RK3568 + bool "RK3568 CLOCK CONTROLLER" + help + Enable support for rk3568 clock controller driver. diff --git a/drivers/clock_control/Kconfig.rk3568_cru b/drivers/clock_control/Kconfig.rk3568_cru deleted file mode 100644 index 3cc45d8ea12422534df6fd569e45c8480eea4648..0000000000000000000000000000000000000000 --- a/drivers/clock_control/Kconfig.rk3568_cru +++ /dev/null @@ -1,9 +0,0 @@ -# MCUXpresso SDK CRU - -# Copyright (c) 2017, HNU -# SPDX-License-Identifier: Apache-2.0 - -config CLOCK_CONTROL_RK3568_CRU - bool "RK3568 CRU driver" - help - Enable support for rk3568 cru driver. diff --git a/drivers/clock_control/clock_control_rk3568_cru.c b/drivers/clock_control/clock_control_rk3568_cru.c index 54f0889fc30fcc91affbf95931a2ba7e986d6707..3a6e1b322e59a6c280c95867bfbd54489f420acd 100644 --- a/drivers/clock_control/clock_control_rk3568_cru.c +++ b/drivers/clock_control/clock_control_rk3568_cru.c @@ -1,48 +1,60 @@ -// SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * Author: Elaine Zhang + * Copyright 2023 HNU-ESNL + * Copyright 2023 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 */ -//need edit -#define DT_DRV_COMPAT rockchip_rk3568_cru +//need edit not for vm system first. #include #include #include #include -#include -#include -#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL -#include -LOG_MODULE_REGISTER(clock_control); - +#include +#include +static int rk3568_cru_clk_init(const struct device *dev) +{ + dev->state->init_res = VM_DEVICE_INIT_RES; + return 0; +} -static int rk3568_clk_on(const struct device *dev, +static int rk3568_cru_clk_on(const struct device *dev, clock_control_subsys_t sub_system) { return 0; } -static int rk3568_clk_off(const struct device *dev, +static int rk3568_cru_clk_off(const struct device *dev, clock_control_subsys_t sub_system) { return 0; } -static int rk3568_clk_init(const struct device *dev) +static const struct clock_control_driver_api rk3568_cru_driver_api = { + .on = rk3568_cru_clk_on, + .off = rk3568_cru_clk_off, +}; + +static int vm_cru_init(const struct device *dev, struct vm *vm, struct virt_dev *vdev_desc) { return 0; } -static const struct clock_control_driver_api rk3568_clk_driver_api = { - .on = rk3568_clk_on, - .off = rk3568_clk_off, +static const struct virt_device_api virt_cru_api = { + .init_fn = vm_cru_init, + .device_driver_api = &rk3568_cru_driver_api, +}; + +static struct virt_device_config virt_cru_cfg = { + .reg_base = DT_REG_ADDR(DT_NODELABEL(cru)), + .reg_size = DT_REG_SIZE(DT_NODELABEL(cru)), + .hirq_num = VM_DEVICE_INVALID_VIRQ, }; -DEVICE_DT_INST_DEFINE(0, - &rk3568_clk_init, +DEVICE_DT_DEFINE(DT_NODELABEL(cru), + &rk3568_cru_clk_init, NULL, - NULL, NULL, + NULL, &virt_cru_cfg, PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, - &rk3568_clk_driver_api); + &virt_cru_api); diff --git a/drivers/clock_control/clock_control_rk3568_pmucru.c b/drivers/clock_control/clock_control_rk3568_pmucru.c new file mode 100644 index 0000000000000000000000000000000000000000..68c5e9d8bf2558df1497172ae4fc08d6230ff22d --- /dev/null +++ b/drivers/clock_control/clock_control_rk3568_pmucru.c @@ -0,0 +1,61 @@ +/* + * Copyright 2023 HNU-ESNL + * Copyright 2023 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ +//need edit not for vm system first. + +#include +#include +#include +#include +#include + +#include + +static int rk3568_pmucru_clk_init(const struct device *dev) +{ + dev->state->init_res = VM_DEVICE_INIT_RES; + return 0; +} + +static int rk3568_pmucru_clk_on(const struct device *dev, + clock_control_subsys_t sub_system) +{ + return 0; +} + +static int rk3568_pmucru_clk_off(const struct device *dev, + clock_control_subsys_t sub_system) +{ + return 0; +} + +static const struct clock_control_driver_api rk3568_pmucru_driver_api = { + .on = rk3568_pmucru_clk_on, + .off = rk3568_pmucru_clk_off, +}; + +static int vm_pmucru_init(const struct device *dev, struct vm *vm, struct virt_dev *vdev_desc) +{ + return 0; +} + +static const struct virt_device_api virt_pmucru_api = { + .init_fn = vm_pmucru_init, + .device_driver_api = &rk3568_pmucru_driver_api, +}; + +static struct virt_device_config virt_pmucru_cfg = { + .reg_base = DT_REG_ADDR(DT_NODELABEL(pmucru)), + .reg_size = DT_REG_SIZE(DT_NODELABEL(pmucru)), + .hirq_num = VM_DEVICE_INVALID_VIRQ, +}; + +DEVICE_DT_DEFINE(DT_NODELABEL(pmucru), + &rk3568_pmucru_clk_init, + NULL, + NULL, &virt_pmucru_cfg, + PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, + &virt_pmucru_api); diff --git a/drivers/interrupt_controller/intc_gicv3.c b/drivers/interrupt_controller/intc_gicv3.c index 46e7e8732d8df07ce45e8a1d23a4645c51f211bc..05b44d061a02fe11bfa86062354114acc7e8c80f 100644 --- a/drivers/interrupt_controller/intc_gicv3.c +++ b/drivers/interrupt_controller/intc_gicv3.c @@ -10,7 +10,6 @@ #include #include "intc_gic_common_priv.h" #include "intc_gicv3_priv.h" -#include #include @@ -174,6 +173,13 @@ void arm_gic_irq_enable(unsigned int intid) else sys_write64(vcpu->cpu << 8, IROUTER(GET_DIST_BASE(intid), intid)); } +#elif defined(CONFIG_ZVM) && defined(CONFIG_SOC_RK3568) + struct vcpu *vcpu = _current_vcpu; + if(vcpu == NULL){ + sys_write64(0x00000000, IROUTER(GET_DIST_BASE(intid), intid)); + }else{ + sys_write64(vcpu->cpu << 8, IROUTER(GET_DIST_BASE(intid), intid)); + } #elif defined(CONFIG_ZVM) struct vcpu *vcpu = _current_vcpu; if(vcpu == NULL){ @@ -271,7 +277,7 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, /** * In this stage, we call all the cpu except itself @TODO try to figure out why the * affx cannot work well , I guess it may need to find the differece affx mechanism - * between qemu and fvp. + * between qemu and fvp. When enable affx for cpu, system can not boot up! */ sgi_val |= BIT(40); write_sysreg(sgi_val, ICC_SGI1R); @@ -494,7 +500,11 @@ static void __arm_gic_init(void) uint8_t cpu; cpu = arch_curr_cpu()->id; +#if defined(CONFIG_SOC_RK3568) + gic_rdists[cpu] = GIC_RDIST_BASE + (MPIDR_TO_CORE(GET_MPIDR())>>8) * 0x20000; +#else gic_rdists[cpu] = GIC_RDIST_BASE + MPIDR_TO_CORE(GET_MPIDR()) * 0x20000; +#endif #ifdef CONFIG_GIC_V3_ITS /* Enable LPIs in Redistributor */ diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c index 005f900165425dcb57661aff1435eb71caf43bb8..b70dcddc60c72adbab2bd75590cec6ffff9c8c4f 100644 --- a/drivers/serial/uart_ns16550.c +++ b/drivers/serial/uart_ns16550.c @@ -39,8 +39,6 @@ #include "uart_ns16550.h" -#include - #define INST_HAS_PCP_HELPER(inst) DT_INST_NODE_HAS_PROP(inst, pcp) || #define INST_HAS_DLF_HELPER(inst) DT_INST_NODE_HAS_PROP(inst, dlf) || #define INST_HAS_REG_SHIFT_HELPER(inst) \ diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 770f165d2b0b2fc5b414e331df7e148a301faff3..f6c9e2e28183cf34c12390f05f981539ffa64d01 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -546,69 +546,6 @@ static void pl011_irq_config_func_1(const struct device *dev) #endif /* CONFIG_UART_PL011_PORT1 */ -#ifdef CONFIG_UART_PL011_PORT2 - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN -static void pl011_irq_config_func_2(const struct device *dev); -#endif - -static struct uart_device_config pl011_cfg_port_2 = { - .base = (uint8_t *)DT_INST_REG_ADDR(2), - .sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency), -#ifdef CONFIG_UART_INTERRUPT_DRIVEN - .irq_config_func = pl011_irq_config_func_2, -#endif -}; - -static struct pl011_data pl011_data_port_2 = { - .baud_rate = DT_INST_PROP(2, current_speed), -}; - -DEVICE_DT_INST_DEFINE(2, - &pl011_init, - NULL, - &pl011_data_port_2, - &pl011_cfg_port_2, PRE_KERNEL_1, - CONFIG_SERIAL_INIT_PRIORITY, - &pl011_driver_api); - -#ifdef CONFIG_UART_INTERRUPT_DRIVEN -static void pl011_irq_config_func_2(const struct device *dev) -{ -#if DT_NUM_IRQS(DT_INST(2, arm_pl011)) == 1 - IRQ_CONNECT(DT_INST_IRQN(2), - DT_INST_IRQ(2, priority), - pl011_isr, - DEVICE_DT_INST_GET(2), - 0); - irq_enable(DT_INST_IRQN(2)); -#else - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(2, tx, irq), - DT_INST_IRQ_BY_NAME(2, tx, priority), - pl011_isr, - DEVICE_DT_INST_GET(2), - 0); - irq_enable(DT_INST_IRQ_BY_NAME(2, tx, irq)); - - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(2, rx, irq), - DT_INST_IRQ_BY_NAME(2, rx, priority), - pl011_isr, - DEVICE_DT_INST_GET(2), - 0); - irq_enable(DT_INST_IRQ_BY_NAME(2, rx, irq)); - - IRQ_CONNECT(DT_INST_IRQ_BY_NAME(2, rxtim, irq), - DT_INST_IRQ_BY_NAME(2, rxtim, priority), - pl011_isr, - DEVICE_DT_INST_GET(2), - 0); - irq_enable(DT_INST_IRQ_BY_NAME(2, rxtim, irq)); -#endif -} -#endif - -#endif /* CONFIG_UART_PL011_PORT2 */ - #ifdef CONFIG_UART_PL011_SBSA #undef DT_DRV_COMPAT diff --git a/drivers/syscon/CMakeLists.txt b/drivers/syscon/CMakeLists.txt index 00e3b8ab7b2287dd9c5b85160eec92185614ea0a..70ceba9390673917e928dc4300149d5dea430ff5 100644 --- a/drivers/syscon/CMakeLists.txt +++ b/drivers/syscon/CMakeLists.txt @@ -2,3 +2,4 @@ zephyr_library() zephyr_library_sources_ifdef(CONFIG_SYSCON syscon.c) +zephyr_library_sources_ifdef(CONFIG_RK3568_SYSCON rk3568_syscon.c) diff --git a/drivers/syscon/Kconfig b/drivers/syscon/Kconfig index 573f27811646bf38c0be01e68b8da67089e8697d..4cd9db426da2f004520f2c6436b57fb84c44ebcc 100644 --- a/drivers/syscon/Kconfig +++ b/drivers/syscon/Kconfig @@ -40,3 +40,8 @@ config SYSCON_INIT_PRIORITY value endif # SYSCON + +config RK3568_SYSCON + bool "RK3568 SYSCON driver" + help + Enable RK3568 generic SYSCON (System Controller) driver diff --git a/drivers/syscon/rk3568_syscon.c b/drivers/syscon/rk3568_syscon.c new file mode 100644 index 0000000000000000000000000000000000000000..c58aace728cf8fb3f2ff68fe7e84257c42a246d5 --- /dev/null +++ b/drivers/syscon/rk3568_syscon.c @@ -0,0 +1,33 @@ +/* + * Copyright 2023 HNU-ESNL + * Copyright 2023 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +#define DT_DRV_COMPAT syscon + +void rk3568_syscon_generic_init(const struct device *dev) +{ + /*Set flag as the idle device which can bind to vm */ + dev->state->init_res = VM_DEVICE_INIT_RES; +} + +#define SYSCON_INIT(inst) \ + static const struct virt_device_config virt_syscon_generic_config_##inst = { \ + .reg_base = DT_INST_REG_ADDR(inst), \ + .reg_size = DT_INST_REG_SIZE(inst), \ + .hirq_num = VM_DEVICE_INVALID_VIRQ, \ + }; \ \ + DEVICE_DT_INST_DEFINE(inst, rk3568_syscon_generic_init, NULL, NULL, \ + &virt_syscon_generic_config_##inst, PRE_KERNEL_1, \ + CONFIG_SYSCON_INIT_PRIORITY, NULL); + +DT_INST_FOREACH_STATUS_OKAY(SYSCON_INIT); diff --git a/drivers/syscon/syscon.c b/drivers/syscon/syscon.c index 5a0ccee586296b06e75d0ad01eed2969b37e184b..b68d8ba4280472fd470ac3ab48c5d6917dc4bdeb 100644 --- a/drivers/syscon/syscon.c +++ b/drivers/syscon/syscon.c @@ -11,7 +11,7 @@ #include #include - +#include #include "syscon_common.h" struct syscon_generic_config { @@ -24,6 +24,16 @@ struct syscon_generic_data { size_t size; }; +static int syscon_generic_init(const struct device *dev) +{ + DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); +#ifdef CONFIG_SOC_RK3568 + /*Set flag as the idle device which can bind to vm */ + dev->state->init_res = VM_DEVICE_INIT_RES; +#endif + return 0; +} + static int syscon_generic_get_base(const struct device *dev, uintptr_t *addr) { if (!dev) { @@ -125,23 +135,27 @@ static const struct syscon_driver_api syscon_generic_driver_api = { .get_size = syscon_generic_get_size, }; -static int syscon_generic_init(const struct device *dev) +static int vm_syscon_init(const struct device *dev, struct vm *vm, struct virt_dev *vdev_desc) { - DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE); - return 0; } -#define SYSCON_INIT(inst) \ - static const struct syscon_generic_config syscon_generic_config_##inst = { \ - DEVICE_MMIO_ROM_INIT(DT_DRV_INST(inst)), \ - .reg_width = DT_INST_PROP_OR(inst, reg_io_width, 4), \ - }; \ - static struct syscon_generic_data syscon_generic_data_##inst = { \ +static const struct virt_device_api virt_syscon_api = { + .init_fn = vm_syscon_init, + .device_driver_api = &syscon_generic_driver_api, +}; + +#define SYSCON_INIT(inst) \ + static const struct virt_device_config syscon_generic_config_##inst = { \ + .reg_base = DT_INST_REG_ADDR(inst), \ + .reg_size = DT_INST_REG_SIZE(inst), \ + .hirq_num = VM_DEVICE_INVALID_VIRQ, \ + }; \ + static struct syscon_generic_data syscon_generic_data_##inst = { \ .size = DT_INST_REG_SIZE(inst), \ - }; \ - DEVICE_DT_INST_DEFINE(inst, syscon_generic_init, NULL, &syscon_generic_data_##inst, \ + }; \ + DEVICE_DT_INST_DEFINE(inst, syscon_generic_init, NULL, &syscon_generic_data_##inst, \ &syscon_generic_config_##inst, PRE_KERNEL_1, \ - CONFIG_SYSCON_INIT_PRIORITY, &syscon_generic_driver_api); + CONFIG_SYSCON_INIT_PRIORITY, &virt_syscon_api); DT_INST_FOREACH_STATUS_OKAY(SYSCON_INIT); diff --git a/drivers/timer/arm_arch_timer.c b/drivers/timer/arm_arch_timer.c index ff9876325475e2338082e1a04457f89d663167d0..233da8a54ebcc60e9d758d89f31a085b0a92cd0d 100644 --- a/drivers/timer/arm_arch_timer.c +++ b/drivers/timer/arm_arch_timer.c @@ -9,7 +9,6 @@ #include #include #include -#include #ifdef CONFIG_ZVM #include diff --git a/dts/arm64/rockchip/rk3568.dtsi b/dts/arm64/rockchip/rk3568.dtsi index 89ab1cfdae3df9d06c37d01a372dbc87d8b813bb..07643a5b5f6cee9138ef201df334692b7f27404d 100644 --- a/dts/arm64/rockchip/rk3568.dtsi +++ b/dts/arm64/rockchip/rk3568.dtsi @@ -1,5 +1,7 @@ /* * Copyright 2020 NXP + * Copyright 2022 HNU-ESNL + * Copyright 2022 openEuler SIG-Zephyr * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,7 +10,6 @@ #include #include - / { #address-cells = <2>; #size-cells = <2>; @@ -16,47 +17,59 @@ compatible = "rockchip,rk3568"; interrupt-parent = <&gic>; - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram; - }; - cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; - cpu0: cpu@0 { + cpu@000 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; - reg = <0x0 0x0>; + reg = <0x000>; }; - cpu1: cpu@1 { + cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; - reg = <0x0 0x1>; + reg = <0x100>; }; - cpu2: cpu@2 { + cpu@200 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; - reg = <0x0 0x2>; + reg = <0x200>; + }; - cpu3: cpu@3 { + cpu@300 { device_type = "cpu"; compatible = "arm,cortex-a55"; enable-method = "psci"; - reg = <0x0 0x3>; + reg = <0x300>; }; }; + gic: interrupt-controller@fd400000 { + #address-cells = <1>; + compatible = "arm,gic-v3","arm,gic"; + #interrupt-cells = <4>; + interrupt-controller; + + reg = <0x0 0xfd400000 0x0 0x10000>, /* GICD */ + <0x0 0xfd460000 0x0 0xc0000>; /* GICR */ + status = "okay"; + label = "GIC"; + }; + + psci { + compatible = "arm,psci-0.2", "arm,psci"; + method = "smc"; + label = "PSCI"; + }; - arch_timer: timer { + timer { compatible = "arm,armv8-timer"; interrupts = , , @@ -66,36 +79,53 @@ label = "arch_timer"; }; - gic: interrupt-controller@fd400000 { - compatible = "arm,gic"; - #interrupt-cells = <4>; - interrupt-controller; + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf","syscon", "simple-mfd"; + reg = <0x00 0xfdc20000 0x00 0x10000>; + label = "PMUGRF"; + status = "okay"; + }; - reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ - <0x0 0xfd460000 0 0xc0000>; /* GICR */ + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf","syscon","simple-mfd"; + reg = <0x00 0xfdc60000 0x00 0x10000>; + label = "GRF"; status = "okay"; - label = "GIC"; }; - psci { - compatible = "arm,psci-0.2", "arm,psci"; - method = "smc"; - label = "PSCI"; + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x00 0xfdd00000 0x00 0x1000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + status = "okay"; + label = "PMUCRU"; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x00 0xfdd20000 0x00 0x1000>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + status = "okay"; + label = "CRU"; }; - sram: sram@10000000 { - compatible = "mmio-sram"; - reg = <0x0 0x10000000 0x0 DT_SIZE_M(64)>; + uartclk: apb-pclk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + #clock-cells = <0>; }; - uart0: serial@fe660000 { + /* uart2 in the rk3568 */ + uart2: serial@fe670000 { compatible = "rockchip,rk3568-uart", "ns16550"; - reg = <0x0 0xfe660000 0x0 0x10000>; - interrupts = ; - clock-frequency = <24000000>; + reg = <0x0 0xfe670000 0x0 0x10000>; + interrupts = ; + clock-frequency = <12000000>; reg-shift = <2>; - label = "UART0"; status = "disabled"; + label = "UART2"; }; }; diff --git a/dts/bindings/clock/rockchip,rk3568-pmucru.yaml b/dts/bindings/clock/rockchip,rk3568-pmucru.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3a6083e65f8dd9f9a3d9befb4d4c461c2ce8a685 --- /dev/null +++ b/dts/bindings/clock/rockchip,rk3568-pmucru.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2022, NXP +# SPDX-License-Identifier: Apache-2.0 + + +description: | + The RK3568 clock controller generates the clock and also implements a + reset controller for SoC peripherals(PMU). + +compatible: "rockchip,rk3568-pmucru" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 1 + + "#reset-cells": + type: int + const: 1 + required: true + +clock-cells: + - name diff --git a/include/arch/arm64/asm_inline_gcc.h b/include/arch/arm64/asm_inline_gcc.h index 5d9ddc9458ac480918205a6ff7124967e42da78b..47b2dc4deadb6888572c55816bb433809886bbdc 100644 --- a/include/arch/arm64/asm_inline_gcc.h +++ b/include/arch/arm64/asm_inline_gcc.h @@ -19,8 +19,6 @@ #include #include -#include - #ifdef __cplusplus extern "C" { #endif diff --git a/include/arch/arm64/cpu.h b/include/arch/arm64/cpu.h index a1cc5baae7c4a605d3cdb0d31df23f5e2f3a42e7..1057958ce38546cd43d21e76e435fcaa75abbae8 100644 --- a/include/arch/arm64/cpu.h +++ b/include/arch/arm64/cpu.h @@ -9,8 +9,6 @@ #include -#define RK3568_ASM_PRINTK 1 - #define DAIFSET_FIQ_BIT BIT(0) #define DAIFSET_IRQ_BIT BIT(1) #define DAIFSET_ABT_BIT BIT(2) @@ -74,7 +72,7 @@ #define SCR_RES1 (BIT(4) | BIT(5)) /* MPIDR */ -#define MPIDR_AFFLVL_MASK (0xff) +#define MPIDR_AFFLVL_MASK (0xffff) #define MPIDR_AFF0_SHIFT (0) #define MPIDR_AFF1_SHIFT (8) @@ -86,7 +84,7 @@ #define GET_MPIDR() read_sysreg(mpidr_el1) -#if defined(CONFIG_SOC_FVP_BASE_A55X4_A75X2) || defined(CONFIG_SOC_RK3568) +#if defined(CONFIG_SOC_FVP_BASE_A55X4_A75X2) #define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 1) #else #define MPIDR_TO_CORE(mpidr) MPIDR_AFFLVL(mpidr, 0) diff --git a/include/arch/arm64/debug_uart.h b/include/arch/arm64/debug_uart.h deleted file mode 100644 index 9d3c03cb6c3f150b7c0ca6eb3a2e9a4bcceb8d20..0000000000000000000000000000000000000000 --- a/include/arch/arm64/debug_uart.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2021-2022 HNU - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef __DEBUG_UART_H__ -#define __DEBUG_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#ifndef _ASMLANGUAGE - -int save_boot_params(void); - -int tpl_main(void); - -void printascii(const char *str); - -void early_print_debug(unsigned long long reg, unsigned long long reg2); -void asm_register_print_smp(unsigned long long reg0, unsigned long long reg1); - -void show_print_debug_delay(void); - -int debug_earlyprint(const char *fmt, ...); - -#endif /* _ASMLANGUAGE */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/include/device.h b/include/device.h index db281421d7d229fa776fa35cae9b6d0513022817..cf56d507f3902524ccc1f2d3641c1deea2776b24 100644 --- a/include/device.h +++ b/include/device.h @@ -69,7 +69,7 @@ typedef int16_t device_handle_t; /** @brief Flag value used to identify an unknown device. */ #define DEVICE_HANDLE_NULL 0 -#define Z_DEVICE_MAX_NAME_LEN 48 +#define Z_DEVICE_MAX_NAME_LEN 96 /** * @def DEVICE_NAME_GET diff --git a/include/dt-bindings/clock/rk3568-cru.h b/include/dt-bindings/clock/rk3568-cru.h deleted file mode 100644 index aecfdd4ce0841b276f03515dbdc446703ca92f00..0000000000000000000000000000000000000000 --- a/include/dt-bindings/clock/rk3568-cru.h +++ /dev/null @@ -1,932 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Rockchip Electronics Co. Ltd. - * Author: Elaine Zhang - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H - -/* pmucru-clocks indices */ - -/* pmucru plls */ -#define PLL_PPLL 1 -#define PLL_HPLL 2 - -/* pmucru clocks */ -#define XIN_OSC0_DIV 4 -#define CLK_RTC_32K 5 -#define CLK_PMU 6 -#define CLK_I2C0 7 -#define CLK_RTC32K_FRAC 8 -#define CLK_UART0_DIV 9 -#define CLK_UART0_FRAC 10 -#define SCLK_UART0 11 -#define DBCLK_GPIO0 12 -#define CLK_PWM0 13 -#define CLK_CAPTURE_PWM0_NDFT 14 -#define CLK_PMUPVTM 15 -#define CLK_CORE_PMUPVTM 16 -#define CLK_REF24M 17 -#define XIN_OSC0_USBPHY0_G 18 -#define CLK_USBPHY0_REF 19 -#define XIN_OSC0_USBPHY1_G 20 -#define CLK_USBPHY1_REF 21 -#define XIN_OSC0_MIPIDSIPHY0_G 22 -#define CLK_MIPIDSIPHY0_REF 23 -#define XIN_OSC0_MIPIDSIPHY1_G 24 -#define CLK_MIPIDSIPHY1_REF 25 -#define CLK_WIFI_DIV 26 -#define CLK_WIFI_OSC0 27 -#define CLK_WIFI 28 -#define CLK_PCIEPHY0_DIV 29 -#define CLK_PCIEPHY0_OSC0 30 -#define CLK_PCIEPHY0_REF 31 -#define CLK_PCIEPHY1_DIV 32 -#define CLK_PCIEPHY1_OSC0 33 -#define CLK_PCIEPHY1_REF 34 -#define CLK_PCIEPHY2_DIV 35 -#define CLK_PCIEPHY2_OSC0 36 -#define CLK_PCIEPHY2_REF 37 -#define CLK_PCIE30PHY_REF_M 38 -#define CLK_PCIE30PHY_REF_N 39 -#define CLK_HDMI_REF 40 -#define XIN_OSC0_EDPPHY_G 41 -#define PCLK_PDPMU 42 -#define PCLK_PMU 43 -#define PCLK_UART0 44 -#define PCLK_I2C0 45 -#define PCLK_GPIO0 46 -#define PCLK_PMUPVTM 47 -#define PCLK_PWM0 48 -#define CLK_PDPMU 49 -#define SCLK_32K_IOE 50 - -#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) - -/* cru-clocks indices */ - -/* cru plls */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define PLL_VPLL 5 -#define PLL_NPLL 6 - -/* cru clocks */ -#define CPLL_333M 9 -#define ARMCLK 10 -#define USB480M 11 -#define ACLK_CORE_NIU2BUS 18 -#define CLK_CORE_PVTM 19 -#define CLK_CORE_PVTM_CORE 20 -#define CLK_CORE_PVTPLL 21 -#define CLK_GPU_SRC 22 -#define CLK_GPU_PRE_NDFT 23 -#define CLK_GPU_PRE_MUX 24 -#define ACLK_GPU_PRE 25 -#define PCLK_GPU_PRE 26 -#define CLK_GPU 27 -#define CLK_GPU_NP5 28 -#define PCLK_GPU_PVTM 29 -#define CLK_GPU_PVTM 30 -#define CLK_GPU_PVTM_CORE 31 -#define CLK_GPU_PVTPLL 32 -#define CLK_NPU_SRC 33 -#define CLK_NPU_PRE_NDFT 34 -#define CLK_NPU 35 -#define CLK_NPU_NP5 36 -#define HCLK_NPU_PRE 37 -#define PCLK_NPU_PRE 38 -#define ACLK_NPU_PRE 39 -#define ACLK_NPU 40 -#define HCLK_NPU 41 -#define PCLK_NPU_PVTM 42 -#define CLK_NPU_PVTM 43 -#define CLK_NPU_PVTM_CORE 44 -#define CLK_NPU_PVTPLL 45 -#define CLK_DDRPHY1X_SRC 46 -#define CLK_DDRPHY1X_HWFFC_SRC 47 -#define CLK_DDR1X 48 -#define CLK_MSCH 49 -#define CLK24_DDRMON 50 -#define ACLK_GIC_AUDIO 51 -#define HCLK_GIC_AUDIO 52 -#define HCLK_SDMMC_BUFFER 53 -#define DCLK_SDMMC_BUFFER 54 -#define ACLK_GIC600 55 -#define ACLK_SPINLOCK 56 -#define HCLK_I2S0_8CH 57 -#define HCLK_I2S1_8CH 58 -#define HCLK_I2S2_2CH 59 -#define HCLK_I2S3_2CH 60 -#define CLK_I2S0_8CH_TX_SRC 61 -#define CLK_I2S0_8CH_TX_FRAC 62 -#define MCLK_I2S0_8CH_TX 63 -#define I2S0_MCLKOUT_TX 64 -#define CLK_I2S0_8CH_RX_SRC 65 -#define CLK_I2S0_8CH_RX_FRAC 66 -#define MCLK_I2S0_8CH_RX 67 -#define I2S0_MCLKOUT_RX 68 -#define CLK_I2S1_8CH_TX_SRC 69 -#define CLK_I2S1_8CH_TX_FRAC 70 -#define MCLK_I2S1_8CH_TX 71 -#define I2S1_MCLKOUT_TX 72 -#define CLK_I2S1_8CH_RX_SRC 73 -#define CLK_I2S1_8CH_RX_FRAC 74 -#define MCLK_I2S1_8CH_RX 75 -#define I2S1_MCLKOUT_RX 76 -#define CLK_I2S2_2CH_SRC 77 -#define CLK_I2S2_2CH_FRAC 78 -#define MCLK_I2S2_2CH 79 -#define I2S2_MCLKOUT 80 -#define CLK_I2S3_2CH_TX_SRC 81 -#define CLK_I2S3_2CH_TX_FRAC 82 -#define MCLK_I2S3_2CH_TX 83 -#define I2S3_MCLKOUT_TX 84 -#define CLK_I2S3_2CH_RX_SRC 85 -#define CLK_I2S3_2CH_RX_FRAC 86 -#define MCLK_I2S3_2CH_RX 87 -#define I2S3_MCLKOUT_RX 88 -#define HCLK_PDM 89 -#define MCLK_PDM 90 -#define HCLK_VAD 91 -#define HCLK_SPDIF_8CH 92 -#define MCLK_SPDIF_8CH_SRC 93 -#define MCLK_SPDIF_8CH_FRAC 94 -#define MCLK_SPDIF_8CH 95 -#define HCLK_AUDPWM 96 -#define SCLK_AUDPWM_SRC 97 -#define SCLK_AUDPWM_FRAC 98 -#define SCLK_AUDPWM 99 -#define HCLK_ACDCDIG 100 -#define CLK_ACDCDIG_I2C 101 -#define CLK_ACDCDIG_DAC 102 -#define CLK_ACDCDIG_ADC 103 -#define ACLK_SECURE_FLASH 104 -#define HCLK_SECURE_FLASH 105 -#define ACLK_CRYPTO_NS 106 -#define HCLK_CRYPTO_NS 107 -#define CLK_CRYPTO_NS_CORE 108 -#define CLK_CRYPTO_NS_PKA 109 -#define CLK_CRYPTO_NS_RNG 110 -#define HCLK_TRNG_NS 111 -#define CLK_TRNG_NS 112 -#define PCLK_OTPC_NS 113 -#define CLK_OTPC_NS_SBPI 114 -#define CLK_OTPC_NS_USR 115 -#define HCLK_NANDC 116 -#define NCLK_NANDC 117 -#define HCLK_SFC 118 -#define HCLK_SFC_XIP 119 -#define SCLK_SFC 120 -#define ACLK_EMMC 121 -#define HCLK_EMMC 122 -#define BCLK_EMMC 123 -#define CCLK_EMMC 124 -#define TCLK_EMMC 125 -#define ACLK_PIPE 126 -#define PCLK_PIPE 127 -#define PCLK_PIPE_GRF 128 -#define ACLK_PCIE20_MST 129 -#define ACLK_PCIE20_SLV 130 -#define ACLK_PCIE20_DBI 131 -#define PCLK_PCIE20 132 -#define CLK_PCIE20_AUX_NDFT 133 -#define CLK_PCIE20_AUX_DFT 134 -#define CLK_PCIE20_PIPE_DFT 135 -#define ACLK_PCIE30X1_MST 136 -#define ACLK_PCIE30X1_SLV 137 -#define ACLK_PCIE30X1_DBI 138 -#define PCLK_PCIE30X1 139 -#define CLK_PCIE30X1_AUX_NDFT 140 -#define CLK_PCIE30X1_AUX_DFT 141 -#define CLK_PCIE30X1_PIPE_DFT 142 -#define ACLK_PCIE30X2_MST 143 -#define ACLK_PCIE30X2_SLV 144 -#define ACLK_PCIE30X2_DBI 145 -#define PCLK_PCIE30X2 146 -#define CLK_PCIE30X2_AUX_NDFT 147 -#define CLK_PCIE30X2_AUX_DFT 148 -#define CLK_PCIE30X2_PIPE_DFT 149 -#define ACLK_SATA0 150 -#define CLK_SATA0_PMALIVE 151 -#define CLK_SATA0_RXOOB 152 -#define CLK_SATA0_PIPE_NDFT 153 -#define CLK_SATA0_PIPE_DFT 154 -#define ACLK_SATA1 155 -#define CLK_SATA1_PMALIVE 156 -#define CLK_SATA1_RXOOB 157 -#define CLK_SATA1_PIPE_NDFT 158 -#define CLK_SATA1_PIPE_DFT 159 -#define ACLK_SATA2 160 -#define CLK_SATA2_PMALIVE 161 -#define CLK_SATA2_RXOOB 162 -#define CLK_SATA2_PIPE_NDFT 163 -#define CLK_SATA2_PIPE_DFT 164 -#define ACLK_USB3OTG0 165 -#define CLK_USB3OTG0_REF 166 -#define CLK_USB3OTG0_SUSPEND 167 -#define ACLK_USB3OTG1 168 -#define CLK_USB3OTG1_REF 169 -#define CLK_USB3OTG1_SUSPEND 170 -#define CLK_XPCS_EEE 171 -#define PCLK_XPCS 172 -#define ACLK_PHP 173 -#define HCLK_PHP 174 -#define PCLK_PHP 175 -#define HCLK_SDMMC0 176 -#define CLK_SDMMC0 177 -#define HCLK_SDMMC1 178 -#define CLK_SDMMC1 179 -#define ACLK_GMAC0 180 -#define PCLK_GMAC0 181 -#define CLK_MAC0_2TOP 182 -#define CLK_MAC0_OUT 183 -#define CLK_MAC0_REFOUT 184 -#define CLK_GMAC0_PTP_REF 185 -#define ACLK_USB 186 -#define HCLK_USB 187 -#define PCLK_USB 188 -#define HCLK_USB2HOST0 189 -#define HCLK_USB2HOST0_ARB 190 -#define HCLK_USB2HOST1 191 -#define HCLK_USB2HOST1_ARB 192 -#define HCLK_SDMMC2 193 -#define CLK_SDMMC2 194 -#define ACLK_GMAC1 195 -#define PCLK_GMAC1 196 -#define CLK_MAC1_2TOP 197 -#define CLK_MAC1_OUT 198 -#define CLK_MAC1_REFOUT 199 -#define CLK_GMAC1_PTP_REF 200 -#define ACLK_PERIMID 201 -#define HCLK_PERIMID 202 -#define ACLK_VI 203 -#define HCLK_VI 204 -#define PCLK_VI 205 -#define ACLK_VICAP 206 -#define HCLK_VICAP 207 -#define DCLK_VICAP 208 -#define ICLK_VICAP_G 209 -#define ACLK_ISP 210 -#define HCLK_ISP 211 -#define CLK_ISP 212 -#define PCLK_CSI2HOST1 213 -#define CLK_CIF_OUT 214 -#define CLK_CAM0_OUT 215 -#define CLK_CAM1_OUT 216 -#define ACLK_VO 217 -#define HCLK_VO 218 -#define PCLK_VO 219 -#define ACLK_VOP_PRE 220 -#define ACLK_VOP 221 -#define HCLK_VOP 222 -#define DCLK_VOP0 223 -#define DCLK_VOP1 224 -#define DCLK_VOP2 225 -#define CLK_VOP_PWM 226 -#define ACLK_HDCP 227 -#define HCLK_HDCP 228 -#define PCLK_HDCP 229 -#define PCLK_HDMI_HOST 230 -#define CLK_HDMI_SFR 231 -#define PCLK_DSITX_0 232 -#define PCLK_DSITX_1 233 -#define PCLK_EDP_CTRL 234 -#define CLK_EDP_200M 235 -#define ACLK_VPU_PRE 236 -#define HCLK_VPU_PRE 237 -#define ACLK_VPU 238 -#define HCLK_VPU 239 -#define ACLK_RGA_PRE 240 -#define HCLK_RGA_PRE 241 -#define PCLK_RGA_PRE 242 -#define ACLK_RGA 243 -#define HCLK_RGA 244 -#define CLK_RGA_CORE 245 -#define ACLK_IEP 246 -#define HCLK_IEP 247 -#define CLK_IEP_CORE 248 -#define HCLK_EBC 249 -#define DCLK_EBC 250 -#define ACLK_JDEC 251 -#define HCLK_JDEC 252 -#define ACLK_JENC 253 -#define HCLK_JENC 254 -#define PCLK_EINK 255 -#define HCLK_EINK 256 -#define ACLK_RKVENC_PRE 257 -#define HCLK_RKVENC_PRE 258 -#define ACLK_RKVENC 259 -#define HCLK_RKVENC 260 -#define CLK_RKVENC_CORE 261 -#define ACLK_RKVDEC_PRE 262 -#define HCLK_RKVDEC_PRE 263 -#define ACLK_RKVDEC 264 -#define HCLK_RKVDEC 265 -#define CLK_RKVDEC_CA 266 -#define CLK_RKVDEC_CORE 267 -#define CLK_RKVDEC_HEVC_CA 268 -#define ACLK_BUS 269 -#define PCLK_BUS 270 -#define PCLK_TSADC 271 -#define CLK_TSADC_TSEN 272 -#define CLK_TSADC 273 -#define PCLK_SARADC 274 -#define CLK_SARADC 275 -#define PCLK_SCR 276 -#define PCLK_WDT_NS 277 -#define TCLK_WDT_NS 278 -#define ACLK_DMAC0 279 -#define ACLK_DMAC1 280 -#define ACLK_MCU 281 -#define PCLK_INTMUX 282 -#define PCLK_MAILBOX 283 -#define PCLK_UART1 284 -#define CLK_UART1_SRC 285 -#define CLK_UART1_FRAC 286 -#define SCLK_UART1 287 -#define PCLK_UART2 288 -#define CLK_UART2_SRC 289 -#define CLK_UART2_FRAC 290 -#define SCLK_UART2 291 -#define PCLK_UART3 292 -#define CLK_UART3_SRC 293 -#define CLK_UART3_FRAC 294 -#define SCLK_UART3 295 -#define PCLK_UART4 296 -#define CLK_UART4_SRC 297 -#define CLK_UART4_FRAC 298 -#define SCLK_UART4 299 -#define PCLK_UART5 300 -#define CLK_UART5_SRC 301 -#define CLK_UART5_FRAC 302 -#define SCLK_UART5 303 -#define PCLK_UART6 304 -#define CLK_UART6_SRC 305 -#define CLK_UART6_FRAC 306 -#define SCLK_UART6 307 -#define PCLK_UART7 308 -#define CLK_UART7_SRC 309 -#define CLK_UART7_FRAC 310 -#define SCLK_UART7 311 -#define PCLK_UART8 312 -#define CLK_UART8_SRC 313 -#define CLK_UART8_FRAC 314 -#define SCLK_UART8 315 -#define PCLK_UART9 316 -#define CLK_UART9_SRC 317 -#define CLK_UART9_FRAC 318 -#define SCLK_UART9 319 -#define PCLK_CAN0 320 -#define CLK_CAN0 321 -#define PCLK_CAN1 322 -#define CLK_CAN1 323 -#define PCLK_CAN2 324 -#define CLK_CAN2 325 -#define CLK_I2C 326 -#define PCLK_I2C1 327 -#define CLK_I2C1 328 -#define PCLK_I2C2 329 -#define CLK_I2C2 330 -#define PCLK_I2C3 331 -#define CLK_I2C3 332 -#define PCLK_I2C4 333 -#define CLK_I2C4 334 -#define PCLK_I2C5 335 -#define CLK_I2C5 336 -#define PCLK_SPI0 337 -#define CLK_SPI0 338 -#define PCLK_SPI1 339 -#define CLK_SPI1 340 -#define PCLK_SPI2 341 -#define CLK_SPI2 342 -#define PCLK_SPI3 343 -#define CLK_SPI3 344 -#define PCLK_PWM1 345 -#define CLK_PWM1 346 -#define CLK_PWM1_CAPTURE 347 -#define PCLK_PWM2 348 -#define CLK_PWM2 349 -#define CLK_PWM2_CAPTURE 350 -#define PCLK_PWM3 351 -#define CLK_PWM3 352 -#define CLK_PWM3_CAPTURE 353 -#define DBCLK_GPIO 354 -#define PCLK_GPIO1 355 -#define DBCLK_GPIO1 356 -#define PCLK_GPIO2 357 -#define DBCLK_GPIO2 358 -#define PCLK_GPIO3 359 -#define DBCLK_GPIO3 360 -#define PCLK_GPIO4 361 -#define DBCLK_GPIO4 362 -#define OCC_SCAN_CLK_GPIO 363 -#define PCLK_TIMER 364 -#define CLK_TIMER0 365 -#define CLK_TIMER1 366 -#define CLK_TIMER2 367 -#define CLK_TIMER3 368 -#define CLK_TIMER4 369 -#define CLK_TIMER5 370 -#define ACLK_TOP_HIGH 371 -#define ACLK_TOP_LOW 372 -#define HCLK_TOP 373 -#define PCLK_TOP 374 -#define PCLK_PCIE30PHY 375 -#define CLK_OPTC_ARB 376 -#define PCLK_MIPICSIPHY 377 -#define PCLK_MIPIDSIPHY0 378 -#define PCLK_MIPIDSIPHY1 379 -#define PCLK_PIPEPHY0 380 -#define PCLK_PIPEPHY1 381 -#define PCLK_PIPEPHY2 382 -#define PCLK_CPU_BOOST 383 -#define CLK_CPU_BOOST 384 -#define PCLK_OTPPHY 385 -#define SCLK_GMAC0 386 -#define SCLK_GMAC0_RGMII_SPEED 387 -#define SCLK_GMAC0_RMII_SPEED 388 -#define SCLK_GMAC0_RX_TX 389 -#define SCLK_GMAC1 390 -#define SCLK_GMAC1_RGMII_SPEED 391 -#define SCLK_GMAC1_RMII_SPEED 392 -#define SCLK_GMAC1_RX_TX 393 -#define SCLK_SDMMC0_DRV 394 -#define SCLK_SDMMC0_SAMPLE 395 -#define SCLK_SDMMC1_DRV 396 -#define SCLK_SDMMC1_SAMPLE 397 -#define SCLK_SDMMC2_DRV 398 -#define SCLK_SDMMC2_SAMPLE 399 -#define SCLK_EMMC_DRV 400 -#define SCLK_EMMC_SAMPLE 401 -#define PCLK_EDPPHY_GRF 402 -#define CLK_HDMI_CEC 403 -#define CLK_I2S0_8CH_TX 404 -#define CLK_I2S0_8CH_RX 405 -#define CLK_I2S1_8CH_TX 406 -#define CLK_I2S1_8CH_RX 407 -#define CLK_I2S2_2CH 408 -#define CLK_I2S3_2CH_TX 409 -#define CLK_I2S3_2CH_RX 410 -#define CPLL_500M 411 -#define CPLL_250M 412 -#define CPLL_125M 413 -#define CPLL_62P5M 414 -#define CPLL_50M 415 -#define CPLL_25M 416 -#define CPLL_100M 417 -#define SCLK_DDRCLK 418 -#define I2S1_MCLKOUT 419 -#define I2S3_MCLKOUT 420 -#define I2S1_MCLK_RX_IOE 421 -#define I2S1_MCLK_TX_IOE 422 -#define I2S2_MCLK_IOE 423 -#define I2S3_MCLK_IOE 424 - -#define PCLK_CORE_PVTM 450 - -#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) - -/* pmu soft-reset indices */ -/* pmucru_softrst_con0 */ -#define SRST_P_PDPMU_NIU 0 -#define SRST_P_PMUCRU 1 -#define SRST_P_PMUGRF 2 -#define SRST_P_I2C0 3 -#define SRST_I2C0 4 -#define SRST_P_UART0 5 -#define SRST_S_UART0 6 -#define SRST_P_PWM0 7 -#define SRST_PWM0 8 -#define SRST_P_GPIO0 9 -#define SRST_GPIO0 10 -#define SRST_P_PMUPVTM 11 -#define SRST_PMUPVTM 12 - -/* soft-reset indices */ - -/* cru_softrst_con0 */ -#define SRST_NCORERESET0 0 -#define SRST_NCORERESET1 1 -#define SRST_NCORERESET2 2 -#define SRST_NCORERESET3 3 -#define SRST_NCPUPORESET0 4 -#define SRST_NCPUPORESET1 5 -#define SRST_NCPUPORESET2 6 -#define SRST_NCPUPORESET3 7 -#define SRST_NSRESET 8 -#define SRST_NSPORESET 9 -#define SRST_NATRESET 10 -#define SRST_NGICRESET 11 -#define SRST_NPRESET 12 -#define SRST_NPERIPHRESET 13 - -/* cru_softrst_con1 */ -#define SRST_A_CORE_NIU2DDR 16 -#define SRST_A_CORE_NIU2BUS 17 -#define SRST_P_DBG_NIU 18 -#define SRST_P_DBG 19 -#define SRST_P_DBG_DAPLITE 20 -#define SRST_DAP 21 -#define SRST_A_ADB400_CORE2GIC 22 -#define SRST_A_ADB400_GIC2CORE 23 -#define SRST_P_CORE_GRF 24 -#define SRST_P_CORE_PVTM 25 -#define SRST_CORE_PVTM 26 -#define SRST_CORE_PVTPLL 27 - -/* cru_softrst_con2 */ -#define SRST_GPU 32 -#define SRST_A_GPU_NIU 33 -#define SRST_P_GPU_NIU 34 -#define SRST_P_GPU_PVTM 35 -#define SRST_GPU_PVTM 36 -#define SRST_GPU_PVTPLL 37 -#define SRST_A_NPU_NIU 40 -#define SRST_H_NPU_NIU 41 -#define SRST_P_NPU_NIU 42 -#define SRST_A_NPU 43 -#define SRST_H_NPU 44 -#define SRST_P_NPU_PVTM 45 -#define SRST_NPU_PVTM 46 -#define SRST_NPU_PVTPLL 47 - -/* cru_softrst_con3 */ -#define SRST_A_MSCH 51 -#define SRST_HWFFC_CTRL 52 -#define SRST_DDR_ALWAYSON 53 -#define SRST_A_DDRSPLIT 54 -#define SRST_DDRDFI_CTL 55 -#define SRST_A_DMA2DDR 57 - -/* cru_softrst_con4 */ -#define SRST_A_PERIMID_NIU 64 -#define SRST_H_PERIMID_NIU 65 -#define SRST_A_GIC_AUDIO_NIU 66 -#define SRST_H_GIC_AUDIO_NIU 67 -#define SRST_A_GIC600 68 -#define SRST_A_GIC600_DEBUG 69 -#define SRST_A_GICADB_CORE2GIC 70 -#define SRST_A_GICADB_GIC2CORE 71 -#define SRST_A_SPINLOCK 72 -#define SRST_H_SDMMC_BUFFER 73 -#define SRST_D_SDMMC_BUFFER 74 -#define SRST_H_I2S0_8CH 75 -#define SRST_H_I2S1_8CH 76 -#define SRST_H_I2S2_2CH 77 -#define SRST_H_I2S3_2CH 78 - -/* cru_softrst_con5 */ -#define SRST_M_I2S0_8CH_TX 80 -#define SRST_M_I2S0_8CH_RX 81 -#define SRST_M_I2S1_8CH_TX 82 -#define SRST_M_I2S1_8CH_RX 83 -#define SRST_M_I2S2_2CH 84 -#define SRST_M_I2S3_2CH_TX 85 -#define SRST_M_I2S3_2CH_RX 86 -#define SRST_H_PDM 87 -#define SRST_M_PDM 88 -#define SRST_H_VAD 89 -#define SRST_H_SPDIF_8CH 90 -#define SRST_M_SPDIF_8CH 91 -#define SRST_H_AUDPWM 92 -#define SRST_S_AUDPWM 93 -#define SRST_H_ACDCDIG 94 -#define SRST_ACDCDIG 95 - -/* cru_softrst_con6 */ -#define SRST_A_SECURE_FLASH_NIU 96 -#define SRST_H_SECURE_FLASH_NIU 97 -#define SRST_A_CRYPTO_NS 103 -#define SRST_H_CRYPTO_NS 104 -#define SRST_CRYPTO_NS_CORE 105 -#define SRST_CRYPTO_NS_PKA 106 -#define SRST_CRYPTO_NS_RNG 107 -#define SRST_H_TRNG_NS 108 -#define SRST_TRNG_NS 109 - -/* cru_softrst_con7 */ -#define SRST_H_NANDC 112 -#define SRST_N_NANDC 113 -#define SRST_H_SFC 114 -#define SRST_H_SFC_XIP 115 -#define SRST_S_SFC 116 -#define SRST_A_EMMC 117 -#define SRST_H_EMMC 118 -#define SRST_B_EMMC 119 -#define SRST_C_EMMC 120 -#define SRST_T_EMMC 121 - -/* cru_softrst_con8 */ -#define SRST_A_PIPE_NIU 128 -#define SRST_P_PIPE_NIU 130 -#define SRST_P_PIPE_GRF 133 -#define SRST_A_SATA0 134 -#define SRST_SATA0_PIPE 135 -#define SRST_SATA0_PMALIVE 136 -#define SRST_SATA0_RXOOB 137 -#define SRST_A_SATA1 138 -#define SRST_SATA1_PIPE 139 -#define SRST_SATA1_PMALIVE 140 -#define SRST_SATA1_RXOOB 141 - -/* cru_softrst_con9 */ -#define SRST_A_SATA2 144 -#define SRST_SATA2_PIPE 145 -#define SRST_SATA2_PMALIVE 146 -#define SRST_SATA2_RXOOB 147 -#define SRST_USB3OTG0 148 -#define SRST_USB3OTG1 149 -#define SRST_XPCS 150 -#define SRST_XPCS_TX_DIV10 151 -#define SRST_XPCS_RX_DIV10 152 -#define SRST_XPCS_XGXS_RX 153 - -/* cru_softrst_con10 */ -#define SRST_P_PCIE20 160 -#define SRST_PCIE20_POWERUP 161 -#define SRST_MSTR_ARESET_PCIE20 162 -#define SRST_SLV_ARESET_PCIE20 163 -#define SRST_DBI_ARESET_PCIE20 164 -#define SRST_BRESET_PCIE20 165 -#define SRST_PERST_PCIE20 166 -#define SRST_CORE_RST_PCIE20 167 -#define SRST_NSTICKY_RST_PCIE20 168 -#define SRST_STICKY_RST_PCIE20 169 -#define SRST_PWR_RST_PCIE20 170 - -/* cru_softrst_con11 */ -#define SRST_P_PCIE30X1 176 -#define SRST_PCIE30X1_POWERUP 177 -#define SRST_M_ARESET_PCIE30X1 178 -#define SRST_S_ARESET_PCIE30X1 179 -#define SRST_D_ARESET_PCIE30X1 180 -#define SRST_BRESET_PCIE30X1 181 -#define SRST_PERST_PCIE30X1 182 -#define SRST_CORE_RST_PCIE30X1 183 -#define SRST_NSTC_RST_PCIE30X1 184 -#define SRST_STC_RST_PCIE30X1 185 -#define SRST_PWR_RST_PCIE30X1 186 - -/* cru_softrst_con12 */ -#define SRST_P_PCIE30X2 192 -#define SRST_PCIE30X2_POWERUP 193 -#define SRST_M_ARESET_PCIE30X2 194 -#define SRST_S_ARESET_PCIE30X2 195 -#define SRST_D_ARESET_PCIE30X2 196 -#define SRST_BRESET_PCIE30X2 197 -#define SRST_PERST_PCIE30X2 198 -#define SRST_CORE_RST_PCIE30X2 199 -#define SRST_NSTC_RST_PCIE30X2 200 -#define SRST_STC_RST_PCIE30X2 201 -#define SRST_PWR_RST_PCIE30X2 202 - -/* cru_softrst_con13 */ -#define SRST_A_PHP_NIU 208 -#define SRST_H_PHP_NIU 209 -#define SRST_P_PHP_NIU 210 -#define SRST_H_SDMMC0 211 -#define SRST_SDMMC0 212 -#define SRST_H_SDMMC1 213 -#define SRST_SDMMC1 214 -#define SRST_A_GMAC0 215 -#define SRST_GMAC0_TIMESTAMP 216 - -/* cru_softrst_con14 */ -#define SRST_A_USB_NIU 224 -#define SRST_H_USB_NIU 225 -#define SRST_P_USB_NIU 226 -#define SRST_P_USB_GRF 227 -#define SRST_H_USB2HOST0 228 -#define SRST_H_USB2HOST0_ARB 229 -#define SRST_USB2HOST0_UTMI 230 -#define SRST_H_USB2HOST1 231 -#define SRST_H_USB2HOST1_ARB 232 -#define SRST_USB2HOST1_UTMI 233 -#define SRST_H_SDMMC2 234 -#define SRST_SDMMC2 235 -#define SRST_A_GMAC1 236 -#define SRST_GMAC1_TIMESTAMP 237 - -/* cru_softrst_con15 */ -#define SRST_A_VI_NIU 240 -#define SRST_H_VI_NIU 241 -#define SRST_P_VI_NIU 242 -#define SRST_A_VICAP 247 -#define SRST_H_VICAP 248 -#define SRST_D_VICAP 249 -#define SRST_I_VICAP 250 -#define SRST_P_VICAP 251 -#define SRST_H_ISP 252 -#define SRST_ISP 253 -#define SRST_P_CSI2HOST1 255 - -/* cru_softrst_con16 */ -#define SRST_A_VO_NIU 256 -#define SRST_H_VO_NIU 257 -#define SRST_P_VO_NIU 258 -#define SRST_A_VOP_NIU 259 -#define SRST_A_VOP 260 -#define SRST_H_VOP 261 -#define SRST_VOP0 262 -#define SRST_VOP1 263 -#define SRST_VOP2 264 -#define SRST_VOP_PWM 265 -#define SRST_A_HDCP 266 -#define SRST_H_HDCP 267 -#define SRST_P_HDCP 268 -#define SRST_P_HDMI_HOST 270 -#define SRST_HDMI_HOST 271 - -/* cru_softrst_con17 */ -#define SRST_P_DSITX_0 272 -#define SRST_P_DSITX_1 273 -#define SRST_P_EDP_CTRL 274 -#define SRST_EDP_24M 275 -#define SRST_A_VPU_NIU 280 -#define SRST_H_VPU_NIU 281 -#define SRST_A_VPU 282 -#define SRST_H_VPU 283 -#define SRST_H_EINK 286 -#define SRST_P_EINK 287 - -/* cru_softrst_con18 */ -#define SRST_A_RGA_NIU 288 -#define SRST_H_RGA_NIU 289 -#define SRST_P_RGA_NIU 290 -#define SRST_A_RGA 292 -#define SRST_H_RGA 293 -#define SRST_RGA_CORE 294 -#define SRST_A_IEP 295 -#define SRST_H_IEP 296 -#define SRST_IEP_CORE 297 -#define SRST_H_EBC 298 -#define SRST_D_EBC 299 -#define SRST_A_JDEC 300 -#define SRST_H_JDEC 301 -#define SRST_A_JENC 302 -#define SRST_H_JENC 303 - -/* cru_softrst_con19 */ -#define SRST_A_VENC_NIU 304 -#define SRST_H_VENC_NIU 305 -#define SRST_A_RKVENC 307 -#define SRST_H_RKVENC 308 -#define SRST_RKVENC_CORE 309 - -/* cru_softrst_con20 */ -#define SRST_A_RKVDEC_NIU 320 -#define SRST_H_RKVDEC_NIU 321 -#define SRST_A_RKVDEC 322 -#define SRST_H_RKVDEC 323 -#define SRST_RKVDEC_CA 324 -#define SRST_RKVDEC_CORE 325 -#define SRST_RKVDEC_HEVC_CA 326 - -/* cru_softrst_con21 */ -#define SRST_A_BUS_NIU 336 -#define SRST_P_BUS_NIU 338 -#define SRST_P_CAN0 340 -#define SRST_CAN0 341 -#define SRST_P_CAN1 342 -#define SRST_CAN1 343 -#define SRST_P_CAN2 344 -#define SRST_CAN2 345 -#define SRST_P_GPIO1 346 -#define SRST_GPIO1 347 -#define SRST_P_GPIO2 348 -#define SRST_GPIO2 349 -#define SRST_P_GPIO3 350 -#define SRST_GPIO3 351 - -/* cru_softrst_con22 */ -#define SRST_P_GPIO4 352 -#define SRST_GPIO4 353 -#define SRST_P_I2C1 354 -#define SRST_I2C1 355 -#define SRST_P_I2C2 356 -#define SRST_I2C2 357 -#define SRST_P_I2C3 358 -#define SRST_I2C3 359 -#define SRST_P_I2C4 360 -#define SRST_I2C4 361 -#define SRST_P_I2C5 362 -#define SRST_I2C5 363 -#define SRST_P_OTPC_NS 364 -#define SRST_OTPC_NS_SBPI 365 -#define SRST_OTPC_NS_USR 366 - -/* cru_softrst_con23 */ -#define SRST_P_PWM1 368 -#define SRST_PWM1 369 -#define SRST_P_PWM2 370 -#define SRST_PWM2 371 -#define SRST_P_PWM3 372 -#define SRST_PWM3 373 -#define SRST_P_SPI0 374 -#define SRST_SPI0 375 -#define SRST_P_SPI1 376 -#define SRST_SPI1 377 -#define SRST_P_SPI2 378 -#define SRST_SPI2 379 -#define SRST_P_SPI3 380 -#define SRST_SPI3 381 - -/* cru_softrst_con24 */ -#define SRST_P_SARADC 384 -#define SRST_P_TSADC 385 -#define SRST_TSADC 386 -#define SRST_P_TIMER 387 -#define SRST_TIMER0 388 -#define SRST_TIMER1 389 -#define SRST_TIMER2 390 -#define SRST_TIMER3 391 -#define SRST_TIMER4 392 -#define SRST_TIMER5 393 -#define SRST_P_UART1 394 -#define SRST_S_UART1 395 - -/* cru_softrst_con25 */ -#define SRST_P_UART2 400 -#define SRST_S_UART2 401 -#define SRST_P_UART3 402 -#define SRST_S_UART3 403 -#define SRST_P_UART4 404 -#define SRST_S_UART4 405 -#define SRST_P_UART5 406 -#define SRST_S_UART5 407 -#define SRST_P_UART6 408 -#define SRST_S_UART6 409 -#define SRST_P_UART7 410 -#define SRST_S_UART7 411 -#define SRST_P_UART8 412 -#define SRST_S_UART8 413 -#define SRST_P_UART9 414 -#define SRST_S_UART9 415 - -/* cru_softrst_con26 */ -#define SRST_P_GRF 416 -#define SRST_P_GRF_VCCIO12 417 -#define SRST_P_GRF_VCCIO34 418 -#define SRST_P_GRF_VCCIO567 419 -#define SRST_P_SCR 420 -#define SRST_P_WDT_NS 421 -#define SRST_T_WDT_NS 422 -#define SRST_P_DFT2APB 423 -#define SRST_A_MCU 426 -#define SRST_P_INTMUX 427 -#define SRST_P_MAILBOX 428 - -/* cru_softrst_con27 */ -#define SRST_A_TOP_HIGH_NIU 432 -#define SRST_A_TOP_LOW_NIU 433 -#define SRST_H_TOP_NIU 434 -#define SRST_P_TOP_NIU 435 -#define SRST_P_TOP_CRU 438 -#define SRST_P_DDRPHY 439 -#define SRST_DDRPHY 440 -#define SRST_P_MIPICSIPHY 442 -#define SRST_P_MIPIDSIPHY0 443 -#define SRST_P_MIPIDSIPHY1 444 -#define SRST_P_PCIE30PHY 445 -#define SRST_PCIE30PHY 446 -#define SRST_P_PCIE30PHY_GRF 447 - -/* cru_softrst_con28 */ -#define SRST_P_APB2ASB_LEFT 448 -#define SRST_P_APB2ASB_BOTTOM 449 -#define SRST_P_ASB2APB_LEFT 450 -#define SRST_P_ASB2APB_BOTTOM 451 -#define SRST_P_PIPEPHY0 452 -#define SRST_PIPEPHY0 453 -#define SRST_P_PIPEPHY1 454 -#define SRST_PIPEPHY1 455 -#define SRST_P_PIPEPHY2 456 -#define SRST_PIPEPHY2 457 -#define SRST_P_USB2PHY0_GRF 458 -#define SRST_P_USB2PHY1_GRF 459 -#define SRST_P_CPU_BOOST 460 -#define SRST_CPU_BOOST 461 -#define SRST_P_OTPPHY 462 -#define SRST_OTPPHY 463 - -/* cru_softrst_con29 */ -#define SRST_USB2PHY0_POR 464 -#define SRST_USB2PHY0_USB3OTG0 465 -#define SRST_USB2PHY0_USB3OTG1 466 -#define SRST_USB2PHY1_POR 467 -#define SRST_USB2PHY1_USB2HOST0 468 -#define SRST_USB2PHY1_USB2HOST1 469 -#define SRST_P_EDPPHY_GRF 470 -#define SRST_TSADCPHY 471 -#define SRST_GMAC0_DELAYLINE 472 -#define SRST_GMAC1_DELAYLINE 473 -#define SRST_OTPC_ARB 474 -#define SRST_P_PIPEPHY0_GRF 475 -#define SRST_P_PIPEPHY1_GRF 476 -#define SRST_P_PIPEPHY2_GRF 477 - -#endif diff --git a/include/spinlock.h b/include/spinlock.h index 9c1004d9a96e7ac830d5537f25b0ba6d33ea1078..e6568c40edf1072b92cdafc2053711955df5d57e 100644 --- a/include/spinlock.h +++ b/include/spinlock.h @@ -11,8 +11,6 @@ #include #include -#include - #ifdef __cplusplus extern "C" { #endif diff --git a/include/virtualization/arm/cpu.h b/include/virtualization/arm/cpu.h index ebaacaddfcdfc7e5cf826f209f9e00524018c5c1..40ec0d43b498722f974227bd5080964b52334cba 100644 --- a/include/virtualization/arm/cpu.h +++ b/include/virtualization/arm/cpu.h @@ -18,8 +18,8 @@ #define HCR_NVHE_FLAGS (HCR_RW_BIT | HCR_API_BIT | HCR_APK_BIT | HCR_ATA_BIT) /* Host os NVHE flag */ /* Ignored bit: HCR_TVM, and ignore HCR_TSW to avoid cache DC trap */ -#define HCR_VM_FLAGS (0UL | HCR_VM_BIT | HCR_FB_BIT | HCR_AMO_BIT | \ - HCR_FMO_BIT | HCR_IMO_BIT | HCR_BSU_IS_BIT | HCR_TAC_BIT | HCR_E2H_BIT |\ +#define HCR_VM_FLAGS (0UL | HCR_VM_BIT | HCR_FB_BIT | HCR_AMO_BIT | \ + HCR_FMO_BIT | HCR_IMO_BIT | HCR_BSU_IS_BIT | HCR_TAC_BIT | HCR_E2H_BIT | \ HCR_TIDCP_BIT | HCR_RW_BIT | HCR_PTW_BIT ) #define VTTBR_VMID_SHIFT (48UL) @@ -40,6 +40,7 @@ #define ICH_SRE_EL2 S3_4_C12_C9_5 #define ICH_HCR_EL2 S3_4_C12_C11_0 +#define ICH_EISR_EL2 S3_4_C12_C11_3 #define ICH_VTR_EL2 S3_4_C12_C11_1 #define ICH_VMCR_EL2 S3_4_C12_C11_7 diff --git a/include/virtualization/arm/mm.h b/include/virtualization/arm/mm.h index f4b38b3a6a70f0b2683517ba19577d7cc5f9bfa0..4ab954e525db6170a21163df371a29a9ae0a5acc 100644 --- a/include/virtualization/arm/mm.h +++ b/include/virtualization/arm/mm.h @@ -25,6 +25,7 @@ #define MT_S2_NORMAL_NC 3U #define MT_S2_NORMAL 4U #define MT_S2_NORMAL_WT 5U +#define MT_S2_NORMAL_WB 6U /* Reuse host's mair for configure */ #define MEMORY_S2_ATTRIBUTES ((0x00 << (MT_S2_DEVICE_nGnRnE * 8)) | \ @@ -69,6 +70,14 @@ * Block and Page descriptor attributes fields for stage-2 */ #define S2_PTE_BLOCK_DESC_MEMTYPE(x) (x << 2) +#define S2_PTE_BLOCK_DESC_I_DEV_CACHE (0ULL << 2) +#define S2_PTE_BLOCK_DESC_I_NO_CACHE (1ULL << 2) +#define S2_PTE_BLOCK_DESC_I_WT_CACHE (2ULL << 2) +#define S2_PTE_BLOCK_DESC_I_WB_CACHE (3ULL << 2) +#define S2_PTE_BLOCK_DESC_O_DEV_CACHE (0ULL << 4) +#define S2_PTE_BLOCK_DESC_O_NO_CACHE (1ULL << 4) +#define S2_PTE_BLOCK_DESC_O_WT_CACHE (2ULL << 4) +#define S2_PTE_BLOCK_DESC_O_WB_CACHE (3ULL << 4) #define S2_PTE_BLOCK_DESC_AP_NO_RW (0ULL << 6) #define S2_PTE_BLOCK_DESC_AP_RO (1ULL << 6) #define S2_PTE_BLOCK_DESC_AP_WO (2ULL << 6) diff --git a/include/virtualization/arm/trap_handler.h b/include/virtualization/arm/trap_handler.h index 93e5271a71702ab354927d5b7638d004ecfb8bc8..75b29f156ef8b7e1c2634cd645bdc1b64a32577c 100644 --- a/include/virtualization/arm/trap_handler.h +++ b/include/virtualization/arm/trap_handler.h @@ -73,12 +73,12 @@ void* z_vm_lower_sync_handler(uint64_t esr_elx); void* z_vm_lower_irq_handler(z_arch_esf_t *esf_ctxt); -static ALWAYS_INLINE uint64_t get_fault_ipa(uint64_t hpfar_ipa, uint64_t far_ipa) +static ALWAYS_INLINE uint64_t get_fault_ipa(uint64_t hpfar_el2, uint64_t far_el2) { uint64_t fault_ipa; - fault_ipa = hpfar_ipa & HPFAR_EL2_MASK; + fault_ipa = hpfar_el2 & HPFAR_EL2_MASK; fault_ipa = (fault_ipa >> HPFAR_EL2_SHIFT) << HPFAR_EL2_PAGE_SHIFT; - fault_ipa |= far_ipa & HPFAR_EL2_PAGE_MASK; + fault_ipa |= far_el2 & HPFAR_EL2_PAGE_MASK; return fault_ipa; } diff --git a/include/virtualization/arm/vtimer.h b/include/virtualization/arm/vtimer.h index 2f39d97d164877b444a430e293c413aea77e6346..06bd68990e5f9694ca5debf5c17fe69b6a66abce 100644 --- a/include/virtualization/arm/vtimer.h +++ b/include/virtualization/arm/vtimer.h @@ -119,7 +119,7 @@ static ALWAYS_INLINE void arm_arch_virt_timer_set_irq_mask(bool mask) /** * @brief Get virtual timer irq number */ -int zvm_arch_vtimer_init(); +int zvm_arch_vtimer_init(void); /** * @brief Simulate cntp_tval_el0 register diff --git a/include/virtualization/os/os.h b/include/virtualization/os/os.h index 8676a2de3b23e1251ad36e26d804bfb974998383..bfcc9e42bfaf8c59f72d19734a3d4b3306fd0f2e 100644 --- a/include/virtualization/os/os.h +++ b/include/virtualization/os/os.h @@ -15,20 +15,17 @@ struct getopt_state; #define OS_NAME_LENGTH 32 /* Default vcpu num is 1 */ -#define VM_DEFAULT_VCPU_NUM (1) +#define VM_DEFAULT_VCPU_NUM (1) +#define OS_TYPE_ZEPHYR (0) +#define OS_TYPE_LINUX (1) +#define OS_TYPE_OTHERS (2) +#define OS_TYPE_MAX (3) /* For clear warning for unknow reason */ struct z_vm_info; struct vm; -enum { - OS_TYPE_ZEPHYR = 0, - OS_TYPE_LINUX = 1, - OS_TYPE_OTHERS = 2, - OS_TYPE_MAX = 3, -}; - struct os { char *name; uint16_t type; diff --git a/include/virtualization/vdev/fiq_debugger.h b/include/virtualization/vdev/fiq_debugger.h new file mode 100644 index 0000000000000000000000000000000000000000..ff06de893b4a824bdd7c353d5b8f8d984cab7cfd --- /dev/null +++ b/include/virtualization/vdev/fiq_debugger.h @@ -0,0 +1,43 @@ +/* + * Copyright 2023 HNU-ESNL + * Copyright 2023 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_ZVM_VDEV_FIQ_DEBUGGER_H_ +#define ZEPHYR_INCLUDE_ZVM_VDEV_FIQ_DEBUGGER_H_ + +#include +#include +#include + +/** + * @brief fiq debugger configuration. + * + * @param is_fiq Is it a fiq interrupt? if 'false', it is a irq interrupt + * @param serial_id The serial that used to debugger system + * @param baudrate baudrate of this serial + */ +struct fiq_debugger_device_config { + bool is_fiq; + uint8_t serial_id; + + uint32_t baudrate; + + void (*irq_config_func)(const struct device *dev); + +}; + +/** + * @brief Inject fiq debugger for rk3568 linux vm. Because + * the hardware debugger irq is not triggered. +*/ +void vm_debugger_softirq_inject(void *user_data); + +/** + * @brief init fiq debug for rk3568 borad. +*/ +int vm_init_bdspecific_device(struct vm *vm); + +#endif /* ZEPHYR_INCLUDE_ZVM_VDEV_FIQ_DEBUGGER_H_ */ diff --git a/include/virtualization/vdev/vgic_common.h b/include/virtualization/vdev/vgic_common.h index b0f56461225bee3a88cf13db0c9da0071542ac4c..65675a74b8219b171be35067f0b86eaaf77b68c2 100644 --- a/include/virtualization/vdev/vgic_common.h +++ b/include/virtualization/vdev/vgic_common.h @@ -40,6 +40,9 @@ struct virt_dev; #define VGICD_TYPER 0x0004 #define VGICD_IIDR 0x0008 #define VGICD_STATUSR 0x0010 + +#define VGIC_RESERVED 0x0F30 +#define VGIC_INMIRn 0x0f80 #define VGICD_PIDR2 0xFFE8 /* Vgic control block flag */ diff --git a/include/virtualization/vdev/vgic_v3.h b/include/virtualization/vdev/vgic_v3.h index f8026a875a54b31eeee357cd56d2cee735f9887c..f9c94874a2d879f984f8457d33d5d3cec3bf4220 100644 --- a/include/virtualization/vdev/vgic_v3.h +++ b/include/virtualization/vdev/vgic_v3.h @@ -43,6 +43,7 @@ #define GICH_HCR_UIE (1 << 1) #define GICH_HCR_LRENPIE (1 << 2) #define GICH_HCR_NPIE (1 << 3) +#define GICH_HCR_TALL1 (1 << 12) /* list register */ #define LIST_REG_GTOUP0 (0) diff --git a/include/virtualization/vdev/virt_device.h b/include/virtualization/vdev/virt_device.h index 521e1606d18aaf6cdd2a8b38e208693febb88dd4..59901352d20af9e61180a8a9d985800255beae57 100644 --- a/include/virtualization/vdev/virt_device.h +++ b/include/virtualization/vdev/virt_device.h @@ -13,8 +13,6 @@ #include #include -#define CONFIG_VIRT_DEVICE_INTERRUPT_DRIVEN 1 - #define VM_DEVICE_INIT_RES (0xFF) #define VM_DEVICE_INVALID_BASE (0xFFFFFFFF) #define VM_DEVICE_INVALID_VIRQ (0xFF) diff --git a/include/virtualization/vm_console.h b/include/virtualization/vm_console.h index 255c6dd5e173185d79c552a7dbed6ac86d142c83..9ba305dcbcdc894048601d302733835e7b2013e1 100644 --- a/include/virtualization/vm_console.h +++ b/include/virtualization/vm_console.h @@ -15,9 +15,9 @@ #include /* VM debug console uart hardware info. */ -#define VM_DEBUG_CONSOLE_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_shell_uart)) -#define VM_DEBUG_CONSOLE_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_shell_uart)) -#define VM_DEBUG_CONSOLE_IRQ DT_IRQN(DT_CHOSEN(zephyr_shell_uart)) +#define VM_DEBUG_CONSOLE_BASE DT_REG_ADDR(DT_CHOSEN(vm_console)) +#define VM_DEBUG_CONSOLE_SIZE DT_REG_SIZE(DT_CHOSEN(vm_console)) +#define VM_DEBUG_CONSOLE_IRQ DT_IRQN(DT_CHOSEN(vm_console)) #define VM_DEFAULT_CONSOLE_NAME "UART" #define VM_DEFAULT_CONSOLE_NAME_LEN (4) diff --git a/include/virtualization/vm_irq.h b/include/virtualization/vm_irq.h index 0f643f5bb388d7a3a54e90b507e8636776b21e9e..1149ccfdef17abcc44029b1339ccc795de498d7b 100644 --- a/include/virtualization/vm_irq.h +++ b/include/virtualization/vm_irq.h @@ -25,7 +25,7 @@ * flag is unset when virt irq is inject to hardware device, which * will assert vm's irq. */ -#define VIRQ_HW_FLAG BIT(0) +#define VIRQ_HW_FLAG BIT(0) /*@TODO: HW_FLAG may not enbaled for each spi.*/ #define VIRQ_PENDING_FLAG BIT(1) #define VIRQ_ACTIVED_FLAG BIT(2) #define VIRQ_ENABLED_FLAG BIT(3) diff --git a/include/virtualization/zvm.h b/include/virtualization/zvm.h index d3ef1ab10e1f4c406055f01591bd387e8d4cab43..9c304be3483e4e28b8575257d8f4b1edb726068a 100644 --- a/include/virtualization/zvm.h +++ b/include/virtualization/zvm.h @@ -71,8 +71,17 @@ #ifdef CONFIG_LOG #define ZVM_LOG_ERR(...) LOG_ERR(__VA_ARGS__) #define ZVM_LOG_WARN(...) LOG_WRN(__VA_ARGS__) + +/* print system log info */ +#ifdef CONFIG_ZVM_DEBUG_LOG_INFO #define ZVM_LOG_INFO(...) LOG_PRINTK(__VA_ARGS__) #else +#define ZVM_LOG_INFO(...) +#endif +#define ZVM_PRINTK(...) LOG_PRINTK(__VA_ARGS__) + +#else + #define ZVM_LOG_ERR(format, ...) \ do {\ DEBUG("\033[36m[ERR:]File:%s Line:%d. " format "\n\033[0m", __FILE__, \ @@ -84,6 +93,7 @@ do {\ __LINE__, ##__VA_ARGS__);\ } while(0); #define ZVM_LOG_INFO(...) printk(__VA_ARGS__) + #endif diff --git a/kernel/device.c b/kernel/device.c index 5b6c2a604ca37844dca2961c9a0c73652a47daf0..cfd2551ad36a7289a2a9644857d7ba40e6827c59 100644 --- a/kernel/device.c +++ b/kernel/device.c @@ -8,7 +8,6 @@ #include #include #include -#include extern const struct init_entry __init_start[]; extern const struct init_entry __init_PRE_KERNEL_1_start[]; diff --git a/kernel/mmu.c b/kernel/mmu.c index 476366b7a87ff5d45e47bdebe07e619a06fa97f8..4dd96589adcadabdc9f470788ab3b535597762d9 100644 --- a/kernel/mmu.c +++ b/kernel/mmu.c @@ -322,10 +322,7 @@ static void *virt_region_alloc(size_t size, size_t align) dest_addr = aligned_dest_addr; } -#if defined(CONFIG_SOC_RK3568) && defined(CONFIG_NS16650_EARLYPRINT_DEBUG) - printascii("\n dest_addr and start addr: "); - early_print_debug(dest_addr, POINTER_TO_UINT(Z_VIRT_REGION_START_ADDR)); -#endif + /* Need to make sure this does not step into kernel memory */ if (dest_addr < POINTER_TO_UINT(Z_VIRT_REGION_START_ADDR)) { (void)sys_bitarray_free(&virt_region_bitmap, size, offset); diff --git a/samples/_zvm/CMakeLists.txt b/samples/_zvm/CMakeLists.txt index b86ab63ce5f24cdbf981974f8144798930b7321a..d0440e0f50e354c230cb4d920bc6fe4c559d4def 100644 --- a/samples/_zvm/CMakeLists.txt +++ b/samples/_zvm/CMakeLists.txt @@ -1,7 +1,9 @@ -# Copyright 2021-2022 HNU - +# Copyright 2021-2022 HNU-ESNL # SPDX-License-Identifier: Apache-2.0 +#Add env for build zvm +set(CMAKE_PREFIX_PATH ${CMAKE_CURRENT_SOURCE_DIR}/../..) + cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(_zvm) diff --git a/samples/_zvm/boards/qemu_cortex_max_smp.conf b/samples/_zvm/boards/qemu_cortex_max_smp.conf index 0c7ee2e3c81b66ad66cb65b1d2c345dd5171afa2..adac4b289f1b82d95354fc38a224aed65cb0931b 100644 --- a/samples/_zvm/boards/qemu_cortex_max_smp.conf +++ b/samples/_zvm/boards/qemu_cortex_max_smp.conf @@ -1,23 +1,27 @@ # Project configuration # Copyright 2021-2022 HNU +#ARMV8 NO-SECURE MODE +CONFIG_ARMV8_A_NS=y + +# kernel vm size(16M virt ram start + size) +# It is the virt size of kernel, must bigger than true kernel size. +#CONFIG_KERNEL_VM_SIZE=0xb0c00000 +CONFIG_KERNEL_VM_SIZE=0x20000000 + # uart CONFIG_UART_PL011_PORT1=n -CONFIG_UART_PL011_PORT2=n +# vgic device. CONFIG_VM_VGICV3=y +# vuart device. CONFIG_VM_SERIAL1=y CONFIG_VM_SERIAL2=y # make more table for vm's pgd CONFIG_ZVM_ZEPHYR_MAX_XLAT_TABLES=512 -CONFIG_ZVM_LINUX_MAX_XLAT_TABLES=16384 - -# kernel vm size(16M virt ram start + size) -# It is the virt size of kernel, must bigger than true kernel size. -#CONFIG_KERNEL_VM_SIZE=0xb0c00000 -CONFIG_KERNEL_VM_SIZE=0x20000000 +CONFIG_ZVM_LINUX_MAX_XLAT_TABLES=8192 # heap size of zephyr # CONFIG_HEAP_MEM_POOL_SIZE=1610612736 diff --git a/samples/_zvm/boards/qemu_cortex_max_smp.overlay b/samples/_zvm/boards/qemu_cortex_max_smp.overlay index c189b08b74d85bc151a9f2baa51a74d4cb579043..9997f4a9315380bea405499f06591b49f1ba8b9c 100644 --- a/samples/_zvm/boards/qemu_cortex_max_smp.overlay +++ b/samples/_zvm/boards/qemu_cortex_max_smp.overlay @@ -28,6 +28,10 @@ vmflash = "/soc/flash@0"; }; + chosen { + vm,console = &uart0; + }; + soc { vgic: vgic@8000000 { @@ -40,22 +44,21 @@ uart1: uart@9001000 { compatible = "arm,pl011"; reg = <0x00 0x09001000 0x00 0x1000>; - status = "disabled"; interrupts = ; interrupt-names = "irq_0"; clocks = <&uartclk>; - status = "okay"; + status = "reserved"; current-speed = <115200>; label = "UART_1"; }; + uart2: uart@9002000 { compatible = "arm,pl011"; reg = <0x00 0x09002000 0x00 0x1000>; - status = "disabled"; interrupts = ; interrupt-names = "irq_0"; clocks = <&uartclk>; - status = "okay"; + status = "reserved"; current-speed = <115200>; label = "UART_2"; }; @@ -227,7 +230,7 @@ address_type = "normal_memory"; vm_reg_base = <0x40000000>; vm_reg_size = ; - reg = <0x0 0xf3000000 0x0 DT_SIZE_M(64)>; + reg = <0x0 0xf3000000 0x0 DT_SIZE_M(128)>; label = "VM1_MEM"; }; }; diff --git a/samples/_zvm/boards/roc_rk3568_pc.conf b/samples/_zvm/boards/roc_rk3568_pc_smp.conf similarity index 39% rename from samples/_zvm/boards/roc_rk3568_pc.conf rename to samples/_zvm/boards/roc_rk3568_pc_smp.conf index fbff6e3d034aacc1f574fd9f1fabdc14f978f8ff..4e6f1720132276598dc9eb4f461406d36e7b9442 100644 --- a/samples/_zvm/boards/roc_rk3568_pc.conf +++ b/samples/_zvm/boards/roc_rk3568_pc_smp.conf @@ -1,10 +1,25 @@ # Project configuration # Copyright 2021-2022 HNU -# make more table for vm's pgd -CONFIG_ZVM_ZEPHYR_MAX_XLAT_TABLES=128 -CONFIG_ZVM_LINUX_MAX_XLAT_TABLES=1024 +#ARMV8 NO-SECURE MODE +CONFIG_ARMV8_A_NS=y # kernel vm size(16M virt ram start + size) # It is the virt size of kernel, must bigger than true kernel size. -CONFIG_KERNEL_VM_SIZE=0x3200000 +# 128 Mbit +CONFIG_KERNEL_VM_SIZE=0x10000000 + +# vgic device. +CONFIG_VM_VGICV3=y + +# vuart device. +CONFIG_VM_SERIAL1=y +CONFIG_VM_SERIAL2=y + +# fiq debugger +CONFIG_VM_FIQ_DEBUGGER=y + +# make more table for vm's pgd +CONFIG_ZVM_ZEPHYR_MAX_XLAT_TABLES=1024 +CONFIG_ZVM_LINUX_MAX_XLAT_TABLES=8192 + diff --git a/samples/_zvm/boards/roc_rk3568_pc.overlay b/samples/_zvm/boards/roc_rk3568_pc_smp.overlay similarity index 56% rename from samples/_zvm/boards/roc_rk3568_pc.overlay rename to samples/_zvm/boards/roc_rk3568_pc_smp.overlay index 5c7407611fefee0d2036151b531eaa210dff1123..7986e1348a724cd71922a23d44e1f087f3443cc0 100644 --- a/samples/_zvm/boards/roc_rk3568_pc.overlay +++ b/samples/_zvm/boards/roc_rk3568_pc_smp.overlay @@ -5,29 +5,62 @@ */ /{ + aliases { + vmvgic = "/soc/vgic@fd400000"; + vmserial1 = "/soc/serial@fe660000"; + vmserial2 = "/soc/serial@fe6d0000"; + linuxdebugger = "/soc/fiq-debugger"; + }; + + chosen { + vm,console = &uart3; + }; + soc { + vgic: vgic@fd400000 { + compatible = "arm,gic"; + reg = <0x00 0xfd400000 0x00 0x10000>, + <0x00 0xfd460000 0x00 0xc0000>; + label = "VM_VGIC"; + }; + /* VM0's uart here! rk3568's port num is uart3 */ - uart1: serial@fe670000 { + uart3: serial@fe660000 { compatible = "rockchip,rk3568-uart", "ns16550"; - reg = <0x0 0xfe670000 0x0 0x10000>; - interrupts = ; + reg = <0x0 0xfe660000 0x0 0x10000>; + interrupts = ; + clocks = <&uartclk>; clock-frequency = <12000000>; reg-shift = <2>; - label = "UART_1"; - status = "disabled"; + status = "reserved"; + current-speed = <1500000>; + label = "UART3"; }; /* VM1's uart here! rk3568's port num is uart9 */ - uart2: serial@fe6d0000 { + uart9: serial@fe6d0000 { compatible = "rockchip,rk3568-uart", "ns16550"; reg = <0x0 0xfe6d0000 0x0 0x10000>; interrupts = ; + clocks = <&uartclk>; clock-frequency = <12000000>; reg-shift = <2>; - label = "UART_2"; - status = "disabled"; + status = "reserved"; + current-speed = <1500000>; + label = "UART9"; + }; + + debug_uart: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x02>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <1500000>; + interrupts = ; + status = "okay"; }; + }; /*TODO: The device that used by vm will be added below. */ @@ -44,7 +77,7 @@ address_type = "normal_memory"; vm_reg_base = <0x40000000>; vm_reg_size = ; - reg = <0x0 0x48000000 0x0 DT_SIZE_M(1)>; + reg = <0x0 0x48000000 0x0 DT_SIZE_M(2)>; label = "VM0_MEM"; }; @@ -69,14 +102,3 @@ }; }; - - -&uart1 { - status = "okay"; - current-speed = <1500000>; -}; - -&uart2 { - status = "okay"; - current-speed = <1500000>; -}; diff --git a/samples/_zvm/prj.conf b/samples/_zvm/prj.conf index 4ebd8355bcae53c602609a7517f11d0e844aa451..48fbea35ffdf2bbd60dcf24802829b9b8c5fec31 100644 --- a/samples/_zvm/prj.conf +++ b/samples/_zvm/prj.conf @@ -20,9 +20,6 @@ CONFIG_MAX_VCPU_PER_VM=2 CONFIG_MINIMAL_LIBC_RAND=y CONFIG_MINIMAL_LIBC_MALLOC_ARENA_SIZE=8192 -#ARMV8 NO-SECURE MODE -CONFIG_ARMV8_A_NS=y - # SMP CONFIG_SMP=y CONFIG_MP_NUM_CPUS=4 @@ -36,6 +33,7 @@ CONFIG_CONSOLE=y CONFIG_CONSOLE_SUBSYS=y CONFIG_CONSOLE_GETLINE=y CONFIG_UART_CONSOLE=y +CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n # If disable, system will always be interrupted by # periodic shell timeout. @@ -47,6 +45,9 @@ CONFIG_LOG_MODE_MINIMAL=y #Enable __ASSERT() macro CONFIG_ASSERT=y +#zvm log info system +CONFIG_ZVM_DEBUG_LOG_INFO=y + # ZVM Max PREEMPT_PRIORITIES CONFIG_NUM_PREEMPT_PRIORITIES=15 diff --git a/samples/hello_world/prj.conf b/samples/hello_world/prj.conf index 03a96b5c74591cd93c71bca3e869371bc221c5d7..8e6dfc96c1cee2af8d2d9970d2f02a06cdecaa14 100644 --- a/samples/hello_world/prj.conf +++ b/samples/hello_world/prj.conf @@ -1,3 +1,3 @@ # nothing here -#CONFIG_ARMV8_A_NS=y + diff --git a/share/zephyr-package/cmake/ZephyrConfig.cmake b/share/zephyr-package/cmake/ZephyrConfig.cmake index 7c1e6212ba7bc8d296fea60982a118abe312dccd..6a9cca6c8e39af839efc1e36841a165222b72015 100644 --- a/share/zephyr-package/cmake/ZephyrConfig.cmake +++ b/share/zephyr-package/cmake/ZephyrConfig.cmake @@ -25,6 +25,8 @@ macro(include_boilerplate location) endif() endmacro() +set(CMAKE_CONFIGURATION ${CMAKE_CURRENT_SOURCE_DIR}) + set(ENV_ZEPHYR_BASE $ENV{ZEPHYR_BASE}) if((NOT DEFINED ZEPHYR_BASE) AND (DEFINED ENV_ZEPHYR_BASE)) # Get rid of any double folder string before comparison, as example, user provides diff --git a/soc/arm64/rockchip/CMakeLists.txt b/soc/arm64/rockchip/CMakeLists.txt index 8efadf409f1716c0e0158c369b5643643d101dc6..a002d302cf61e4394af17aa1ae1e5875321e984f 100644 --- a/soc/arm64/rockchip/CMakeLists.txt +++ b/soc/arm64/rockchip/CMakeLists.txt @@ -1,5 +1,5 @@ # -# Copyright (c) 2022, HNU +# Copyright 2022 Huawei France Technologies SASU # # SPDX-License-Identifier: Apache-2.0 # diff --git a/soc/arm64/rockchip/Kconfig b/soc/arm64/rockchip/Kconfig index 518219ebc759af532c30fcbe88abb3d11bca2380..b8e20228824ca16f7754c0810c7389991c1c6dbd 100644 --- a/soc/arm64/rockchip/Kconfig +++ b/soc/arm64/rockchip/Kconfig @@ -18,4 +18,4 @@ source "soc/arm64/rockchip/*/Kconfig.soc" config SOC_PART_NUMBER default "RK3568" if SOC_SERIES_RK3568 -endif # SOC_FAMILY_ROCKCHIP \ No newline at end of file +endif # SOC_FAMILY_ROCKCHIP diff --git a/soc/arm64/rockchip/Kconfig.soc b/soc/arm64/rockchip/Kconfig.soc index 5996e4cb8e3f20bef78cebfbdf59d2fa701ae19a..19bbc3f798fbf3aa453c29d8068d714aa30e6ac0 100644 --- a/soc/arm64/rockchip/Kconfig.soc +++ b/soc/arm64/rockchip/Kconfig.soc @@ -1,4 +1,7 @@ -# Copyright (c) 2022, HNU +# +# Copyright 2022 Huawei France Technologies SASU +# # SPDX-License-Identifier: Apache-2.0 +# source "soc/arm64/rockchip/*/Kconfig.series" diff --git a/soc/arm64/rockchip/rk3568/CMakeLists.txt b/soc/arm64/rockchip/rk3568/CMakeLists.txt index 5705f4c210ac3419c83dc8ffda81332270a94033..47acbd4bfea52c824f4107e818c98b2fa19b19bb 100644 --- a/soc/arm64/rockchip/rk3568/CMakeLists.txt +++ b/soc/arm64/rockchip/rk3568/CMakeLists.txt @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -zephyr_include_directories(.) -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) +zephyr_library_sources( + soc.c +) -zephyr_library_sources_ifdef(CONFIG_SOC_RK3568 plat_core.c) -zephyr_library_sources_ifdef(CONFIG_SOC_RK3568 soc.c) \ No newline at end of file +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) diff --git a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 b/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 index 2c1afb603273a4dcced1160eae75e432ed45f01c..851d08c86a526ddc8e5e9ff7848fe0fa869e5493 100644 --- a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 +++ b/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 @@ -1,27 +1,28 @@ -# Copyright 2022 HNU +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 -# it is a soc default config file if SOC_RK3568 config SOC default "rk3568" -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + default 0 config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + default 0 config NUM_IRQS int - default 240 + default 256 config SYS_CLOCK_HW_CYCLES_PER_SEC int default 24000000 +config SOC_RK3568_EL2_INIT + bool "RK3568 SoC hardware init" + default false + endif diff --git a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series b/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series index 5912d799ba04cfcf4d3f0b3be5d1645ca0e1981c..96279038e4a197f1d0e284dfac3b935ed4ddb121 100644 --- a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series +++ b/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series @@ -1,4 +1,5 @@ -# Copyright 2022 HNU +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 if SOC_SERIES_RK3568 diff --git a/soc/arm64/rockchip/rk3568/Kconfig.series b/soc/arm64/rockchip/rk3568/Kconfig.series index 90fff98427168b738a545bdfbcfd5069fbfc4ec0..15909e5bff018922a966974fb3ba7bd1dc8f28a0 100644 --- a/soc/arm64/rockchip/rk3568/Kconfig.series +++ b/soc/arm64/rockchip/rk3568/Kconfig.series @@ -1,4 +1,5 @@ -# Copyright 2022 HNU +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyrs # SPDX-License-Identifier: Apache-2.0 config SOC_SERIES_RK3568 diff --git a/soc/arm64/rockchip/rk3568/Kconfig.soc b/soc/arm64/rockchip/rk3568/Kconfig.soc index e9aa7c39b13c6871832c4b2e8aba549ccf8350d8..7bb2be41909c99065e0a2960ffbf0162d27cea34 100644 --- a/soc/arm64/rockchip/rk3568/Kconfig.soc +++ b/soc/arm64/rockchip/rk3568/Kconfig.soc @@ -1,4 +1,5 @@ -# Copyright 2022 HNU +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr # SPDX-License-Identifier: Apache-2.0 choice @@ -11,8 +12,5 @@ config SOC_RK3568 select CPU_CORTEX_A55 select ARM_ARCH_TIMER select GIC_V3 - select CLOCK_CONTROL_RK3568_CRU - select HAS_ARM_VHE_EXTN endchoice - diff --git a/soc/arm64/rockchip/rk3568/mmu_regions.c b/soc/arm64/rockchip/rk3568/mmu_regions.c index a021a279e798c4972b7b949677831ace1a59edf7..4fa7d6f4c9296f9d7b6e6bccfdb500395bb62c21 100644 --- a/soc/arm64/rockchip/rk3568/mmu_regions.c +++ b/soc/arm64/rockchip/rk3568/mmu_regions.c @@ -1,5 +1,7 @@ /* * Copyright 2020 NXP + * Copyright 2022 HNU-ESNL + * Copyright 2022 openEuler SIG-Zephyr * * SPDX-License-Identifier: Apache-2.0 */ @@ -19,23 +21,22 @@ static const struct arm_mmu_region mmu_regions[] = { DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1), MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS), - MMU_REGION_FLAT_ENTRY("UART0", - DT_REG_ADDR(DT_NODELABEL(uart0)), - DT_REG_SIZE(DT_NODELABEL(uart0)), - MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS), - -#if defined(CONFIG_ZVM) - MMU_REGION_FLAT_ENTRY("UART1", - DT_REG_ADDR(DT_NODELABEL(uart1)), - DT_REG_SIZE(DT_NODELABEL(uart1)), - MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS), - MMU_REGION_FLAT_ENTRY("UART2", DT_REG_ADDR(DT_NODELABEL(uart2)), DT_REG_SIZE(DT_NODELABEL(uart2)), MT_DEVICE_nGnRnE | MT_P_RW_U_RW | MT_NS), -#endif +#if defined(CONFIG_ZVM) + MMU_REGION_FLAT_ENTRY("UART3", + DT_REG_ADDR(DT_NODELABEL(uart3)), + DT_REG_SIZE(DT_NODELABEL(uart3)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), + + MMU_REGION_FLAT_ENTRY("UART9", + DT_REG_ADDR(DT_NODELABEL(uart9)), + DT_REG_SIZE(DT_NODELABEL(uart9)), + MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE), +#endif }; const struct arm_mmu_config mmu_config = { diff --git a/soc/arm64/rockchip/rk3568/plat_core.c b/soc/arm64/rockchip/rk3568/plat_core.c deleted file mode 100644 index 6f26ba5778b621250018fd05215bfaaa4bc9b572..0000000000000000000000000000000000000000 --- a/soc/arm64/rockchip/rk3568/plat_core.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright 2020 Carlo Caione - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -/* For get GICv3 address */ -#include "../../../../drivers/interrupt_controller/intc_gicv3_priv.h" - -void z_arm64_el3_plat_init(void) -{ - uint64_t reg = 0; - - reg = (ICC_SRE_ELx_DFB_BIT | ICC_SRE_ELx_DIB_BIT | - ICC_SRE_ELx_SRE_BIT | ICC_SRE_EL3_EN_BIT); - - write_sysreg(reg, ICC_SRE_EL3); - - /* Init GICv3 ctrl register for NS group1 route enable*/ -#ifdef CONFIG_ARMV8_A_NS - /* set DS bit to enable NS mode */ - sys_write32(BIT(GICD_CTRL_NS), GICD_CTLR); - - /* Direct write to GICD_CTRL_ARE_NS may have some unpredictable value */ - sys_write32(BIT(GICD_CTRL_NS)|BIT(GICD_CTRL_ARE_NS), GICD_CTLR); -#endif -} diff --git a/soc/arm64/rockchip/rk3568/soc.c b/soc/arm64/rockchip/rk3568/soc.c index 618e9d763e2db12e7abeafc206502fc2c74d774b..85e514e7eccbf0e544df15b15571d92fee1f87bd 100644 --- a/soc/arm64/rockchip/rk3568/soc.c +++ b/soc/arm64/rockchip/rk3568/soc.c @@ -4,17 +4,11 @@ */ #include -#ifdef CONFIG_SOC_RK3568 +#ifdef CONFIG_SOC_RK3568_EL2_INIT -/* - * fvp can work on the mode that all core run together when it start. - * So an implementation for FVP is needed. - */ -#ifndef CONFIG_PM_CPU_OPS_PSCI -int pm_cpu_on(unsigned long cpuid, uintptr_t entry_point) +void z_arm64_el2_plat_init(void) { - return 0; + } -#endif #endif diff --git a/soc/arm64/rockchip/rk3568/soc.h b/soc/arm64/rockchip/rk3568/soc.h index 9232937a7964f880405272c058e83129dd10bd5e..3ca14cc6fddd1ade82773ebc9b4d10d94adb7a7f 100644 --- a/soc/arm64/rockchip/rk3568/soc.h +++ b/soc/arm64/rockchip/rk3568/soc.h @@ -7,6 +7,8 @@ #ifndef SOC_H #define SOC_H +#include +#include /* TODO: Place Holder */ diff --git a/subsys/virtualization/Kconfig b/subsys/virtualization/Kconfig index a0382e454d74b104716087a504043367b0834ad1..27fdf6309b6c5bc6326bf884f38eb80ce4cb624a 100644 --- a/subsys/virtualization/Kconfig +++ b/subsys/virtualization/Kconfig @@ -40,6 +40,13 @@ config ZVM_INIT_PRIORITY help ZVM module initialization priority. +config ZVM_DEBUG_LOG_INFO + bool "Show system boot info" + help + When code level debug is not suitable for + the this system, we can use log_info to locate + the boot issue. + config ZVM_TIME_MEASURE bool "ZVM measure system latency" help diff --git a/subsys/virtualization/os/os.c b/subsys/virtualization/os/os.c index 8218e92d272b14716313ec3687fb556d82666ae4..dd779e54d7f17492033b48d855e4ec460b80bec6 100644 --- a/subsys/virtualization/os/os.c +++ b/subsys/virtualization/os/os.c @@ -15,10 +15,6 @@ LOG_MODULE_DECLARE(ZVM_MODULE_NAME); - -/** - * @brief Initialize OS basic information of a virtual machine - */ int vm_os_create(struct vm* vm, struct z_vm_info *vm_info) { struct os* os = vm->os; diff --git a/subsys/virtualization/os/os_linux.c b/subsys/virtualization/os/os_linux.c index f75fbfede8230b8e79f236b3d139fdff4c4c017b..a2dad88493882e676be024959a0021a53e4de21c 100644 --- a/subsys/virtualization/os/os_linux.c +++ b/subsys/virtualization/os/os_linux.c @@ -67,5 +67,4 @@ int load_linux_image(struct vm_mem_domain *vmem_domain) } return ret; - } diff --git a/subsys/virtualization/tools/elfloader.c b/subsys/virtualization/tools/elfloader.c index eab42c08561d418b836afe030d3e571d4e32a2c2..1477022490c2dc4423669ef79f872b3f1539f5f3 100644 --- a/subsys/virtualization/tools/elfloader.c +++ b/subsys/virtualization/tools/elfloader.c @@ -205,9 +205,6 @@ static el_status elf_load(el_ctx *ctx, el_alloc_cb alloc, void *src) return EL_ENOMEM; } - ZVM_LOG_INFO("\nLoading seg fileoff %x, vaddr %x to %p\n", - ph.p_offset, ph.p_vaddr, dest); - /* read loaded portion */ if ((rv = el_pread(ctx, dest, src+ph.p_offset, ph.p_filesz))){ return rv; diff --git a/subsys/virtualization/vdev/CMakeLists.txt b/subsys/virtualization/vdev/CMakeLists.txt index 4adfbb25d1c03555deeb9243a721f7abc0b2e2bb..5cdbeed725d702dab8ce3117d3a1a2c3f7f21b91 100644 --- a/subsys/virtualization/vdev/CMakeLists.txt +++ b/subsys/virtualization/vdev/CMakeLists.txt @@ -19,3 +19,8 @@ zephyr_sources_ifdef( CONFIG_VM_VIRTIO_BLOCK virtio_blk.c ) + +zephyr_sources_ifdef( + CONFIG_VM_FIQ_DEBUGGER + fiq_debugger.c +) diff --git a/subsys/virtualization/vdev/Kconfig b/subsys/virtualization/vdev/Kconfig index 214ddeee617d7103fbab44a58c89906d01d3816d..79dec2dc571e6834e9bf8f4bffbf5b629ec38dd7 100644 --- a/subsys/virtualization/vdev/Kconfig +++ b/subsys/virtualization/vdev/Kconfig @@ -7,10 +7,17 @@ # described by dts file, and bind to aliases. menuconfig ZVM_DEVICE_SUPPORT bool "Zephyr Based Virtualization device menu" - default n + default y help Zephyr device virtualization support. +config VIRT_DEVICE_INTERRUPT_DRIVEN + bool "Virt device interrupt flag" + default y + help + When VM devices need interrupts, this option must be + chosen for set callback function. + config VM_VGICV3 bool "VM gicv3 device that get from vm." help @@ -63,3 +70,19 @@ config VIRTIO_MMIO_INIT_PRIORITY When virtio is init, it judge the initialization priority in POST_KERNLE. endif + +config VM_FIQ_DEBUGGER + bool "Linux VM debugger console on rk3568." + help + When booting linux VM on rk3568, a debugger console must be inited, + this option is used to map irq to linux vm. + +if VM_FIQ_DEBUGGER + +config VM_FIQ_DEBUGGER_INIT_PRIORITY + int "VM fiq debugger init priority." + default 62 + help + When fiq debugger is init, it judge the initialization priority in POST_KERNLE. + +endif diff --git a/subsys/virtualization/vdev/fiq_debugger.c b/subsys/virtualization/vdev/fiq_debugger.c new file mode 100644 index 0000000000000000000000000000000000000000..4657090a65754b488e55ee6547bf0d1fbe3f2a0e --- /dev/null +++ b/subsys/virtualization/vdev/fiq_debugger.c @@ -0,0 +1,169 @@ +/* + * Copyright 2023 HNU-ESNL + * Copyright 2023 openEuler SIG-Zephyr + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +LOG_MODULE_DECLARE(ZVM_MODULE_NAME); + +extern const struct device __device_start[]; +extern const struct device __device_end[]; + +#define DEV_CFG(dev) \ + ((const struct virt_device_config * const)(dev)->config) +#define DEV_DATA(dev) \ + ((struct virt_device_data *)(dev)->data) + +void vm_debugger_softirq_inject(void *user_data) +{ + uint32_t virq; + int err = 0; + const struct device *dev; + const struct virt_dev *vdev = (const struct virt_dev *)user_data; + + if(vdev->vm->os->type != OS_TYPE_LINUX){ + return; + } + + /* scan the host dts and get the device list */ + for (dev = __device_start; dev != __device_end; dev++) { + /** + * Inject virq to vm by soft irq. + */ + if (!strcmp(dev->name, DEVICE_DT_NAME(DT_ALIAS(linuxdebugger)))) { + virq = DEV_CFG(dev)->hirq_num; + err = set_virq_to_vm(vdev->vm, virq); + if (err < 0) { + ZVM_LOG_WARN("Send virq to vm error!"); + } + } + } + +} + +static int vm_fiq_debugger_init(const struct device *dev, struct vm *vm, struct virt_dev *vdev_desc) +{ + ARG_UNUSED(vdev_desc); + uint16_t name_len; + struct virt_dev *vdev; + + vdev = (struct virt_dev *)k_malloc(sizeof(struct virt_dev)); + if (!vdev) { + ZVM_LOG_ERR("Allocate memory for vm device error!\n"); + return -ENOMEM; + } + name_len = strlen(dev->name); + name_len = name_len > VIRT_DEV_NAME_LENGTH ? VIRT_DEV_NAME_LENGTH : name_len; + strncpy(vdev->name, dev->name, name_len); + vdev->name[name_len] = '\0'; + + /* directly map irq */ + vdev->dev_pt_flag = true; + vdev->virq = DEV_CFG(dev)->hirq_num; + vdev->hirq = DEV_CFG(dev)->hirq_num; + vdev->vm = vm; + + sys_dlist_append(&vm->vdev_list, &vdev->vdev_node); + + vm_device_irq_init(vm, vdev); + + vdev_irq_callback_user_data_set(dev, vm_device_callback_func, vdev); + + return 0; +} + +static void virt_fiq_debugger_irq_callback_set(const struct device *dev, + void *cb, void *user_data) +{ + /* Binding to the user's callback function and get the user data. */ + DEV_DATA(dev)->irq_cb = cb; + DEV_DATA(dev)->irq_cb_data = user_data; +} + +static const struct virt_device_api virt_fiq_debugger_api = { + .init_fn = vm_fiq_debugger_init, + .device_driver_api = NULL, +#ifdef CONFIG_VIRT_DEVICE_INTERRUPT_DRIVEN + .virt_irq_callback_set = virt_fiq_debugger_irq_callback_set, +#endif +}; + +void virt_fiq_debugger_isr(const struct device *dev) +{ + struct virt_device_data *data = DEV_DATA(dev); + /* Verify if the callback has been registered */ + if (data->irq_cb) { + data->irq_cb(dev, data->irq_cb, data->irq_cb_data); + } +} + +static void fiq_debugger_irq_config_func(const struct device *dev) +{ + IRQ_CONNECT(DT_IRQN(DT_ALIAS(linuxdebugger)), + DT_IRQ(DT_ALIAS(linuxdebugger), priority), + virt_fiq_debugger_isr, + DEVICE_DT_GET(DT_ALIAS(linuxdebugger)), + 0); + irq_enable(DT_IRQN(DT_ALIAS(linuxdebugger))); +} + +static struct virt_device_data virt_fiq_debugger_data_port = { +#ifdef CONFIG_VIRT_DEVICE_INTERRUPT_DRIVEN + .irq_cb = NULL, + .irq_cb_data = NULL, +#endif +}; + +static struct fiq_debugger_device_config fiq_debugger_cfg_port = { + .irq_config_func = fiq_debugger_irq_config_func, +}; + +static struct virt_device_config virt_fiq_debugger_cfg = { + .hirq_num = DT_IRQN(DT_ALIAS(linuxdebugger)), + .device_config = &fiq_debugger_cfg_port, +}; + +int vm_init_bdspecific_device(struct vm *vm) +{ + const struct device *dev; + + /* scan the host dts and get the device list */ + for (dev = __device_start; dev != __device_end; dev++) { + /** + * through the `init_res` to judge whether the device is + * ready to allocate to vm. + */ + if (!strcmp(dev->name, DEVICE_DT_NAME(DT_ALIAS(linuxdebugger)))) { + return vm_fiq_debugger_init(dev, vm, NULL); + } + } + return -1; +} + + +static int fiq_debugger_init(const struct device *dev) +{ + dev->state->init_res = VM_DEVICE_INIT_RES; + ZVM_LOG_INFO("** Ready to init fiq debugger, dev name is: %s. \n", dev->name); + return 0; +} + +DEVICE_DT_DEFINE(DT_ALIAS(linuxdebugger), + &fiq_debugger_init, + NULL, + &virt_fiq_debugger_data_port, + &virt_fiq_debugger_cfg, POST_KERNEL, + CONFIG_VM_FIQ_DEBUGGER_INIT_PRIORITY, + &virt_fiq_debugger_api); diff --git a/subsys/virtualization/vdev/serial.c b/subsys/virtualization/vdev/serial.c index 1266862da5b6d4a864ff953bc826c096bc531c31..e5771a1046f3d83b74a9164d0302aa486124d1a4 100644 --- a/subsys/virtualization/vdev/serial.c +++ b/subsys/virtualization/vdev/serial.c @@ -17,6 +17,7 @@ #include #include #include +#include LOG_MODULE_DECLARE(ZVM_MODULE_NAME); @@ -25,6 +26,11 @@ LOG_MODULE_DECLARE(ZVM_MODULE_NAME); #define DEV_DATA(dev) \ ((struct virt_device_data *)(dev)->data) +void __weak vm_debugger_softirq_inject(void *user_data) +{ + ARG_UNUSED(user_data); +} + /** * @brief init vm serial device for the vm. Including: * 1. Allocating virt device to vm, and build map. @@ -75,6 +81,7 @@ static const struct virt_device_api virt_serial_api = { static int serial_init(const struct device *dev) { dev->state->init_res = VM_DEVICE_INIT_RES; + ZVM_LOG_INFO("** Ready to init vm serial, dev name is: %s. \n", dev->name); #ifdef CONFIG_UART_INTERRUPT_DRIVEN ((const struct uart_device_config * const)(DEV_CFG(dev)->device_config))->irq_config_func(dev); #endif @@ -86,11 +93,11 @@ static int serial_init(const struct device *dev) void virt_serial_isr(const struct device *dev) { struct virt_device_data *data = DEV_DATA(dev); - /* Verify if the callback has been registered */ if (data->irq_cb) { // uart_irq_update(dev); data->irq_cb(dev, data->irq_cb, data->irq_cb_data); + vm_debugger_softirq_inject(data->irq_cb_data); } } #endif diff --git a/subsys/virtualization/vdev/vgic_common.c b/subsys/virtualization/vdev/vgic_common.c index e43eef4aec4974f0662acc2713fbc07e333219d6..de378c8460120e12865411e66f1414ebf9286d77 100644 --- a/subsys/virtualization/vdev/vgic_common.c +++ b/subsys/virtualization/vdev/vgic_common.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -97,28 +98,72 @@ static int vgic_irq_disable(struct vcpu *vcpu, uint32_t virt_irq) return 0; } -static int virt_irq_set_type(struct vcpu *vcpu, uint32_t virt_irq, int value) +static int virt_irq_set_type(struct vcpu *vcpu, uint32_t offset, uint32_t *value) { + uint8_t lowbit_value; + int i, irq, idx_base; + uint32_t reg_val; + mem_addr_t base; struct virt_irq_desc *desc; - desc = vgic_get_virt_irq_desc(vcpu, virt_irq); - if (!desc) { - return -ENOENT; - } + /* Get the register base. */ + idx_base = (offset-GICD_ICFGRn) / 4; + irq = 16 * idx_base; + base = GIC_DIST_BASE; - if (desc->type != value) { - desc->type = value; - if (desc->virq_flags & VIRQ_HW_FLAG) { - if (value) { - value = IRQ_TYPE_EDGE; - } else { - value = IRQ_TYPE_LEVEL; + /** + * Per-register control 16 interrupt signals. + * @TODO: This may be more simple for reduce + * time. + */ + for (i = 0; i < 16; i++, irq++) { + desc = vgic_get_virt_irq_desc(vcpu, irq); + if (!desc) { + return -ENOENT; + } + lowbit_value = (*value>>2*i) & GICD_ICFGR_MASK; + if (desc->type != lowbit_value) { + desc->type = lowbit_value; + /* If it is a hardware device interrupt */ + if (desc->virq_flags & VIRQ_HW_FLAG) { + /* may be need to set to hardware. */ + reg_val = sys_read32(GICD_ICFGRn + (idx_base*4)); + reg_val &= ~(GICD_ICFGR_MASK << 2*i); + if (lowbit_value){ + reg_val |= (GICD_ICFGR_TYPE << 2*i); + } + /* clear the enabled flag of interrupt */ + irq_disable(irq); + sys_write32(reg_val, GICD_ICFGRn + (idx_base*4)); } } } return 0; } +/** + * @breif: this type value is got from desc. + * @TODO: may be direct read from vgic register. +*/ +static int virt_irq_get_type(struct vcpu *vcpu, uint32_t offset, uint32_t *value) +{ + int i, irq, idx_base; + struct virt_irq_desc *desc; + + idx_base = (offset-GICD_ICFGRn) / 4; + irq = 16 * idx_base; + + /*Per-register control 16 interrupt signals.*/ + for (i = 0; i < 16; i++, irq++) { + desc = vgic_get_virt_irq_desc(vcpu, irq); + if(!desc) { + continue; + } + *value = *value | (desc->type << i * 2); + } + return 0; +} + /**  * @brief Set priority for specific virtual interrupt requests  */ @@ -149,6 +194,7 @@ static int vgic_set_virq(struct vcpu *vcpu, struct virt_irq_desc *desc) key = k_spin_lock(&vb->spinlock); lr_state = desc->virq_states; + switch (lr_state) { case VIRQ_STATE_INVALID: desc->virq_flags |= VIRQ_PENDING_FLAG; @@ -187,6 +233,7 @@ static int vgic_set_virq(struct vcpu *vcpu, struct virt_irq_desc *desc) if(vcpu->work->vcpu_thread != _current){ if(zvm_thread_active_elsewhere(vcpu->work->vcpu_thread)){ #if defined(CONFIG_SMP) && defined(CONFIG_SCHED_IPI_SUPPORTED) + ZVM_LOG_INFO("Ready to send arch_sched_ipi \n"); arch_sched_ipi(); #endif }else{ @@ -209,10 +256,7 @@ static bool vgic_set_sgi2vcpu(struct vcpu *vcpu, struct virt_irq_desc *desc) static int vgic_gicd_mem_read(struct vcpu *vcpu, struct virt_gic_gicd *gicd, uint32_t offset, uint64_t *v) { - int i, irq; - uint32_t tmp_value; - uint64_t *value = v; - struct virt_irq_desc *desc; + uint32_t *value = (uint32_t *)v; offset += GIC_DIST_BASE; switch (offset) { @@ -222,29 +266,25 @@ static int vgic_gicd_mem_read(struct vcpu *vcpu, struct virt_gic_gicd *gicd, case GICD_TYPER: *value = vgic_sysreg_read32(gicd->gicd_regs_base, VGICD_TYPER); break; + case GICD_IIDR: + *value = vgic_sysreg_read32(gicd->gicd_regs_base, offset-GIC_DIST_BASE); case GICD_STATUSR: *value = 0; break; - case GICD_ISENABLERn...(GIC_DIST_BASE + 0x017c - 1): + case GICD_ISENABLERn...(GICD_ICENABLERn - 1): *value = 0; break; - case GICD_ICENABLERn...(GIC_DIST_BASE + 0x01fc - 1): + case GICD_ICENABLERn...(GICD_ISPENDRn - 1): *value = 0; break; - case (GIC_DIST_BASE + 0xffe8): - *value = vgic_sysreg_read32(gicd->gicd_regs_base, VGICD_PIDR2); + case (GIC_DIST_BASE+VGIC_RESERVED)...(GIC_DIST_BASE+VGIC_INMIRn - 1): + *value = vgic_sysreg_read32(gicd->gicd_base, offset-GIC_DIST_BASE); break; case GICD_ICFGRn...(GIC_DIST_BASE + 0x0cfc - 1): - offset = (GIC_DIST_BASE+offset-GICD_ICFGRn) / 4; - irq = 16 * offset; - for (i = 0; i < 16; i++, irq++) { - desc = vgic_get_virt_irq_desc(vcpu, irq); - if(!desc) { - continue; - } - tmp_value = desc->type; - *value = *value | (tmp_value << i * 2); - } + virt_irq_get_type(vcpu, offset, value); + break; + case (GIC_DIST_BASE + VGICD_PIDR2): + *value = vgic_sysreg_read32(gicd->gicd_regs_base, VGICD_PIDR2); break; default: *value = 0; @@ -256,7 +296,6 @@ static int vgic_gicd_mem_read(struct vcpu *vcpu, struct virt_gic_gicd *gicd, static int vgic_gicd_mem_write(struct vcpu *vcpu, struct virt_gic_gicd *gicd, uint32_t offset, uint64_t *v) { - int i, irq; uint32_t x, y, bit, t; uint32_t *value = (uint32_t *)v; k_spinlock_key_t key; @@ -271,12 +310,12 @@ static int vgic_gicd_mem_write(struct vcpu *vcpu, struct virt_gic_gicd *gicd, break; case GICD_STATUSR: break; - case GICD_ISENABLERn...(GIC_DIST_BASE + 0x017c - 1): + case GICD_ISENABLERn...(GICD_ICENABLERn - 1): x = (offset - GICD_ISENABLERn) / 4; y = x * 32; vgic_irq_test_and_set_bit(vcpu, y, value, 32, 1); break; - case GICD_ICENABLERn...(GIC_DIST_BASE + 0x01fc - 1): + case GICD_ICENABLERn...(GICD_ISPENDRn - 1): x = (offset - GICD_ICENABLERn) / 4; y = x * 32; vgic_irq_test_and_set_bit(vcpu, y, value, 32, 0); @@ -295,13 +334,10 @@ static int vgic_gicd_mem_write(struct vcpu *vcpu, struct virt_gic_gicd *gicd, vgic_virq_set_priority(vcpu, y + 4, bit); break; case GICD_ICFGRn...(GIC_DIST_BASE + 0x0cfc - 1): - offset = (GIC_DIST_BASE+offset-GICD_ICFGRn) / 4; - irq = 16 * offset; - - for (i = 0; i < 16; i++, irq++) { - virt_irq_set_type(vcpu, irq, *value & 0x3); - *value = *value >> 2; - } + virt_irq_set_type(vcpu, offset, value); + break; + case (GIC_DIST_BASE+VGIC_RESERVED)...(GIC_DIST_BASE+VGIC_INMIRn - 1): + vgic_sysreg_write32(*value, gicd->gicd_base, offset-GIC_DIST_BASE); break; default: break; @@ -339,8 +375,6 @@ void arch_vdev_irq_enable(struct vcpu *vcpu) struct _dnode *d_node, *ds_node; SYS_DLIST_FOR_EACH_NODE_SAFE(&vm->vdev_list, d_node, ds_node) { - - /* Find the virt dev */ vdev = CONTAINER_OF(d_node, struct virt_dev, vdev_node); /* enable spi interrupt */ @@ -361,8 +395,6 @@ void arch_vdev_irq_disable(struct vcpu *vcpu) struct _dnode *d_node, *ds_node; SYS_DLIST_FOR_EACH_NODE_SAFE(&vm->vdev_list, d_node, ds_node) { - - /* Find the virt dev */ vdev = CONTAINER_OF(d_node, struct virt_dev, vdev_node); /* disable spi interrupt */ @@ -414,6 +446,9 @@ int vgic_vdev_mem_read(struct virt_dev *vdev, uint64_t addr, uint64_t *value) struct virt_gic_gicd *gicd = &vgic->gicd; struct virt_gic_gicr *gicr = vgic->gicr[vcpu->vcpu_id]; + /*Avoid some case that we only just use '|' to get the value */ + *value = 0; + if ((addr >= gicd->gicd_base) && (addr < gicd->gicd_base + gicd->gicd_size)) { type = TYPE_GIC_GICD; offset = addr - gicd->gicd_base; @@ -449,7 +484,6 @@ int vgic_vdev_mem_read(struct virt_dev *vdev, uint64_t addr, uint64_t *value) return vgic_gicrsgi_mem_read(vcpu, gicr, offset, value); case TYPE_GIC_GICR_VLPI: /* ignore vlpi register */ - *value = 0; return 0; default: ZVM_LOG_WARN("unsupport gic type %d\n", type); @@ -588,6 +622,7 @@ int virt_irq_sync_vgic(struct vcpu *vcpu) } case VIRQ_STATE_INVALID: gicv3_update_lr(vcpu, desc, ACTION_CLEAR_VIRQ, 0); + vcpu->arch->hcr_el2 &= ~(uint64_t)HCR_VI_BIT; sys_dlist_remove(&desc->desc_node); /* if software irq is still triggered */ if (desc->vdev_trigger) { @@ -625,7 +660,7 @@ int virt_irq_flush_vgic(struct vcpu *vcpu) /* no idle list register */ if(vcpu->arch->list_regs_map == ((1<spinlock, key); - ZVM_LOG_INFO("There is no idle list register! "); + ZVM_LOG_WARN("There is no idle list register! "); return 0; } diff --git a/subsys/virtualization/vdev/vgic_v3.c b/subsys/virtualization/vdev/vgic_v3.c index b80e420cb0261fc732ad37009062ade1616f7c87..93c43f13dccec108d62275a947fb5685b33f3185 100644 --- a/subsys/virtualization/vdev/vgic_v3.c +++ b/subsys/virtualization/vdev/vgic_v3.c @@ -132,6 +132,40 @@ static void vgicv3_lrs_save(struct gicv3_vcpuif_ctxt *ctxt) } } +static void vgicv3_lrs_init(void) +{ + uint32_t rg_cout = VGIC_TYPER_LR_NUM; + + if (rg_cout > VGIC_TYPER_LR_NUM) { + ZVM_LOG_WARN("System list registers do not support! \n"); + return; + } + + rg_cout = rg_cout>8 ? 8 : rg_cout; + + switch (rg_cout) { + case 8: + write_sysreg(0, ICH_LR7_EL2); + case 7: + write_sysreg(0, ICH_LR6_EL2); + case 6: + write_sysreg(0, ICH_LR5_EL2); + case 5: + write_sysreg(0, ICH_LR4_EL2); + case 4: + write_sysreg(0, ICH_LR3_EL2); + case 3: + write_sysreg(0, ICH_LR2_EL2); + case 2: + write_sysreg(0, ICH_LR1_EL2); + case 1: + write_sysreg(0, ICH_LR0_EL2); + break; + default: + break; + } +} + static void vgicv3_prios_save(struct gicv3_vcpuif_ctxt *ctxt) { uint32_t rg_cout = VGIC_TYPER_PRIO_NUM; @@ -184,11 +218,9 @@ int gicv3_inject_virq(struct vcpu *vcpu, struct virt_irq_desc *desc) lr->vINTID = desc->virq_num; lr->pINTID = desc->pirq_num; lr->priority = desc->prio; - /* lr->nmi = 0; */ lr->group = LIST_REG_GROUP1; lr->hw = LIST_REG_HW_VIRQ; lr->state = VIRQ_STATE_PENDING; - gicv3_update_lr(vcpu, desc, ACTION_SET_VIRQ, value); return 0; } @@ -303,7 +335,7 @@ int get_vcpu_gicr_type(struct virt_gic_gicr *gicr, uint32_t vcpu_id = gicr->vcpu_id; /* master core can access all the other core's gicr */ - if(vcpu_id == 0){ + if (vcpu_id == 0) { for(i=0; i= gicr->gicr_sgi_base + i*VGIC_RD_SGI_SIZE) && (addr < gicr->gicr_sgi_base + i*VGIC_RD_SGI_SIZE + gicr->gicr_sgi_size)) { @@ -317,7 +349,7 @@ int get_vcpu_gicr_type(struct virt_gic_gicr *gicr, return TYPE_GIC_GICR_RD; } } - }else{ + } else { if ((addr >= gicr->gicr_sgi_base + vcpu_id*VGIC_RD_SGI_SIZE) && (addr < (gicr->gicr_sgi_base + vcpu_id*VGIC_RD_SGI_SIZE + gicr->gicr_sgi_size))) { *offset = addr - (gicr->gicr_sgi_base + vcpu_id*VGIC_RD_SGI_SIZE); @@ -330,6 +362,7 @@ int get_vcpu_gicr_type(struct virt_gic_gicr *gicr, return TYPE_GIC_GICR_RD; } } + return TYPE_GIC_INVAILD; } @@ -378,7 +411,6 @@ static int vdev_gicv3_init(struct vm *vm, struct vgicv3_dev *gicv3_vdev, uint32_ struct virt_gic_gicd *gicd = &gicv3_vdev->gicd; struct virt_gic_gicr *gicr; - ZVM_SPINLOCK_INIT(&gicd->gicd_lock); gicd->gicd_base = gicd_base; gicd->gicd_size = gicd_size; gicd->gicd_regs_base = k_malloc(gicd->gicd_size); @@ -437,6 +469,9 @@ static int vdev_gicv3_init(struct vm *vm, struct vgicv3_dev *gicv3_vdev, uint32_ gicv3_vdev->gicr[i] = gicr; } + ZVM_LOG_INFO("** List register num: %lld \n", VGIC_TYPER_LR_NUM); + vgicv3_lrs_init(); + return 0; } diff --git a/subsys/virtualization/vdev/virt_device.c b/subsys/virtualization/vdev/virt_device.c index 8068e5da85c4a96577f5ca1157b53d606d687ddd..dee669e677901e75c3a44542c41eb6f5fd7eedd5 100644 --- a/subsys/virtualization/vdev/virt_device.c +++ b/subsys/virtualization/vdev/virt_device.c @@ -70,9 +70,8 @@ struct virt_dev *allocate_device_to_vm(const struct device *dev, struct vm *vm, void vm_device_callback_func(const struct device *dev, void *cb, void *user_data) { - uint32_t virq, pirq; + uint32_t virq; ARG_UNUSED(cb); - ARG_UNUSED(pirq); int err = 0; const struct virt_dev *vdev = (const struct virt_dev *)user_data; diff --git a/subsys/virtualization/vm_console.c b/subsys/virtualization/vm_console.c index 045de45db4739becb8131d2e3c624d4f52bbafbe..383e3e9617759f6b1c669f7974724eccca37ea0c 100644 --- a/subsys/virtualization/vm_console.c +++ b/subsys/virtualization/vm_console.c @@ -53,7 +53,7 @@ int vm_console_create(struct vm *vm) vm_device_irq_init(vm, chosen_dev); dev = (struct device *)vm_dev->priv_data; vdev_irq_callback_user_data_set(dev, vm_device_callback_func, chosen_dev); - + ZVM_LOG_INFO("** Add %s device to vm successful. \n", dev->name); return 0; } return -ENODEV; diff --git a/subsys/virtualization/vm_cpu.c b/subsys/virtualization/vm_cpu.c index 6c639587c1e9271ae7338483b229dbe071d2370c..bf4334477687cce08aa06db2b2786008301f3dd2 100644 --- a/subsys/virtualization/vm_cpu.c +++ b/subsys/virtualization/vm_cpu.c @@ -30,7 +30,7 @@ static void init_vcpu_virt_irq_desc(struct vcpu_virt_irq_block *virq_block) desc->id = VM_INVALID_DESC_ID; desc->pirq_num = i; desc->virq_num = i; - desc->prio = VM_DEFAULT_LOCAL_VIRQ_PRIO; + desc->prio = 0; desc->vdev_trigger = 0; desc->vcpu_id = DEFAULT_VCPU; desc->virq_flags = VIRQ_NOUSED_FLAG; @@ -99,7 +99,7 @@ static void vcpu_context_switch(struct k_thread *new_thread, break; } } - + ZVM_LOG_INFO("** load_vcpu_context, thread: %p, new vcpu thread? : %d \n ", new_thread, VCPU_THREAD(new_thread)); if (VCPU_THREAD(new_thread)) { struct vcpu *new_vcpu = new_thread->vcpu_struct; @@ -315,11 +315,11 @@ int vcpu_ipi_scheduler(uint32_t cpu_mask, uint32_t timeout) int z_vcpu_run(struct vcpu *vcpu) { int ret = 0; - + ZVM_LOG_INFO("\n** Start running vcpu: %s-%d. \n", vcpu->vm->vm_name, vcpu->vcpu_id); do{ ret = arch_vcpu_run(vcpu); }while(ret >= 0); - + ZVM_LOG_INFO("** Stop running vcpu: %s-%d. \n", vcpu->vm->vm_name, vcpu->vcpu_id); vm_delete(vcpu->vm); return ret; diff --git a/subsys/virtualization/vm_dev.c b/subsys/virtualization/vm_dev.c index 6739032aa7534a4e4f116f5a0634f9cbe9c4c799..720a32bd0ea5eda98665bc5ee200cb1bb8827123 100644 --- a/subsys/virtualization/vm_dev.c +++ b/subsys/virtualization/vm_dev.c @@ -15,11 +15,17 @@ #include #include #include +#include #include #include LOG_MODULE_DECLARE(ZVM_MODULE_NAME); +int __weak vm_init_bdspecific_device(struct vm *vm) +{ + return 0; +} + static int vm_vdev_mem_add(struct vm *vm, struct virt_dev *vdev) { uint32_t attrs = 0; @@ -217,7 +223,15 @@ int vm_device_init(struct vm *vm) return -EMMAO; } - /* @TODO: scan the dtb and get the device's node. */ + /* Board specific device init, for example fig debugger. */ + switch (vm->os->type){ + case OS_TYPE_LINUX: + ret = vm_init_bdspecific_device(vm); + break; + default: + break; + } - return 0; + /* @TODO: scan the dtb and get the device's node. */ + return ret; } diff --git a/subsys/virtualization/vm_irq.c b/subsys/virtualization/vm_irq.c index b6e92db9cd543dd8750e55c92ef4fc168d5c738e..4464a3ae40f87dbab772bcc119c55f847e9bb17e 100644 --- a/subsys/virtualization/vm_irq.c +++ b/subsys/virtualization/vm_irq.c @@ -62,6 +62,7 @@ static int vm_virq_desc_init(struct vm *vm) desc->pirq_num = i; desc->id = VM_INVALID_DESC_ID; desc->virq_states = VIRQ_STATE_INVALID; + desc->type = 0; sys_dnode_init(&(desc->desc_node)); } diff --git a/subsys/virtualization/vm_manager.c b/subsys/virtualization/vm_manager.c index bc2c17ab816b29290a22db9869041ef24cf0d765..427822570b02fe5eb171cfa0e54b487badb1c5f5 100644 --- a/subsys/virtualization/vm_manager.c +++ b/subsys/virtualization/vm_manager.c @@ -44,58 +44,64 @@ int zvm_new_guest(size_t argc, char **argv) ZVM_LOG_WARN("Can not create vm struct, VM struct init failed!\n"); return ret; } + ZVM_LOG_INFO("** Create VM instance successful! \n"); ret = vm_ops_init(new_vm); if (ret) { ZVM_LOG_WARN("VM ops init failed!\n"); return ret; } + ZVM_LOG_INFO("** Init VM ops successful! \n"); ret = vm_irq_block_init(new_vm); if (ret < 0) { ZVM_LOG_WARN(" Init vm's irq block error!\n"); return ret; } + ZVM_LOG_INFO("** Init VM irq block successful! \n"); ret = vm_vcpus_init(new_vm); if (ret < 0) { ZVM_LOG_WARN("create vcpu error! \n"); return -ENXIO; } + ZVM_LOG_INFO("** Init VM vcpus instances successful! \n"); ret = vm_device_init(new_vm); if (ret) { ZVM_LOG_WARN(" Init vm's virtual device error! \n"); return ret; } + ZVM_LOG_INFO("** Init VM devices successful! \n"); ret = vm_mem_init(new_vm); if(ret < 0){ return ret; } + ZVM_LOG_INFO("** Init VM memory successful! \n"); k_free(vm_info); - ZVM_LOG_INFO("\n|*********************************************|\n"); - ZVM_LOG_INFO("|******\t Create vm successful! **************| \n"); - ZVM_LOG_INFO("|******\t\t VM INFO \t \t******| \n"); - ZVM_LOG_INFO("|******\t VM-NAME: %s \t******| \n", new_vm->vm_name); - ZVM_LOG_INFO("|******\t VM-ID: \t %d \t\t******| \n", new_vm->vmid); - ZVM_LOG_INFO("|******\t VCPU NUM: \t %d \t\t******| \n", new_vm->vcpu_num); + ZVM_PRINTK("\n|*********************************************|\n"); + ZVM_PRINTK("|******\t Create vm successful! **************| \n"); + ZVM_PRINTK("|******\t\t VM INFO \t \t******| \n"); + ZVM_PRINTK("|******\t VM-NAME: %s \t******| \n", new_vm->vm_name); + ZVM_PRINTK("|******\t VM-ID: \t %d \t\t******| \n", new_vm->vmid); + ZVM_PRINTK("|******\t VCPU NUM: \t %d \t\t******| \n", new_vm->vcpu_num); switch (new_vm->os->type) { case OS_TYPE_LINUX: - ZVM_LOG_INFO("|******\t VMEM SIZE: \t %d(M) \t******| \n", + ZVM_PRINTK("|******\t VMEM SIZE: \t %d(M) \t******| \n", LINUX_VMSYS_SIZE/(1024*1024)); break; case OS_TYPE_ZEPHYR: - ZVM_LOG_INFO("|******\t VMEM SIZE: \t %d(M) \t\t******| \n", + ZVM_PRINTK("|******\t VMEM SIZE: \t %d(M) \t\t******| \n", ZEPHYR_VMSYS_SIZE/(1024*1024)); break; default: - ZVM_LOG_INFO("|******\t OTHER VM, NO MEMORY MSG \t\t******| \n"); + ZVM_PRINTK("|******\t OTHER VM, NO MEMORY MSG \t\t******| \n"); } - ZVM_LOG_INFO("|*********************************************|\n"); + ZVM_PRINTK("|*********************************************|\n"); return 0; } @@ -107,6 +113,7 @@ int zvm_run_guest(size_t argc, char **argv) int ret = 0; struct vm *vm; + ZVM_LOG_INFO("** Ready to run VM. \n"); vm_id = z_parse_run_vm_args(argc, argv, state); if (!(BIT(vm_id) & zvm_overall_info->alloced_vmid)) { ZVM_LOG_WARN("This vmid is not exist!\n Please input zvm info to show info! \n"); @@ -129,13 +136,13 @@ int zvm_run_guest(size_t argc, char **argv) return -ENODEV; } - ZVM_LOG_INFO("\n|*********************************************|\n"); - ZVM_LOG_INFO("|******\t Start vm successful! ***************| \n"); - ZVM_LOG_INFO("|******\t\t VM INFO \t \t******| \n"); - ZVM_LOG_INFO("|******\t VM-NAME: %s \t******| \n", vm->vm_name); - ZVM_LOG_INFO("|******\t VM-ID: \t %d \t\t******| \n", vm->vmid); - ZVM_LOG_INFO("|******\t VCPU NUM: \t %d \t\t******| \n", vm->vcpu_num); - ZVM_LOG_INFO("|*********************************************|\n"); + ZVM_PRINTK("\n|*********************************************|\n"); + ZVM_PRINTK("|******\t Start vm successful! ***************| \n"); + ZVM_PRINTK("|******\t\t VM INFO \t \t******| \n"); + ZVM_PRINTK("|******\t VM-NAME: %s \t******| \n", vm->vm_name); + ZVM_PRINTK("|******\t VM-ID: \t %d \t\t******| \n", vm->vmid); + ZVM_PRINTK("|******\t VCPU NUM: \t %d \t\t******| \n", vm->vcpu_num); + ZVM_PRINTK("|*********************************************|\n"); return ret; } @@ -183,15 +190,15 @@ int zvm_delete_guest(size_t argc, char **argv) vm = zvm_overall_info->vms[vm_id]; switch (vm->vm_status) { case VM_STATE_RUNNING: - ZVM_LOG_INFO("This vm is running!\n Try to stop and delete it!\n"); + ZVM_PRINTK("This vm is running!\n Try to stop and delete it!\n"); vm_vcpus_halt(vm); break; case VM_STATE_PAUSE: - ZVM_LOG_INFO("This vm is paused!\n Just delete it!\n"); + ZVM_PRINTK("This vm is paused!\n Just delete it!\n"); vm_delete(vm); break; case VM_STATE_NEVER_RUN: - ZVM_LOG_INFO("This vm is created but not run!\n Just delete it!\n"); + ZVM_PRINTK("This vm is created but not run!\n Just delete it!\n"); vm_delete(vm); break; default: diff --git a/subsys/virtualization/vm_mm.c b/subsys/virtualization/vm_mm.c index cd3b38af81b08c68a4dbbcf80f7aae7474482048..9d73ad5da0941a52b97b47cc66aaada505e93028 100644 --- a/subsys/virtualization/vm_mm.c +++ b/subsys/virtualization/vm_mm.c @@ -507,7 +507,6 @@ int vm_mem_domain_partitions_add(struct vm_mem_domain *vmem_dm) key = k_spin_lock(&vmem_dm->spin_mmlock); SYS_DLIST_FOR_EACH_NODE_SAFE(&vmem_dm->idle_vpart_list, d_node, ds_node){ vpart = CONTAINER_OF(d_node, struct vm_mem_partition, vpart_node); - ret = vm_mem_domain_partition_add(vmem_dm, vpart); if (ret) { k_spin_unlock(&vmem_dm->spin_mmlock, key); diff --git a/zvm_config/rk3568_platform/Image b/zvm_config/rk3568_platform/Image new file mode 100644 index 0000000000000000000000000000000000000000..88f57f64bd3be48c15a7eb662c17ac262a71933a Binary files /dev/null and b/zvm_config/rk3568_platform/Image differ diff --git a/zvm_config/rk3568_platform/firefly-roc-rk3568-pc.dts b/zvm_config/rk3568_platform/firefly-roc-rk3568-pc.dts new file mode 100644 index 0000000000000000000000000000000000000000..c2aa88ce9d07c127d5eb3f5273ca866c5f2c29ef --- /dev/null +++ b/zvm_config/rk3568_platform/firefly-roc-rk3568-pc.dts @@ -0,0 +1,375 @@ +/dts-v1/; + +/ { + compatible = "rockchip,rk3568-firefly-roc-pc\0rockchip,rk3568"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Firefly RK3568-ROC-PC SIMPLE (Linux)"; + + aliases { + gpio0 = "/pinctrl/gpio@fdd60000"; + gpio1 = "/pinctrl/gpio@fe740000"; + gpio2 = "/pinctrl/gpio@fe750000"; + gpio3 = "/pinctrl/gpio@fe760000"; + gpio4 = "/pinctrl/gpio@fe770000"; + i2c0 = "/i2c@fdd40000"; + i2c1 = "/i2c@fe5a0000"; + i2c2 = "/i2c@fe5b0000"; + i2c3 = "/i2c@fe5c0000"; + i2c4 = "/i2c@fe5d0000"; + i2c5 = "/i2c@fe5e0000"; + serial0 = "/serial@fdd50000"; + serial1 = "/serial@fe650000"; + serial2 = "/serial@fe660000"; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <0x0a 0x0b 0x0c>; + nvmem-cell-names = "id\0cpu-version\0cpu-code"; + }; + + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + arm,no-tick-in-suspend; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + phandle = <0x160>; + }; + + + interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + + interrupt-controller@fd440000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <0x01>; + reg = <0x00 0xfd440000 0x00 0x20000>; + status = "okay"; + phandle = <0xab>; + }; + }; + + + syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc20000 0x00 0x10000>; + phandle = <0x31>; + + io-domains { + compatible = "rockchip,rk3568-pmu-io-voltage-domain"; + status = "okay"; + pmuio1-supply = <0x27>; + pmuio2-supply = <0x27>; + vccio1-supply = <0x28>; + vccio3-supply = <0x29>; + vccio4-supply = <0x2a>; + vccio5-supply = <0x2b>; + vccio6-supply = <0x2a>; + vccio7-supply = <0x2b>; + phandle = <0x16e>; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = <0x5242c301>; + mode-charge = <0x5242c30b>; + mode-fastboot = <0x5242c309>; + mode-loader = <0x5242c301>; + mode-normal = <0x5242c300>; + mode-recovery = <0x5242c303>; + mode-ums = <0x5242c30c>; + mode-panic = <0x5242c307>; + mode-watchdog = <0x5242c308>; + phandle = <0x16f>; + }; + }; + + + syscon@fdc60000 { + compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc60000 0x00 0x10000>; + phandle = <0x30>; + + io-domains { + compatible = "rockchip,rk3568-io-voltage-domain"; + status = "disabled"; + phandle = <0x170>; + }; + }; + + clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x00 0xfdd00000 0x00 0x1000>; + rockchip,grf = <0x30>; + rockchip,pmugrf = <0x31>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x2f 0x32>; + assigned-clock-parents = <0x2f 0x05>; + phandle = <0x2f>; + }; + + clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x00 0xfdd20000 0x00 0x1000>; + rockchip,grf = <0x30>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x2f 0x05 0x1c 0x106 0x1c 0x10b 0x2f 0x01 0x2f 0x2b 0x1c 0x03 0x1c 0x19b 0x1c 0x09 0x1c 0x19c 0x1c 0x19d 0x1c 0x1a1 0x1c 0x19e 0x1c 0x19f 0x1c 0x1a0 0x1c 0x04 0x1c 0x10d 0x1c 0x10e 0x1c 0x173 0x1c 0x174 0x1c 0x175 0x1c 0x176 0x1c 0xc9 0x1c 0xca 0x1c 0x06 0x1c 0x7e 0x1c 0x7f 0x1c 0x3d 0x1c 0x41 0x1c 0x45 0x1c 0x49 0x1c 0x4d 0x1c 0x4d 0x1c 0x55 0x1c 0x51 0x1c 0x5d 0x1c 0xdd>; + assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; + assigned-clock-parents = <0x2f 0x08 0x1c 0x04 0x1c 0x04>; + phandle = <0x1c>; + }; + + sdhci@fe310000 { + compatible = "rockchip,dwcmshc-sdhci\0snps,dwcmshc-sdhci"; + reg = <0x00 0xfe310000 0x00 0x10000>; + interrupts = <0x00 0x13 0x04>; + assigned-clocks = <0x1c 0x7b 0x1c 0x7d 0x1c 0x7c>; + assigned-clock-rates = <0xbebc200 0x16e3600 0xbebc200>; + clocks = <0x1c 0x7c 0x1c 0x7a 0x1c 0x79 0x1c 0x7b 0x1c 0x7d>; + clock-names = "core\0bus\0axi\0block\0timer"; + status = "okay"; + bus-width = <0x08>; + supports-emmc; + non-removable; + max-frequency = <0xbebc200>; + phandle = <0x1b0>; + }; + + otp@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x00 0xfe38c000 0x00 0x4000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + clocks = <0x1c 0x73 0x1c 0x72 0x1c 0x71 0x1c 0x181>; + clock-names = "usr\0sbpi\0apb\0phy"; + resets = <0x1c 0x1cf>; + reset-names = "otp_phy"; + phandle = <0x1b4>; + + cpu-code@2 { + reg = <0x02 0x02>; + phandle = <0x0c>; + }; + + cpu-version@8 { + reg = <0x08 0x01>; + bits = <0x03 0x03>; + phandle = <0x0b>; + }; + + mbist-vmin@9 { + reg = <0x09 0x01>; + bits = <0x00 0x04>; + phandle = <0x08>; + }; + + id@a { + reg = <0x0a 0x10>; + phandle = <0x0a>; + }; + + cpu-leakage@1a { + reg = <0x1a 0x01>; + phandle = <0x06>; + }; + + log-leakage@1b { + reg = <0x1b 0x01>; + phandle = <0xa9>; + }; + + core-pvtm@2a { + reg = <0x2a 0x02>; + phandle = <0x07>; + }; + }; + + serial@fe650000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe650000 0x00 0x100>; + interrupts = <0x00 0x75 0x04>; + clocks = <0x1c 0x11f 0x1c 0x11c>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x41 0x02 0x41 0x03>; + pinctrl-names = "default"; + pinctrl-0 = <0xf6>; + status = "disabled"; + phandle = <0x1cf>; + }; + + serial@fe660000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe660000 0x00 0x100>; + interrupts = <0x00 0x76 0x04>; + clocks = <0x1c 0x123 0x1c 0x120>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + dmas = <0x41 0x04 0x41 0x05>; + pinctrl-names = "default"; + pinctrl-0 = <0xf7>; + status = "disabled"; + phandle = <0x1d0>; + }; + + + pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <0x30>; + rockchip,pmu = <0x31>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + phandle = <0x11e>; + + + pcfg-pull-up { + bias-pull-up; + phandle = <0x121>; + }; + + pcfg-pull-down { + bias-pull-down; + phandle = <0x128>; + }; + + uart0 { + + uart0-xfer { + rockchip,pins = <0x00 0x10 0x03 0x121 0x00 0x11 0x03 0x121>; + phandle = <0x42>; + }; + }; + + uart1 { + + uart1m0-xfer { + rockchip,pins = <0x02 0x0b 0x02 0x121 0x02 0x0c 0x02 0x121>; + phandle = <0xf6>; + }; + }; + + uart2 { + + uart2m0-xfer { + rockchip,pins = <0x00 0x18 0x01 0x121 0x00 0x19 0x01 0x121>; + phandle = <0xf7>; + }; + }; + + uart3 { + + uart3m1-xfer { + rockchip,pins = <0x03 0x10 0x04 0x121 0x03 0x0f 0x04 0x121>; + phandle = <0xf8>; + }; + }; + + uart4 { + + uart4m1-xfer { + rockchip,pins = <0x03 0x09 0x04 0x121 0x03 0x0a 0x04 0x121>; + phandle = <0xf9>; + }; + }; + + uart5 { + + uart5m0-xfer { + rockchip,pins = <0x02 0x01 0x03 0x121 0x02 0x02 0x03 0x121>; + phandle = <0xfa>; + }; + }; + + uart6 { + + uart6m0-xfer { + rockchip,pins = <0x02 0x03 0x03 0x121 0x02 0x04 0x03 0x121>; + phandle = <0xfb>; + }; + }; + + uart7 { + + uart7m0-xfer { + rockchip,pins = <0x02 0x05 0x03 0x121 0x02 0x06 0x03 0x121>; + phandle = <0xfc>; + }; + }; + + + }; + + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x02>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <0x16e360>; + interrupts = <0x00 0xfc 0x08>; + pinctrl-names = "default"; + pinctrl-0 = <0xf7>; + status = "okay"; + }; + + + __symbols__ { + xin24m = "/xin24m"; + gic = "/interrupt-controller@fd400000"; + its = "/interrupt-controller@fd400000/interrupt-controller@fd440000"; + pmugrf = "/syscon@fdc20000"; + pmu_io_domains = "/syscon@fdc20000/io-domains"; + reboot_mode = "/syscon@fdc20000/reboot-mode"; + grf = "/syscon@fdc60000"; + io_domains = "/syscon@fdc60000/io-domains"; + pmucru = "/clock-controller@fdd00000"; + cru = "/clock-controller@fdd20000"; + sdhci = "/sdhci@fe310000"; + otp = "/otp@fe38c000"; + cpu_code = "/otp@fe38c000/cpu-code@2"; + otp_cpu_version = "/otp@fe38c000/cpu-version@8"; + mbist_vmin = "/otp@fe38c000/mbist-vmin@9"; + otp_id = "/otp@fe38c000/id@a"; + cpu_leakage = "/otp@fe38c000/cpu-leakage@1a"; + log_leakage = "/otp@fe38c000/log-leakage@1b"; + core_pvtm = "/otp@fe38c000/core-pvtm@2a"; + uart1 = "/serial@fe650000"; + uart2 = "/serial@fe660000"; + pinctrl = "/pinctrl"; + pcfg_pull_up = "/pinctrl/pcfg-pull-up"; + pcfg_pull_down = "/pinctrl/pcfg-pull-down"; + uart0_xfer = "/pinctrl/uart0/uart0-xfer"; + uart1m0_xfer = "/pinctrl/uart1/uart1m0-xfer"; + uart2m0_xfer = "/pinctrl/uart2/uart2m0-xfer"; + uart3m1_xfer = "/pinctrl/uart3/uart3m1-xfer"; + uart4m1_xfer = "/pinctrl/uart4/uart4m1-xfer"; + uart5m0_xfer = "/pinctrl/uart5/uart5m0-xfer"; + uart6m0_xfer = "/pinctrl/uart6/uart6m0-xfer"; + uart7m0_xfer = "/pinctrl/uart7/uart7m0-xfer"; + uart8m0_xfer = "/pinctrl/uart8/uart8m0-xfer"; + }; +}; diff --git a/zvm_config/rk3568_platform/rk3568-firefly-roc-pc-simple.dtb b/zvm_config/rk3568_platform/rk3568-firefly-roc-pc-simple.dtb new file mode 100644 index 0000000000000000000000000000000000000000..38a9aaa99f6e2d09db7a6a8e63a8156fc69e6efe Binary files /dev/null and b/zvm_config/rk3568_platform/rk3568-firefly-roc-pc-simple.dtb differ diff --git a/zvm_config/rk3568_platform/rk3568-firefly-roc-pc-simple.dts b/zvm_config/rk3568_platform/rk3568-firefly-roc-pc-simple.dts new file mode 100644 index 0000000000000000000000000000000000000000..c66e06a68b753173ac94ea2ca0a9807c6da9db12 --- /dev/null +++ b/zvm_config/rk3568_platform/rk3568-firefly-roc-pc-simple.dts @@ -0,0 +1,134 @@ +/dts-v1/; + +/ { + compatible = "rockchip,rk3568-firefly-roc-pc\0rockchip,rk3568"; + interrupt-parent = <0x01>; + #address-cells = <0x02>; + #size-cells = <0x02>; + model = "Firefly RK3568-ROC-PC SIMPLE (Linux)"; + + aliases { + serial2 = "/serial@fe660000"; + }; + + memory@40000000 { + compatible = "linux,usable-memory"; + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + enable-method = "psci"; + reg = <0x0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <0x01 0x0d 0xf04 0x01 0x0e 0xf04 0x01 0x0b 0xf04 0x01 0x0a 0xf04>; + arm,no-tick-in-suspend; + }; + + xin24m { + compatible = "fixed-clock"; + #clock-cells = <0x00>; + clock-frequency = <0x16e3600>; + clock-output-names = "xin24m"; + phandle = <0x160>; + }; + + interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <0x03>; + #address-cells = <0x02>; + #size-cells = <0x02>; + ranges; + interrupt-controller; + reg = <0x00 0xfd400000 0x00 0x10000 0x00 0xfd460000 0x00 0xc0000>; + interrupts = <0x01 0x09 0x04>; + phandle = <0x01>; + }; + + /* system configure space(pmugrf), do not delete */ + syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc20000 0x00 0x10000>; + phandle = <0x31>; + }; + /* system configure space(grf), do not delete */ + syscon@fdc60000 { + compatible = "rockchip,rk3568-grf\0syscon\0simple-mfd"; + reg = <0x00 0xfdc60000 0x00 0x10000>; + phandle = <0x30>; + }; + + /* system clock controler(pmucru) */ + clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x00 0xfdd00000 0x00 0x1000>; + rockchip,grf = <0x30>; + rockchip,pmugrf = <0x31>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x2f 0x32>; + assigned-clock-parents = <0x2f 0x05>; + phandle = <0x2f>; + }; + /* system clock controler(cru) */ + clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x00 0xfdd20000 0x00 0x1000>; + rockchip,grf = <0x30>; + #clock-cells = <0x01>; + #reset-cells = <0x01>; + assigned-clocks = <0x2f 0x05 0x1c 0x106 0x1c 0x10b 0x2f 0x01 0x2f 0x2b 0x1c 0x03 0x1c 0x19b 0x1c 0x09 0x1c 0x19c 0x1c 0x19d 0x1c 0x1a1 0x1c 0x19e 0x1c 0x19f 0x1c 0x1a0 0x1c 0x04 0x1c 0x10d 0x1c 0x10e 0x1c 0x173 0x1c 0x174 0x1c 0x175 0x1c 0x176 0x1c 0xc9 0x1c 0xca 0x1c 0x06 0x1c 0x7e 0x1c 0x7f 0x1c 0x3d 0x1c 0x41 0x1c 0x45 0x1c 0x49 0x1c 0x4d 0x1c 0x4d 0x1c 0x55 0x1c 0x51 0x1c 0x5d 0x1c 0xdd>; + assigned-clock-rates = <0x8000 0x11e1a300 0x11e1a300 0xbebc200 0x5f5e100 0x3b9aca00 0x1dcd6500 0x13d92d40 0xee6b280 0x7735940 0x5f5e100 0x3b9aca0 0x2faf080 0x17d7840 0x46cf7100 0x8f0d180 0x5f5e100 0x1dcd6500 0x17d78400 0x8f0d180 0x5f5e100 0x11e1a300 0x8f0d180 0x47868c00 0x17d78400 0x5f5e100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x46cf7100 0x1dcd6500>; + assigned-clock-parents = <0x2f 0x08 0x1c 0x04 0x1c 0x04>; + phandle = <0x1c>; + }; + + serial@fe660000 { + compatible = "rockchip,rk3568-uart\0snps,dw-apb-uart"; + reg = <0x00 0xfe660000 0x00 0x100>; + interrupts = <0x00 0x76 0x04>; + clocks = <0x1c 0x123 0x1c 0x120>; + clock-names = "baudclk\0apb_pclk"; + reg-shift = <0x02>; + reg-io-width = <0x04>; + status = "disable"; + phandle = <0x1d0>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0x02>; + rockchip,wake-irq = <0x00>; + rockchip,irq-mode-enable = <0x01>; + rockchip,baudrate = <1500000>; + interrupts = <0x00 0xdc 0x08>; + status = "okay"; + }; + + __symbols__ { + xin24m = "/xin24m"; + gic = "/interrupt-controller@fd400000"; + pmugrf = "/syscon@fdc20000"; + grf = "/syscon@fdc60000"; + pmucru = "/clock-controller@fdd00000"; + cru = "/clock-controller@fdd20000"; + uart2 = "/serial@fe660000"; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; + stdout-path = "/serial@fe660000"; + kaslr-seed = <0xfe5f4802 0xd861995f>; + }; + +};