diff --git a/arch/arm/BUILD.gn b/arch/arm/BUILD.gn index 917a005b9b43fd5294d6d67865296b4c61b196a1..ffb64757d9e6ddc8453067ff2854732419e4c2ad 100644 --- a/arch/arm/BUILD.gn +++ b/arch/arm/BUILD.gn @@ -1,5 +1,5 @@ # Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. -# Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved. +# Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, # are permitted provided that the following conditions are met: @@ -34,10 +34,12 @@ config("arm_config") { } module_group("arm") { - if (defined(LOSCFG_COMPILER_ICCARM)) { + if ("$board_cpu" == "cortex-m4") { + modules = [ "$board_cpu" ] + } else if (defined(LOSCFG_COMPILER_ICCARM)) { modules = [ "$board_cpu/iar" ] } else { modules = [ "$board_cpu/gcc" ] } configs = [ ":arm_config" ] -} +} \ No newline at end of file diff --git a/arch/arm/cortex-m4/gcc/BUILD.gn b/arch/arm/cortex-m4/BUILD.gn similarity index 81% rename from arch/arm/cortex-m4/gcc/BUILD.gn rename to arch/arm/cortex-m4/BUILD.gn index f7ba5104f560ca97d6347c3d075fc109cc0e1385..08dd8686d3df0293c6f70339085719bfe35546fb 100644 --- a/arch/arm/cortex-m4/gcc/BUILD.gn +++ b/arch/arm/cortex-m4/BUILD.gn @@ -1,5 +1,4 @@ -# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. -# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. +# Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. # # Redistribution and use in source and binary forms, with or without modification, # are permitted provided that the following conditions are met: @@ -33,15 +32,29 @@ module_name = "arch" kernel_module(module_name) { sources = [ "los_context.c", - "los_dispatch.S", - "los_exc.S", "los_interrupt.c", "los_mpu.c", "los_timer.c", ] + if (defined(LOSCFG_COMPILER_ICCARM)) { + sources += [ + "./iar/los_dispatch.S", + "./iar/los_exc.S", + ] + } else { + sources += [ + "./gcc/los_dispatch.S", + "./gcc/los_exc.S", + ] + } configs += [ "$LITEOSTOPDIR:warn_config" ] } config("public") { include_dirs = [ "." ] + if (defined(LOSCFG_COMPILER_ICCARM)) { + include_dirs += [ "./iar" ] + } else { + include_dirs += [ "./gcc" ] + } } diff --git a/arch/arm/cortex-m4/gcc/los_arch_interrupt.h b/arch/arm/cortex-m4/gcc/los_arch_interrupt.h deleted file mode 100644 index 326b72f23ab47c830c27eb424165daab69f0bf0d..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/gcc/los_arch_interrupt.h +++ /dev/null @@ -1,683 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _LOS_ARCH_INTERRUPT_H -#define _LOS_ARCH_INTERRUPT_H - -#include "los_config.h" -#include "los_compiler.h" -#include "los_interrupt.h" - -#ifdef __cplusplus -#if __cplusplus -extern "C" { -#endif /* __cplusplus */ -#endif /* __cplusplus */ - -/* * - * @ingroup los_arch_interrupt - * Maximum number of used hardware interrupts. - */ -#ifndef OS_HWI_MAX_NUM -#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT -#endif - -/* * - * @ingroup los_arch_interrupt - * Highest priority of a hardware interrupt. - */ -#ifndef OS_HWI_PRIO_HIGHEST -#define OS_HWI_PRIO_HIGHEST 0 -#endif - -/* * - * @ingroup los_arch_interrupt - * Lowest priority of a hardware interrupt. - */ -#ifndef OS_HWI_PRIO_LOWEST -#define OS_HWI_PRIO_LOWEST 7 -#endif - - -/* * - * @ingroup los_arch_interrupt - * Define the type of a hardware interrupt vector table function. - */ -typedef VOID (**HWI_VECTOR_FUNC)(void); - -/* * - * @ingroup los_arch_interrupt - * Count of interrupts. - */ -extern UINT32 g_intCount; - -/* * - * @ingroup los_arch_interrupt - * Count of M-Core system interrupt vector. - */ -#define OS_SYS_VECTOR_CNT 16 - -/* * - * @ingroup los_arch_interrupt - * Count of M-Core interrupt vector. - */ -#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM) - -/* * - * @ingroup los_arch_interrupt - * AIRCR register priority group parameter . - */ -#define OS_NVIC_AIRCR_PRIGROUP 7 - -/* * - * @ingroup los_arch_interrupt - * Boot interrupt vector table. - */ -extern UINT32 _BootVectors[]; - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: Invalid interrupt number. - * - * Value: 0x02000900 - * - * Solution: Ensure that the interrupt number is valid. - * The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX]. - */ -#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: Null hardware interrupt handling function. - * - * Value: 0x02000901 - * - * Solution: Pass in a valid non-null hardware interrupt handling function. - */ -#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation. - * - * Value: 0x02000902 - * - * Solution: Increase the configured maximum number of supported hardware interrupts. - */ -#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization. - * - * Value: 0x02000903 - * - * Solution: Expand the configured memory. - */ -#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: The interrupt has already been created. - * - * Value: 0x02000904 - * - * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. - */ -#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: Invalid interrupt priority. - * - * Value: 0x02000905 - * - * Solution: Ensure that the interrupt priority is valid. - * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15]. - */ -#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: Incorrect interrupt creation mode. - * - * Value: 0x02000906 - * - * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or - * OS_HWI_MODE_FAST of which the value can be 0 or 1. - */ -#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06) - -/* * - * @ingroup los_arch_interrupt - * Hardware interrupt error code: The interrupt has already been created as a fast interrupt. - * - * Value: 0x02000907 - * - * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created. - */ -#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07) - -/* * - * @ingroup los_arch_interrupt - * SysTick control and status register. - */ -#define OS_SYSTICK_CONTROL_REG 0xE000E010 - -/* * - * @ingroup los_hw - * SysTick current value register. - */ -#define OS_SYSTICK_CURRENT_REG 0xE000E018 - -/* * - * @ingroup los_arch_interrupt - * Interrupt Priority-Level Registers. - */ -#define OS_NVIC_PRI_BASE 0xE000E400 - -/* * - * @ingroup los_arch_interrupt - * Interrupt enable register for 0-31. - */ -#define OS_NVIC_SETENA_BASE 0xE000E100 - -/* * - * @ingroup los_arch_interrupt - * interrupt pending register. - */ -#define OS_NVIC_SETPEND_BASE 0xE000E200 - -/* * - * @ingroup los_arch_interrupt - * Interrupt active register. - */ -#define OS_NVIC_INT_ACT_BASE 0xE000E300 - -/* * - * @ingroup los_arch_interrupt - * Interrupt disable register for 0-31. - */ -#define OS_NVIC_CLRENA_BASE 0xE000E180 - -/* * - * @ingroup los_arch_interrupt - * Interrupt control and status register. - */ -#define OS_NVIC_INT_CTRL 0xE000ED04 - -/* * - * @ingroup los_arch_interrupt - * Vector table offset register. - */ -#define OS_NVIC_VTOR 0xE000ED08 - -/* * - * @ingroup los_arch_interrupt - * Application interrupt and reset control register - */ -#define OS_NVIC_AIRCR 0xE000ED0C - -/* * - * @ingroup los_arch_interrupt - * System exception priority register. - */ -#define OS_NVIC_EXCPRI_BASE 0xE000ED18 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 1 :reset. - */ -#define OS_EXC_RESET 1 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 2 :Non-Maskable Interrupt. - */ -#define OS_EXC_NMI 2 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 3 :(hard)fault. - */ -#define OS_EXC_HARD_FAULT 3 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 4 :MemManage fault. - */ -#define OS_EXC_MPU_FAULT 4 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 5 :Bus fault. - */ -#define OS_EXC_BUS_FAULT 5 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 6 :Usage fault. - */ -#define OS_EXC_USAGE_FAULT 6 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 11 :SVCall. - */ -#define OS_EXC_SVC_CALL 11 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 12 :Debug monitor. - */ -#define OS_EXC_DBG_MONITOR 12 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 14 :PendSV. - */ -#define OS_EXC_PEND_SV 14 - -/* * - * @ingroup los_arch_interrupt - * Interrupt No. 15 :SysTick. - */ -#define OS_EXC_SYS_TICK 15 - -#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1) -/* * - * @ingroup los_arch_interrupt - * Set interrupt vector table. - */ -extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg); -#else -/* * - * @ingroup los_arch_interrupt - * Set interrupt vector table. - */ -extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector); -#endif - -/* * - * @ingroup los_arch_interrupt - * @brief: Hardware interrupt entry function. - * - * @par Description: - * This API is used as all hardware interrupt handling function entry. - * - * @attention: - * - * - * @param:None. - * - * @retval:None. - * @par Dependency: - * - * @see None. - */ -extern VOID HalInterrupt(VOID); - -/* * - * @ingroup los_arch_interrupt - * @brief: Default vector handling function. - * - * @par Description: - * This API is used to configure interrupt for null function. - * - * @attention: - * - * - * @param:None. - * - * @retval:None. - * @par Dependency: - * - * @see None. - */ -extern VOID HalHwiDefaultHandler(VOID); - -/* * - * @ingroup los_arch_interrupt - * @brief: Reset the vector table. - * - * @par Description: - * This API is used to reset the vector table. - * - * @attention: - * - * - * @param:None. - * - * @retval:None. - * @par Dependency: - * - * @see None. - */ -extern VOID Reset_Handler(VOID); - -/* * - * @ingroup los_arch_interrupt - * @brief: Pended System Call. - * - * @par Description: - * PendSV can be pended and is useful for an OS to pend an exception - * so that an action can be performed after other important tasks are completed. - * - * @attention: - * - * - * @param:None. - * - * @retval:None. - * @par Dependency: - * - * @see None. - */ -extern VOID HalPendSV(VOID); - - -#define OS_EXC_IN_INIT 0 -#define OS_EXC_IN_TASK 1 -#define OS_EXC_IN_HWI 2 - -#define OS_EXC_MAX_BUF_LEN 25 -#define OS_EXC_MAX_NEST_DEPTH 1 - -#define OS_NVIC_SHCSR 0xE000ED24 -#define OS_NVIC_CCR 0xE000ED14 - -#define OS_NVIC_INT_ENABLE_SIZE 0x20 -#define OS_NVIC_INT_PRI_SIZE 0xF0 -#define OS_NVIC_EXCPRI_SIZE 0xC -#define OS_NVIC_INT_CTRL_SIZE 4 -#define OS_NVIC_SHCSR_SIZE 4 - -#define OS_NVIC_INT_PEND_SIZE OS_NVIC_INT_ACT_SIZE -#define OS_NVIC_INT_ACT_SIZE OS_NVIC_INT_ENABLE_SIZE - -#define OS_EXC_FLAG_NO_FLOAT 0x10000000 -#define OS_EXC_FLAG_FAULTADDR_VALID 0x01 -#define OS_EXC_FLAG_IN_HWI 0x02 - -#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB - -#define OS_EXC_EVENT 0x00000001 - -/** - * @ingroup los_exc - * the struct of register files - * - * description: the register files that saved when exception triggered - * - * notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet. - */ -typedef struct TagExcContext { -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - UINT32 S16; - UINT32 S17; - UINT32 S18; - UINT32 S19; - UINT32 S20; - UINT32 S21; - UINT32 S22; - UINT32 S23; - UINT32 S24; - UINT32 S25; - UINT32 S26; - UINT32 S27; - UINT32 S28; - UINT32 S29; - UINT32 S30; - UINT32 S31; -#endif - UINT32 uwR4; - UINT32 uwR5; - UINT32 uwR6; - UINT32 uwR7; - UINT32 uwR8; - UINT32 uwR9; - UINT32 uwR10; - UINT32 uwR11; - UINT32 uwPriMask; - /* auto save */ - UINT32 uwSP; - UINT32 uwR0; - UINT32 uwR1; - UINT32 uwR2; - UINT32 uwR3; - UINT32 uwR12; - UINT32 uwLR; - UINT32 uwPC; - UINT32 uwxPSR; -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED) && (__FPU_USED== 1U))) - UINT32 S0; - UINT32 S1; - UINT32 S2; - UINT32 S3; - UINT32 S4; - UINT32 S5; - UINT32 S6; - UINT32 S7; - UINT32 S8; - UINT32 S9; - UINT32 S10; - UINT32 S11; - UINT32 S12; - UINT32 S13; - UINT32 S14; - UINT32 S15; - UINT32 FPSCR; - UINT32 NO_NAME; -#endif -} EXC_CONTEXT_S; - -typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *); -VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr); - -VOID HalExcNMI(VOID); -VOID HalExcHardFault(VOID); -VOID HalExcMemFault(VOID); -VOID HalExcBusFault(VOID); -VOID HalExcUsageFault(VOID); -VOID HalExcSvcCall(VOID); -VOID HalHwiInit(VOID); - -/** - * @ingroup los_exc - * Cortex-M exception types: An error occurred while the bus status register was being pushed. - */ -#define OS_EXC_BF_STKERR 1 - -/** - * @ingroup los_exc - * Cortex-M exception types: An error occurred while the bus status register was out of the stack. - */ -#define OS_EXC_BF_UNSTKERR 2 - -/** - * @ingroup los_exc - * Cortex-M exception types: Bus status register imprecise data access violation. - */ -#define OS_EXC_BF_IMPRECISERR 3 - -/** - * @ingroup los_exc - * Cortex-M exception types: Bus status register exact data access violation. - */ -#define OS_EXC_BF_PRECISERR 4 - -/** - * @ingroup los_exc - * Cortex-M exception types: Bus status register access violation while pointing. - */ -#define OS_EXC_BF_IBUSERR 5 - -/** - * @ingroup los_exc - * Cortex-M exception types: An error occurred while the memory management status register was being pushed. - */ -#define OS_EXC_MF_MSTKERR 6 - -/** - * @ingroup los_exc - * Cortex-M exception types: An error occurred while the memory management status register was out of the stack. - */ -#define OS_EXC_MF_MUNSTKERR 7 - -/** - * @ingroup los_exc - * Cortex-M exception types: Memory management status register data access violation. - */ -#define OS_EXC_MF_DACCVIOL 8 - -/** - * @ingroup los_exc - * Cortex-M exception types: Memory management status register access violation. - */ -#define OS_EXC_MF_IACCVIOL 9 - - -/** - * @ingroup los_exc - * Cortex-M exception types: Incorrect usage indicating that the divisor is zero during the division operation. - */ -#define OS_EXC_UF_DIVBYZERO 10 - -/** - * @ingroup los_exc - * Cortex-M exception types: Usage error, error caused by unaligned access. - */ -#define OS_EXC_UF_UNALIGNED 11 - -/** - * @ingroup los_exc - * Cortex-M exception types: Incorrect usage attempting to execute coprocessor related instruction. - */ -#define OS_EXC_UF_NOCP 12 - -/** - * @ingroup los_exc - * Cortex-M exception types: Usage error attempting to load EXC_RETURN to PC illegally on exception return. - */ -#define OS_EXC_UF_INVPC 13 - -/** - * @ingroup los_exc - * Cortex-M exception types: Incorrect usage, attempting to cut to ARM state. - */ -#define OS_EXC_UF_INVSTATE 14 - -/** - * @ingroup los_exc - * Cortex-M exception types: Incorrect usage. Executed instruction whose code is undefined. - */ -#define OS_EXC_UF_UNDEFINSTR 15 - -/** - * @ingroup los_exc - * Cortex-M exception types: NMI - */ - -#define OS_EXC_CAUSE_NMI 16 - -/** - * @ingroup los_exc - * Cortex-M exception types: hard fault - */ -#define OS_EXC_CAUSE_HARDFAULT 17 - -/** - * @ingroup los_exc - * Cortex-M exception types: The task handler exits. - */ -#define OS_EXC_CAUSE_TASK_EXIT 18 - -/** - * @ingroup los_exc - * Cortex-M exception types: A fatal error. - */ -#define OS_EXC_CAUSE_FATAL_ERR 19 - -/** - * @ingroup los_exc - * Cortex-M exception types: Hard Fault caused by a debug event. - */ -#define OS_EXC_CAUSE_DEBUGEVT 20 - -/** - * @ingroup los_exc - * Cortex-M exception types: A hard fault that occurs when a quantity is oriented. - */ -#define OS_EXC_CAUSE_VECTBL 21 - -/** - * @ingroup los_exc - * Exception information structure - * - * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform. - * - */ -typedef struct TagExcInfo { - /**< Exception occurrence phase: 0 means that an exception occurs in initialization, - * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */ - UINT16 phase; - /**< Exception type. When exceptions occur, check the numbers 1 - 21 listed above */ - UINT16 type; - /**< If the exact address access error indicates the wrong access address when the exception occurred */ - UINT32 faultAddr; - /**< An exception occurs in an interrupt, indicating the interrupt number. - * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */ - UINT32 thrdPid; - /**< Number of nested exceptions. Currently only registered hook functions are supported - * when an exception is entered for the first time */ - UINT16 nestCnt; - /**< reserve */ - UINT16 reserved; - /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */ - EXC_CONTEXT_S *context; -} ExcInfo; - -extern UINT32 g_curNestCount; -extern UINT32 g_intCount; -extern UINT8 g_uwExcTbl[32]; -extern ExcInfo g_excInfo; - -#define MAX_INT_INFO_SIZE (8 + 0x164) - -#ifdef __cplusplus -#if __cplusplus -} -#endif /* __cplusplus */ -#endif /* __cplusplus */ - -#endif /* _LOS_ARCH_INTERRUPT_H */ diff --git a/arch/arm/cortex-m4/gcc/los_arch_timer.h b/arch/arm/cortex-m4/gcc/los_arch_timer.h deleted file mode 100644 index 2b2c41f94dfe74e70412ce94c468eebc3768bb84..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/gcc/los_arch_timer.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _LOS_ARCH_TIMER_H -#define _LOS_ARCH_TIMER_H - -#include "los_config.h" -#include "los_compiler.h" -#include "los_timer.h" - -#ifdef __cplusplus -#if __cplusplus -extern "C" { -#endif /* __cplusplus */ -#endif /* __cplusplus */ - -#ifdef __cplusplus -#if __cplusplus -} -#endif /* __cplusplus */ -#endif /* __cplusplus */ - -#endif /* _LOS_ARCH_TIMER_H */ diff --git a/arch/arm/cortex-m4/gcc/los_mpu.c b/arch/arm/cortex-m4/gcc/los_mpu.c deleted file mode 100644 index 8d1dc25b1931e63a661864aa2f85d18fac1ed760..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/gcc/los_mpu.c +++ /dev/null @@ -1,237 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "los_mpu.h" -#include "los_config.h" -#include "los_context.h" - -#if (LOSCFG_MPU_ENABLE == 1) - -#define SIZE_4G_BYTE 0x100000000 -#define MPU_MAX_REGION_NUM 8 - -STATIC UINT8 g_regionNumBeUsed[MPU_MAX_REGION_NUM] = {0}; - -typedef enum { - MPU_AP_FORBID_USER_FORBID = 0x0, /* Privileged:No access Unprivileged:No access */ - MPU_AP_RW_USER_FORBID = 0x1, /* Privileged:Read/Write Unprivileged:No access */ - MPU_AP_RW_USER_RO = 0x2, /* Privileged:Read/Write Unprivileged:Read-only */ - MPU_AP_RW_USER_RW = 0x3, /* Privileged:Read/Write Unprivileged:Read/Write */ - MPU_AP_NA_USER_NA = 0x4, /* Privileged:UNPREDICTABLE Unprivileged:UNPREDICTABLE */ - MPU_AP_RO_USER_FORBID = 0x5, /* Privileged:Read-only Unprivileged:No access */ - MPU_AP_RO_USER_RO = 0x6, /* Privileged:Read-only Unprivileged:Read-only */ -} MpuApConfig; - -VOID ArchMpuEnable(UINT32 defaultRegionEnable) -{ - UINT32 intSave = ArchIntLock(); - MPU->CTRL = (MPU_CTRL_ENABLE_Msk | ((defaultRegionEnable << MPU_CTRL_PRIVDEFENA_Pos) & MPU_CTRL_PRIVDEFENA_Msk)); - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - __DSB(); - __ISB(); - ArchIntRestore(intSave); -} -VOID ArchMpuDisable(VOID) -{ - UINT32 intSave = ArchIntLock(); - MPU->CTRL = 0; - __DSB(); - __ISB(); - ArchIntRestore(intSave); -} - -STATIC VOID HalMpuRASRAddMemAttr(MPU_CFG_PARA *para, UINT32 *RASR) -{ - BOOL cachable = 0; - BOOL buffable = 0; - switch (para->memType) { - case MPU_MEM_ON_CHIP_ROM: - case MPU_MEM_ON_CHIP_RAM: - cachable = 1; - buffable = 0; - break; - case MPU_MEM_XIP_PSRAM: - cachable = 1; - buffable = 1; - break; - case MPU_MEM_XIP_NOR_FLASH: - cachable = 0; - buffable = 1; - break; - default: - break; - } - (*RASR) |= ((cachable << MPU_RASR_C_Pos) | (buffable << MPU_RASR_B_Pos)); -} - -STATIC UINT32 HalMpuEncodeSize(UINT64 size) -{ - UINT32 encodeSize = 0; - if (size > SIZE_4G_BYTE) { - return 0; - } - if ((size & 0x1F) != 0) { /* size should aligned to 32 byte at least. */ - return 0; - } - size = (size >> 2); - while (size != 0) { - if (((size & 1) != 0) && ((size & 0xFFFFFFFE) != 0)) { /* size != 2^x (5 <= x <= 32) 128B - 4GB */ - return 0; - } - size = (size >> 1); - encodeSize++; - } - return encodeSize; -} - -STATIC UINT32 HalMpuEncodeAP(MpuAccessPermission permission) -{ - UINT32 ap; - switch (permission) { - case MPU_RW_BY_PRIVILEGED_ONLY: - ap = MPU_AP_RW_USER_FORBID; - break; - case MPU_RW_ANY: - ap = MPU_AP_RW_USER_RW; - break; - case MPU_RO_BY_PRIVILEGED_ONLY: - ap = MPU_AP_RO_USER_FORBID; - break; - case MPU_RO_ANY: - ap = MPU_AP_RO_USER_RO; - break; - default: - ap = MPU_AP_RW_USER_RW; - break; - } - return ap; -} - -STATIC UINT32 HalMpuGetRASR(UINT32 encodeSize, MPU_CFG_PARA *para) -{ - UINT32 RASR; - UINT32 ap; - ap = HalMpuEncodeAP(para->permission); - RASR = MPU_RASR_ENABLE_Msk; - RASR |= ((encodeSize << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk); - RASR |= ((ap << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | ((para->executable << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | - ((para->shareability << MPU_RASR_S_Pos) & MPU_RASR_S_Msk); - HalMpuRASRAddMemAttr(para, &RASR); - return RASR; -} - -UINT32 ArchMpuSetRegion(UINT32 regionId, MPU_CFG_PARA *para) -{ - UINT32 RASR; - UINT32 RBAR; - UINT32 RNR; - UINT32 encodeSize; - UINT32 intSave; - UINT64 size; - - if ((regionId >= MPU_MAX_REGION_NUM) || (para == NULL)) { - return LOS_NOK; - } - - if ((MPU_TYPE_DREGION_Msk & MPU->TYPE) == 0) { - return LOS_NOK; - } - - RNR = regionId; - encodeSize = HalMpuEncodeSize(para->size); - if (encodeSize == 0) { - return LOS_NOK; - } - size = para->size - 1; /* size aligned after encode check */ - if ((para->baseAddr & size) != 0) { /* base addr should aligned to region size */ - return LOS_NOK; - } - RBAR = para->baseAddr & MPU_RBAR_ADDR_Msk; - RASR = HalMpuGetRASR(encodeSize, para); - intSave = ArchIntLock(); - if (g_regionNumBeUsed[regionId]) { - ArchIntRestore(intSave); - return LOS_NOK; - } - MPU->RNR = RNR; - MPU->RBAR = RBAR; - MPU->RASR = RASR; - __DSB(); - __ISB(); - g_regionNumBeUsed[regionId] = 1; /* Set mpu region used flag */ - ArchIntRestore(intSave); - return LOS_OK; -} - -UINT32 ArchMpuDisableRegion(UINT32 regionId) -{ - volatile UINT32 type; - UINT32 intSave; - - if (regionId >= MPU_MAX_REGION_NUM) { - return LOS_NOK; - } - - intSave = ArchIntLock(); - if (!g_regionNumBeUsed[regionId]) { - ArchIntRestore(intSave); - return LOS_NOK; - } - - type = MPU->TYPE; - if ((MPU_TYPE_DREGION_Msk & type) != 0) { - MPU->RNR = regionId; - MPU->RASR = 0; - __DSB(); - __ISB(); - } - g_regionNumBeUsed[regionId] = 0; /* clear mpu region used flag */ - ArchIntRestore(intSave); - return LOS_OK; -} - -INT32 ArchMpuUnusedRegionGet(VOID) -{ - INT32 id; - UINT32 intSave = ArchIntLock(); - for (id = 0; id < MPU_MAX_REGION_NUM; id++) { - if (!g_regionNumBeUsed[id]) { - break; - } - } - ArchIntRestore(intSave); - - if (id == MPU_MAX_REGION_NUM) { - return -1; - } else { - return id; - } -} -#endif diff --git a/arch/arm/cortex-m4/gcc/los_timer.c b/arch/arm/cortex-m4/gcc/los_timer.c deleted file mode 100644 index 45ae62c5128c30ebc3fb335691ddad6f9c73ea65..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/gcc/los_timer.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "los_timer.h" -#include "los_config.h" -#include "los_tick.h" -#include "los_arch_interrupt.h" -#include "los_debug.h" - -STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler); -STATIC UINT64 SysTickReload(UINT64 nextResponseTime); -STATIC UINT64 SysTickCycleGet(UINT32 *period); -STATIC VOID SysTickLock(VOID); -STATIC VOID SysTickUnlock(VOID); - -STATIC ArchTickTimer g_archTickTimer = { - .freq = 0, - .irqNum = SysTick_IRQn, - .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX, - .init = SysTickStart, - .getCycle = SysTickCycleGet, - .reload = SysTickReload, - .lock = SysTickLock, - .unlock = SysTickUnlock, - .tickHandler = NULL, -}; - -STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler) -{ - UINT32 ret; - ArchTickTimer *tick = &g_archTickTimer; - - tick->freq = OS_SYS_CLOCK; - -#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1) -#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1) - OsSetVector(tick->irqNum, handler, NULL); -#else - OsSetVector(tick->irqNum, handler); -#endif -#endif - - ret = SysTick_Config(LOSCFG_BASE_CORE_TICK_RESPONSE_MAX); - if (ret == 1) { - return LOS_ERRNO_TICK_PER_SEC_TOO_SMALL; - } - - return LOS_OK; -} - -STATIC UINT64 SysTickReload(UINT64 nextResponseTime) -{ - if (nextResponseTime > g_archTickTimer.periodMax) { - nextResponseTime = g_archTickTimer.periodMax; - } - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; - SysTick->LOAD = (UINT32)(nextResponseTime - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - NVIC_ClearPendingIRQ(SysTick_IRQn); - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; - return nextResponseTime; -} - -STATIC UINT64 SysTickCycleGet(UINT32 *period) -{ - UINT32 hwCycle = 0; - UINT32 intSave = LOS_IntLock(); - UINT32 val = SysTick->VAL; - *period = SysTick->LOAD; - if (val != 0) { - hwCycle = *period - val; - } - LOS_IntRestore(intSave); - return (UINT64)hwCycle; -} - -STATIC VOID SysTickLock(VOID) -{ - SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; -} - -STATIC VOID SysTickUnlock(VOID) -{ - SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; -} - -ArchTickTimer *ArchSysTickTimerGet(VOID) -{ - return &g_archTickTimer; -} - -UINT32 ArchEnterSleep(VOID) -{ - __DSB(); - __WFI(); - __ISB(); - - return LOS_OK; -} - diff --git a/arch/arm/cortex-m4/iar/BUILD.gn b/arch/arm/cortex-m4/iar/BUILD.gn deleted file mode 100644 index 57f7c0db79707f5884c683cefd3d35d6b6b131aa..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/iar/BUILD.gn +++ /dev/null @@ -1,47 +0,0 @@ -# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. -# Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without modification, -# are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, this list of -# conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright notice, this list -# of conditions and the following disclaimer in the documentation and/or other materials -# provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific prior written -# permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -import("//kernel/liteos_m/liteos.gni") - -module_name = "arch" -kernel_module(module_name) { - sources = [ - "los_context.c", - "los_dispatch.S", - "los_exc.S", - "los_interrupt.c", - "los_mpu.c", - "los_timer.c", - ] - configs += [ "$LITEOSTOPDIR:warn_config" ] -} - -config("public") { - include_dirs = [ "." ] -} diff --git a/arch/arm/cortex-m4/iar/los_arch_context.h b/arch/arm/cortex-m4/iar/los_arch_context.h deleted file mode 100644 index fa8bc209db9e8d515bf88f429589a4478527b67b..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/iar/los_arch_context.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _LOS_ARCH_CONTEXT_H -#define _LOS_ARCH_CONTEXT_H - -#include "los_config.h" -#include "los_compiler.h" - -#ifdef __cplusplus -#if __cplusplus -extern "C" { -#endif /* __cplusplus */ -#endif /* __cplusplus */ - -typedef struct TagTskContext { -#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined(__FPU_USED) && (__FPU_USED == 1U))) - UINT32 S16; - UINT32 S17; - UINT32 S18; - UINT32 S19; - UINT32 S20; - UINT32 S21; - UINT32 S22; - UINT32 S23; - UINT32 S24; - UINT32 S25; - UINT32 S26; - UINT32 S27; - UINT32 S28; - UINT32 S29; - UINT32 S30; - UINT32 S31; -#endif - UINT32 uwR4; - UINT32 uwR5; - UINT32 uwR6; - UINT32 uwR7; - UINT32 uwR8; - UINT32 uwR9; - UINT32 uwR10; - UINT32 uwR11; - UINT32 uwPriMask; - UINT32 uwR0; - UINT32 uwR1; - UINT32 uwR2; - UINT32 uwR3; - UINT32 uwR12; - UINT32 uwLR; - UINT32 uwPC; - UINT32 uwxPSR; -#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined(__FPU_USED) && (__FPU_USED == 1U))) - UINT32 S0; - UINT32 S1; - UINT32 S2; - UINT32 S3; - UINT32 S4; - UINT32 S5; - UINT32 S6; - UINT32 S7; - UINT32 S8; - UINT32 S9; - UINT32 S10; - UINT32 S11; - UINT32 S12; - UINT32 S13; - UINT32 S14; - UINT32 S15; - UINT32 FPSCR; - UINT32 NO_NAME; -#endif -} TaskContext; - -/** - * @ingroup los_config - * @brief: Task start running function. - * - * @par Description: - * This API is used to start a task. - * - * @attention: - * - * - * @param: None. - * - * @retval None. - * - * @par Dependency: - * - * @see None. - */ -extern VOID HalStartToRun(VOID); - -#ifdef __cplusplus -#if __cplusplus -} -#endif /* __cplusplus */ -#endif /* __cplusplus */ - -#endif /* _LOS_ARCH_CONTEXT_H */ diff --git a/arch/arm/cortex-m4/iar/los_context.c b/arch/arm/cortex-m4/iar/los_context.c deleted file mode 100644 index 1629224cfef06c52c625a128120e2f4404513507..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/iar/los_context.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "los_context.h" -#include "securec.h" -#include "los_arch_context.h" -#include "los_arch_interrupt.h" -#include "los_task.h" -#include "los_sched.h" -#include "los_interrupt.h" -#include "los_timer.h" -#include "los_debug.h" - - -/* **************************************************************************** - Function : ArchInit - Description : arch init function - Input : None - Output : None - Return : None - **************************************************************************** */ -LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID) -{ - HalHwiInit(); -} - -/* **************************************************************************** - Function : ArchSysExit - Description : Task exit function - Input : None - Output : None - Return : None - **************************************************************************** */ -LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID) -{ - (VOID)LOS_IntLock(); - while (1) { - } -} - -/* **************************************************************************** - Function : ArchTskStackInit - Description : Task stack initialization function - Input : taskID --- TaskID - stackSize --- Total size of the stack - topStack --- Top of task's stack - Output : None - Return : Context pointer - **************************************************************************** */ -LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack) -{ - TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext)); - -#if ((defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined(__FPU_USED) && (__FPU_USED == 1U))) - context->S16 = 0xAA000010; - context->S17 = 0xAA000011; - context->S18 = 0xAA000012; - context->S19 = 0xAA000013; - context->S20 = 0xAA000014; - context->S21 = 0xAA000015; - context->S22 = 0xAA000016; - context->S23 = 0xAA000017; - context->S24 = 0xAA000018; - context->S25 = 0xAA000019; - context->S26 = 0xAA00001A; - context->S27 = 0xAA00001B; - context->S28 = 0xAA00001C; - context->S29 = 0xAA00001D; - context->S30 = 0xAA00001E; - context->S31 = 0xAA00001F; - context->S0 = 0xAA000000; - context->S1 = 0xAA000001; - context->S2 = 0xAA000002; - context->S3 = 0xAA000003; - context->S4 = 0xAA000004; - context->S5 = 0xAA000005; - context->S6 = 0xAA000006; - context->S7 = 0xAA000007; - context->S8 = 0xAA000008; - context->S9 = 0xAA000009; - context->S10 = 0xAA00000A; - context->S11 = 0xAA00000B; - context->S12 = 0xAA00000C; - context->S13 = 0xAA00000D; - context->S14 = 0xAA00000E; - context->S15 = 0xAA00000F; - context->FPSCR = 0x00000000; - context->NO_NAME = 0xAA000011; -#endif - - context->uwR4 = 0x04040404L; - context->uwR5 = 0x05050505L; - context->uwR6 = 0x06060606L; - context->uwR7 = 0x07070707L; - context->uwR8 = 0x08080808L; - context->uwR9 = 0x09090909L; - context->uwR10 = 0x10101010L; - context->uwR11 = 0x11111111L; - context->uwPriMask = 0; - context->uwR0 = taskID; - context->uwR1 = 0x01010101L; - context->uwR2 = 0x02020202L; - context->uwR3 = 0x03030303L; - context->uwR12 = 0x12121212L; - context->uwLR = (UINTPTR)ArchSysExit; - context->uwPC = (UINTPTR)OsTaskEntry; - context->uwxPSR = 0x01000000L; - - return (VOID *)context; -} - -VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandler, UINT32 param) -{ - UNUSED(stackTop); - TaskContext *context = (TaskContext *)((UINTPTR)stackPointer - sizeof(TaskContext)); - (VOID)memset_s((VOID *)context, sizeof(TaskContext), 0, sizeof(TaskContext)); - - context->uwR0 = param; - context->uwPC = sigHandler; - context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */ - - return (VOID *)context; -} - -LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID) -{ - (VOID)LOS_IntLock(); - OsSchedStart(); - HalStartToRun(); - return LOS_OK; /* never return */ -} - diff --git a/arch/arm/cortex-m4/iar/los_interrupt.c b/arch/arm/cortex-m4/iar/los_interrupt.c deleted file mode 100644 index 3c2037df4c02cdcdf7e8d85d9e3367e960f4e538..0000000000000000000000000000000000000000 --- a/arch/arm/cortex-m4/iar/los_interrupt.c +++ /dev/null @@ -1,660 +0,0 @@ -/* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list of - * conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this list - * of conditions and the following disclaimer in the documentation and/or other materials - * provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific prior written - * permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, - * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; - * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR - * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "los_interrupt.h" -#include "securec.h" -#include -#include "los_arch_interrupt.h" -#include "los_context.h" -#include "los_debug.h" -#include "los_hook.h" -#include "los_task.h" -#include "los_sched.h" -#include "los_memory.h" -#include "los_membox.h" -#if (LOSCFG_CPUP_INCLUDE_IRQ == 1) -#include "los_cpup.h" -#endif - -UINT32 g_intCount = 0; - -#ifdef __ICCARM__ -#pragma location = ".data.vector" -#pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN -#elif defined(__CC_ARM) || defined(__GNUC__) -LITE_OS_SEC_VEC -#endif -/* * - * @ingroup los_hwi - * Hardware interrupt form mapping handling function array. - */ -STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0}; - -#if (LOSCFG_DEBUG_TOOLS == 1) -STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0}; -STATIC CHAR *g_hwiFormName[OS_HWI_MAX_NUM] = {0}; - -UINT32 OsGetHwiFormCnt(UINT32 index) -{ - return g_hwiFormCnt[index]; -} - -CHAR *OsGetHwiFormName(UINT32 index) -{ - return g_hwiFormName[index]; -} - -BOOL OsGetHwiCreated(UINT32 index) -{ - if (g_hwiForm[index] != (HWI_PROC_FUNC)HalHwiDefaultHandler) { - return TRUE; - } - - return FALSE; -} -#endif - -#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1) - -typedef struct { - HWI_PROC_FUNC pfnHandler; - VOID *pParm; -} HWI_HANDLER_FUNC; - -/* * - * @ingroup los_hwi - * Hardware interrupt handler form mapping handling function array. - */ -STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }}; - -/* * - * @ingroup los_hwi - * Set interrupt vector table. - */ -VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg) -{ - if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) { - g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt; - g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector; - g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg; - } -} - -#else -/* * - * @ingroup los_hwi - * hardware interrupt handler form mapping handling function array. - */ -STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0}; - -/* * - * @ingroup los_hwi - * Set interrupt vector table. - */ -VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector) -{ - if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) { - g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt; - g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector; - } -} -#endif - -WEAK VOID SysTick_Handler(VOID) -{ - return; -} - -/* **************************************************************************** - Function : HwiNumGet - Description : Get an interrupt number - Input : None - Output : None - Return : Interrupt Indexes number - **************************************************************************** */ -STATIC UINT32 HwiNumGet(VOID) -{ - return __get_IPSR(); -} - -STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum) -{ - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - NVIC_EnableIRQ((IRQn_Type)hwiNum); - - return LOS_OK; -} - -STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum) -{ - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - NVIC_DisableIRQ((IRQn_Type)hwiNum); - - return LOS_OK; -} - -STATIC UINT32 HwiSetPriority(HWI_HANDLE_T hwiNum, UINT8 priority) -{ - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - if (priority > OS_HWI_PRIO_LOWEST) { - return OS_ERRNO_HWI_PRIO_INVALID; - } - - NVIC_SetPriority((IRQn_Type)hwiNum, priority); - - return LOS_OK; -} - -STATIC UINT32 HwiPending(HWI_HANDLE_T hwiNum) -{ - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - NVIC_SetPendingIRQ((IRQn_Type)hwiNum); - - return LOS_OK; -} - -STATIC UINT32 HwiClear(HWI_HANDLE_T hwiNum) -{ - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - NVIC_ClearPendingIRQ((IRQn_Type)hwiNum); - - return LOS_OK; -} - -HwiControllerOps g_archHwiOps = { - .enableIrq = HwiUnmask, - .disableIrq = HwiMask, - .setIrqPriority = HwiSetPriority, - .getCurIrqNum = HwiNumGet, - .triggerIrq = HwiPending, - .clearIrq = HwiClear, -}; - -inline UINT32 ArchIsIntActive(VOID) -{ - return (g_intCount > 0); -} -/* **************************************************************************** - Function : HalHwiDefaultHandler - Description : default handler of the hardware interrupt - Input : None - Output : None - Return : None - **************************************************************************** */ -/*lint -e529*/ -LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID) -{ - PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet()); - while (1) {} -} - -WEAK VOID HalPreInterruptHandler(UINT32 arg) -{ - (VOID)arg; - return; -} - -WEAK VOID HalAftInterruptHandler(UINT32 arg) -{ - (VOID)arg; - return; -} - -/* **************************************************************************** - Function : HalInterrupt - Description : Hardware interrupt entry function - Input : None - Output : None - Return : None - **************************************************************************** */ -LITE_OS_SEC_TEXT VOID HalInterrupt(VOID) -{ - UINT32 hwiIndex; - UINT32 intSave; - -#if (LOSCFG_KERNEL_RUNSTOP == 1) - SCB->SCR &= (UINT32) ~((UINT32)SCB_SCR_SLEEPDEEP_Msk); -#endif - - intSave = LOS_IntLock(); - g_intCount++; - LOS_IntRestore(intSave); - - hwiIndex = HwiNumGet(); - - OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex); -#if (LOSCFG_CPUP_INCLUDE_IRQ == 1) - OsCpupIrqStart(hwiIndex); -#endif - - HalPreInterruptHandler(hwiIndex); - -#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1) - if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) { - g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm); - } -#else - if (g_hwiHandlerForm[hwiIndex] != 0) { - g_hwiHandlerForm[hwiIndex](); - } -#endif - -#if (LOSCFG_DEBUG_TOOLS == 1) - ++g_hwiFormCnt[hwiIndex]; -#endif - - HalAftInterruptHandler(hwiIndex); - -#if (LOSCFG_CPUP_INCLUDE_IRQ == 1) - OsCpupIrqEnd(hwiIndex); -#endif - - OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex); - - intSave = LOS_IntLock(); - g_intCount--; - LOS_IntRestore(intSave); -} - -/* **************************************************************************** - Function : ArchHwiCreate - Description : create hardware interrupt - Input : hwiNum --- hwi num to create - hwiPrio --- priority of the hwi - hwiMode --- unused - hwiHandler --- hwi handler - irqParam --- param of the hwi handler - Output : None - Return : LOS_OK on success or error code on failure - **************************************************************************** */ -LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum, - HWI_PRIOR_T hwiPrio, - HWI_MODE_T hwiMode, - HWI_PROC_FUNC hwiHandler, - HwiIrqParam *irqParam) -{ - (VOID)hwiMode; - UINT32 intSave; - - if (hwiHandler == NULL) { - return OS_ERRNO_HWI_PROC_FUNC_NULL; - } - - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) { - return OS_ERRNO_HWI_ALREADY_CREATED; - } - - if (hwiPrio > OS_HWI_PRIO_LOWEST) { - return OS_ERRNO_HWI_PRIO_INVALID; - } - - intSave = LOS_IntLock(); -#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1) - if (irqParam != NULL) { - OsSetVector(hwiNum, hwiHandler, irqParam->pDevId); - } else { - OsSetVector(hwiNum, hwiHandler, NULL); - } -#else - (VOID)irqParam; - OsSetVector(hwiNum, hwiHandler); -#endif - -#if (LOSCFG_DEBUG_TOOLS == 1) - if ((irqParam != NULL) && (irqParam->pName != NULL)) { - g_hwiFormName[hwiNum + OS_SYS_VECTOR_CNT] = (CHAR *)irqParam->pName; - } - g_hwiFormCnt[hwiNum + OS_SYS_VECTOR_CNT] = 0; -#endif - - HwiUnmask((IRQn_Type)hwiNum); - HwiSetPriority((IRQn_Type)hwiNum, hwiPrio); - - LOS_IntRestore(intSave); - - return LOS_OK; -} - -/* **************************************************************************** - Function : ArchHwiDelete - Description : Delete hardware interrupt - Input : hwiNum --- hwi num to delete - irqParam --- param of the hwi handler - Output : None - Return : LOS_OK on success or error code on failure - **************************************************************************** */ -LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam) -{ - (VOID)irqParam; - UINT32 intSave; - - if (hwiNum >= OS_HWI_MAX_NUM) { - return OS_ERRNO_HWI_NUM_INVALID; - } - - NVIC_DisableIRQ((IRQn_Type)hwiNum); - - intSave = LOS_IntLock(); - - g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler; - - LOS_IntRestore(intSave); - - return LOS_OK; -} - -#define FAULT_STATUS_REG_BIT 32 -#define USGFAULT (1 << 18) -#define BUSFAULT (1 << 17) -#define MEMFAULT (1 << 16) -#define DIV0FAULT (1 << 4) -#define UNALIGNFAULT (1 << 3) -#define HARDFAULT_IRQN (-13) - -ExcInfo g_excInfo = {0}; - -UINT8 g_uwExcTbl[FAULT_STATUS_REG_BIT] = { - 0, 0, 0, 0, 0, 0, OS_EXC_UF_DIVBYZERO, OS_EXC_UF_UNALIGNED, - 0, 0, 0, 0, OS_EXC_UF_NOCP, OS_EXC_UF_INVPC, OS_EXC_UF_INVSTATE, OS_EXC_UF_UNDEFINSTR, - 0, 0, 0, OS_EXC_BF_STKERR, OS_EXC_BF_UNSTKERR, OS_EXC_BF_IMPRECISERR, OS_EXC_BF_PRECISERR, OS_EXC_BF_IBUSERR, - 0, 0, 0, OS_EXC_MF_MSTKERR, OS_EXC_MF_MUNSTKERR, 0, OS_EXC_MF_DACCVIOL, OS_EXC_MF_IACCVIOL -}; - -#if (LOSCFG_KERNEL_PRINTF != 0) -STATIC VOID OsExcNvicDump(VOID) -{ -#define OS_NR_NVIC_EXC_DUMP_TYPES 7 - UINT32 *base = NULL; - UINT32 len, i, j; - UINT32 rgNvicBases[OS_NR_NVIC_EXC_DUMP_TYPES] = { - OS_NVIC_SETENA_BASE, OS_NVIC_SETPEND_BASE, OS_NVIC_INT_ACT_BASE, - OS_NVIC_PRI_BASE, OS_NVIC_EXCPRI_BASE, OS_NVIC_SHCSR, OS_NVIC_INT_CTRL - }; - UINT32 rgNvicLens[OS_NR_NVIC_EXC_DUMP_TYPES] = { - OS_NVIC_INT_ENABLE_SIZE, OS_NVIC_INT_PEND_SIZE, OS_NVIC_INT_ACT_SIZE, - OS_NVIC_INT_PRI_SIZE, OS_NVIC_EXCPRI_SIZE, OS_NVIC_SHCSR_SIZE, - OS_NVIC_INT_CTRL_SIZE - }; - CHAR strRgEnable[] = "enable"; - CHAR strRgPending[] = "pending"; - CHAR strRgActive[] = "active"; - CHAR strRgPriority[] = "priority"; - CHAR strRgException[] = "exception"; - CHAR strRgShcsr[] = "shcsr"; - CHAR strRgIntCtrl[] = "control"; - CHAR *strRgs[] = { - strRgEnable, strRgPending, strRgActive, strRgPriority, - strRgException, strRgShcsr, strRgIntCtrl - }; - - PRINTK("\r\nOS exception NVIC dump:\n"); - for (i = 0; i < OS_NR_NVIC_EXC_DUMP_TYPES; i++) { - base = (UINT32 *)rgNvicBases[i]; - len = rgNvicLens[i]; - PRINTK("interrupt %s register, base address: %p, size: 0x%x\n", strRgs[i], base, len); - len = (len >> 2); /* 2: Gets the next register offset */ - for (j = 0; j < len; j++) { - PRINTK("0x%x ", *(base + j)); - if ((j != 0) && ((j % 16) == 0)) { /* 16: print wrap line */ - PRINTK("\n"); - } - } - PRINTK("\n"); - } -} - -STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo) -{ - CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"}; - - PRINTK("Type = %d\n", excInfo->type); - PRINTK("ThrdPid = %d\n", excInfo->thrdPid); - PRINTK("Phase = %s\n", phaseStr[excInfo->phase]); - PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr); -} - -STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo) -{ - PRINTK("Current task info:\n"); - if (excInfo->phase == OS_EXC_IN_TASK) { - LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet()); - PRINTK("Task name = %s\n", taskCB->taskName); - PRINTK("Task ID = %d\n", taskCB->taskID); - PRINTK("Task SP = %p\n", taskCB->stackPointer); - PRINTK("Task ST = 0x%x\n", taskCB->topOfStack); - PRINTK("Task SS = 0x%x\n", taskCB->stackSize); - } else if (excInfo->phase == OS_EXC_IN_HWI) { - PRINTK("Exception occur in interrupt phase!\n"); - } else { - PRINTK("Exception occur in system init phase!\n"); - } -} - -STATIC VOID OsExcRegInfo(const ExcInfo *excInfo) -{ - PRINTK("Exception reg dump:\n"); - PRINTK("PC = 0x%x\n", excInfo->context->uwPC); - PRINTK("LR = 0x%x\n", excInfo->context->uwLR); - PRINTK("SP = 0x%x\n", excInfo->context->uwSP); - PRINTK("R0 = 0x%x\n", excInfo->context->uwR0); - PRINTK("R1 = 0x%x\n", excInfo->context->uwR1); - PRINTK("R2 = 0x%x\n", excInfo->context->uwR2); - PRINTK("R3 = 0x%x\n", excInfo->context->uwR3); - PRINTK("R4 = 0x%x\n", excInfo->context->uwR4); - PRINTK("R5 = 0x%x\n", excInfo->context->uwR5); - PRINTK("R6 = 0x%x\n", excInfo->context->uwR6); - PRINTK("R7 = 0x%x\n", excInfo->context->uwR7); - PRINTK("R8 = 0x%x\n", excInfo->context->uwR8); - PRINTK("R9 = 0x%x\n", excInfo->context->uwR9); - PRINTK("R10 = 0x%x\n", excInfo->context->uwR10); - PRINTK("R11 = 0x%x\n", excInfo->context->uwR11); - PRINTK("R12 = 0x%x\n", excInfo->context->uwR12); - PRINTK("PriMask = 0x%x\n", excInfo->context->uwPriMask); - PRINTK("xPSR = 0x%x\n", excInfo->context->uwxPSR); -} - -#if (LOSCFG_KERNEL_BACKTRACE == 1) -STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo) -{ - UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0}; - UINT32 index; - - OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->uwSP); - - PRINTK("----- backtrace start -----\n"); - for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) { - if (LR[index] == 0) { - break; - } - PRINTK("backtrace %d -- lr = 0x%x\n", index, LR[index]); - } - PRINTK("----- backtrace end -----\n"); -} -#endif - -STATIC VOID OsExcMemPoolCheckInfo(VOID) -{ - PRINTK("\r\nmemory pools check:\n"); -#if (LOSCFG_PLATFORM_EXC == 1) - MemInfoCB memExcInfo[OS_SYS_MEM_NUM]; - UINT32 errCnt; - UINT32 i; - - (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo)); - - errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo); - if (errCnt < OS_SYS_MEM_NUM) { - errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt); - } - - if (errCnt == 0) { - PRINTK("all memory pool check passed!\n"); - return; - } - - for (i = 0; i < errCnt; i++) { - PRINTK("pool num = %d\n", i); - PRINTK("pool type = %d\n", memExcInfo[i].type); - PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr); - PRINTK("pool size = 0x%x\n", memExcInfo[i].size); - PRINTK("pool free = 0x%x\n", memExcInfo[i].free); - PRINTK("pool blkNum = %d\n", memExcInfo[i].blockSize); - PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr); - PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen); - PRINTK("pool error node owner = %d\n", memExcInfo[i].errorOwner); - } -#endif - UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR); - if (ret == LOS_OK) { - PRINTK("system heap memcheck over, all passed!\n"); - } - - PRINTK("memory pool check end!\n"); -} -#endif - -STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo) -{ -#if (LOSCFG_KERNEL_PRINTF != 0) - PRINTK("*************Exception Information**************\n"); - OsExcTypeInfo(excInfo); - OsExcCurTaskInfo(excInfo); - OsExcRegInfo(excInfo); -#if (LOSCFG_KERNEL_BACKTRACE == 1) - OsExcBackTraceInfo(excInfo); -#endif - OsGetAllTskInfo(); - OsExcNvicDump(); - OsExcMemPoolCheckInfo(); -#endif -} - -LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr) -{ - UINT16 tmpFlag = (excType >> 16) & OS_NULL_SHORT; /* 16: Get Exception Type */ - g_intCount++; - g_excInfo.nestCnt++; - - g_excInfo.type = excType & OS_NULL_SHORT; - - if (tmpFlag & OS_EXC_FLAG_FAULTADDR_VALID) { - g_excInfo.faultAddr = faultAddr; - } else { - g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR; - } - if (g_losTask.runTask != NULL) { - if (tmpFlag & OS_EXC_FLAG_IN_HWI) { - g_excInfo.phase = OS_EXC_IN_HWI; - g_excInfo.thrdPid = pid; - } else { - g_excInfo.phase = OS_EXC_IN_TASK; - g_excInfo.thrdPid = g_losTask.runTask->taskID; - } - } else { - g_excInfo.phase = OS_EXC_IN_INIT; - g_excInfo.thrdPid = OS_NULL_INT; - } - if (excType & OS_EXC_FLAG_NO_FLOAT) { - g_excInfo.context = (EXC_CONTEXT_S *)((CHAR *)excBufAddr - LOS_OFF_SET_OF(EXC_CONTEXT_S, uwR4)); - } else { - g_excInfo.context = excBufAddr; - } - - OsDoExcHook(EXC_INTERRUPT); - OsExcInfoDisplay(&g_excInfo); - ArchSysExit(); -} - -/* **************************************************************************** - Function : HalHwiInit - Description : initialization of the hardware interrupt - Input : None - Output : None - Return : None - **************************************************************************** */ -LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID) -{ -#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1) - UINT32 index; - g_hwiForm[0] = 0; /* [0] Top of Stack */ - g_hwiForm[1] = (HWI_PROC_FUNC)Reset_Handler; /* [1] reset */ - for (index = 2; index < OS_VECTOR_CNT; index++) { /* 2: The starting position of the interrupt */ - g_hwiForm[index] = (HWI_PROC_FUNC)HalHwiDefaultHandler; - } - /* Exception handler register */ - g_hwiForm[NonMaskableInt_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcNMI; - g_hwiForm[HARDFAULT_IRQN + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcHardFault; - g_hwiForm[MemoryManagement_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcMemFault; - g_hwiForm[BusFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcBusFault; - g_hwiForm[UsageFault_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcUsageFault; - g_hwiForm[SVCall_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalExcSvcCall; - g_hwiForm[PendSV_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalPendSV; - g_hwiForm[SysTick_IRQn + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)SysTick_Handler; - - /* Interrupt vector table location */ - SCB->VTOR = (UINT32)(UINTPTR)g_hwiForm; -#endif -#if (__CORTEX_M >= 0x03U) /* only for Cortex-M3 and above */ - NVIC_SetPriorityGrouping(OS_NVIC_AIRCR_PRIGROUP); -#endif - - /* Enable USGFAULT, BUSFAULT, MEMFAULT */ - *(volatile UINT32 *)OS_NVIC_SHCSR |= (USGFAULT | BUSFAULT | MEMFAULT); - - /* Enable DIV 0 and unaligned exception */ -#ifdef LOSCFG_ARCH_UNALIGNED_EXC - *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT | UNALIGNFAULT); -#else - *(volatile UINT32 *)OS_NVIC_CCR |= (DIV0FAULT); -#endif - - return; -} - diff --git a/arch/arm/cortex-m4/gcc/los_arch_context.h b/arch/arm/cortex-m4/los_arch_context.h similarity index 96% rename from arch/arm/cortex-m4/gcc/los_arch_context.h rename to arch/arm/cortex-m4/los_arch_context.h index 16659b4112f1ed9889dccbb9c90490311e6ac93f..bc7edacbc4b712f6a971d72b0dfbfd4fea41b21f 100644 --- a/arch/arm/cortex-m4/gcc/los_arch_context.h +++ b/arch/arm/cortex-m4/los_arch_context.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -121,6 +120,7 @@ typedef struct TagTskContext { */ extern VOID HalStartToRun(VOID); +#if (LOSCFG_COMPILER_ICCARM == 1) #if (LOSCFG_SECURE == 1) /** * @ingroup los_config @@ -143,6 +143,7 @@ extern VOID HalStartToRun(VOID); */ extern VOID HalUserTaskStackInit(TaskContext *context, UINTPTR taskEntry, UINTPTR stack); #endif +#endif #ifdef __cplusplus #if __cplusplus diff --git a/arch/arm/cortex-m4/iar/los_arch_interrupt.h b/arch/arm/cortex-m4/los_arch_interrupt.h similarity index 95% rename from arch/arm/cortex-m4/iar/los_arch_interrupt.h rename to arch/arm/cortex-m4/los_arch_interrupt.h index 326b72f23ab47c830c27eb424165daab69f0bf0d..7419eb1b2d6acecbd750e84ecbf5e5b82a9e0ffd 100644 --- a/arch/arm/cortex-m4/iar/los_arch_interrupt.h +++ b/arch/arm/cortex-m4/los_arch_interrupt.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/arch/arm/cortex-m4/iar/los_arch_timer.h b/arch/arm/cortex-m4/los_arch_timer.h similarity index 92% rename from arch/arm/cortex-m4/iar/los_arch_timer.h rename to arch/arm/cortex-m4/los_arch_timer.h index 2b2c41f94dfe74e70412ce94c468eebc3768bb84..126a473ea7b5eb6c5900e302538832f813a169d0 100644 --- a/arch/arm/cortex-m4/iar/los_arch_timer.h +++ b/arch/arm/cortex-m4/los_arch_timer.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/arch/arm/cortex-m4/gcc/los_context.c b/arch/arm/cortex-m4/los_context.c similarity index 91% rename from arch/arm/cortex-m4/gcc/los_context.c rename to arch/arm/cortex-m4/los_context.c index b10e3b56680adc1cf1467a85072b056997d0783e..180159c336f29be7177cbc722c98b8c9c996a2eb 100644 --- a/arch/arm/cortex-m4/gcc/los_context.c +++ b/arch/arm/cortex-m4/los_context.c @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -36,7 +35,10 @@ #include "los_task.h" #include "los_sched.h" #include "los_interrupt.h" - +#if (LOSCFG_COMPILER_ICCARM == 1) +#include "los_timer.h" +#include "los_debug.h" +#endif /* **************************************************************************** Function : ArchInit Description : arch init function @@ -128,8 +130,13 @@ LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VO context->uwR2 = 0x02020202L; context->uwR3 = 0x03030303L; context->uwR12 = 0x12121212L; +#if (LOSCFG_COMPILER_ICCARM == 1) + context->uwLR = (UINTPTR)ArchSysExit; + context->uwPC = (UINTPTR)OsTaskEntry; +#else context->uwLR = (UINT32)(UINTPTR)ArchSysExit; context->uwPC = (UINT32)(UINTPTR)OsTaskEntry; +#endif context->uwxPSR = 0x01000000L; return (VOID *)context; @@ -148,6 +155,7 @@ VOID *ArchSignalContextInit(VOID *stackPointer, VOID *stackTop, UINTPTR sigHandl return (VOID *)context; } +#if (LOSCFG_COMPILER_ICCARM == 0) #if (LOSCFG_SECURE == 1) VOID HalUserTaskStackInit(TaskContext *context, UINTPTR taskEntry, UINTPTR stack) { @@ -156,6 +164,7 @@ VOID HalUserTaskStackInit(TaskContext *context, UINTPTR taskEntry, UINTPTR stack context->uwxPSR = 0x01000000L; /* Thumb flag, always set 1 */ } #endif +#endif LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID) { diff --git a/arch/arm/cortex-m4/gcc/los_interrupt.c b/arch/arm/cortex-m4/los_interrupt.c similarity index 89% rename from arch/arm/cortex-m4/gcc/los_interrupt.c rename to arch/arm/cortex-m4/los_interrupt.c index fd8c1b8b7b98a72015cef1f1f09f657552a2eced..b5a2a0d3776f7cea2a4128c0be8900c390b5fe30 100644 --- a/arch/arm/cortex-m4/gcc/los_interrupt.c +++ b/arch/arm/cortex-m4/los_interrupt.c @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,11 +44,23 @@ UINT32 g_intCount = 0; +#if (LOSCFG_COMPILER_ICCARM == 1) +#ifdef __ICCARM__ +#pragma location = ".data.vector" +#pragma data_alignment = LOSCFG_ARCH_HWI_VECTOR_ALIGN +#elif defined(__CC_ARM) || defined(__GNUC__) +LITE_OS_SEC_VEC +#endif +#endif /* * * @ingroup los_hwi * Hardware interrupt form mapping handling function array. */ +#if (LOSCFG_COMPILER_ICCARM == 1) +STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0}; +#else STATIC HWI_PROC_FUNC __attribute__((aligned(LOSCFG_ARCH_HWI_VECTOR_ALIGN))) g_hwiForm[OS_VECTOR_CNT] = {0}; +#endif #if (LOSCFG_DEBUG_TOOLS == 1) STATIC UINT32 g_hwiFormCnt[OS_HWI_MAX_NUM] = {0}; @@ -206,6 +217,59 @@ HwiControllerOps g_archHwiOps = { .clearIrq = HwiClear, }; +UINT32 ArchIntTrigger(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.triggerIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.triggerIrq(hwiNum); +} + +UINT32 ArchIntEnable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.enableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.enableIrq(hwiNum); +} + +UINT32 ArchIntDisable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.disableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.disableIrq(hwiNum); +} + +UINT32 ArchIntClear(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.clearIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.clearIrq(hwiNum); +} + +UINT32 ArchIntSetPriority(HWI_HANDLE_T hwiNum, HWI_PRIOR_T priority) +{ + if (g_archHwiOps.setIrqPriority == NULL) { + return LOS_NOK; + } + return g_archHwiOps.setIrqPriority(hwiNum, priority); +} + +UINT32 ArchIntCurIrqNum(VOID) +{ + if (g_archHwiOps.getCurIrqNum == NULL) { + return LOS_NOK; + } + return g_archHwiOps.getCurIrqNum(); +} + +HwiControllerOps *ArchIntOpsGet(VOID) +{ + return &g_archHwiOps; +} + inline UINT32 ArchIsIntActive(VOID) { return (g_intCount > 0); @@ -371,7 +435,11 @@ LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irq return OS_ERRNO_HWI_NUM_INVALID; } +#if (LOSCFG_COMPILER_ICCARM == 1) + NVIC_DisableIRQ((IRQn_Type)hwiNum); +#else HwiMask((IRQn_Type)hwiNum); +#endif intSave = LOS_IntLock(); @@ -604,6 +672,7 @@ LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, U ArchSysExit(); } +#if (LOSCFG_COMPILER_ICCARM == 0) /* stack protector */ WEAK UINT32 __stack_chk_guard = 0xd00a0dff; @@ -613,7 +682,7 @@ WEAK VOID __stack_chk_fail(VOID) LOS_Panic("stack-protector: Kernel stack is corrupted in: %p\n", __builtin_return_address(0)); } - +#endif /* **************************************************************************** Function : HalHwiInit Description : initialization of the hardware interrupt diff --git a/arch/arm/cortex-m4/iar/los_mpu.c b/arch/arm/cortex-m4/los_mpu.c similarity index 94% rename from arch/arm/cortex-m4/iar/los_mpu.c rename to arch/arm/cortex-m4/los_mpu.c index 8d1dc25b1931e63a661864aa2f85d18fac1ed760..43dee54fdd1893681da8392756ea2b71dddbb4bf 100644 --- a/arch/arm/cortex-m4/iar/los_mpu.c +++ b/arch/arm/cortex-m4/los_mpu.c @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/arch/arm/cortex-m4/iar/los_timer.c b/arch/arm/cortex-m4/los_timer.c similarity index 93% rename from arch/arm/cortex-m4/iar/los_timer.c rename to arch/arm/cortex-m4/los_timer.c index 99721b87f43ccadee0d2986de15c7b5c8e3f7682..25383d826f8bfa547200b852bb1273c56359c750 100644 --- a/arch/arm/cortex-m4/iar/los_timer.c +++ b/arch/arm/cortex-m4/los_timer.c @@ -1,6 +1,5 @@ /* - * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c b/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c index 8507f8ee031589c3fbe314cfb40755ff2c9d69f5..eab315957c75bea7ecc0fe158977091ed7392db9 100644 --- a/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c +++ b/arch/arm/cortex-m55/gcc/NTZ/los_interrupt.c @@ -207,10 +207,64 @@ HwiControllerOps g_archHwiOps = { .clearIrq = HwiClear, }; +UINT32 ArchIntTrigger(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.triggerIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.triggerIrq(hwiNum); +} + +UINT32 ArchIntEnable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.enableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.enableIrq(hwiNum); +} + +UINT32 ArchIntDisable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.disableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.disableIrq(hwiNum); +} + +UINT32 ArchIntClear(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.clearIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.clearIrq(hwiNum); +} + +UINT32 ArchIntSetPriority(HWI_HANDLE_T hwiNum, HWI_PRIOR_T priority) +{ + if (g_archHwiOps.setIrqPriority == NULL) { + return LOS_NOK; + } + return g_archHwiOps.setIrqPriority(hwiNum, priority); +} + +UINT32 ArchIntCurIrqNum(VOID) +{ + if (g_archHwiOps.getCurIrqNum == NULL) { + return LOS_NOK; + } + return g_archHwiOps.getCurIrqNum(); +} + +HwiControllerOps *ArchIntOpsGet(VOID) +{ + return &g_archHwiOps; +} + inline UINT32 ArchIsIntActive(VOID) { return (g_intCount > 0); } + /* **************************************************************************** Function : HalHwiDefaultHandler Description : default handler of the hardware interrupt diff --git a/arch/csky/v2/gcc/los_interrupt.c b/arch/csky/v2/gcc/los_interrupt.c index 66c0977a3733275b1fce8bf23fd2915fb8a5f2ec..4e0725b05128b813a4de6956a90b1e151ca50d4b 100644 --- a/arch/csky/v2/gcc/los_interrupt.c +++ b/arch/csky/v2/gcc/los_interrupt.c @@ -267,6 +267,59 @@ HwiControllerOps g_archHwiOps = { .clearIrq = HwiClear, }; +UINT32 ArchIntTrigger(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.triggerIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.triggerIrq(hwiNum); +} + +UINT32 ArchIntEnable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.enableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.enableIrq(hwiNum); +} + +UINT32 ArchIntDisable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.disableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.disableIrq(hwiNum); +} + +UINT32 ArchIntClear(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.clearIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.clearIrq(hwiNum); +} + +UINT32 ArchIntSetPriority(HWI_HANDLE_T hwiNum, HWI_PRIOR_T priority) +{ + if (g_archHwiOps.setIrqPriority == NULL) { + return LOS_NOK; + } + return g_archHwiOps.setIrqPriority(hwiNum, priority); +} + +UINT32 ArchIntCurIrqNum(VOID) +{ + if (g_archHwiOps.getCurIrqNum == NULL) { + return LOS_NOK; + } + return g_archHwiOps.getCurIrqNum(); +} + +HwiControllerOps *ArchIntOpsGet(VOID) +{ + return &g_archHwiOps; +} + inline UINT32 ArchIsIntActive(VOID) { return (g_intCount > 0); diff --git a/arch/include/los_interrupt.h b/arch/include/los_interrupt.h index fcb1d8809912252c1ac898a0e616f5342700c874..54c987183d6e399f304e7c5de507527ed79287f8 100644 --- a/arch/include/los_interrupt.h +++ b/arch/include/los_interrupt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. - * Copyright (c) 2020-2022 Huawei Device Co., Ltd. All rights reserved. + * Copyright (c) 2020-2023 Huawei Device Co., Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -40,6 +40,136 @@ extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ +#if ((LOSCFG_ARCH_CORTEX_M4 == 1) || (LOSCFG_ARCH_CORTEX_M55 == 1) || \ + (LOSCFG_ARCH_CSKY == 1) || (LOSCFG_ARCH_XTENSA == 1)) +typedef UINT32 HWI_HANDLE_T; +typedef UINT16 HWI_PRIOR_T; +typedef UINT16 HWI_MODE_T; +typedef UINT32 HWI_ARG_T; + +#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1) +typedef VOID (*HWI_PROC_FUNC)(VOID *parm); +#else +typedef VOID (*HWI_PROC_FUNC)(void); +#endif +typedef struct tagIrqParam { + int swIrq; /**< The interrupt number */ + VOID *pDevId; /**< The pointer to the device ID that launches the interrupt */ + const CHAR *pName; /**< The interrupt name */ +} HwiIrqParam; + +typedef struct { + UINT32 (*triggerIrq)(HWI_HANDLE_T hwiNum); + UINT32 (*clearIrq)(HWI_HANDLE_T hwiNum); + UINT32 (*enableIrq)(HWI_HANDLE_T hwiNum); + UINT32 (*disableIrq)(HWI_HANDLE_T hwiNum); + UINT32 (*setIrqPriority)(HWI_HANDLE_T hwiNum, UINT8 priority); + UINT32 (*getCurIrqNum)(VOID); +} HwiControllerOps; + +/* stack protector */ +extern UINT32 __stack_chk_guard; +extern VOID __stack_chk_fail(VOID); + +#define OS_INT_ACTIVE (ArchIsIntActive()) +#define OS_INT_INACTIVE (!(OS_INT_ACTIVE)) +#define LOS_HwiTrigger ArchIntTrigger +#define LOS_HwiEnable ArchIntEnable +#define LOS_HwiDisable ArchIntDisable +#define LOS_HwiClear ArchIntClear +#define LOS_HwiSetPriority ArchIntSetPriority +#define LOS_HwiCurIrqNum ArchIntCurIrqNum +#define LOS_IntLock ArchIntLock +#define LOS_IntRestore ArchIntRestore +#define LOS_IntUnLock ArchIntUnLock +#define LOS_HwiOpsGet ArchIntOpsGet +#define LOS_HwiCreate ArchHwiCreate +#define LOS_HwiDelete ArchHwiDelete + +UINT32 ArchIsIntActive(VOID); +UINT32 ArchIntTrigger(HWI_HANDLE_T hwiNum); +UINT32 ArchIntEnable(HWI_HANDLE_T hwiNum); +UINT32 ArchIntDisable(HWI_HANDLE_T hwiNum); +UINT32 ArchIntClear(HWI_HANDLE_T hwiNum); +UINT32 ArchIntSetPriority(HWI_HANDLE_T hwiNum, HWI_PRIOR_T priority); +UINT32 ArchIntCurIrqNum(VOID); +UINT32 ArchIntLock(VOID); +VOID ArchIntRestore(UINT32 intSave); +UINT32 ArchIntUnLock(VOID); +HwiControllerOps *ArchIntOpsGet(VOID); + +/** + * @ingroup los_interrupt + * @brief Delete hardware interrupt. + * + * @par Description: + * This API is used to delete hardware interrupt. + * + * @attention + * + * + * @param hwiNum [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable + * for a Cortex-A7 platform is [32,95]. + * @param irqParam [IN] Type #HwiIrqParam *. ID of hardware interrupt which will base on + * when delete the hardware interrupt. + * @retval #OS_ERRNO_HWI_NUM_INVALID 0x02000900: Invalid interrupt number. + * @retval #LOS_OK 0 : The interrupt is successfully delete. + * @par Dependency: + * + * @see None. + */ +UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam); + +/** + * @ingroup los_interrupt + * @brief Create a hardware interrupt. + * + * @par Description: + * This API is used to configure a hardware interrupt and register a hardware interrupt handling function. + * + * @attention + * + * + * @param hwiNum [IN] Type#HWI_HANDLE_T: hardware interrupt number. The value range applicable for a + * Cortex-A7 platform is [32,95]. + * @param hwiPrio [IN] Type#HWI_PRIOR_T: hardware interrupt priority. Ignore this parameter temporarily. + * @param mode [IN] Type#HWI_MODE_T: hardware interrupt mode. Ignore this parameter temporarily. + * @param handler [IN] Type#HWI_PROC_FUNC: interrupt handler used when a hardware interrupt is triggered. + * @param irqParam [IN] Type#HwiIrqParam: input parameter of the interrupt + * handler used when a hardware interrupt is triggered. + * + * @retval #OS_ERRNO_HWI_PROC_FUNC_NULL 0x02000901: Null hardware interrupt handling function. + * @retval #OS_ERRNO_HWI_NUM_INVALID 0x02000900: Invalid interrupt number. + * @retval #OS_ERRNO_HWI_NO_MEMORY 0x02000903: Insufficient memory for hardware interrupt creation. + * @retval #OS_ERRNO_HWI_ALREADY_CREATED 0x02000904: The interrupt handler being created has + * already been created. + * @retval #LOS_OK 0 : The interrupt is successfully created. + * @par Dependency: + * + * @see None. + */ +UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum, + HWI_PRIOR_T hwiPrio, + HWI_MODE_T mode, + HWI_PROC_FUNC handler, + HwiIrqParam *irqParam); + +#else /* #ifdef LOS_CFG_ARCH_CORTEX_M4 */ + typedef UINT32 HWI_HANDLE_T; typedef UINT16 HWI_PRIOR_T; @@ -221,6 +351,8 @@ STATIC INLINE HwiControllerOps *ArchIntOpsGet(VOID) return &g_archHwiOps; } +#endif /* #ifdef LOS_CFG_ARCH_CORTEX_M4 */ + #if (LOSCFG_DEBUG_TOOLS == 1) extern UINT32 OsGetHwiFormCnt(UINT32 index); extern CHAR *OsGetHwiFormName(UINT32 index); diff --git a/arch/include/los_timer.h b/arch/include/los_timer.h index 655cda46a9108b3dd255136df00be01bb8217fdf..0e777c5c91267ab5a6115fb22395ad6ae0c4badc 100644 --- a/arch/include/los_timer.h +++ b/arch/include/los_timer.h @@ -41,17 +41,17 @@ extern "C" { #endif /* __cplusplus */ #endif /* __cplusplus */ -#define TICK_CHECK 0x4000000 -#define CYCLE_CHECK 0xFFFFFFFFU -#define SHIFT_32_BIT 32 -#define MAX_HOUR 24 -#define MAX_MINUTES 60 -#define MAX_SECONDS 60 -#define MILSEC 1000 -#define RTC_WAKEUPCLOCK_RTCCLK 32768 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV 16 -#define RTC_CALIBRATE_SLEEP_TIME 8 -#define MACHINE_CYCLE_DEALAY_TIMES (LOSCFG_BASE_CORE_TICK_PER_SECOND << 2) +#define TICK_CHECK 0x4000000 +#define CYCLE_CHECK 0xFFFFFFFFU +#define SHIFT_32_BIT 32 +#define MAX_HOUR 24 +#define MAX_MINUTES 60 +#define MAX_SECONDS 60 +#define MILSEC 1000 +#define RTC_WAKEUPCLOCK_RTCCLK 32768 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV 16 +#define RTC_CALIBRATE_SLEEP_TIME 8 +#define MACHINE_CYCLE_DEALAY_TIMES (LOSCFG_BASE_CORE_TICK_PER_SECOND << 2) typedef struct { UINT32 freq; diff --git a/arch/xtensa/lx6/gcc/los_interrupt.c b/arch/xtensa/lx6/gcc/los_interrupt.c index 14d1fcee22fa1e82cd748600231ca65f9736e72e..2eca1f895f7231174437feaf1f756a1d2435456c 100644 --- a/arch/xtensa/lx6/gcc/los_interrupt.c +++ b/arch/xtensa/lx6/gcc/los_interrupt.c @@ -235,6 +235,59 @@ HwiControllerOps g_archHwiOps = { .clearIrq = HwiClear, }; +UINT32 ArchIntTrigger(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.triggerIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.triggerIrq(hwiNum); +} + +UINT32 ArchIntEnable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.enableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.enableIrq(hwiNum); +} + +UINT32 ArchIntDisable(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.disableIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.disableIrq(hwiNum); +} + +UINT32 ArchIntClear(HWI_HANDLE_T hwiNum) +{ + if (g_archHwiOps.clearIrq == NULL) { + return LOS_NOK; + } + return g_archHwiOps.clearIrq(hwiNum); +} + +UINT32 ArchIntSetPriority(HWI_HANDLE_T hwiNum, HWI_PRIOR_T priority) +{ + if (g_archHwiOps.setIrqPriority == NULL) { + return LOS_NOK; + } + return g_archHwiOps.setIrqPriority(hwiNum, priority); +} + +UINT32 ArchIntCurIrqNum(VOID) +{ + if (g_archHwiOps.getCurIrqNum == NULL) { + return LOS_NOK; + } + return g_archHwiOps.getCurIrqNum(); +} + +HwiControllerOps *ArchIntOpsGet(VOID) +{ + return &g_archHwiOps; +} + INLINE UINT32 ArchIsIntActive(VOID) { return (g_intCount > 0);