diff --git a/Kconfig b/Kconfig
index d1116bea449e68d6e717be3da1eacd879c95c5c9..849223a2cbccaa62d1233bc9fe0b701e4075b073 100644
--- a/Kconfig
+++ b/Kconfig
@@ -250,7 +250,7 @@ choice
config BACKTRACE_TYPE_1
bool "1: Call stack analysis for cortex-m series by scanning the stack"
- depends on ARCH_ARM && !ARCH_ARM9
+ depends on ARCH_ARM && !ARCH_ARM9 && !ARCH_CORTEX_R5
config BACKTRACE_TYPE_2
bool "2: Call stack analysis for risc-v by using frame pointer"
@@ -270,7 +270,7 @@ config BACKTRACE_TYPE_5
config BACKTRACE_TYPE_6
bool "6: Call stack analysis for arm9 by scanning the stack"
- depends on ARCH_ARM9
+ depends on ARCH_ARM9 || ARCH_CORTEX_R5
endchoice
diff --git a/arch/BUILD.gn b/arch/BUILD.gn
index b027c2e15242fa148f9897f083062bb7e2d2ca93..0d47bafa3f2f79b3d5bb2f2b4c71b18352603c97 100644
--- a/arch/BUILD.gn
+++ b/arch/BUILD.gn
@@ -37,7 +37,8 @@ module_group("arch") {
modules = []
if ("$board_cpu" == "arm9" || "$board_cpu" == "cortex-m3" ||
"$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
- "$board_cpu" == "cortex-m33" || "$board_cpu" == "cortex-m55") {
+ "$board_cpu" == "cortex-m33" || "$board_cpu" == "cortex-m55" ||
+ "$board_cpu" == "cortex-r5") {
modules += [ "arm" ]
} else if ("$board_cpu" == "ck802" || "$board_cpu" == "e802" ||
"$board_cpu" == "ck804ef") {
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dfff72b589b8d649d36d637f5cbf8ebe3c1dd3e8..8859b6f53918078007c0d2b4ad6050aef9cecf6d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -21,12 +21,16 @@ config ARCH_ARM_V8M
config ARCH_ARM_V5TE
bool
+
+config ARCH_ARM_V7R
+ bool
config ARCH_ARM_VER
string
default "armv7-m" if ARCH_ARM_V7M
default "armv8-m" if ARCH_ARM_V8M
default "armv5te" if ARCH_ARM_V5TE
+ default "armv7-r" if ARCH_ARM_V7R
#
# VFP Hardware
@@ -107,6 +111,13 @@ config ARCH_ARM9
bool
select ARCH_ARM_V5TE
select ARCH_ARM_AARCH32
+
+config ARCH_CORTEX_R5
+ bool
+ select ARCH_ARM_V7R
+ select ARCH_ARM_AARCH32
+ select ARCH_FPU_VFP_V3
+ select ARCH_FPU_VFP_D16
config ARCH_CPU
string
@@ -116,3 +127,4 @@ config ARCH_CPU
default "cortex-m33" if ARCH_CORTEX_M33
default "cortex-m55" if ARCH_CORTEX_M55
default "arm9" if ARCH_ARM9
+ default "cortex-r5" if ARCH_CORTEX_R5
diff --git a/arch/arm/cortex-r5/gcc/BUILD.gn b/arch/arm/cortex-r5/gcc/BUILD.gn
new file mode 100644
index 0000000000000000000000000000000000000000..e9370f810034969ae60547a642ac16abea207584
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/BUILD.gn
@@ -0,0 +1,46 @@
+# Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without modification,
+# are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice, this list of
+# conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice, this list
+# of conditions and the following disclaimer in the documentation and/or other materials
+# provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific prior written
+# permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+import("//kernel/liteos_m/liteos.gni")
+
+module_name = "arch"
+kernel_module(module_name) {
+ sources = [
+ "los_context.c",
+ "los_dispatch.S",
+ "los_exc.S",
+ "los_interrupt.c",
+ "los_timer.c",
+ "reset_vector.S",
+ ]
+ configs += [ "$LITEOSTOPDIR:warn_config" ]
+}
+
+config("public") {
+ include_dirs = [ "." ]
+}
diff --git a/arch/arm/cortex-r5/gcc/los_arch_atomic.h b/arch/arm/cortex-r5/gcc/los_arch_atomic.h
new file mode 100644
index 0000000000000000000000000000000000000000..69c1857969ae20be5d4e36a5bda86c720b8400f6
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_arch_atomic.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_ATOMIC_H
+#define _LOS_ARCH_ATOMIC_H
+
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+STATIC INLINE INT32 ArchAtomicRead(const Atomic *v)
+{
+ INT32 val;
+
+ __asm__ __volatile__("ldrex %0, [%1]\n"
+ : "=&r"(val)
+ : "r"(v)
+ : "cc");
+
+ return val;
+}
+
+STATIC INLINE VOID ArchAtomicSet(Atomic *v, INT32 setVal)
+{
+ UINT32 status;
+
+ do {
+ __asm__ __volatile__("ldrex %0, [%1]\n"
+ "strex %0, %2, [%1]\n"
+ : "=&r"(status)
+ : "r"(v), "r"(setVal)
+ : "cc");
+ } while (__builtin_expect(status != 0, 0));
+}
+
+STATIC INLINE INT32 ArchAtomicAdd(Atomic *v, INT32 addVal)
+{
+ INT32 val;
+ UINT32 status;
+
+ do {
+ __asm__ __volatile__("ldrex %1, [%2]\n"
+ "add %1, %1, %3\n"
+ "strex %0, %1, [%2]"
+ : "=&r"(status), "=&r"(val)
+ : "r"(v), "r"(addVal)
+ : "cc");
+ } while (__builtin_expect(status != 0, 0));
+
+ return val;
+}
+
+STATIC INLINE INT32 ArchAtomicSub(Atomic *v, INT32 subVal)
+{
+ INT32 val;
+ UINT32 status;
+
+ do {
+ __asm__ __volatile__("ldrex %1, [%2]\n"
+ "sub %1, %1, %3\n"
+ "strex %0, %1, [%2]"
+ : "=&r"(status), "=&r"(val)
+ : "r"(v), "r"(subVal)
+ : "cc");
+ } while (__builtin_expect(status != 0, 0));
+
+ return val;
+}
+
+STATIC INLINE VOID ArchAtomicInc(Atomic *v)
+{
+ (VOID)ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomicDec(Atomic *v)
+{
+ (VOID)ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicIncRet(Atomic *v)
+{
+ return ArchAtomicAdd(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicDecRet(Atomic *v)
+{
+ return ArchAtomicSub(v, 1);
+}
+
+STATIC INLINE INT32 ArchAtomicXchg32bits(Atomic *v, INT32 val)
+{
+ INT32 prevVal = 0;
+ UINT32 status = 0;
+
+ do {
+ __asm__ __volatile__("ldrex %0, [%3]\n"
+ "strex %1, %4, [%3]"
+ : "=&r"(prevVal), "=&r"(status), "+m"(*v)
+ : "r"(v), "r"(val)
+ : "cc");
+ } while (__builtin_expect(status != 0, 0));
+
+ return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg32bits(Atomic *v, INT32 val, INT32 oldVal)
+{
+ INT32 prevVal = 0;
+ UINT32 status = 0;
+
+ do {
+ __asm__ __volatile__("ldrex %0, %2\n"
+ "mov %1, #0\n"
+ "cmp %0, %3\n"
+ "bne 1f\n"
+ "strex %1, %4, %2\n"
+ "1:"
+ : "=&r"(prevVal), "=&r"(status), "+Q"(*v)
+ : "r"(oldVal), "r"(val)
+ : "cc");
+ } while (__builtin_expect(status != 0, 0));
+
+ return prevVal != oldVal;
+}
+
+STATIC INLINE INT64 ArchAtomic64Read(const Atomic64 *v)
+{
+ INT64 val;
+ UINT32 intSave;
+
+ intSave = LOS_IntLock();
+ val = *v;
+ LOS_IntRestore(intSave);
+
+ return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Set(Atomic64 *v, INT64 setVal)
+{
+ UINT32 intSave;
+
+ intSave = LOS_IntLock();
+ *v = setVal;
+ LOS_IntRestore(intSave);
+}
+
+STATIC INLINE INT64 ArchAtomic64Add(Atomic64 *v, INT64 addVal)
+{
+ INT64 val;
+ UINT32 intSave;
+
+ intSave = LOS_IntLock();
+ *v += addVal;
+ val = *v;
+ LOS_IntRestore(intSave);
+
+ return val;
+}
+
+STATIC INLINE INT64 ArchAtomic64Sub(Atomic64 *v, INT64 subVal)
+{
+ INT64 val;
+ UINT32 intSave;
+
+ intSave = LOS_IntLock();
+ *v -= subVal;
+ val = *v;
+ LOS_IntRestore(intSave);
+
+ return val;
+}
+
+STATIC INLINE VOID ArchAtomic64Inc(Atomic64 *v)
+{
+ (VOID)ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64IncRet(Atomic64 *v)
+{
+ return ArchAtomic64Add(v, 1);
+}
+
+STATIC INLINE VOID ArchAtomic64Dec(Atomic64 *v)
+{
+ (VOID)ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomic64DecRet(Atomic64 *v)
+{
+ return ArchAtomic64Sub(v, 1);
+}
+
+STATIC INLINE INT64 ArchAtomicXchg64bits(Atomic64 *v, INT64 val)
+{
+ INT64 prevVal;
+ UINT32 intSave;
+
+ intSave = LOS_IntLock();
+ prevVal = *v;
+ *v = val;
+ LOS_IntRestore(intSave);
+
+ return prevVal;
+}
+
+STATIC INLINE BOOL ArchAtomicCmpXchg64bits(Atomic64 *v, INT64 val, INT64 oldVal)
+{
+ INT64 prevVal;
+ UINT32 intSave;
+
+ intSave = LOS_IntLock();
+ prevVal = *v;
+ if (prevVal == oldVal) {
+ *v = val;
+ }
+ LOS_IntRestore(intSave);
+
+ return prevVal != oldVal;
+}
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_ATOMIC_H */
+
diff --git a/arch/arm/cortex-r5/gcc/los_arch_context.h b/arch/arm/cortex-r5/gcc/los_arch_context.h
new file mode 100644
index 0000000000000000000000000000000000000000..03c25d0ce688fbbe5d738542eb6cd8fed928f18f
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_arch_context.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_CONTEXT_H
+#define _LOS_ARCH_CONTEXT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#define PSR_T_ARM 0x00000000U
+#define PSR_T_THUMB 0x00000020U
+#define PSR_MODE_SVC 0x00000013U
+#define PSR_MODE_SYS 0x0000001FU
+#define PSR_MODE_MASK 0x0000001FU
+#define PSR_E_MASK 0x00000200U
+
+#define PSR_MODE_SVC_THUMB (PSR_MODE_SVC | PSR_T_THUMB)
+#define PSR_MODE_SVC_ARM (PSR_MODE_SVC | PSR_T_ARM)
+
+#define PSR_MODE_SYS_THUMB (PSR_MODE_SYS | PSR_T_THUMB)
+#define PSR_MODE_SYS_ARM (PSR_MODE_SYS | PSR_T_ARM)
+
+VOID OsTaskEntryArm(VOID);
+VOID OsTaskEntryThumb(VOID);
+
+typedef struct TagTskContext {
+ UINT32 spsr;
+ UINT32 r0;
+ UINT32 r1;
+ UINT32 r2;
+ UINT32 r3;
+ UINT32 r4;
+ UINT32 r5;
+ UINT32 r6;
+ UINT32 r7;
+ UINT32 r8;
+ UINT32 r9;
+ UINT32 r10;
+ UINT32 r11;
+ UINT32 r12;
+ UINT32 sp;
+ UINT32 lr;
+ UINT32 pc;
+} TaskContext;
+
+/**
+ * @ingroup los_arch_context
+ * @brief: Task start running function.
+ *
+ * @par Description:
+ * This API is used to start a task.
+ *
+ * @attention:
+ *
+ *
+ * @param: None.
+ *
+ * @retval None.
+ *
+ * @par Dependency:
+ * - los_arch_context.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID HalStartToRun(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief Wait for interrupt.
+ *
+ * @par Description:
+ * - This API is used to suspend execution until interrupt or a debug request occurs.
+ * @attention None.
+ *
+ * @param None.
+ *
+ * @retval: None.
+ *
+ * @par Dependency:
+ * - los_arch_context.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID wfi(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief: mem fence function.
+ *
+ * @par Description:
+ * This API is used to fence for memory.
+ *
+ * @attention:
+ *
+ *
+ * @param: None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * - los_arch_context.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID dmb(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief: mem fence function.
+ *
+ * @par Description:
+ * This API is same as dmb, it just for adaptation.
+ *
+ * @attention:
+ *
+ *
+ * @param: None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * - los_arch_context.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID dsb(VOID);
+
+/**
+ * @ingroup los_arch_context
+ * @brief: instruction fence function.
+ *
+ * @par Description:
+ * This API is used to fence for instruction.
+ *
+ * @attention:
+ *
+ *
+ * @param: None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * - los_arch_context.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID isb(VOID);
+
+extern UINT32 HalGetCpsr(VOID);
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_CONTEXT_H */
diff --git a/arch/arm/cortex-r5/gcc/los_arch_interrupt.h b/arch/arm/cortex-r5/gcc/los_arch_interrupt.h
new file mode 100644
index 0000000000000000000000000000000000000000..93e125f2939d5f46e92df4977c04660633a90014
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_arch_interrupt.h
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_INTERRUPT_H
+#define _LOS_ARCH_INTERRUPT_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_interrupt.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Maximum number of used hardware interrupts.
+ */
+#ifndef OS_HWI_MAX_NUM
+#define OS_HWI_MAX_NUM LOSCFG_PLATFORM_HWI_LIMIT
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Highest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_HIGHEST
+#define OS_HWI_PRIO_HIGHEST 0
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Lowest priority of a hardware interrupt.
+ */
+#ifndef OS_HWI_PRIO_LOWEST
+#define OS_HWI_PRIO_LOWEST 7
+#endif
+
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Define the type of a hardware interrupt vector table function.
+ */
+typedef VOID (**HWI_VECTOR_FUNC)(void);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of interrupts.
+ */
+extern UINT32 g_intCount;
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of arm9 system interrupt vector.
+ */
+#define OS_SYS_VECTOR_CNT 0
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Count of arm9 interrupt vector.
+ */
+#define OS_VECTOR_CNT (OS_SYS_VECTOR_CNT + OS_HWI_MAX_NUM)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt number.
+ *
+ * Value: 0x02000900
+ *
+ * Solution: Ensure that the interrupt number is valid.
+ * The value range of the interrupt number applicable for a arm9 platform is [OS_USER_HWI_MIN,OS_USER_HWI_MAX].
+ */
+#define OS_ERRNO_HWI_NUM_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x00)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Null hardware interrupt handling function.
+ *
+ * Value: 0x02000901
+ *
+ * Solution: Pass in a valid non-null hardware interrupt handling function.
+ */
+#define OS_ERRNO_HWI_PROC_FUNC_NULL LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x01)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient interrupt resources for hardware interrupt creation.
+ *
+ * Value: 0x02000902
+ *
+ * Solution: Increase the configured maximum number of supported hardware interrupts.
+ */
+#define OS_ERRNO_HWI_CB_UNAVAILABLE LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x02)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Insufficient memory for hardware interrupt initialization.
+ *
+ * Value: 0x02000903
+ *
+ * Solution: Expand the configured memory.
+ */
+#define OS_ERRNO_HWI_NO_MEMORY LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x03)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created.
+ *
+ * Value: 0x02000904
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x04)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Invalid interrupt priority.
+ *
+ * Value: 0x02000905
+ *
+ * Solution: Ensure that the interrupt priority is valid.
+ * The value range of the interrupt priority applicable for a arm9 platform is [0,15].
+ */
+#define OS_ERRNO_HWI_PRIO_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x05)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: Incorrect interrupt creation mode.
+ *
+ * Value: 0x02000906
+ *
+ * Solution: The interrupt creation mode can be only set to OS_HWI_MODE_COMM or
+ * OS_HWI_MODE_FAST of which the value can be 0 or 1.
+ */
+#define OS_ERRNO_HWI_MODE_INVALID LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x06)
+
+/* *
+ * @ingroup los_arch_interrupt
+ * Hardware interrupt error code: The interrupt has already been created as a fast interrupt.
+ *
+ * Value: 0x02000907
+ *
+ * Solution: Check whether the interrupt specified by the passed-in interrupt number has already been created.
+ */
+#define OS_ERRNO_HWI_FASTMODE_ALREADY_CREATED LOS_ERRNO_OS_ERROR(LOS_MOD_HWI, 0x07)
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg);
+#else
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+extern VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector);
+#endif
+
+/* *
+ * @ingroup los_arch_interrupt
+ * @brief: Hardware interrupt entry function.
+ *
+ * @par Description:
+ * This API is used as all hardware interrupt handling function entry.
+ *
+ * @attention:
+ *
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * - los_arch_interrupt.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID HalInterrupt(VOID);
+
+/* *
+ * @ingroup los_arch_interrupt
+ * @brief: Default vector handling function.
+ *
+ * @par Description:
+ * This API is used to configure interrupt for null function.
+ *
+ * @attention:
+ *
+ *
+ * @param:None.
+ *
+ * @retval:None.
+ * @par Dependency:
+ * - los_arch_interrupt.h: the header file that contains the API declaration.
+ * @see None.
+ */
+extern VOID HalHwiDefaultHandler(VOID);
+
+#define OS_EXC_IN_INIT 0
+#define OS_EXC_IN_TASK 1
+#define OS_EXC_IN_HWI 2
+
+#define OS_EXC_FLAG_FAULTADDR_VALID 0x01
+#define OS_EXC_FLAG_IN_HWI 0x02
+
+#define OS_EXC_IMPRECISE_ACCESS_ADDR 0xABABABAB
+
+/**
+ * @ingroup los_exc
+ * the struct of register files
+ *
+ * description: the register files that saved when exception triggered
+ *
+ * notes:the following register with prefix 'uw' correspond to the registers in the cpu data sheet.
+ */
+typedef struct TagExcContext {
+ UINT32 spsr;
+ UINT32 r0;
+ UINT32 r1;
+ UINT32 r2;
+ UINT32 r3;
+ UINT32 r4;
+ UINT32 r5;
+ UINT32 r6;
+ UINT32 r7;
+ UINT32 r8;
+ UINT32 r9;
+ UINT32 r10;
+ UINT32 r11;
+ UINT32 r12;
+ UINT32 sp;
+ UINT32 lr;
+ UINT32 pc;
+} EXC_CONTEXT_S;
+
+typedef VOID (*EXC_PROC_FUNC)(UINT32, EXC_CONTEXT_S *);
+VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr);
+VOID HalHwiInit(VOID);
+
+/**
+ * @ingroup los_exc
+ * exception types: undefined instruction exception.
+ */
+#define OS_EXCEPT_UNDEF_INSTR 1
+
+/**
+ * @ingroup los_exc
+ * exception types: software interrupt.
+ */
+#define OS_EXCEPT_SWI 2
+
+/**
+ * @ingroup los_exc
+ * exception types: prefetch abort exception.
+ */
+#define OS_EXCEPT_PREFETCH_ABORT 3
+
+/**
+ * @ingroup los_exc
+ * exception types: data abort exception.
+ */
+#define OS_EXCEPT_DATA_ABORT 4
+
+/**
+ * @ingroup los_exc
+ * exception types: FIQ exception.
+ */
+#define OS_EXCEPT_FIQ 5
+
+/**
+ * @ingroup los_exc
+ * Exception information structure
+ *
+ * Description: Exception information saved when an exception is triggered on the Cortex-M4 platform.
+ *
+ */
+typedef struct TagExcInfo {
+ /**< Exception occurrence phase: 0 means that an exception occurs in initialization,
+ * 1 means that an exception occurs in a task, and 2 means that an exception occurs in an interrupt */
+ UINT16 phase;
+ /**< Exception type. When exceptions occur, check the numbers 1 - 19 listed above */
+ UINT16 type;
+ /**< If the exact address access error indicates the wrong access address when the exception occurred */
+ UINT32 faultAddr;
+ /**< An exception occurs in an interrupt, indicating the interrupt number.
+ * An exception occurs in the task, indicating the task ID, or 0xFFFFFFFF if it occurs during initialization */
+ UINT32 thrdPid;
+ /**< Number of nested exceptions. Currently only registered hook functions are supported
+ * when an exception is entered for the first time */
+ UINT16 nestCnt;
+ /**< reserve */
+ UINT16 reserved;
+ /**< Hardware context at the time an exception to the automatic stack floating-point register occurs */
+ EXC_CONTEXT_S *context;
+} ExcInfo;
+
+extern UINT32 g_intCount;
+extern ExcInfo g_excInfo;
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_INTERRUPT_H */
diff --git a/arch/arm/cortex-r5/gcc/los_arch_timer.h b/arch/arm/cortex-r5/gcc/los_arch_timer.h
new file mode 100644
index 0000000000000000000000000000000000000000..652f7e36ed23fa6efc83fdbab09f81fcb84fe02f
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_arch_timer.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _LOS_ARCH_TIMER_H
+#define _LOS_ARCH_TIMER_H
+
+#include "los_config.h"
+#include "los_compiler.h"
+#include "los_timer.h"
+
+#ifdef __cplusplus
+#if __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#ifdef __cplusplus
+#if __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __cplusplus */
+
+#endif /* _LOS_ARCH_TIMER_H */
diff --git a/arch/arm/cortex-r5/gcc/los_context.c b/arch/arm/cortex-r5/gcc/los_context.c
new file mode 100644
index 0000000000000000000000000000000000000000..964f52cffafa4b581544af1f62bb95ff9d51bde6
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_context.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_context.h"
+#include "securec.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_interrupt.h"
+#include "los_debug.h"
+
+/* ****************************************************************************
+ Function : ArchInit
+ Description : arch init function
+ Input : None
+ Output : None
+ Return : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID ArchInit(VOID)
+{
+ HalHwiInit();
+}
+
+/* ****************************************************************************
+ Function : ArchSysExit
+ Description : Task exit function
+ Input : None
+ Output : None
+ Return : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID ArchSysExit(VOID)
+{
+ LOS_IntLock();
+ while (1) {
+ }
+}
+
+/* ****************************************************************************
+ Function : ArchTskStackInit
+ Description : Task stack initialization function
+ Input : taskID --- TaskID
+ stackSize --- Total size of the stack
+ topStack --- Top of task's stack
+ Output : None
+ Return : Context pointer
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID *ArchTskStackInit(UINT32 taskID, UINT32 stackSize, VOID *topStack)
+{
+ TaskContext *context = (TaskContext *)((UINTPTR)topStack + stackSize - sizeof(TaskContext));
+ LosTaskCB *taskCB = OS_TCB_FROM_TID(taskID);
+ UINT32 cpsr;
+
+ context->r0 = taskID;
+ context->r1 = 0x01010101L;
+ context->r2 = 0x02020202L;
+ context->r3 = 0x03030303L;
+ context->r4 = 0x04040404L;
+ context->r5 = 0x05050505L;
+ context->r6 = 0x06060606L;
+ context->r7 = 0x07070707L;
+ context->r8 = 0x08080808L;
+ context->r9 = 0x09090909L;
+ context->r10 = 0x10101010L;
+ context->r11 = 0x11111111L;
+ context->r12 = 0x12121212L;
+ context->sp = (UINTPTR)topStack + stackSize;
+ context->lr = (UINTPTR)ArchSysExit;
+ cpsr = HalGetCpsr();
+ if ((UINTPTR)taskCB->taskEntry & 0x01) {
+ context->pc = (UINTPTR)OsTaskEntryThumb;
+ context->spsr = PSR_MODE_SYS_THUMB | (cpsr & PSR_E_MASK); /* thumb mode */
+ } else {
+ context->pc = (UINTPTR)OsTaskEntryArm;
+ context->spsr = PSR_MODE_SYS_ARM | (cpsr & PSR_E_MASK); /* arm mode */
+ }
+
+ return (VOID *)context;
+}
+
+LITE_OS_SEC_TEXT_INIT UINT32 ArchStartSchedule(VOID)
+{
+ (VOID)LOS_IntLock();
+ OsSchedStart();
+ HalStartToRun();
+
+ return LOS_OK; /* never return */
+}
+
+BOOL g_ScheduleInIrq = FALSE;
+LITE_OS_SEC_TEXT_INIT VOID ArchTaskSchedule(VOID)
+{
+ UINT32 cpsr;
+ cpsr = HalGetCpsr();
+ if ((cpsr & PSR_MODE_MASK) == PSR_MODE_SYS) {
+ __asm__ __volatile__(" swi #0");
+ } else {
+ g_ScheduleInIrq = TRUE;
+ }
+}
+
+LITE_OS_SEC_TEXT_INIT VOID dmb(VOID)
+{
+ __asm __volatile(" dmb");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID dsb(VOID)
+{
+ __asm __volatile(" dsb");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID isb(VOID)
+{
+ __asm __volatile(" isb");
+}
+
+LITE_OS_SEC_TEXT_INIT VOID wfi(VOID)
+{
+ __asm __volatile(" wfi");
+}
+
diff --git a/arch/arm/cortex-r5/gcc/los_dispatch.S b/arch/arm/cortex-r5/gcc/los_dispatch.S
new file mode 100644
index 0000000000000000000000000000000000000000..235926573ee71c2b220ec15b17627160fb344d5f
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_dispatch.S
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .equ OS_PSR_THUMB, 0x20
+ .equ OS_PSR_INT_DIS, 0xC0
+ .equ OS_PSR_FIQ_DIS, 0x40
+ .equ OS_PSR_IRQ_DIS, 0x80
+ .equ OS_PSR_MODE_MASK, 0x1F
+ .equ OS_PSR_MODE_USR, 0x10
+ .equ OS_PSR_MODE_FIQ, 0x11
+ .equ OS_PSR_MODE_IRQ, 0x12
+ .equ OS_PSR_MODE_SVC, 0x13
+ .equ OS_PSR_MODE_ABT, 0x17
+ .equ OS_PSR_MODE_UND, 0x1B
+ .equ OS_PSR_MODE_SYS, 0x1F
+
+ .global HalStartToRun
+ .global OsTaskEntryArm
+ .global OsTaskEntryThumb
+ .global HalExceptSwiHdl
+ .global HalExceptFiqHdl
+ .global HalExceptIrqHdl
+ .global HalGetCpsr
+ .global ArchIntLock
+ .global ArchIntRestore
+ .global ArchIntUnLock
+
+ .extern OsTaskEntry
+ .extern OsSchedTaskSwitch
+ .extern HalInterrupt
+ .extern g_losTask
+ .extern g_ScheduleInIrq
+
+ .code 32
+ .text
+
+.macro SAVE_CONTEXT
+ STMFD SP!, {R0}
+
+ MRS R0, SPSR
+ AND R0, R0, #OS_PSR_MODE_SYS
+ CMP R0, #OS_PSR_MODE_SYS
+ BNE 1f
+
+ STMFD SP, {SP}^
+ LDR R0, [SP, #-4]
+
+ STMFD R0!, {LR}
+ MOV LR, R0
+ LDMFD SP!, {R0}
+
+ STMFD LR, {R0-R14}^
+
+ SUB LR, LR, #60
+ MRS R0, SPSR
+ STMFD LR!, {R0}
+
+ LDR R1, =g_losTask
+ LDR R1, [R1]
+ STR LR, [R1]
+ B 2f
+
+1:
+ LDMFD SP!, {R0}
+ STMFD SP!, {R0-R12, LR}
+ MRS R0, SPSR
+ STMFD SP!, {R0}
+
+2:
+.endm
+
+.macro RESTORE_CONTEXT
+ MRS R0, SPSR
+ AND R0, R0, #OS_PSR_MODE_SYS
+ CMP R0, #OS_PSR_MODE_SYS
+ BNE 3f
+
+ LDR R1, =g_losTask
+ LDR R1, [R1]
+ LDR LR, [R1]
+
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
+ LDMFD LR, {R0-R14}^
+ ADD LR, LR, #60
+ LDMFD LR!, {PC}^
+3:
+ LDMFD SP!, {R0}
+ MSR SPSR_cxsf, R0
+ LDMFD SP!, {R0-R12, LR}
+ MOVS PC, LR
+.endm
+
+.macro TASK_SWITCH
+ MRS R0, CPSR
+ ORR R0, R0, #OS_PSR_INT_DIS
+ MSR CPSR_cxsf, R0
+ BLX OsSchedTaskSwitch
+ CMP R0, #0
+ BEQ 4f
+
+ LDR R0, =g_losTask
+ LDR R1, [R0, #4]
+ STR R1, [R0]
+
+4:
+.endm
+
+.macro MOCK_PENDSVC
+ LDR R1, =g_ScheduleInIrq
+ LDR R0, [R1]
+ CMP R0, #0
+ BEQ 5f
+ MOV R0, #0
+ STR R0, [R1]
+ SWI #0
+5:
+.endm
+
+HalGetCpsr:
+ MRS R0, CPSR
+ BX LR
+
+HalStartToRun:
+ LDR R0, =g_losTask
+ LDR R0, [R0, #4]
+ LDR LR, [R0]
+
+ LDMFD LR!, {R0}
+ MSR SPSR_cxsf, R0
+
+ LDMFD LR, {R0-R14}^
+ ADD LR, LR, #60
+ LDMFD LR!, {PC}^
+
+HalExceptSwiHdl:
+ SAVE_CONTEXT
+
+ TASK_SWITCH
+
+ RESTORE_CONTEXT
+
+HalExceptFiqHdl:
+ SUB LR, LR, #4
+ SAVE_CONTEXT
+
+ BLX HalInterrupt
+ MOCK_PENDSVC
+ RESTORE_CONTEXT
+
+HalExceptIrqHdl:
+ SUB LR, LR, #4
+
+ SAVE_CONTEXT
+
+ BLX HalInterrupt
+ MOCK_PENDSVC
+ RESTORE_CONTEXT
+
+ArchIntLock:
+ MRS R0, CPSR
+ CPSID FI
+ BX LR
+
+ArchIntUnLock:
+ MRS R0, CPSR
+ CPSIE FI
+ BX LR
+
+ArchIntRestore:
+ MSR CPSR_c, R0
+ BX LR
+
+OsTaskEntryArm:
+ STMFD SP!, {LR}
+ BL OsTaskEntry
+ LDMFD SP!, {LR}
+ BX LR
+
+ .code 16
+ .text
+OsTaskEntryThumb:
+ PUSH {LR}
+ BL OsTaskEntry
+ POP {R0}
+ MOV LR, R0
+ BX LR
+
diff --git a/arch/arm/cortex-r5/gcc/los_exc.S b/arch/arm/cortex-r5/gcc/los_exc.S
new file mode 100644
index 0000000000000000000000000000000000000000..3bd95f52d1606d834cbb7a7498b0d8affcfdaeb0
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_exc.S
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .equ OS_PSR_INT_DIS, 0xC0
+ .equ OS_PSR_FIQ_DIS, 0x40
+ .equ OS_PSR_IRQ_DIS, 0x80
+ .equ OS_PSR_MODE_MASK, 0x1F
+ .equ OS_PSR_MODE_USR, 0x10
+ .equ OS_PSR_MODE_FIQ, 0x11
+ .equ OS_PSR_MODE_IRQ, 0x12
+ .equ OS_PSR_MODE_SVC, 0x13
+ .equ OS_PSR_MODE_ABT, 0x17
+ .equ OS_PSR_MODE_UND, 0x1B
+ .equ OS_PSR_MODE_SYS, 0x1F
+
+ .equ OS_EXCEPT_RESET, 0x00
+ .equ OS_EXCEPT_UNDEF_INSTR, 0x01
+ .equ OS_EXCEPT_SWI, 0x02
+ .equ OS_EXCEPT_PREFETCH_ABORT, 0x03
+ .equ OS_EXCEPT_DATA_ABORT, 0x04
+ .equ OS_EXCEPT_FIQ, 0x05
+ .equ OS_EXCEPT_ADDR_ABORT, 0x06
+ .equ OS_EXCEPT_IRQ, 0x07
+
+ .global HalExceptAddrAbortHdl
+ .global HalExceptDataAbortHdl
+ .global HalExceptPrefetchAbortHdl
+ .global HalExceptUndefInstrHdl
+
+ .extern HalExcHandleEntry
+ .extern __exc_stack_top
+
+ .code 32
+ .text
+
+HalExceptUndefInstrHdl:
+ STMFD SP!, {R0-R5}
+ MOV R0, #OS_EXCEPT_UNDEF_INSTR
+ B _osExceptDispatch
+
+HalExceptPrefetchAbortHdl:
+ SUB LR, LR, #4
+ STMFD SP!, {R0-R5}
+
+ MOV R0, #OS_EXCEPT_PREFETCH_ABORT
+
+ B _osExceptDispatch
+
+HalExceptDataAbortHdl:
+ SUB LR, LR, #4
+ STMFD SP!, {R0-R5}
+
+ MOV R0, #OS_EXCEPT_DATA_ABORT
+
+ B _osExceptDispatch
+
+HalExceptAddrAbortHdl:
+ SUB LR, LR, #8
+ STMFD SP!, {R0-R5}
+
+ MOV R0, #OS_EXCEPT_ADDR_ABORT
+
+ B _osExceptDispatch
+
+_osExceptDispatch:
+ MRS R1, SPSR
+ MOV R2, LR
+ MOV R4, SP
+ ADD SP, SP, #(6 * 4)
+
+ AND R3, R1, #OS_PSR_MODE_SYS
+ ORR R3, R3, #OS_PSR_INT_DIS
+ MSR CPSR_c, R3
+ MOV R3, SP
+ LDR SP, =__exc_stack_top
+
+ STMFD SP!, {R2}
+ STMFD SP!, {LR}
+ STMFD SP!, {R3}
+ STMFD SP!, {R6-R12}
+ LDMFD R4!, {R6-R12}
+ STMFD SP!, {R6-R11}
+ STMFD SP!, {R1}
+ MOV R3, SP
+
+_osExceptionGetSP:
+ STMFD SP!, {R3}
+ LDR R2, =HalExcHandleEntry
+
+ MOV LR, PC
+ BX R2
+
+ LDMFD SP!, {R3}
+ MOV SP, R3
+
+ LDMFD SP!, {R1}
+ MSR CPSR_cxsf, R1
+ LDMFD SP!, {R0-R12}
+ ADD SP, SP, #(4 * 2)
+ LDMFD SP!, {LR}
+ SUB SP, SP, #(4 * 3)
+ LDMFD SP, {SP}
+ ADD LR, LR, #4
+ MOV PC, LR
+
+ .end
diff --git a/arch/arm/cortex-r5/gcc/los_interrupt.c b/arch/arm/cortex-r5/gcc/los_interrupt.c
new file mode 100644
index 0000000000000000000000000000000000000000..8073f8b73093318af554529800015ac411280466
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_interrupt.c
@@ -0,0 +1,480 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "los_interrupt.h"
+#include
+#include "securec.h"
+#include "los_context.h"
+#include "los_arch_interrupt.h"
+#include "los_debug.h"
+#include "los_hook.h"
+#include "los_task.h"
+#include "los_sched.h"
+#include "los_memory.h"
+#include "los_membox.h"
+#include "los_reg.h"
+
+#define OS_INT_IRQ_ENABLE (1U << 0)
+#define OS_INT_FIQ_ENABLE (1U << 1)
+#define OS_INT_REG_BASE (0xFFFFFD00U)
+#define OS_INT_PEND_ADDR (OS_INT_REG_BASE + 0x0120)
+#define OS_INT_ENABLE_ADDR (OS_INT_REG_BASE + 0x0130)
+#define OS_INT_DISABLE_ADDR (OS_INT_REG_BASE + 0x0140)
+#define OS_IRQ_STATUS_ADDR (OS_INT_REG_BASE + 0x0100)
+#define OS_FIQ_STATUS_ADDR (OS_INT_REG_BASE + 0x0104)
+#define OS_IRQ_VEC_ADDR (OS_INT_REG_BASE + 0x0170)
+#define OS_FIQ_VEC_ADDR (OS_INT_REG_BASE + 0x0174)
+
+#define OS_INSTR_SET_MASK 0x01000020U
+#define OS_ARM_INSTR_LEN 4
+#define OS_THUMB_INSTR_LEN 2
+
+UINT32 g_intCount = 0;
+ExcInfo g_excInfo = {0};
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiForm[OS_VECTOR_CNT] = {0};
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+
+typedef struct {
+ HWI_PROC_FUNC pfnHandler;
+ VOID *pParm;
+} HWI_HANDLER_FUNC;
+
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_HANDLER_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {{ (HWI_PROC_FUNC)0, (HWI_ARG_T)0 }};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector, VOID *arg)
+{
+ if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+ g_hwiForm[num + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalInterrupt;
+ g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pfnHandler = vector;
+ g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT].pParm = arg;
+ }
+}
+
+#else
+/* *
+ * @ingroup los_hwi
+ * hardware interrupt handler form mapping handling function array.
+ */
+STATIC HWI_PROC_FUNC g_hwiHandlerForm[OS_VECTOR_CNT] = {0};
+
+/* *
+ * @ingroup los_hwi
+ * Set interrupt vector table.
+ */
+VOID OsSetVector(UINT32 num, HWI_PROC_FUNC vector)
+{
+ if ((num + OS_SYS_VECTOR_CNT) < OS_VECTOR_CNT) {
+ g_hwiForm[num + OS_SYS_VECTOR_CNT] = HalInterrupt;
+ g_hwiHandlerForm[num + OS_SYS_VECTOR_CNT] = vector;
+ }
+}
+#endif
+
+
+/* ****************************************************************************
+ Function : HwiNumGet
+ Description : Get an interrupt number
+ Input : None
+ Output : None
+ Return : Interrupt Indexes number
+ **************************************************************************** */
+STATIC UINT32 HwiNumGet(VOID)
+{
+ UINT32 status;
+
+ READ_UINT32(status, OS_FIQ_STATUS_ADDR);
+ if (status == 0) {
+ READ_UINT32(status, OS_IRQ_STATUS_ADDR);
+ }
+ --status;
+ return status;
+}
+
+STATIC UINT32 HwiUnmask(HWI_HANDLE_T hwiNum)
+{
+ return LOS_OK;
+}
+
+STATIC UINT32 HwiMask(HWI_HANDLE_T hwiNum)
+{
+ return LOS_OK;
+}
+
+HwiControllerOps g_archHwiOps = {
+ .enableIrq = HwiUnmask,
+ .disableIrq = HwiMask,
+ .getCurIrqNum = HwiNumGet,
+};
+
+inline UINT32 ArchIsIntActive(VOID)
+{
+ return (g_intCount > 0);
+}
+/* ****************************************************************************
+ Function : HalHwiDefaultHandler
+ Description : default handler of the hardware interrupt
+ Input : None
+ Output : None
+ Return : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_MINOR VOID HalHwiDefaultHandler(VOID)
+{
+ PRINT_ERR("%s irqnum:%u\n", __FUNCTION__, HwiNumGet());
+ while (1) {}
+}
+
+WEAK VOID HalPreInterruptHandler(UINT32 arg)
+{
+ (VOID)arg;
+ return;
+}
+
+WEAK VOID HalAftInterruptHandler(UINT32 arg)
+{
+ (VOID)arg;
+ return;
+}
+
+/* ****************************************************************************
+ Function : HalInterrupt
+ Description : Hardware interrupt entry function
+ Input : None
+ Output : None
+ Return : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT VOID HalInterrupt(VOID)
+{
+ UINT32 intSave;
+ UINT32 hwiIndex;
+
+ intSave = LOS_IntLock();
+ g_intCount++;
+ LOS_IntRestore(intSave);
+
+#if (LOSCFG_BASE_CORE_SCHED_SLEEP == 1)
+ OsSchedUpdateSleepTime();
+#endif
+
+ hwiIndex = HwiNumGet();
+ if (hwiIndex >= LOSCFG_PLATFORM_HWI_LIMIT) {
+ intSave = LOS_IntLock();
+ g_intCount--;
+ LOS_IntRestore(intSave);
+ return;
+ }
+
+ OsHookCall(LOS_HOOK_TYPE_ISR_ENTER, hwiIndex);
+
+ HalPreInterruptHandler(hwiIndex);
+
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+ if (g_hwiHandlerForm[hwiIndex].pfnHandler != 0) {
+ g_hwiHandlerForm[hwiIndex].pfnHandler((VOID *)g_hwiHandlerForm[hwiIndex].pParm);
+ }
+#else
+ if (g_hwiHandlerForm[hwiIndex] != 0) {
+ g_hwiHandlerForm[hwiIndex]();
+ }
+#endif
+
+ HalAftInterruptHandler(hwiIndex);
+
+ OsHookCall(LOS_HOOK_TYPE_ISR_EXIT, hwiIndex);
+
+ intSave = LOS_IntLock();
+ g_intCount--;
+ LOS_IntRestore(intSave);
+}
+
+/* ****************************************************************************
+ Function : ArchHwiCreate
+ Description : create hardware interrupt
+ Input : hwiNum --- hwi num to create
+ hwiPrio --- priority of the hwi
+ hwiMode --- unused
+ hwiHandler --- hwi handler
+ irqParam --- param of the hwi handler
+ Output : None
+ Return : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiCreate(HWI_HANDLE_T hwiNum,
+ HWI_PRIOR_T hwiPrio,
+ HWI_MODE_T hwiMode,
+ HWI_PROC_FUNC hwiHandler,
+ HwiIrqParam *irqParam)
+{
+ (VOID)hwiMode;
+ UINT32 intSave;
+
+ if (hwiHandler == NULL) {
+ return OS_ERRNO_HWI_PROC_FUNC_NULL;
+ }
+
+ if (hwiNum >= OS_HWI_MAX_NUM) {
+ return OS_ERRNO_HWI_NUM_INVALID;
+ }
+
+ if (g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] != (HWI_PROC_FUNC)HalHwiDefaultHandler) {
+ return OS_ERRNO_HWI_ALREADY_CREATED;
+ }
+
+ intSave = LOS_IntLock();
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+ if (irqParam != NULL) {
+ OsSetVector(hwiNum, hwiHandler, irqParam->pDevId);
+ } else {
+ OsSetVector(hwiNum, hwiHandler, NULL);
+ }
+#else
+ (VOID)irqParam;
+ OsSetVector(hwiNum, hwiHandler);
+#endif
+ HwiUnmask(hwiNum);
+ LOS_IntRestore(intSave);
+
+ return LOS_OK;
+}
+
+/* ****************************************************************************
+ Function : ArchHwiDelete
+ Description : Delete hardware interrupt
+ Input : hwiNum --- hwi num to delete
+ irqParam --- param of the hwi handler
+ Output : None
+ Return : LOS_OK on success or error code on failure
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT UINT32 ArchHwiDelete(HWI_HANDLE_T hwiNum, HwiIrqParam *irqParam)
+{
+ (VOID)irqParam;
+ UINT32 intSave;
+
+ if (hwiNum >= OS_HWI_MAX_NUM) {
+ return OS_ERRNO_HWI_NUM_INVALID;
+ }
+
+ HwiMask(hwiNum);
+
+ intSave = LOS_IntLock();
+ g_hwiForm[hwiNum + OS_SYS_VECTOR_CNT] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+ LOS_IntRestore(intSave);
+
+ return LOS_OK;
+}
+
+#if (LOSCFG_KERNEL_PRINTF != 0)
+STATIC VOID OsExcTypeInfo(const ExcInfo *excInfo)
+{
+ CHAR *phaseStr[] = {"exc in init", "exc in task", "exc in hwi"};
+
+ PRINTK("Type = %u\n", excInfo->type);
+ PRINTK("ThrdPid = %u\n", excInfo->thrdPid);
+ PRINTK("Phase = %s\n", phaseStr[excInfo->phase]);
+ PRINTK("FaultAddr = 0x%x\n", excInfo->faultAddr);
+}
+
+STATIC VOID OsExcCurTaskInfo(const ExcInfo *excInfo)
+{
+ PRINTK("Current task info:\n");
+ if (excInfo->phase == OS_EXC_IN_TASK) {
+ LosTaskCB *taskCB = OS_TCB_FROM_TID(LOS_CurTaskIDGet());
+ PRINTK("Task name = %s\n", taskCB->taskName);
+ PRINTK("Task ID = %u\n", taskCB->taskID);
+ PRINTK("Task SP = %p\n", taskCB->stackPointer);
+ PRINTK("Task ST = 0x%x\n", taskCB->topOfStack);
+ PRINTK("Task SS = 0x%x\n", taskCB->stackSize);
+ } else if (excInfo->phase == OS_EXC_IN_HWI) {
+ PRINTK("Exception occur in interrupt phase!\n");
+ } else {
+ PRINTK("Exception occur in system init phase!\n");
+ }
+}
+
+STATIC VOID OsExcRegInfo(const ExcInfo *excInfo)
+{
+ PRINTK("Exception reg dump:\n");
+ PRINTK("PC = 0x%x\n", excInfo->context->pc);
+ PRINTK("LR = 0x%x\n", excInfo->context->lr);
+ PRINTK("R0 = 0x%x\n", excInfo->context->r0);
+ PRINTK("R1 = 0x%x\n", excInfo->context->r1);
+ PRINTK("R2 = 0x%x\n", excInfo->context->r2);
+ PRINTK("R3 = 0x%x\n", excInfo->context->r3);
+ PRINTK("R4 = 0x%x\n", excInfo->context->r4);
+ PRINTK("R5 = 0x%x\n", excInfo->context->r5);
+ PRINTK("R6 = 0x%x\n", excInfo->context->r6);
+ PRINTK("R7 = 0x%x\n", excInfo->context->r7);
+ PRINTK("R8 = 0x%x\n", excInfo->context->r8);
+ PRINTK("R9 = 0x%x\n", excInfo->context->r9);
+ PRINTK("R10 = 0x%x\n", excInfo->context->r10);
+ PRINTK("R11 = 0x%x\n", excInfo->context->r11);
+ PRINTK("R12 = 0x%x\n", excInfo->context->r12);
+ PRINTK("xPSR = 0x%x\n", excInfo->context->spsr);
+}
+
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+STATIC VOID OsExcBackTraceInfo(const ExcInfo *excInfo)
+{
+ UINTPTR LR[LOSCFG_BACKTRACE_DEPTH] = {0};
+ UINT32 index;
+
+ OsBackTraceHookCall(LR, LOSCFG_BACKTRACE_DEPTH, 0, excInfo->context->sp);
+
+ PRINTK("----- backtrace start -----\n");
+ for (index = 0; index < LOSCFG_BACKTRACE_DEPTH; index++) {
+ if (LR[index] == 0) {
+ break;
+ }
+ PRINTK("backtrace %u -- lr = 0x%x\n", index, LR[index]);
+ }
+ PRINTK("----- backtrace end -----\n");
+}
+#endif
+
+STATIC VOID OsExcMemPoolCheckInfo(VOID)
+{
+ PRINTK("\r\nmemory pools check:\n");
+#if (LOSCFG_PLATFORM_EXC == 1)
+ MemInfoCB memExcInfo[OS_SYS_MEM_NUM];
+ UINT32 errCnt;
+ UINT32 i;
+
+ (VOID)memset_s(memExcInfo, sizeof(memExcInfo), 0, sizeof(memExcInfo));
+
+ errCnt = OsMemExcInfoGet(OS_SYS_MEM_NUM, memExcInfo);
+ if (errCnt < OS_SYS_MEM_NUM) {
+ errCnt += OsMemboxExcInfoGet(OS_SYS_MEM_NUM - errCnt, memExcInfo + errCnt);
+ }
+
+ if (errCnt == 0) {
+ PRINTK("all memory pool check passed!\n");
+ return;
+ }
+
+ for (i = 0; i < errCnt; i++) {
+ PRINTK("pool num = %u\n", i);
+ PRINTK("pool type = %d\n", memExcInfo[i].type);
+ PRINTK("pool addr = 0x%x\n", memExcInfo[i].startAddr);
+ PRINTK("pool size = 0x%x\n", memExcInfo[i].size);
+ PRINTK("pool free = 0x%x\n", memExcInfo[i].free);
+ PRINTK("pool blkNum = %u\n", memExcInfo[i].blockSize);
+ PRINTK("pool error node addr = 0x%x\n", memExcInfo[i].errorAddr);
+ PRINTK("pool error node len = 0x%x\n", memExcInfo[i].errorLen);
+ PRINTK("pool error node owner = %u\n", memExcInfo[i].errorOwner);
+ }
+#endif
+ UINT32 ret = LOS_MemIntegrityCheck(LOSCFG_SYS_HEAP_ADDR);
+ if (ret == LOS_OK) {
+ PRINTK("system heap memcheck over, all passed!\n");
+ }
+
+ PRINTK("memory pool check end!\n");
+}
+#endif
+
+STATIC VOID OsExcInfoDisplay(const ExcInfo *excInfo)
+{
+#if (LOSCFG_KERNEL_PRINTF != 0)
+ PRINTK("*************Exception Information**************\n");
+ OsExcTypeInfo(excInfo);
+ OsExcCurTaskInfo(excInfo);
+ OsExcRegInfo(excInfo);
+#if (LOSCFG_KERNEL_BACKTRACE == 1)
+ OsExcBackTraceInfo(excInfo);
+#endif
+ OsGetAllTskInfo();
+ OsExcMemPoolCheckInfo();
+#endif
+}
+
+LITE_OS_SEC_TEXT_INIT VOID HalExcHandleEntry(UINT32 excType, UINT32 faultAddr, UINT32 pid, EXC_CONTEXT_S *excBufAddr)
+{
+ g_intCount++;
+ g_excInfo.nestCnt++;
+
+ g_excInfo.type = excType;
+
+ if ((excType == OS_EXCEPT_UNDEF_INSTR) || (excType == OS_EXCEPT_SWI)) {
+ if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0) { /* Work status: ARM */
+ excBufAddr->pc -= OS_ARM_INSTR_LEN;
+ } else if ((excBufAddr->spsr & OS_INSTR_SET_MASK) == 0x20) { /* Work status: Thumb */
+ excBufAddr->pc -= OS_THUMB_INSTR_LEN;
+ }
+ }
+ g_excInfo.faultAddr = OS_EXC_IMPRECISE_ACCESS_ADDR;
+
+ if (g_losTask.runTask != NULL) {
+ g_excInfo.phase = OS_EXC_IN_TASK;
+ g_excInfo.thrdPid = g_losTask.runTask->taskID;
+ } else {
+ g_excInfo.phase = OS_EXC_IN_INIT;
+ g_excInfo.thrdPid = OS_NULL_INT;
+ }
+ g_excInfo.context = excBufAddr;
+
+ OsDoExcHook(EXC_INTERRUPT);
+ OsExcInfoDisplay(&g_excInfo);
+ ArchSysExit();
+}
+
+/* ****************************************************************************
+ Function : HalHwiInit
+ Description : initialization of the hardware interrupt
+ Input : None
+ Output : None
+ Return : None
+ **************************************************************************** */
+LITE_OS_SEC_TEXT_INIT VOID HalHwiInit(VOID)
+{
+#if (LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT == 1)
+ UINT32 val;
+
+ for (val = OS_SYS_VECTOR_CNT; val < OS_VECTOR_CNT; val++) {
+#if (LOSCFG_PLATFORM_HWI_WITH_ARG == 1)
+ g_hwiForm[val].pfnHook = HalHwiDefaultHandler;
+ g_hwiForm[val].uwParam = 0;
+#else
+ g_hwiForm[val] = (HWI_PROC_FUNC)HalHwiDefaultHandler;
+#endif
+ }
+#endif
+ return;
+}
diff --git a/arch/arm/cortex-r5/gcc/los_timer.c b/arch/arm/cortex-r5/gcc/los_timer.c
new file mode 100644
index 0000000000000000000000000000000000000000..97a73c748c842f6ff34b8e5ff9a48b61f17cf98e
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/los_timer.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "los_timer.h"
+#include "los_config.h"
+#include "los_arch_context.h"
+#include "los_arch_interrupt.h"
+#include "los_reg.h"
+
+/* Register required to configure the Real-Time Interrupt (RTI) */
+#define RTI_REG_BASE 0xFFFFFC00UL
+#define RTI_GCTRL_REG (RTI_REG_BASE) /* RTI Global Control Register */
+#define RTI_TBCTRL_REG (RTI_REG_BASE + 0x04) /* RTI Timebase Control Register */
+#define RTI_COMPCTRL_REG (RTI_REG_BASE + 0x0C) /* RTI Compare Control Register */
+#define RTI_FRC0_REG (RTI_REG_BASE + 0x10) /* RTI Free Running Counter 0 Register */
+#define RTI_UC0_REG (RTI_REG_BASE + 0x14) /* RTI Up Counter 0 Register */
+#define RTI_CPUC0_REG (RTI_REG_BASE + 0x18) /* RTI Compare Up Counter 0 Register */
+#define RTI_COMP0_REG (RTI_REG_BASE + 0x50) /* RTI Compare 0 Register */
+#define RTI_UDCP0_REG (RTI_REG_BASE + 0x54) /* RTI Update Compare 0 Register */
+#define RTI_SETINTENA_REG (RTI_REG_BASE + 0x80) /* RTI Set Interrupt Enable Register */
+#define RTI_CLEARINTENA_REG (RTI_REG_BASE + 0x84) /* RTI Clear Interrupt Enable Register */
+#define RTI_INTFLAG_REG (RTI_REG_BASE + 0x88) /* RTI Interrupt Flag Register */
+
+#define RTI_IRQ_NUM 2U
+#define RTI_CLOCK_HZ 75000000U
+#define RTI_ENABLE_BIT 0x00000001U
+#define RTI_INT_ENABLE_BIT 0x00000001U
+#define RTI_INT_DISABLE_BIT 0x00000001U
+#define RTI_INT_CLEAR_BIT 0x00000001U
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler);
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime);
+STATIC UINT64 SysTickCycleGet(UINT32 *period);
+STATIC VOID SysTickLock(VOID);
+STATIC VOID SysTickUnlock(VOID);
+
+STATIC ArchTickTimer g_archTickTimer = {
+ .freq = 0,
+ .irqNum = RTI_IRQ_NUM,
+ .periodMax = LOSCFG_BASE_CORE_TICK_RESPONSE_MAX,
+ .init = SysTickStart,
+ .getCycle = SysTickCycleGet,
+ .reload = SysTickReload,
+ .lock = SysTickLock,
+ .unlock = SysTickUnlock,
+ .tickHandler = NULL,
+};
+
+STATIC UINT32 SysTickStart(HWI_PROC_FUNC handler)
+{
+ UINT32 intSave = LOS_IntLock();
+ UINT32 value = 0;
+
+ ArchTickTimer *tick = &g_archTickTimer;
+ tick->freq = OS_SYS_CLOCK;
+
+ (VOID)ArchHwiCreate(tick->irqNum, 0, 0, (HWI_PROC_FUNC)handler, 0);
+
+ /* Disable timer 0 */
+ READ_UINT32(value, RTI_GCTRL_REG);
+ value &= ~(RTI_ENABLE_BIT);
+ WRITE_UINT32(value, RTI_GCTRL_REG);
+
+ /* Use the internal counter */
+ WRITE_UINT32(0, RTI_TBCTRL_REG);
+
+ /* COMPSEL0 will use the RTIFRC0 counter */
+ WRITE_UINT32(0, RTI_COMPCTRL_REG);
+
+ /* Initialise the counter and the prescale counter register */
+ WRITE_UINT32(0, RTI_UC0_REG);
+ WRITE_UINT32(0, RTI_FRC0_REG);
+
+ /* Set prescalar for RTI clock */
+ value = (RTI_CLOCK_HZ / OS_SYS_CLOCK) - 1;
+ WRITE_UINT32(value, RTI_CPUC0_REG);
+ value = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
+ WRITE_UINT32(value, RTI_COMP0_REG);
+ value = OS_SYS_CLOCK / LOSCFG_BASE_CORE_TICK_PER_SECOND;
+ WRITE_UINT32(value, RTI_UDCP0_REG);
+
+ /* Clear interrupts */
+ value = RTI_INT_DISABLE_BIT;
+ WRITE_UINT32(value, RTI_CLEARINTENA_REG);
+ value = RTI_INT_CLEAR_BIT;
+ WRITE_UINT32(value, RTI_INTFLAG_REG);
+
+ /* Enable the compare 0 interrupt */
+ READ_UINT32(value, RTI_SETINTENA_REG);
+ value |= RTI_INT_ENABLE_BIT;
+ WRITE_UINT32(value, RTI_SETINTENA_REG);
+
+ READ_UINT32(value, RTI_GCTRL_REG);
+ value |= RTI_ENABLE_BIT;
+ WRITE_UINT32(value, RTI_GCTRL_REG);
+
+ LOS_IntRestore(intSave);
+
+ return LOS_OK;
+}
+
+STATIC VOID SysTickClockIrqClear(VOID)
+{
+ UINT32 value = RTI_INT_CLEAR_BIT;
+ WRITE_UINT32(value, RTI_INTFLAG_REG);
+}
+
+STATIC UINT64 SysTickReload(UINT64 nextResponseTime)
+{
+ UINT32 rtiCmpComp = 0;
+ UINT32 rtiCntFrc = 0;
+ if (nextResponseTime > g_archTickTimer.periodMax) {
+ nextResponseTime = g_archTickTimer.periodMax;
+ }
+
+ SysTickLock();
+ WRITE_UINT32((UINT32)nextResponseTime, RTI_UDCP0_REG);
+ READ_UINT32(rtiCntFrc, RTI_FRC0_REG);
+ rtiCmpComp = rtiCntFrc + (UINT32)nextResponseTime;
+ WRITE_UINT32(rtiCmpComp, RTI_COMP0_REG);
+
+ SysTickClockIrqClear();
+ SysTickUnlock();
+ return nextResponseTime;
+}
+
+STATIC UINT64 SysTickCycleGet(UINT32 *period)
+{
+ UINT32 val = 0;
+ UINT32 rtiCmpComp = 0;
+ UINT32 rtiCntFrc = 0;
+ UINT32 rtiCmpUdcp = 0;
+
+ READ_UINT32(rtiCmpComp, RTI_COMP0_REG);
+ READ_UINT32(rtiCntFrc, RTI_FRC0_REG);
+ READ_UINT32(rtiCmpUdcp, RTI_UDCP0_REG);
+
+ val = rtiCntFrc - (rtiCmpComp - rtiCmpUdcp);
+ *period = rtiCmpUdcp;
+
+ return (UINT64)val;
+}
+
+STATIC VOID SysTickLock(VOID)
+{
+ UINT32 value = 0;
+
+ READ_UINT32(value, RTI_GCTRL_REG);
+ value &= ~(RTI_ENABLE_BIT);
+ WRITE_UINT32(value, RTI_GCTRL_REG);
+}
+
+STATIC VOID SysTickUnlock(VOID)
+{
+ UINT32 value = 0;
+
+ READ_UINT32(value, RTI_GCTRL_REG);
+ value |= RTI_ENABLE_BIT;
+ WRITE_UINT32(value, RTI_GCTRL_REG);
+}
+
+ArchTickTimer *ArchSysTickTimerGet(VOID)
+{
+ return &g_archTickTimer;
+}
+
+UINT32 ArchEnterSleep(VOID)
+{
+ dsb();
+ wfi();
+ isb();
+
+ return LOS_OK;
+}
diff --git a/arch/arm/cortex-r5/gcc/reset_vector.S b/arch/arm/cortex-r5/gcc/reset_vector.S
new file mode 100644
index 0000000000000000000000000000000000000000..c98267936a447856d3974f75f83a730900900006
--- /dev/null
+++ b/arch/arm/cortex-r5/gcc/reset_vector.S
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2022-2022 Huawei Device Co., Ltd. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list of
+ * conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this list
+ * of conditions and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific prior written
+ * permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+ .equ CPSR_IRQ_DISABLE, 0x80
+ .equ CPSR_FIQ_DISABLE, 0x40
+ .equ CPSR_THUMB_ENABLE, 0x20
+ .equ CPSR_USER_MODE, 0x10
+ .equ CPSR_FIQ_MODE, 0x11
+ .equ CPSR_IRQ_MODE, 0x12
+ .equ CPSR_SVC_MODE, 0x13
+ .equ CPSR_ABT_MODE, 0x17
+ .equ CPSR_UNDEF_MODE, 0x1B
+
+ .global __exc_stack_top
+ .global __irq_stack_top
+ .global __fiq_stack_top
+ .global __svc_stack_top
+ .global __abt_stack_top
+ .global __undef_stack_top
+ .global __exc_stack
+ .global __irq_stack
+ .global __fiq_stack
+ .global __svc_stack
+ .global __abt_stack
+ .global __undef_stack
+
+ .extern HalExceptFiqHdl
+ .extern HalExceptAddrAbortHdl
+ .extern HalExceptDataAbortHdl
+ .extern HalExceptPrefetchAbortHdl
+ .extern HalExceptSwiHdl
+ .extern HalExceptUndefInstrHdl
+ .extern HalExceptIrqHdl
+ .extern HalResetVector
+
+ .code 32
+ .text
+
+ .section ".vectors", "ax"
+ .global _vector_start
+
+_vector_start:
+ B HalResetVector
+ B HalExceptUndefInstrHdl
+ B HalExceptSwiHdl
+ B HalExceptPrefetchAbortHdl
+ B HalExceptDataAbortHdl
+ B HalExceptAddrAbortHdl
+ B HalExceptIrqHdl
+ B HalExceptFiqHdl
+
+ .section ".vectorsHeap", "wa", %nobits
+ .align 3
+__exc_stack:
+ .space 0x00001000
+__exc_stack_top:
+
+__svc_stack:
+ .space 0x00001000
+__svc_stack_top:
+
+__fiq_stack:
+ .space 0x00000800
+__fiq_stack_top:
+
+__irq_stack:
+ .space 0x00000200
+__irq_stack_top:
+
+__abt_stack:
+ .space 0x00000200
+__abt_stack_top:
+
+__undef_stack:
+ .space 0x00000200
+__undef_stack_top:
+
diff --git a/components/backtrace/los_backtrace.c b/components/backtrace/los_backtrace.c
index 9c1ecfda1ac44afcbd1581f0fdd4d38b0c836f82..7a6ad63ee50b2d4478027da550bab86758ae135e 100644
--- a/components/backtrace/los_backtrace.c
+++ b/components/backtrace/los_backtrace.c
@@ -616,7 +616,7 @@ VOID LOS_RecordLR(UINTPTR *LR, UINT32 LRSize, UINT32 jumpCount, UINTPTR SP)
LosTaskCB *taskCB = NULL;
UINT32 taskID;
UINT32 stackStart, stackEnd;
- UINTPTR framePtr, tmpFramePtr, linkReg;
+ UINTPTR linkReg;
if (LR == NULL) {
return;