diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index b7b5bc247899732530eb8fa6cb6d6008c45aaecf..79174ff5d50acf3834fc2ced5ae23ce99783d780 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -549,6 +549,7 @@ option(BUILD_ARK_GC_SUPPORT "ARK support GC. If ON, support GC." OFF) if(BUILD_ARK_GC_SUPPORT) add_definitions(-DARK_GC_SUPPORT) + add_definitions(-DARK_FAST_CODEGEN) endif(BUILD_ARK_GC_SUPPORT) option(LLVM_INCLUDE_EXAMPLES "Generate build targets for the LLVM examples" ON) diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 8d51bb26103ae2ef1d8b5c08b7a51416322f9813..7728884ae06b40024f0ea72456a66e20d692643a 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -281,6 +281,17 @@ static MachineSchedRegistry DefaultSchedRegistry("default", "Use the target's default scheduler choice.", useDefaultMachineSched); +#ifdef ARK_FAST_CODEGEN +static cl::opt EnableMachineSched( + "enable-misched", + cl::desc("Enable the machine instruction scheduling pass."), cl::init(false), + cl::Hidden); + +static cl::opt EnablePostRAMachineSched( + "enable-post-misched", + cl::desc("Enable the post-ra machine instruction scheduling pass."), + cl::init(false), cl::Hidden); +#else static cl::opt EnableMachineSched( "enable-misched", cl::desc("Enable the machine instruction scheduling pass."), cl::init(true), @@ -290,6 +301,7 @@ static cl::opt EnablePostRAMachineSched( "enable-post-misched", cl::desc("Enable the post-ra machine instruction scheduling pass."), cl::init(true), cl::Hidden); +#endif /// Decrement this iterator until reaching the top or a non-debug instr. static MachineBasicBlock::const_iterator diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index e844d03854e258c99cdfa9dcc1517487d3ccbb79..432fb8b4f52db6ee35f2151faf7c234c346e01db 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -93,8 +93,14 @@ static cl::opt DisableLSR("disable-lsr", cl::Hidden, cl::desc("Disable Loop Strength Reduction Pass")); static cl::opt DisableConstantHoisting("disable-constant-hoisting", cl::Hidden, cl::desc("Disable ConstantHoisting")); +#ifdef ARK_FAST_CODEGEN +static cl::opt DisableCGP("disable-cgp", + cl::desc("Disable Codegen Prepare"), + cl::init(true), cl::Hidden); +#else static cl::opt DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare")); +#endif static cl::opt DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass")); static cl::opt DisablePartialLibcallInlining("disable-partial-libcall-inlining", @@ -141,9 +147,16 @@ static cl::opt EnableMachineOutliner( // Enable or disable FastISel. Both options are needed, because // FastISel is enabled by default with -fast, and we wish to be // able to enable or disable fast-isel independently from -O0. +#ifdef ARK_FAST_CODEGEN +static cl::opt +EnableFastISelOption("fast-isel", + cl::desc("Enable the \"fast\" instruction selector"), + cl::init(cl::BOU_TRUE), cl::Hidden); +#else static cl::opt EnableFastISelOption("fast-isel", cl::Hidden, cl::desc("Enable the \"fast\" instruction selector")); +#endif static cl::opt EnableGlobalISelOption( "global-isel", cl::Hidden, @@ -1122,9 +1135,11 @@ void TargetPassConfig::addMachinePasses() { if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID)) addPass(createPrologEpilogInserterPass()); +#ifndef ARK_FAST_CODEGEN /// Add passes that optimize machine instructions after register allocation. if (getOptLevel() != CodeGenOpt::None) addMachineLateOptimization(); +#endif // Expand pseudo instructions before second scheduling pass. addPass(&ExpandPostRAPseudosID); @@ -1152,9 +1167,11 @@ void TargetPassConfig::addMachinePasses() { addPass(createGCInfoPrinter(dbgs()), false); } +#ifndef ARK_FAST_CODEGEN // Basic block placement. if (getOptLevel() != CodeGenOpt::None) addBlockPlacement(); +#endif // Insert before XRay Instrumentation. addPass(&FEntryInserterID); diff --git a/llvm/lib/IR/PassTimingInfo.cpp b/llvm/lib/IR/PassTimingInfo.cpp index d0c1517f480bc50c7a025c6ff7310af910b47d6f..1a344091adb309e6856d0ebfce40821710fa6727 100644 --- a/llvm/lib/IR/PassTimingInfo.cpp +++ b/llvm/lib/IR/PassTimingInfo.cpp @@ -104,7 +104,7 @@ PassTimingInfo::~PassTimingInfo() { } void PassTimingInfo::init() { - if (!TimePassesIsEnabled || TheTimeInfo) + if (!TimePassesIsEnabled || TheTimeInfo != nullptr) return; // Constructed the first time this is called, iff -time-passes is enabled. diff --git a/llvm/lib/Support/Timer.cpp b/llvm/lib/Support/Timer.cpp index f5a512f9a22ddf1088cedad901dd37adacd15473..e1773377ddfe057ec4a173882dfeb5229e6a28f4 100644 --- a/llvm/lib/Support/Timer.cpp +++ b/llvm/lib/Support/Timer.cpp @@ -63,7 +63,7 @@ namespace { std::unique_ptr llvm::CreateInfoOutputFile() { const std::string &OutputFilename = getLibSupportInfoOutputFilename(); if (OutputFilename.empty()) - return std::make_unique(2, false); // stderr. + return std::make_unique(1, false); // stderr. if (OutputFilename == "-") return std::make_unique(1, false); // stdout. diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 8fe2f125982fb08285d1b104be4c4a7085cdc033..fe898bc7c877bfc868c0bbf2a220745512b05be2 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -307,7 +307,11 @@ public: const LegalizerInfo *getLegalizerInfo() const override; const RegisterBankInfo *getRegBankInfo() const override; const Triple &getTargetTriple() const { return TargetTriple; } +#ifdef ARK_FAST_CODEGEN + bool enableMachineScheduler() const override { return false; } +#else bool enableMachineScheduler() const override { return true; } +#endif bool enablePostRAScheduler() const override { return UsePostRAScheduler; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index bec1758a931b112df138b047bf8e77fdea55eecd..5d19f531d552d5dd99d1011525d1691d70c5acdd 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -94,10 +94,17 @@ static cl::opt EnableRedundantCopyElimination( cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden); +#ifdef ARK_FAST_CODEGEN +static cl::opt EnableLoadStoreOpt("aarch64-enable-ldst-opt", + cl::desc("Enable the load/store pair" + " optimization pass"), + cl::init(false), cl::Hidden); +#else static cl::opt EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden); +#endif static cl::opt EnableAtomicTidy( "aarch64-enable-atomic-cfg-tidy", cl::Hidden, @@ -483,6 +490,7 @@ void AArch64PassConfig::addIRPasses() { addPass(createAArch64StackTaggingPass( /*IsOptNone=*/TM->getOptLevel() == CodeGenOpt::None)); +#ifndef ARK_FAST_CODEGEN // Match interleaved memory accesses to ldN/stN intrinsics. if (TM->getOptLevel() != CodeGenOpt::None) { addPass(createInterleavedLoadCombinePass()); @@ -501,6 +509,7 @@ void AArch64PassConfig::addIRPasses() { // invariant. addPass(createLICMPass()); } +#endif // Add Control Flow Guard checks. if (TM->getTargetTriple().isOSWindows()) diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp index 68c721cb0d728861d033e46393f926d9da3bfd6a..08aacfc6cb4927cebe04912cec8be7d16515026e 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -44,10 +44,18 @@ AArch64MCAsmInfoDarwin::AArch64MCAsmInfoDarwin(bool IsILP32) { AlignmentIsInBytes = false; UsesELFSectionDirectiveForBSS = true; +#ifdef ARK_FAST_CODEGEN + SupportsDebugInformation = false; +#else SupportsDebugInformation = true; +#endif UseDataRegionDirectives = true; +#ifdef ARK_FAST_CODEGEN + ExceptionsType = ExceptionHandling::None; +#else ExceptionsType = ExceptionHandling::DwarfCFI; +#endif } const MCExpr *AArch64MCAsmInfoDarwin::getExprForPersonalitySymbol( @@ -90,11 +98,17 @@ AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) { UseDataRegionDirectives = false; WeakRefDirective = "\t.weak\t"; +#ifdef ARK_FAST_CODEGEN + SupportsDebugInformation = false; + // Exceptions handling + ExceptionsType = ExceptionHandling::None; +#else SupportsDebugInformation = true; // Exceptions handling ExceptionsType = ExceptionHandling::DwarfCFI; +#endif HasIdentDirective = true; } @@ -108,11 +122,19 @@ AArch64MCAsmInfoMicrosoftCOFF::AArch64MCAsmInfoMicrosoftCOFF() { Data64bitsDirective = "\t.xword\t"; AlignmentIsInBytes = false; +#ifdef ARK_FAST_CODEGEN + SupportsDebugInformation = false; +#else SupportsDebugInformation = true; +#endif CodePointerSize = 8; CommentString = "//"; +#ifdef ARK_FAST_CODEGEN + ExceptionsType = ExceptionHandling::None; +#else ExceptionsType = ExceptionHandling::WinEH; +#endif WinEHEncodingType = WinEH::EncodingType::Itanium; } @@ -125,10 +147,18 @@ AArch64MCAsmInfoGNUCOFF::AArch64MCAsmInfoGNUCOFF() { Data64bitsDirective = "\t.xword\t"; AlignmentIsInBytes = false; +#ifdef ARK_FAST_CODEGEN + SupportsDebugInformation = false; +#else SupportsDebugInformation = true; +#endif CodePointerSize = 8; CommentString = "//"; +#ifdef ARK_FAST_CODEGEN + ExceptionsType = ExceptionHandling::None; +#else ExceptionsType = ExceptionHandling::WinEH; +#endif WinEHEncodingType = WinEH::EncodingType::Itanium; } diff --git a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp index 068328391dff5491e78b889bdfcd65363d9c785a..592f0c1e5279f4986f61bf0025fdbd8fb17b8eed 100644 --- a/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/llvm/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -315,12 +315,16 @@ void PassManagerBuilder::populateFunctionPassManager( if (OptLevel == 0) return; +#ifdef ARK_FAST_CODEGEN + FPM.add(createCFGSimplificationPass()); +#else addInitialAliasAnalysisPasses(FPM); FPM.add(createCFGSimplificationPass()); FPM.add(createSROAPass()); FPM.add(createEarlyCSEPass()); FPM.add(createLowerExpectIntrinsicPass()); +#endif } // Do PGO instrumentation generation or use pass as the option specified.