diff --git a/llvm/lib/Target/XVM/MCTargetDesc/XVMInstPrinter.cpp b/llvm/lib/Target/XVM/MCTargetDesc/XVMInstPrinter.cpp index f45761417f14c020d14da6eb45f33ef11a1b0456..2974ec81313cd9741e8aa6f19c2a35da55884643 100644 --- a/llvm/lib/Target/XVM/MCTargetDesc/XVMInstPrinter.cpp +++ b/llvm/lib/Target/XVM/MCTargetDesc/XVMInstPrinter.cpp @@ -20,13 +20,13 @@ #include "llvm/Support/Casting.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" -using namespace llvm; -using namespace std; #define DEBUG_TYPE "asm-printer" #define GET_INSTRINFO_CTOR_DTOR // Include the auto-generated portion of the assembly writer. #include "XVMGenAsmWriter.inc" +using namespace llvm; +using namespace std; void XVMInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, @@ -39,7 +39,7 @@ void XVMInstPrinter::printInst(const MCInst *MI, uint64_t Address, O << "\t"; } } - switch(MCInstFlag) { + switch (MCInstFlag) { default: printInstruction(MI, Address, O); break; @@ -70,11 +70,11 @@ void XVMInstPrinter::printCallInstructionImm(const MCInst *MI, raw_ostream &O) { } void XVMInstPrinter::printMovWithFuncID(const MCInst *MI, raw_ostream &O) { - const MCOperand & Op0 = MI->getOperand(0); + const MCOperand &Op0 = MI->getOperand(0); assert(Op0.isReg()); - const MCOperand & Op1 = MI->getOperand(1); + const MCOperand &Op1 = MI->getOperand(1); assert(Op1.isExpr()); - const MCOperand & Op2 = MI->getOperand(2); + const MCOperand &Op2 = MI->getOperand(2); assert(Op2.isImm()); O << "\t"; O << "mov " << getRegisterName(Op0.getReg()) << ", #" << Op2.getImm(); @@ -82,11 +82,11 @@ void XVMInstPrinter::printMovWithFuncID(const MCInst *MI, raw_ostream &O) { void XVMInstPrinter::printDataRefWithGlobalID(const MCInst *MI, raw_ostream &O) { assert(MI->getNumOperands() >= 3); - const MCOperand & Op0 = MI->getOperand(0); + const MCOperand &Op0 = MI->getOperand(0); assert(Op0.isReg()); - const MCOperand & Op1 = MI->getOperand(1); + const MCOperand &Op1 = MI->getOperand(1); assert(Op1.isExpr()); - const MCOperand & Op2 = MI->getOperand(2); + const MCOperand &Op2 = MI->getOperand(2); assert(Op2.isImm()); O << "\t"; O << "dataref " << getRegisterName(Op0.getReg()) << ", #" << Op2.getImm(); @@ -166,7 +166,7 @@ void XVMInstPrinter::printImm64Operand(const MCInst *MI, unsigned OpNo, } void XVMInstPrinter::printBrTargetOperand(const MCInst *MI, unsigned OpNo, - raw_ostream &O) { + raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNo); if (Op.isImm()) { int16_t Imm = Op.getImm(); diff --git a/llvm/lib/Target/XVM/MCTargetDesc/XVMMCTargetDesc.cpp b/llvm/lib/Target/XVM/MCTargetDesc/XVMMCTargetDesc.cpp index ce2b3194ff33f5847f9ae17663ecfc9ec9a1a432..8480f9b8819c575be74a5642f5060c0ac4c770f1 100644 --- a/llvm/lib/Target/XVM/MCTargetDesc/XVMMCTargetDesc.cpp +++ b/llvm/lib/Target/XVM/MCTargetDesc/XVMMCTargetDesc.cpp @@ -83,7 +83,6 @@ class XVMMCInstrAnalysis : public MCInstrAnalysis { public: explicit XVMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} - }; } // end anonymous namespace diff --git a/llvm/lib/Target/XVM/MCTargetDesc/XVMTargetStreamer.cpp b/llvm/lib/Target/XVM/MCTargetDesc/XVMTargetStreamer.cpp index c7ac3ae6bc9427a11b4fc0a432c0127227905598..dd13029a3498dc2a5370b247a67700bf105256a6 100644 --- a/llvm/lib/Target/XVM/MCTargetDesc/XVMTargetStreamer.cpp +++ b/llvm/lib/Target/XVM/MCTargetDesc/XVMTargetStreamer.cpp @@ -15,9 +15,7 @@ using namespace llvm; -// // XVMTargetStreamer Implemenation -// XVMTargetStreamer::XVMTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} XVMTargetStreamer::~XVMTargetStreamer() = default; diff --git a/llvm/lib/Target/XVM/XVMAsmPrinter.cpp b/llvm/lib/Target/XVM/XVMAsmPrinter.cpp index 462e2c8b5cb7a107b9650396d6dbc983c952d29a..30a67c159b83af52f842d154dd8dda25b224930f 100644 --- a/llvm/lib/Target/XVM/XVMAsmPrinter.cpp +++ b/llvm/lib/Target/XVM/XVMAsmPrinter.cpp @@ -67,12 +67,11 @@ public: void emitEndOfAsmFile(Module &M) override; void emitBasicBlockStart(const MachineBasicBlock &MBB) override {}; void emitGlobalVariable(const GlobalVariable *GV) override; - bool runOnMachineFunction(MachineFunction & MF) override; + bool runOnMachineFunction(MachineFunction &MF) override; private: - const Function *F; void emitDecls(const Module &M); - void setFunctionCallInfo(MCInst * Inst); + void setFunctionCallInfo(MCInst *Inst); void setGlobalSymbolInfo(const MachineInstr *MI, MCInst* Inst); DenseMap MIIndentMap; @@ -112,12 +111,12 @@ static std::map DataSectionNameIndexMap; static std::map DataSectionIndexInfoMap; template -inline std::string UnsignedIntTypeToHex(T V, size_t W=sizeof(T)*2) +inline std::string UnsignedIntTypeToHex(T V, size_t W = sizeof(T)*2) { std::stringstream SS; std::string RS; SS << std::setfill('0') << std::setw(W) << std::hex << (V|0); - for(unsigned Index=0; Index::iterator I = DataSectionNameIndexMap.find(_name); +static int GetDataIndex(const char *name, const unsigned char SecOrSubSection) { + std::map::iterator I = DataSectionNameIndexMap.find(name); if (I == DataSectionNameIndexMap.end()) { return -1; } else { @@ -164,8 +163,8 @@ static int GetDataIndex(const char * _name, const unsigned char SecOrSubSection) } } -int GetFuncIndex(const char * _name) { - std::map::iterator I = FunctionNameAndIndex.find(_name); +int GetFuncIndex(const char *name) { + std::map::iterator I = FunctionNameAndIndex.find(name); if (I == FunctionNameAndIndex.end()) { return -1; } else { @@ -173,8 +172,8 @@ int GetFuncIndex(const char * _name) { } } -static int GetDefFuncIndex(const char * _name) { - std::map::iterator I = FunctionDefinitionMap.find(_name); +static int GetDefFuncIndex(const char *name) { + std::map::iterator I = FunctionDefinitionMap.find(name); if (I == FunctionDefinitionMap.end()) return -1; return I->second; @@ -222,8 +221,8 @@ static bool IsConstructorDestructor(const char *FuncName, const Module *M) { IsGlobalVariableType(FuncName, M, "llvm.global_ctors"); } -unsigned int GetPtrRegisterLevelBasedOnName(const char * _name) { - int DataIndex = GetDataIndex(_name, DATA_SUB_SECTION); +unsigned int GetPtrRegisterLevelBasedOnName(const char *name) { + int DataIndex = GetDataIndex(name, DATA_SUB_SECTION); if (DataIndex != -1) { std::map::iterator I = DataSectionIndexInfoMap.find(DataIndex); if (I == DataSectionIndexInfoMap.end()) { @@ -237,8 +236,8 @@ unsigned int GetPtrRegisterLevelBasedOnName(const char * _name) { return 0; } -uint64_t GetSubSecOffsetForGlobal(const char * _name) { - std::map::iterator I = DataSectionNameIndexMap.find(_name); +uint64_t GetSubSecOffsetForGlobal(const char *name) { + std::map::iterator I = DataSectionNameIndexMap.find(name); if (I == DataSectionNameIndexMap.end()) { return -1; } else { @@ -249,8 +248,8 @@ uint64_t GetSubSecOffsetForGlobal(const char * _name) { } } -static int GetOffsetInDataSection(const char * _name) { - int DataIndex = GetDataIndex(_name, DATA_SUB_SECTION); +static int GetOffsetInDataSection(const char *name) { + int DataIndex = GetDataIndex(name, DATA_SUB_SECTION); if (DataIndex != -1) { std::map::iterator I = DataSectionIndexInfoMap.find(DataIndex); if (I == DataSectionIndexInfoMap.end()) { @@ -261,10 +260,10 @@ static int GetOffsetInDataSection(const char * _name) { return -1; } -static int GetMergedSectionIndex(const std::string &_SymName) { +static int GetMergedSectionIndex(const std::string &SymName) { for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; - if (SInfo.SymName.compare(_SymName) == 0) { + XVMSectionInfo &SInfo = I.second; + if (SInfo.SymName.compare(SymName) == 0) { return SInfo.MergedSecIndex; } } @@ -274,24 +273,24 @@ static int GetMergedSectionIndex(const std::string &_SymName) { static inline void PatchSectionInfo(void) { int MergedSectionIndex = 0; // Assign the merged section index to each section - std::map _SectionNameIndex; + std::map SectionNameIndexMap; for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; - std::map::iterator It = _SectionNameIndex.find(SInfo.SecName); - if (It == _SectionNameIndex.end()) { - _SectionNameIndex[SInfo.SecName] = MergedSectionIndex++; + XVMSectionInfo &SInfo = I.second; + std::map::iterator It = SectionNameIndexMap.find(SInfo.SecName); + if (It == SectionNameIndexMap.end()) { + SectionNameIndexMap[SInfo.SecName] = MergedSectionIndex++; } } // patch merged section index for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; - SInfo.MergedSecIndex = _SectionNameIndex[SInfo.SecName]; + XVMSectionInfo &SInfo = I.second; + SInfo.MergedSecIndex = SectionNameIndexMap[SInfo.SecName]; } // patch offset std::map SectionSizes; for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; + XVMSectionInfo &SInfo = I.second; if (SectionSizes.find(SInfo.MergedSecIndex) == SectionSizes.end()) { SInfo.SubSecOffset = 0; SectionSizes[SInfo.MergedSecIndex] = SInfo.SecSize; @@ -302,35 +301,34 @@ static inline void PatchSectionInfo(void) { } // patch the merged section index - for (auto & E: DataSectionNameIndexMap) { - int _MergedSectionIndex = GetMergedSectionIndex(E.first); - if (_MergedSectionIndex != -1) { - E.second.SecNameIndex = _MergedSectionIndex; + for (auto &E: DataSectionNameIndexMap) { + int MergedSectionIndex = GetMergedSectionIndex(E.first); + if (MergedSectionIndex != -1) { + E.second.SecNameIndex = MergedSectionIndex; } } for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; - for(auto & EachPatch : SInfo.PatchListInfo) { + XVMSectionInfo &SInfo = I.second; + for (auto &EachPatch : SInfo.PatchListInfo) { uint64_t DataSectionOffset = GetOffsetInDataSection(EachPatch.SymName.data()); DataSectionOffset += EachPatch.AddEnd; SInfo.PtrSecIndex = GetDataIndex(EachPatch.SymName.data(), DATA_SUB_SECTION); int DataSectionIndex = GetDataIndex(EachPatch.SymName.data(), DATA_SECTION); LLVM_DEBUG(dbgs() << "Add to Buf: " << UnsignedIntTypeToHex(ReverseBytes( - CreateRefContent(DataSectionIndex, DataSectionOffset), - 8), - 8*2).c_str() + CreateRefContent(DataSectionIndex, DataSectionOffset), + 8),8*2).c_str() << " size=" << 8 << "\n"); SInfo.SecBuf += UnsignedIntTypeToHex( - ReverseBytes(CreateRefContent(DataSectionIndex, DataSectionOffset), 8), 16); + ReverseBytes(CreateRefContent(DataSectionIndex, DataSectionOffset), 8), 16); } } } static inline std::string GetDataSectionPerm(XVMSectionInfo* SInfo) { assert(SInfo->Permission != XVM_SECTION_PERM_UNKNOWN && "Permission Unset"); - switch(SInfo->Permission) { + switch (SInfo->Permission) { case XVM_SECTION_PERM_RO: return "ro"; break; @@ -357,40 +355,40 @@ static inline std::string GetDataSectionPerm(XVMSectionInfo* SInfo) { } } -void XVMAsmPrinter::emitDataSectionInfo(raw_svector_ostream & O) { +void XVMAsmPrinter::emitDataSectionInfo(raw_svector_ostream &O) { O << ";; \"data\" index name perm bytes init_data\n"; // Merged section sizes - int _MaxMergedIndex = 0; + int MaxMergedIndex = 0; std::map SectionSizes; for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; + XVMSectionInfo &SInfo = I.second; if (SectionSizes.find(SInfo.MergedSecIndex) == SectionSizes.end()) { SectionSizes[SInfo.MergedSecIndex] = SInfo.SecSize; } else { SectionSizes[SInfo.MergedSecIndex] += SInfo.SecSize; } - if (SInfo.MergedSecIndex > _MaxMergedIndex) - _MaxMergedIndex = SInfo.MergedSecIndex; + if (SInfo.MergedSecIndex > MaxMergedIndex) + MaxMergedIndex = SInfo.MergedSecIndex; } if (DataSectionIndexInfoMap.size()>0) { - for (int _MergedSecIndex = 0; _MergedSecIndex <= _MaxMergedIndex; _MergedSecIndex++) + for (int MergedSecIndex = 0; MergedSecIndex <= MaxMergedIndex; MergedSecIndex++) { // Merged section info std::string MergedSecBuf = ""; - std::string _SecName = ""; - std::string _SecPermit = ""; + std::string SecName = ""; + std::string SecPermit = ""; for (auto& I : DataSectionIndexInfoMap) { - XVMSectionInfo & SInfo = I.second; - if (SInfo.MergedSecIndex == _MergedSecIndex) { + XVMSectionInfo &SInfo = I.second; + if (SInfo.MergedSecIndex == MergedSecIndex) { MergedSecBuf += SInfo.SecBuf; - _SecName = SInfo.SecName; - _SecPermit = GetDataSectionPerm(&SInfo); + SecName = SInfo.SecName; + SecPermit = GetDataSectionPerm(&SInfo); } } // The section data - O << "(data " << _MergedSecIndex << " $" << _SecName << " " << _SecPermit; - O << " " << SectionSizes[_MergedSecIndex]; + O << "(data " << MergedSecIndex << " $" << SecName << " " << SecPermit; + O << " " << SectionSizes[MergedSecIndex]; if (!MergedSecBuf.empty()) { O << " \"" << MergedSecBuf << "\""; } @@ -400,7 +398,7 @@ void XVMAsmPrinter::emitDataSectionInfo(raw_svector_ostream & O) { } void XVMAsmPrinter::InitGlobalConstantDataSequential( - const DataLayout &DL, const ConstantDataSequential *CDS, XVMSectionInfo* SInfo) { + const DataLayout &DL, const ConstantDataSequential *CDS, XVMSectionInfo* SInfo) { LLVM_DEBUG(dbgs() << "\n--------------------InitGlobalConstantDataSequential-------------------\n"); unsigned ElementByteSize = CDS->getElementByteSize(); @@ -408,9 +406,8 @@ void XVMAsmPrinter::InitGlobalConstantDataSequential( for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) { LLVM_DEBUG(dbgs() << "Add to Buf: " << UnsignedIntTypeToHex(ReverseBytes( - CDS->getElementAsInteger(I), - ElementByteSize), - ElementByteSize*2).c_str() + CDS->getElementAsInteger(I), + ElementByteSize), ElementByteSize*2).c_str() << " size=" << ElementByteSize << "\n"); SInfo->SecBuf += UnsignedIntTypeToHex(ReverseBytes(CDS->getElementAsInteger(I), ElementByteSize), ElementByteSize*2); } @@ -430,11 +427,9 @@ void XVMAsmPrinter::InitGlobalConstantDataSequential( } } - -void XVMAsmPrinter::InitGlobalConstantArray(const DataLayout &DL, - const ConstantArray *CA, - const Constant *BaseCV, uint64_t Offset, - XVMSectionInfo* SInfo) { +void XVMAsmPrinter::InitGlobalConstantArray(const DataLayout &DL, const ConstantArray *CA, + const Constant *BaseCV, uint64_t Offset, + XVMSectionInfo* SInfo) { LLVM_DEBUG(dbgs() << "\n--------------------InitGlobalConstantArray-------------------\n"); for (unsigned I = 0, E = CA->getNumOperands(); I != E; ++I) { InitGlobalConstantImpl(DL, CA->getOperand(I), BaseCV, Offset, SInfo); @@ -442,11 +437,9 @@ void XVMAsmPrinter::InitGlobalConstantArray(const DataLayout &DL, } } - -void XVMAsmPrinter::InitGlobalConstantStruct(const DataLayout &DL, - const ConstantStruct *CS, - const Constant *BaseCV, uint64_t Offset, - XVMSectionInfo* SInfo) { +void XVMAsmPrinter::InitGlobalConstantStruct(const DataLayout &DL, const ConstantStruct *CS, + const Constant *BaseCV, uint64_t Offset, + XVMSectionInfo* SInfo) { LLVM_DEBUG(dbgs() << "\n--------------------InitGlobalConstantStruct-------------------\n"); unsigned Size = DL.getTypeAllocSize(CS->getType()); const StructLayout *Layout = DL.getStructLayout(CS->getType()); @@ -462,11 +455,10 @@ void XVMAsmPrinter::InitGlobalConstantStruct(const DataLayout &DL, uint64_t PadSize = ((I == E - 1 ? Size : Layout->getElementOffset(I + 1)) - Layout->getElementOffset(I)) - FieldSize; - // Insert padding - this may include padding to increase the size of the // current field up to the ABI size (if the struct is not packed) as well // as padding to ensure that the next field starts at the right offset. - if(PadSize > 0) { + if (PadSize > 0) { LLVM_DEBUG(dbgs() << "\n------------Struct PADSIZE-----------" << PadSize << "\n"); LLVM_DEBUG(dbgs() << "Add to Buf: " << UnsignedIntTypeToHex(ReverseBytes(0, PadSize), PadSize*2).c_str() @@ -481,9 +473,8 @@ void XVMAsmPrinter::InitGlobalConstantStruct(const DataLayout &DL, } void XVMAsmPrinter::InitGlobalConstantImpl(const DataLayout &DL, const Constant *CV, - const Constant *BaseCV, - uint64_t Offset, - XVMSectionInfo* SInfo) { + const Constant *BaseCV, uint64_t Offset, + XVMSectionInfo* SInfo) { LLVM_DEBUG(dbgs() << "\n--------------------InitGlobalConstantImpl " << CV->getName().str().c_str() << "-------------------\n"); @@ -526,7 +517,6 @@ void XVMAsmPrinter::InitGlobalConstantImpl(const DataLayout &DL, const Constant SInfo->SecBuf += UnsignedIntTypeToHex(ReverseBytes(CI->getZExtValue(), StoreSize), StoreSize*2); } else { llvm_unreachable("Should not have large int global value!"); - // InitGlobalConstantLargeInt(DL, CI, SInfo); } return; } @@ -590,7 +580,6 @@ void XVMAsmPrinter::InitGlobalConstantImpl(const DataLayout &DL, const Constant } int DataSectionIndex = GetDataIndex(CV->getName().data(), DATA_SECTION); - int DataSectionOffset = 0; XVMGVPathInfo PatchInfo; if (DataSectionIndex != -1) { SInfo->BufType = XVM_SECTION_DATA_TYPE_POINTER; @@ -610,7 +599,6 @@ void XVMAsmPrinter::InitGlobalConstantImpl(const DataLayout &DL, const Constant llvm::raw_string_ostream rso(StrME); if (ME != NULL) { DataSectionIndex = 0; - DataSectionOffset = 0; if (ME->getKind() == llvm::MCExpr::Binary) { const MCSymbolRefExpr *SRE; if (const MCBinaryExpr *BE = dyn_cast(ME)) { @@ -700,7 +688,7 @@ void XVMAsmPrinter::InitDataSectionGlobalConstant(Module *M) { SInfo.SecName = "rodata"; } else { SInfo.Permission = XVM_SECTION_PERM_RW; - if ( (SInfo.BufType & XVM_SECTION_DATA_TYPE_BSS) != XVM_SECTION_DATA_TYPE_UNKNOWN) { + if ((SInfo.BufType & XVM_SECTION_DATA_TYPE_BSS) != XVM_SECTION_DATA_TYPE_UNKNOWN) { SInfo.SecName = "bss"; } else { SInfo.SecName = "data"; @@ -711,7 +699,7 @@ void XVMAsmPrinter::InitDataSectionGlobalConstant(Module *M) { DataSectionNameIndexMap.insert(std::pair(GV.getName().data(), SecIndices)); DataSectionIndexInfoMap.insert(std::pair(SectionIndex++, SInfo)); } - // TODO: extern case + // Notes: extern case we may need to consider later } PatchSectionInfo(); } @@ -723,7 +711,7 @@ void XVMAsmPrinter::InitModuleMapFuncnameIndex(Module *M) { /* F1 can't be const because if the function is a constructor * or destructor, we need to add the export attribute to it */ for (Function &F1 : M->getFunctionList()) { - if(F1.getInstructionCount() != 0) { + if (F1.getInstructionCount() != 0) { FunctionDefinitionMap.insert(std::make_pair(F1.getName().data(), Index)); FunctionNameAndIndex.insert(std::make_pair(F1.getName().data(), Index)); if (IsConstructorDestructor(F1.getName().data(), M)) { @@ -731,7 +719,7 @@ void XVMAsmPrinter::InitModuleMapFuncnameIndex(Module *M) { } Index ++; } - else if(!F1.isIntrinsic()) { + else if (!F1.isIntrinsic()) { FuncDecl.push_back(F1.getName().data()); } } @@ -815,29 +803,29 @@ bool XVMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, return false; } -void XVMAsmPrinter::setFunctionCallInfo(MCInst * Inst) { - const char * func_name = NULL; - const MCExpr * TmpExpr; - int64_t func_index = -1; +void XVMAsmPrinter::setFunctionCallInfo(MCInst *Inst) { + const char *FuncName = NULL; + const MCExpr *TmpExpr; + int64_t FuncIndex = -1; if (Inst == NULL) return; assert(Inst->getNumOperands()>0); - MCOperand & FirstMO = Inst->getOperand(0); + MCOperand &FirstMO = Inst->getOperand(0); if (FirstMO.isExpr()) { Inst->setFlags(FUNC_CALL_FLAG_MC_INST_IMM); TmpExpr = Inst->getOperand(0).getExpr(); - func_name = cast(*TmpExpr).getSymbol().getName().data(); - assert(func_name != NULL); + FuncName = cast(*TmpExpr).getSymbol().getName().data(); + assert(FuncName != NULL); assert(Inst->getNumOperands() == 1); - func_index = GetFuncIndex(func_name); - if (func_index == -1) { + FuncIndex = GetFuncIndex(FuncName); + if (FuncIndex == -1) { std::string ErrorMesg("Error: function name "); - ErrorMesg += func_name; + ErrorMesg += FuncName; ErrorMesg += " is called; but could not be found\n"; report_fatal_error(ErrorMesg.data()); } - MCOperand MCOp = MCOperand::createImm(func_index); + MCOperand MCOp = MCOperand::createImm(FuncIndex); Inst->addOperand(MCOp); } if (FirstMO.isReg()) { @@ -851,7 +839,7 @@ void XVMAsmPrinter::setFunctionCallInfo(MCInst * Inst) { void XVMAsmPrinter::setGlobalSymbolInfo(const MachineInstr *MI, MCInst* Inst) { unsigned int numOps = MI->getNumOperands(); bool hasGlobalSymbol = false; - for(unsigned int i=0; igetOperand(i); if (tmp.isGlobal()) { @@ -885,7 +873,7 @@ void XVMAsmPrinter::setGlobalSymbolInfo(const MachineInstr *MI, MCInst* Inst) { SymIndex = GetDataIndex(SymName.c_str(), DATA_SECTION); if (SymIndex == -1) { report_fatal_error( - "TODO: Add the support of non-func-global-var scenarios\n"); + "Note: Add the support of non-func-global-var scenarios\n"); } else { Inst->setFlags(GLOBAL_DATAREF_FLAG_MC_INST); MCOperand MCOp = MCOperand::createImm(SymIndex); @@ -914,8 +902,6 @@ void XVMAsmPrinter::emitInstruction(const MachineInstr *MI) { void XVMAsmPrinter::emitFunctionHeader() { const Function &F = MF->getFunction(); - //OutStreamer->switchSection(MF->getSection()); - SmallString<128> Str; raw_svector_ostream O(Str); int Index = GetDefFuncIndex(F.getName().data()); @@ -1003,25 +989,24 @@ void XVMAsmPrinter::emitStartOfAsmFile(Module &M) { OutStreamer->emitRawText(O.str()); } -static void output_constructor_destructor_metadata( - raw_svector_ostream &O, - std::map> priority_map, - char *MetadataName) { +static void output_constructor_destructor_metadata(raw_svector_ostream &O, + std::map> priority_map, + const char *MetadataName) { O << "(metadata " << MetadataName << " \""; if (strcmp(MetadataName, "$init_array") == 0) { for (auto i = priority_map.begin(); i != priority_map.end(); i++) { - for (int j = 0; j < (i->second).size(); j++) { - int func_index = GetFuncIndex((i->second)[j]); - std::string func_id_data = UnsignedIntTypeToHex(ReverseBytes(func_index, 4), 8); + for (unsigned j = 0; j < (i->second).size(); j++) { + int FuncIndex = GetFuncIndex((i->second)[j]); + std::string func_id_data = UnsignedIntTypeToHex(ReverseBytes(FuncIndex, 4), 8); O << func_id_data.data(); } } } else { /* Destructors are ran from largest number to smallest */ for (auto i = priority_map.rbegin(); i != priority_map.rend(); i++) { - for (int j = 0; j < (i->second).size(); j++) { - int func_index = GetFuncIndex((i->second)[j]); - std::string func_id_data = UnsignedIntTypeToHex(ReverseBytes(func_index, 4), 8); + for (unsigned j = 0; j < (i->second).size(); j++) { + int FuncIndex = GetFuncIndex((i->second)[j]); + std::string func_id_data = UnsignedIntTypeToHex(ReverseBytes(FuncIndex, 4), 8); O << func_id_data.data(); } } @@ -1029,12 +1014,12 @@ static void output_constructor_destructor_metadata( O << "\")\n"; } -static void emitConstructorsDestructors(raw_svector_ostream &O, Module &M, char *GVName, char *MetadataName) { +static void emitConstructorsDestructors(raw_svector_ostream &O, Module &M, + const char *GVName, const char *MetadataName) { GlobalVariable *GV; std::map> priority_map; GV = M.getGlobalVariable(GVName); - if (!GV) { return; } @@ -1060,8 +1045,8 @@ static void emitConstructorsDestructors(raw_svector_ostream &O, Module &M, char continue; } uint16_t PriorityValue = Priority->getLimitedValue(UINT16_MAX); - const char *func_name = CS->getOperand(1)->getName().data(); - priority_map[PriorityValue].push_back(func_name); + const char *FuncName = CS->getOperand(1)->getName().data(); + priority_map[PriorityValue].push_back(FuncName); } output_constructor_destructor_metadata(O, priority_map, MetadataName); diff --git a/llvm/lib/Target/XVM/XVMCFGSort.cpp b/llvm/lib/Target/XVM/XVMCFGSort.cpp index 31fad1dc7edcb1443bb636b726e1888ee87a789e..d8e5d803d4e0196c1a77abacf0c09be0789cb1d1 100644 --- a/llvm/lib/Target/XVM/XVMCFGSort.cpp +++ b/llvm/lib/Target/XVM/XVMCFGSort.cpp @@ -123,7 +123,7 @@ struct Entry { /// Sort the blocks, taking special care to make sure that regions are not /// interrupted by blocks not dominated by their header. -/// TODO: There are many opportunities for improving the heuristics here. +/// Note: There are many opportunities for improving the heuristics here. /// Explore them. static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI, const MachineDominatorTree &MDT) { @@ -276,7 +276,6 @@ static void sortBlocks(MachineFunction &MF, const MachineLoopInfo &MLI, } assert(OnStack.insert(Region) && "Regions should be declared at most once."); - } else { // Not a region header. All predecessors should be sorted above. for (auto Pred : MBB.predecessors()) diff --git a/llvm/lib/Target/XVM/XVMCFGStackify.cpp b/llvm/lib/Target/XVM/XVMCFGStackify.cpp index afb2ff46aa92765b6f692c19348287dc2226e2e6..6215156e3947d7dd42ddfa2e7e9866dc3e8cf0d3 100644 --- a/llvm/lib/Target/XVM/XVMCFGStackify.cpp +++ b/llvm/lib/Target/XVM/XVMCFGStackify.cpp @@ -24,7 +24,6 @@ #include "XVM.h" -//#include "XVMMachineFunctionInfo.h" #include "XVMSortRegion.h" #include "XVMSubtarget.h" #include "llvm/ADT/Statistic.h" @@ -246,7 +245,7 @@ void XVMCFGStackify::fixBackEdgesOfLoops(MachineFunction &MF) { MachineBasicBlock *LoopHeader = Loop->getHeader(); for (auto &MI : MBB.terminators()) { /* skip the added opcode such as THEN ... */ - if (MI.getNumOperands() <=0 ) { + if (MI.getNumOperands() <=0) { continue; } if (TII->isUnCondBranch(&MI) && MI.getOperand(0).getMBB() == LoopHeader) { @@ -258,7 +257,7 @@ void XVMCFGStackify::fixBackEdgesOfLoops(MachineFunction &MF) { } else if (TII->isCondBranch(&MI) && MI.getOperand(0).getMBB() == LoopHeader) { uint32_t action_opcode = XVM::CONTINUE; /* Fix Loop Exiting Fallthrough */ - if(&MBB == Loop->getBottomBlock() && &MI == &*(--MBB.end()) && MLI.getLoopFor(MBB.getFallThrough()) != Loop){ + if (&MBB == Loop->getBottomBlock() && &MI == &*(--MBB.end()) && MLI.getLoopFor(MBB.getFallThrough()) != Loop) { TII->negateCondBranch(&MI); action_opcode = XVM::BREAK; } @@ -277,7 +276,7 @@ void XVMCFGStackify::fixBackEdgesOfLoops(MachineFunction &MF) { } void XVMCFGStackify::registerScope(MachineInstr *Begin, - MachineInstr *End) { + MachineInstr *End) { BeginToEnd[Begin] = End; EndToBegin[End] = Begin; } @@ -304,7 +303,7 @@ static bool isChild(const MachineInstr &MI) { * are in the beginning of the BB, the break_imm needs to increase one. * This is the case where there are multiple conditions ||ed or &&ed in a * loop condition such as for or while loops. - * FIXME: we may find other approach for fixing this. + * Note: we may find other approach for fixing this. */ unsigned XVMCFGStackify::getBranchDepth( const SmallVectorImpl &Stack, @@ -324,14 +323,6 @@ unsigned XVMCFGStackify::getBranchDepth( return Depth; } -static bool isContinueBlock(MachineBasicBlock &MBB) { - for (auto &MI : MBB) { - if (MI.getOpcode() == XVM::CONTINUE) - return true; - } - return false; -} - static inline MachineBasicBlock *getNextBlock(MachineBasicBlock &MBB) { MachineFunction::iterator I = MBB.getIterator(); MachineFunction::iterator E = MBB.getParent()->end(); @@ -351,8 +342,6 @@ static inline MachineInstr *getNextInstruction(MachineInstr &MI) { void XVMCFGStackify::insertWithBreak(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) { DebugLoc DL; - MachineInstr &Inst = *MBBI; - MachineBasicBlock *EndBlock = &MBB.getParent()->back(); const auto &TII = MBB.getParent()->getSubtarget().getInstrInfo(); MBB.addSuccessor(EndBlock); @@ -432,7 +421,6 @@ void XVMCFGStackify::placeMarkers(MachineFunction &MF) { for (auto &MBB : MF) placeLoopMarker(MBB); - const MCAsmInfo *MCAI = MF.getTarget().getMCAsmInfo(); for (auto &MBB : MF) { // Place the BLOCK for MBB if MBB is branched to from above. placeBlockMarker(MBB); @@ -442,7 +430,7 @@ void XVMCFGStackify::placeMarkers(MachineFunction &MF) { } /// Insert a BLOCK marker for branches to MBB (if needed). -// TODO Consider a more generalized way of handling block (and also loop and +// Note: Consider a more generalized way of handling block (and also loop and // try) signatures when we implement the multi-value proposal later. void XVMCFGStackify::placeBlockMarker(MachineBasicBlock &MBB) { assert(!MBB.isEHPad()); @@ -548,8 +536,7 @@ void XVMCFGStackify::placeBlockMarker(MachineBasicBlock &MBB) { MachineInstr *Begin = BuildMI(*Header, InsertPos, Header->findDebugLoc(InsertPos), TII.get(XVM::BLOCK)); -//FIXME: Check if we need it -// .addImm(int64_t(ReturnType)); +//Note: Check if we need it later // Decide where in Header to put the END_BLOCK. BeforeSet.clear(); @@ -622,10 +609,9 @@ void XVMCFGStackify::placeLoopMarker(MachineBasicBlock &MBB) { // Mark the beginning of the loop. auto InsertPos = getEarliestInsertPos(&MBB, BeforeSet, AfterSet); - //FIXME: modify the form of the LOOP instruction + //Note: modify the form of the LOOP instruction MachineInstr *Begin = BuildMI(MBB, InsertPos, MBB.findDebugLoc(InsertPos), TII.get(XVM::LOOP)); -// .addImm(int64_t(XVM::BlockType::Void)); // Decide where in Header to put the END_LOOP. BeforeSet.clear(); @@ -654,7 +640,7 @@ void XVMCFGStackify::placeLoopMarker(MachineBasicBlock &MBB) { } void XVMCFGStackify::extendCondStmt(std::map CondBranchsWithDepth, - MachineFunction &MF) { + MachineFunction &MF) { for (auto& I : CondBranchsWithDepth) { MachineInstr *MI = I.first; unsigned int depth = I.second; @@ -713,7 +699,7 @@ void XVMCFGStackify::rewriteDepthImmediates(MachineFunction &MF) { case XVM::END_LOOP: { Stack.push_back(std::make_pair(EndToBegin[&MI]->getParent(), &MI)); - MachineInstr * PrevMI = MI.getPrevNode(); + MachineInstr *PrevMI = MI.getPrevNode(); if (PrevMI != NULL && PrevMI == MBB.begin()) { if (PrevMI->getOpcode() == XVM::END_BLOCK) { SetEndBlockLoop.insert(&MBB); @@ -767,7 +753,6 @@ bool XVMCFGStackify::runOnMachineFunction(MachineFunction &MF) { LLVM_DEBUG(dbgs() << "********** CFG Stackifying **********\n" "********** Function: " << MF.getName() << '\n'); - const MCAsmInfo *MCAI = MF.getTarget().getMCAsmInfo(); releaseMemory(); @@ -781,12 +766,10 @@ bool XVMCFGStackify::runOnMachineFunction(MachineFunction &MF) { rewriteDepthImmediates(MF); // Add an end instruction at the end of the function body. - const auto &TII = *MF.getSubtarget().getInstrInfo(); if (!MF.getSubtarget() .getTargetTriple() .isOSBinFormatELF()) -//FIXME: See if we need it -// appendEndToFunction(MF, TII); +// Note: See if we need it later appendEndToFunction(MF, TII); cleanupFunctionData(MF); diff --git a/llvm/lib/Target/XVM/XVMCFGStructure.cpp b/llvm/lib/Target/XVM/XVMCFGStructure.cpp index aca00b1be1c65c5741ff5988d54f9c688c326372..db76d9468f30813d7d6c114d46d5bb0c0e160df3 100644 --- a/llvm/lib/Target/XVM/XVMCFGStructure.cpp +++ b/llvm/lib/Target/XVM/XVMCFGStructure.cpp @@ -104,13 +104,13 @@ void XVMCFGStructure::placeLoopMarker(MachineBasicBlock &MBB) { getBeginInsertPos(*LoopTop, LoopInsertPos); getEndInsertPos(*LoopBottom, LoopEndInsertPos); - MachineInstr *Begin = BuildMI(*LoopTop, LoopInsertPos, - LoopTop->findDebugLoc(LoopInsertPos), - TII->get(XVM::LOOP)); - //FIXME: the debug location might be problematic - MachineInstr *End = BuildMI(*LoopBottom, LoopEndInsertPos, - LoopBottom->findDebugLoc(LoopEndInsertPos), - TII->get(XVM::END_LOOP)); + BuildMI(*LoopTop, LoopInsertPos, + LoopTop->findDebugLoc(LoopInsertPos), + TII->get(XVM::LOOP)); + //Note: the debug location might be problematic + BuildMI(*LoopBottom, LoopEndInsertPos, + LoopBottom->findDebugLoc(LoopEndInsertPos), + TII->get(XVM::END_LOOP)); } static bool isContinueBlock(MachineBasicBlock &MBB) { @@ -129,7 +129,7 @@ void XVMCFGStructure::placeIfMarker(MachineBasicBlock &MBB) { // We need to negate the conditions in each branch MachineFunction *MF = MBB.getParent(); const auto &TII = MF->getSubtarget().getInstrInfo(); - auto &MDT = getAnalysis(); + getAnalysis(); auto &MPDT = getAnalysis(); if (!MBB.canFallThrough() || MBB.empty()) @@ -176,13 +176,15 @@ void XVMCFGStructure::placeIfMarker(MachineBasicBlock &MBB) { BuildMI(*ElseEndBlock, ElseEndInsertPos, ElseEndBlock->findDebugLoc(ElseEndInsertPos), TII->get(XVM::END_ELSE)); - BuildMI(*ElseEndBlock, ++ElseEndInsertPos, + ++ElseEndInsertPos; + BuildMI(*ElseEndBlock, ElseEndInsertPos, ElseEndBlock->findDebugLoc(ElseEndInsertPos), TII->get(XVM::END_IF)); } else { - BuildMI(*ThenEndBlock, ++ThenEndInsertPos, - ThenEndBlock->findDebugLoc(ThenEndInsertPos), - TII->get(XVM::END_IF)); + ++ThenEndInsertPos; + BuildMI(*ThenEndBlock, ThenEndInsertPos, + ThenEndBlock->findDebugLoc(ThenEndInsertPos), + TII->get(XVM::END_IF)); } } @@ -230,16 +232,15 @@ void XVMCFGStructure::fixLoops(MachineBasicBlock &MBB) { Pred->getFallThrough() : ContinueBlock; - //FIXME: Does adding the new block destroy the loop structure? + //Note: Does adding the new block destroy the loop structure? MachineFunction::iterator MBBI = ++Pred->getIterator(); MF->insert(MBBI, ContinueBlock); MachineBasicBlock *Old = &MBB; - if (Old != NewSucc){ - // FIXME: do we need to do anything for else case?? + if (Old != NewSucc) { + // Note: do we need to do anything for else case?? Pred->ReplaceUsesOfBlockWith(&MBB, NewSucc); - } - else{ + } else { report_fatal_error("old MBB == new succ, need to handle this case"); } @@ -249,7 +250,7 @@ void XVMCFGStructure::fixLoops(MachineBasicBlock &MBB) { Pred->addSuccessorWithoutProb(ContinueBlock); MPDT.getBase().applyUpdates({{DomTreeT::Insert, &*Pred, ContinueBlock}}); } - ContinueBlock->addSuccessor(&MBB, BranchProbability :: getOne()); + ContinueBlock->addSuccessor(&MBB, BranchProbability::getOne()); MPDT.getBase().applyUpdates({{DomTreeT::Insert, ContinueBlock, &MBB}}); // we jump to the fall through and the continue block became new fall through Loop->addBasicBlockToLoop(ContinueBlock, MLI.getBase()); @@ -266,10 +267,10 @@ void XVMCFGStructure::fixLoops(MachineBasicBlock &MBB) { MachineBasicBlock *BreakBlock = MF->CreateMachineBasicBlock(); auto BreakInsertPos = BreakBlock->begin(); BuildMI(*BreakBlock, BreakInsertPos, - BreakBlock->findDebugLoc(BreakInsertPos), - TII->get(XVM::BREAK)); + BreakBlock->findDebugLoc(BreakInsertPos), + TII->get(XVM::BREAK)); - // TODO: insert blocks for multiple exits + // Note: to insert blocks for multiple exits MachineBasicBlock *FallThrough = LoopExiting->getFallThrough(); MachineFunction::iterator MBBI2 = FallThrough->getIterator(); MF->insert(MBBI2, BreakBlock); @@ -277,7 +278,7 @@ void XVMCFGStructure::fixLoops(MachineBasicBlock &MBB) { // puts the break block in place MachineBasicBlock *JumpTarget = LoopExiting->back().getOperand(0).getMBB(); - if (JumpTarget != FallThrough){ + if (JumpTarget != FallThrough) { // when the last instruction in the block is conditional branch LoopExiting->ReplaceUsesOfBlockWith(JumpTarget, FallThrough); LoopExiting->addSuccessorWithoutProb(BreakBlock); @@ -288,7 +289,7 @@ void XVMCFGStructure::fixLoops(MachineBasicBlock &MBB) { It != E; ++It) { MachineInstr *MI = &*It; if (MI) { - if (TII->isCondBranch(MI)){ + if (TII->isCondBranch(MI)) { JumpTarget = MI->getOperand(0).getMBB(); LoopExiting->ReplaceUsesOfBlockWith(JumpTarget, BreakBlock); break; @@ -300,7 +301,7 @@ void XVMCFGStructure::fixLoops(MachineBasicBlock &MBB) { {DomTreeT::Insert, LoopExiting, FallThrough}}); // The condition need to be negated MPDT.getBase().applyUpdates({{DomTreeT::Insert, LoopExiting, BreakBlock}}); - BreakBlock->addSuccessor(JumpTarget, BranchProbability :: getOne()); + BreakBlock->addSuccessor(JumpTarget, BranchProbability::getOne()); MPDT.getBase().applyUpdates({{DomTreeT::Insert, BreakBlock, JumpTarget}}); } } diff --git a/llvm/lib/Target/XVM/XVMExpandPseudoInsts.cpp b/llvm/lib/Target/XVM/XVMExpandPseudoInsts.cpp index 960fcc1d28f87c29c7768469f671a21c9d33fd49..5e75f124bf2aa5dbb32d4b9c8edde156f84bb1af 100644 --- a/llvm/lib/Target/XVM/XVMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/XVM/XVMExpandPseudoInsts.cpp @@ -39,7 +39,7 @@ bool XVMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { bool XVMExpandPseudo::expandMBB(MachineBasicBlock &MBB) { bool Modified = false; - MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); + MachineBasicBlock::iterator MBBI = MBB.begin(); int InstNumber = std::distance(MBB.begin(), MBB.end()); for (int i = 0; i < InstNumber; i++) { MachineBasicBlock::iterator NMBBI = std::next(MBBI); @@ -98,7 +98,6 @@ bool XVMExpandPseudo::expandSelectCC(MachineBasicBlock &MBB, MachineInstr &MI = *MBBI; const TargetInstrInfo *TII = MBB.getParent()->getSubtarget().getInstrInfo(); DebugLoc DL = MI.getDebugLoc(); - unsigned Opc = MI.getOpcode(); MachineFunction *MF = MBB.getParent(); MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -173,7 +172,6 @@ INITIALIZE_PASS(XVMExpandPseudo, "xvm-expand-pseudo", namespace llvm { FunctionPass *createXVMExpandPseudoPass() { return new XVMExpandPseudo(); } - } #endif diff --git a/llvm/lib/Target/XVM/XVMFrameLowering.cpp b/llvm/lib/Target/XVM/XVMFrameLowering.cpp index 348ae307c5be7776816331ebcba8686ccf600e34..bacd68abd954b085fa48cf184dc611c7798a8c83 100644 --- a/llvm/lib/Target/XVM/XVMFrameLowering.cpp +++ b/llvm/lib/Target/XVM/XVMFrameLowering.cpp @@ -62,7 +62,6 @@ void XVMFrameLowering::emitPrologue(MachineFunction &MF, uint64_t StackSize = MFI.getStackSize(); auto &ST = MF.getSubtarget(); const auto *TII = ST.getInstrInfo(); - auto &MRI = MF.getRegInfo(); auto InsertPt = MBB.begin(); DebugLoc DL; @@ -83,7 +82,6 @@ void XVMFrameLowering::emitEpilogue(MachineFunction &MF, } auto &ST = MF.getSubtarget(); const auto *TII = ST.getInstrInfo(); - auto &MRI = MF.getRegInfo(); auto InsertPt = MBB.getFirstTerminator(); DebugLoc DL; diff --git a/llvm/lib/Target/XVM/XVMISelDAGToDAG.cpp b/llvm/lib/Target/XVM/XVMISelDAGToDAG.cpp index af70cce50a07333a4fcf1078dc7d9f60e679f5d0..2909d9bfbeeba3cb3ec7ec16eaaeddc45aedb275 100644 --- a/llvm/lib/Target/XVM/XVMISelDAGToDAG.cpp +++ b/llvm/lib/Target/XVM/XVMISelDAGToDAG.cpp @@ -25,7 +25,6 @@ #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/IR/Constants.h" #include "llvm/IR/IntrinsicInst.h" -//#include "llvm/IR/IntrinsicsXVM.h" #include "llvm/Support/Debug.h" #include "llvm/Support/Endian.h" #include "llvm/Support/ErrorHandling.h" @@ -40,7 +39,6 @@ using namespace llvm; namespace { class XVMDAGToDAGISel : public SelectionDAGISel { - /// Subtarget - Keep a pointer to the XVMSubtarget around so that we can /// make the right decision when generating code for different subtargets. const XVMSubtarget *Subtarget; @@ -188,7 +186,6 @@ void XVMDAGToDAGISel::Select(SDNode *Node) { } void XVMDAGToDAGISel::PreprocessISelDAG() { - } FunctionPass *llvm::createXVMISelDag(XVMTargetMachine &TM) { diff --git a/llvm/lib/Target/XVM/XVMISelLowering.cpp b/llvm/lib/Target/XVM/XVMISelLowering.cpp index fe50f9ebefaf872d8f17c5221a3b152c4ea45bc5..b22b034e1d28c308c219061812d92161d4d64608 100644 --- a/llvm/lib/Target/XVM/XVMISelLowering.cpp +++ b/llvm/lib/Target/XVM/XVMISelLowering.cpp @@ -55,18 +55,6 @@ static bool is_valid_immediate_size(int32_t imm) return imm <= 0x3FFF && imm >= 0; } -static void fail(const SDLoc &DL, SelectionDAG &DAG, const char *Msg, - SDValue Val) { - MachineFunction &MF = DAG.getMachineFunction(); - std::string Str; - raw_string_ostream OS(Str); - OS << Msg; - Val->print(OS); - OS.flush(); - DAG.getContext()->diagnose( - DiagnosticInfoUnsupported(MF.getFunction(), Str, DL.getDebugLoc())); -} - static bool hasFP(const MachineFunction &MF) { return false; } @@ -116,7 +104,6 @@ static unsigned getBranchOpcodeFromSelectCC(MachineInstr &MI) { XVMTargetLowering::XVMTargetLowering(const TargetMachine &TM, const XVMSubtarget &STI) : TargetLowering(TM), Subtarget(&STI) { - // Set up the register classes. addRegisterClass(MVT::i64, &XVM::XVMGPRRegClass); @@ -248,9 +235,10 @@ XVMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); } -void XVMTargetLowering::ReplaceNodeResults( - SDNode *N, SmallVectorImpl &Results, SelectionDAG &DAG) const { - const char *err_msg; +void XVMTargetLowering::ReplaceNodeResults(SDNode *N, + SmallVectorImpl &Results, + SelectionDAG &DAG) const { + const char *err_msg = nullptr; uint32_t Opcode = N->getOpcode(); switch (Opcode) { default: @@ -359,7 +347,7 @@ SDValue XVMTargetLowering::LowerFormalArguments( if (doesNeedSP) { const MCPhysReg *CSRegs = MF.getRegInfo().getCalleeSavedRegs(); unsigned CSRcounter = 0; - for ( ; CSRegs[CSRcounter]; ++CSRcounter); + for (; CSRegs[CSRcounter]; ++CSRcounter); FI = MFI.CreateFixedObject(ValVT.getSizeInBits()/8, VA.getLocMemOffset() + CSRcounter*8, true); } else { @@ -399,9 +387,9 @@ SDValue XVMTargetLowering::LowerFormalArguments( } XFI->SetVarArgsFrameIndex( - MFI.CreateFixedObject(8, // size - VaArgOffset, // SPOffset - true)); // IsImmutable + MFI.CreateFixedObject(8, // size + VaArgOffset, // SPOffset + true)); // IsImmutable // Copy the registers that have not been used for var argument passing // assume per size is always 8 for (unsigned I = FirstRegIdx; I < ArgRegs.size(); I++, VaArgOffset += 8) { @@ -499,7 +487,7 @@ SDValue XVMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Push arguments into RegsToPass vector if (VA.isRegLoc()) RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - else{ + else { assert(VA.isMemLoc()); int32_t Offset = VA.getLocMemOffset(); @@ -681,7 +669,7 @@ SDValue XVMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { return DAG.getNode(XVMISD::BR_CC, DL, Op.getValueType(), Op.getOperand(0), LHS, RHS, TargetCC, Op.getOperand(2)); } - //FIXME: complete the lowering for other cases + //Note: complete the lowering for other cases later return Op; } @@ -707,10 +695,9 @@ SDValue XVMTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { int VarArgsFrameIndex = MF.getInfo()->GetVarArgsFrameIndex(); SDValue FrameIndex = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy(MF.getDataLayout())); - const Value *SV = cast(Op.getOperand(2))->getValue(); SDValue RetSDValue = DAG.getStore(Op.getOperand(0), SDLoc(Op), FrameIndex, Op.getOperand(1), - MachinePointerInfo() // unsigned AddressSpace = 0, int64_t offset = 0 - ); + MachinePointerInfo()); // unsigned AddressSpace = 0, int64_t offset = 0 + return RetSDValue; } @@ -745,8 +732,9 @@ const char *XVMTargetLowering::getTargetNodeName(unsigned Opcode) const { return "XVMISD::Wrapper"; case XVMISD::MEMCPY: return "XVMISD::MEMCPY"; + default: + return nullptr; } - return nullptr; } SDValue XVMTargetLowering::LowerGlobalAddress(SDValue Op, @@ -769,7 +757,7 @@ XVMTargetLowering::EmitSubregExt(MachineInstr &MI, MachineBasicBlock *BB, MachineBasicBlock * XVMTargetLowering::EmitInstrWithCustomInserterSelectCC(MachineInstr &MI, - MachineBasicBlock *BB) const { + MachineBasicBlock *BB) const { const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); DebugLoc DL = MI.getDebugLoc(); unsigned Opc = MI.getOpcode(); @@ -832,8 +820,7 @@ XVMTargetLowering::EmitInstrWithCustomInserterSelectCC(MachineInstr &MI, uint64_t LeastSignificantBits = ShiftAndGet16Bits(imm32, 0); Register VRegForMov = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * MovMI = BuildMI(BB, DL, TII.get(XVM::MOV_ri), VRegForMov) - .addImm(0); + BuildMI(BB, DL, TII.get(XVM::MOV_ri), VRegForMov).addImm(0); Register PrevReg = VRegForMov; if (LeastSignificantBits) { Register VRegForMovk1 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); @@ -887,15 +874,15 @@ XVMTargetLowering::EmitInstrWithCustomInserterSelectCC(MachineInstr &MI, MachineBasicBlock * XVMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { - const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); DebugLoc DL = MI.getDebugLoc(); unsigned Opc = MI.getOpcode(); - switch(Opc) { + switch (Opc) { case XVM::PseudoSelectCC_rr: case XVM::PseudoSelectCC_ri: return EmitInstrWithCustomInserterSelectCC(MI, BB); + default: + return BB; } - return BB; } EVT XVMTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, diff --git a/llvm/lib/Target/XVM/XVMInstrInfo.cpp b/llvm/lib/Target/XVM/XVMInstrInfo.cpp index c05322fd6f5fde6fbc1ac1c543958012659ca51a..c4b233cc6576fd3433e8119ad786491cc7ba579d 100644 --- a/llvm/lib/Target/XVM/XVMInstrInfo.cpp +++ b/llvm/lib/Target/XVM/XVMInstrInfo.cpp @@ -104,15 +104,14 @@ void XVMInstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, bool KillSrc) const { - if (XVM::XVMGPRRegClass.contains(DestReg, SrcReg) || - (XVM::XVMRRRegClass.contains(SrcReg)) && XVM::XVMGPRRegClass.contains(DestReg)) + if (XVM::XVMGPRRegClass.contains(DestReg, SrcReg) || + ((XVM::XVMRRRegClass.contains(SrcReg)) && XVM::XVMGPRRegClass.contains(DestReg))) BuildMI(MBB, I, DL, get(XVM::MOV_rr), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); else llvm_unreachable("To-be-extended: reg-to-reg copy"); return; - } static int ShiftAndGet16Bits(uint64_t num, int n) { @@ -120,8 +119,8 @@ static int ShiftAndGet16Bits(uint64_t num, int n) { } static inline void replace_imm_with_movk(MachineBasicBlock *BB, - MachineBasicBlock::iterator MI, - DebugLoc dl) + MachineBasicBlock::iterator MI, + DebugLoc dl) { const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); uint64_t imm = MI->getOperand(2).getImm(); @@ -145,7 +144,6 @@ static inline void replace_imm_with_movk(MachineBasicBlock *BB, BuildMI(*BB, MI, dl, TII.get(XVM::MOVK_ri)) .addReg(XVM::R2, RegState::Define).addImm(0).addImm(most_significant_bits).addImm(3); } - } void XVMInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const { @@ -279,7 +277,7 @@ bool XVMInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { - //TODO: consider the case when the CFG is stackified. + //Note: consider the case when the CFG is stackified later. // Maybe need to implement removeBranch and insertBranch bool HaveCond = false; @@ -349,9 +347,9 @@ unsigned XVMInstrInfo::insertBranch(MachineBasicBlock &MBB, assert(Cond.size() == 3 && "Expected 2 operands and an operation!"); - BuildMI(&MBB, DL, get(getBranchOpcFromCond(Cond))).addMBB(TBB) \ - .add(Cond[1]) \ - .add(Cond[2]); + BuildMI(&MBB, DL, get(getBranchOpcFromCond(Cond))).addMBB(TBB) + .add(Cond[1]) + .add(Cond[2]); if (!FBB) return 1; BuildMI(&MBB, DL, get(XVM::BR)).addMBB(FBB); diff --git a/llvm/lib/Target/XVM/XVMMCInstLower.cpp b/llvm/lib/Target/XVM/XVMMCInstLower.cpp index 4be8597b00af6a1b7c4b87a9844e4d583f2dc664..ac58ad2c755b83870b41cbf26b14e6793d92ce00 100644 --- a/llvm/lib/Target/XVM/XVMMCInstLower.cpp +++ b/llvm/lib/Target/XVM/XVMMCInstLower.cpp @@ -36,7 +36,6 @@ XVMMCInstLower::GetExternalSymbolSymbol(const MachineOperand &MO) const { MCOperand XVMMCInstLower::LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const { - const MCExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); if (!MO.isJTI() && MO.getOffset()) diff --git a/llvm/lib/Target/XVM/XVMRegisterInfo.cpp b/llvm/lib/Target/XVM/XVMRegisterInfo.cpp index de1f49848acfc8a893b4d458cf3fc112474e1cbd..4466b1826e3187314b0cf6b15d0e3bcc2c162cd9 100644 --- a/llvm/lib/Target/XVM/XVMRegisterInfo.cpp +++ b/llvm/lib/Target/XVM/XVMRegisterInfo.cpp @@ -25,8 +25,9 @@ #define GET_REGINFO_TARGET_DESC #include "XVMGenRegisterInfo.inc" -using namespace llvm; #include + +using namespace llvm; #define XVM_STACK_SIZE_LIMIT 1024 XVMRegisterInfo::XVMRegisterInfo() @@ -64,7 +65,6 @@ void XVMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); DebugLoc DL = MI.getDebugLoc(); - if (!DL) /* try harder to get some debug loc */ for (auto &I : MBB) @@ -100,7 +100,7 @@ void XVMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, WarnSize(Offset, MF, DL); Register reg = MI.getOperand(i - 1).getReg(); BuildMI(MBB, ++II, DL, TII.get(XVM::MOV_rr), reg).addReg(XVM::SP); - if(StackSize + Offset) { + if (StackSize + Offset) { BuildMI(MBB, II, DL, TII.get(XVM::AddRef_ri), reg).addReg(reg).addImm(StackSize + Offset); } MI.eraseFromParent(); @@ -109,14 +109,13 @@ void XVMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) + MI.getOperand(i + 1).getImm(); - if (!isInt<32>(Offset)) llvm_unreachable("bug in frame offset"); WarnSize(Offset, MF, DL); if (MI.getOpcode() == XVM::FI_ri) { - // TODO: to be tested and modified + // Note: to be tested and modified later // architecture does not really support FI_ri, replace it with // MOV_rr , frame_reg // ADD_ri , imm diff --git a/llvm/lib/Target/XVM/XVMSelectionDAGInfo.cpp b/llvm/lib/Target/XVM/XVMSelectionDAGInfo.cpp index b828765449d709359ad54975bcc8d6d941ba2d91..c2462ef33869157688b2a47aa4bc96daa985d08b 100644 --- a/llvm/lib/Target/XVM/XVMSelectionDAGInfo.cpp +++ b/llvm/lib/Target/XVM/XVMSelectionDAGInfo.cpp @@ -36,11 +36,11 @@ SDValue XVMSelectionDAGInfo::EmitTargetCodeForMemcpy( } SDValue XVMSelectionDAGInfo::EmitTargetCodeForMemmove( - SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, - SDValue Op1, SDValue Op2, SDValue Op3, - Align Alignment, bool isVolatile, - MachinePointerInfo DstPtrInfo, - MachinePointerInfo SrcPtrInfo) const { + SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, + SDValue Op1, SDValue Op2, SDValue Op3, + Align Alignment, bool isVolatile, + MachinePointerInfo DstPtrInfo, + MachinePointerInfo SrcPtrInfo) const { SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); ConstantSDNode *ConstantSize = dyn_cast(Op3); if (ConstantSize) { @@ -55,15 +55,14 @@ SDValue XVMSelectionDAGInfo::EmitTargetCodeForMemmove( } SDValue XVMSelectionDAGInfo::EmitTargetCodeForMemset( - SelectionDAG &DAG, const SDLoc &DL, - SDValue Chain, SDValue Op1, SDValue Op2, - SDValue Op3, Align Alignment, bool IsVolatile, - bool AlwaysInline, - MachinePointerInfo DstPtrInfo) const { + SelectionDAG &DAG, const SDLoc &DL, + SDValue Chain, SDValue Op1, SDValue Op2, + SDValue Op3, Align Alignment, bool IsVolatile, + bool AlwaysInline, + MachinePointerInfo DstPtrInfo) const { SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); ConstantSDNode *ConstantSize = dyn_cast(Op3); if (ConstantSize) { - uint64_t CopyLen = ConstantSize->getZExtValue(); Op1 = DAG.getNode(XVMISD::MEMSET, DL, VTs, Chain, Op1, DAG.getAnyExtOrTrunc(Op2, DL, MVT::i64), DAG.getZExtOrTrunc(Op3, DL, MVT::i64)); } else { diff --git a/llvm/lib/Target/XVM/XVMSubtarget.cpp b/llvm/lib/Target/XVM/XVMSubtarget.cpp index 4b2844c6103b8d79f86389a456b966f19e86c65a..722d55c35e097556e11cb5721c50e864756a22a0 100644 --- a/llvm/lib/Target/XVM/XVMSubtarget.cpp +++ b/llvm/lib/Target/XVM/XVMSubtarget.cpp @@ -16,7 +16,6 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Host.h" -using namespace llvm; #define DEBUG_TYPE "xvm-subtarget" @@ -24,6 +23,8 @@ using namespace llvm; #define GET_SUBTARGETINFO_CTOR #include "XVMGenSubtargetInfo.inc" +using namespace llvm; + void XVMSubtarget::anchor() {} XVMSubtarget &XVMSubtarget::initializeSubtargetDependencies(StringRef CPU, diff --git a/llvm/lib/Target/XVM/XVMTargetMachine.cpp b/llvm/lib/Target/XVM/XVMTargetMachine.cpp index e4982da3bb5c8ca36c2341f1ac44791cf9dd5eb2..f7435f9a193c65b47e6914e074b5932a76f88065 100644 --- a/llvm/lib/Target/XVM/XVMTargetMachine.cpp +++ b/llvm/lib/Target/XVM/XVMTargetMachine.cpp @@ -76,8 +76,6 @@ XVMTargetMachine::XVMTargetMachine(const Target &T, const Triple &TT, initAsmInfo(); this->Options.EmitAddrsig = false; - XVMMCAsmInfo *MAI = - static_cast(const_cast(AsmInfo.get())); setRequiresStructuredCFG(true); } @@ -111,7 +109,6 @@ TargetPassConfig *XVMTargetMachine::createPassConfig(PassManagerBase &PM) { } void XVMPassConfig::addIRPasses() { -// addPass(createXVMCheckAndAdjustIR()); TargetPassConfig::addIRPasses(); } @@ -129,7 +126,6 @@ bool XVMPassConfig::addInstSelector() { } void XVMPassConfig::addPreRegAlloc() { - // addPass(createXVMExpandPseudoPass()); addPass(createXVMUpdateRefInstrForMIPass()); } @@ -140,7 +136,6 @@ void XVMPassConfig::addPreEmitPass() { // Currently, the algorithm is from WebAssembly. addPass(createXVMCFGSort()); addPass(createXVMCFGStackify()); - // addPass(createXVMCFGStructure()); } #else diff --git a/llvm/lib/Target/XVM/XVMUpdateRefInstrForMI.cpp b/llvm/lib/Target/XVM/XVMUpdateRefInstrForMI.cpp index 99b5f8baa8e533af5fbc10997383da3dfdcc6579..11bdb0aad565bd82b0933de74e27a447b9b73f96 100644 --- a/llvm/lib/Target/XVM/XVMUpdateRefInstrForMI.cpp +++ b/llvm/lib/Target/XVM/XVMUpdateRefInstrForMI.cpp @@ -21,7 +21,7 @@ namespace { class XVMUpdateRefInstrForMI : public MachineFunctionPass { public: static char ID; - const XVMInstrInfo * TII = nullptr; + const XVMInstrInfo *TII = nullptr; XVMUpdateRefInstrForMI() : MachineFunctionPass(ID) { initializeXVMUpdateRefInstrForMIPass(*PassRegistry::getPassRegistry()); } @@ -39,16 +39,14 @@ static std::map MapRefRegInFunc; static std::map MapPtrRegInFunc; static std::set SetNonRefRegInFunc; -static void CheckFunctionReturn(Function & F) { +static void CheckFunctionReturn(Function &F) { Type *Ty = F.getReturnType(); /* Return is always r0 for xvm */ if (auto *PTy = dyn_cast(Ty)) { MapRefRegInFunc.insert(std::pair(XVM::R0, XVM_SYM_REG_REF)); - // } else if (Ty->isIntegerTy(64) || Ty->isIntegerTy(32) || Ty->isIntegerTy(16) || Ty->isIntegerTy(8) || Ty->isIntegerTy(1)) { } else if (Ty->isIntegerTy()) { MapRefRegInFunc.insert(std::pair(XVM::R0, XVM_SYM_REG_NON_REF)); - //} else if (Ty->isVoidTy() || Ty->isIntegerTy()){ - } else if (Ty->isVoidTy()){ + } else if (Ty->isVoidTy()) { ; } else { llvm_unreachable("Invalid return type"); @@ -56,7 +54,7 @@ static void CheckFunctionReturn(Function & F) { } static Register inline getPhysicalRegister(unsigned index) { - switch(index) { + switch (index) { case 0: return XVM::R0; case 1: return XVM::R1; case 2: return XVM::R2; @@ -80,7 +78,7 @@ static Register inline getPhysicalRegister(unsigned index) { } } -static void CheckFunctionArgs(Function & F) { +static void CheckFunctionArgs(Function &F) { int idx = 0; /* Here we assume r0, ..., r5 are the registers for input parameters * We only need to check the register ones: for others in stack, @@ -150,7 +148,7 @@ static void checkSimpleMIWithRef(MachineInstr &MI) { } } -static bool updateCopyMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateCopyMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { /* No update for Copy */ return false; } @@ -169,7 +167,7 @@ static void checkMovMIWithRef(MachineInstr &MI) { } } -static bool updateMovMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateMovMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { /* No update for Move */ return false; } @@ -208,7 +206,7 @@ static void checkLoadMIWithRef(MachineInstr &MI) { } } -static bool updateLoadMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateLoadMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { if (MI.getOpcode() == XVM::LDD) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); @@ -228,7 +226,7 @@ static bool updateLoadMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { static void checkAddSubMIWithRef(MachineInstr &MI) { if (MI.getOpcode() == XVM::ADD_ri || MI.getOpcode() == XVM::ADD_rr || - MI.getOpcode() == XVM::SUB_ri || MI.getOpcode() == XVM::SUB_rr ) { + MI.getOpcode() == XVM::SUB_ri || MI.getOpcode() == XVM::SUB_rr) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); @@ -261,7 +259,7 @@ static void checkOrXorAndMIWithRef(MachineInstr &MI) { } } -static inline bool updateAddSubWithSubAddForImm(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateAddSubWithSubAddForImm(MachineInstr &MI, const XVMInstrInfo *TII) { if (MI.getOpcode() == XVM::ADD_ri || MI.getOpcode() == XVM::SUB_ri) { assert(MI.getOperand(2).isImm()); int64_t imm = MI.getOperand(2).getImm(); @@ -280,7 +278,7 @@ static inline bool updateAddSubWithSubAddForImm(MachineInstr &MI, const XVMInstr return false; } -static inline void updateAddRiWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline void updateAddRiWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getOperand(2).isImm()); int64_t imm = MI.getOperand(2).getImm(); if (imm < 0) { @@ -292,7 +290,7 @@ static inline void updateAddRiWithRef(MachineInstr &MI, const XVMInstrInfo * TII } } -static inline bool updateAddMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateAddMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); @@ -305,7 +303,7 @@ static inline bool updateAddMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { // Update MO_use to be ref if MO_def is ref updateRefMapForRefInst(MO_use, XVM_SYM_REG_REF); - if(MI.getOpcode() == XVM::ADD_ri) + if (MI.getOpcode() == XVM::ADD_ri) updateAddRiWithRef(MI, TII); else MI.setDesc(TII->get(XVM::AddRef_rr)); @@ -318,7 +316,7 @@ static inline bool updateAddMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII if (I != MapRefRegInFunc.end()) { if (I->second == XVM_SYM_REG_REF && SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { - if(MI.getOpcode() == XVM::ADD_ri) + if (MI.getOpcode() == XVM::ADD_ri) updateAddRiWithRef(MI, TII); else MI.setDesc(TII->get(XVM::AddRef_rr)); @@ -328,7 +326,7 @@ static inline bool updateAddMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII return false; } -static inline bool updateSubriMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateSubriMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); @@ -351,7 +349,7 @@ static inline bool updateSubriMIWithRef(MachineInstr &MI, const XVMInstrInfo * T if (I != MapRefRegInFunc.end()) { if (I->second == XVM_SYM_REG_REF && SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { - if(MI.getOpcode() == XVM::SUB_ri) + if (MI.getOpcode() == XVM::SUB_ri) MI.setDesc(TII->get(XVM::SubRef_ri)); else MI.setDesc(TII->get(XVM::SubRef_rr)); @@ -361,7 +359,7 @@ static inline bool updateSubriMIWithRef(MachineInstr &MI, const XVMInstrInfo * T return false; } -static inline bool updateSubrrMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateSubrrMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use1 = MI.getOperand(1); @@ -403,7 +401,7 @@ static inline bool updateSubrrMIWithRef(MachineInstr &MI, const XVMInstrInfo * T // Update add/sub with sub/add if negative imm -static bool updateAddSubMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateAddSubMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { bool Modified = false; switch (MI.getOpcode()) { case XVM::ADD_ri: @@ -420,7 +418,7 @@ static bool updateAddSubMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { } } -static inline bool updateOrMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateOrMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); @@ -433,7 +431,7 @@ static inline bool updateOrMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { // Update MO_use to be ref if MO_def is ref updateRefMapForRefInst(MO_use, XVM_SYM_REG_REF); - if(MI.getOpcode() == XVM::OR_ri) + if (MI.getOpcode() == XVM::OR_ri) MI.setDesc(TII->get(XVM::OrRef_ri)); else MI.setDesc(TII->get(XVM::OrRef_rr)); @@ -446,7 +444,7 @@ static inline bool updateOrMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) if (I != MapRefRegInFunc.end()) { if (I->second == XVM_SYM_REG_REF && SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { - if(MI.getOpcode() == XVM::OR_ri) + if (MI.getOpcode() == XVM::OR_ri) MI.setDesc(TII->get(XVM::OrRef_ri)); else MI.setDesc(TII->get(XVM::OrRef_rr)); @@ -456,7 +454,7 @@ static inline bool updateOrMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) return false; } -static inline bool updateXorMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateXorMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); @@ -469,7 +467,7 @@ static inline bool updateXorMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { // Update MO_use to be ref if MO_def is ref updateRefMapForRefInst(MO_use, XVM_SYM_REG_REF); - if(MI.getOpcode() == XVM::XOR_ri) + if (MI.getOpcode() == XVM::XOR_ri) MI.setDesc(TII->get(XVM::XorRef_ri)); else MI.setDesc(TII->get(XVM::XorRef_rr)); @@ -482,7 +480,7 @@ static inline bool updateXorMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII if (I != MapRefRegInFunc.end() && SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { if (I->second == XVM_SYM_REG_REF) { - if(MI.getOpcode() == XVM::XOR_ri) + if (MI.getOpcode() == XVM::XOR_ri) MI.setDesc(TII->get(XVM::XorRef_ri)); else MI.setDesc(TII->get(XVM::XorRef_rr)); @@ -492,7 +490,7 @@ static inline bool updateXorMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII return false; } -static inline bool updateAndMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static inline bool updateAndMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { assert(MI.getNumOperands() == 3); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); @@ -505,7 +503,7 @@ static inline bool updateAndMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { // Update MO_use to be ref if MO_def is ref updateRefMapForRefInst(MO_use, XVM_SYM_REG_REF); - if(MI.getOpcode() == XVM::AND_ri) + if (MI.getOpcode() == XVM::AND_ri) MI.setDesc(TII->get(XVM::AndRef_ri)); else MI.setDesc(TII->get(XVM::AndRef_rr)); @@ -518,7 +516,7 @@ static inline bool updateAndMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII if (I != MapRefRegInFunc.end() && SetNonRefRegInFunc.find(regNo) == SetNonRefRegInFunc.end()) { if (I->second == XVM_SYM_REG_REF) { - if(MI.getOpcode() == XVM::AND_ri) + if (MI.getOpcode() == XVM::AND_ri) MI.setDesc(TII->get(XVM::AndRef_ri)); else MI.setDesc(TII->get(XVM::AndRef_rr)); @@ -528,7 +526,7 @@ static inline bool updateAndMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII return false; } -static bool updateOrXorAndMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateOrXorAndMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { switch (MI.getOpcode()) { case XVM::OR_ri: @@ -545,7 +543,7 @@ static bool updateOrXorAndMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) } } -static std::map MachineOperandRegisterReplacementMap; +static std::map MORegReplaceMap; static std::set MachineInstrExceptionSet; /** mov rd #simm (16 bits) * movk rd, #uimm (16 bits), #shift (0:no 1:16bits 2:32bits 3:48bits) @@ -555,13 +553,12 @@ static std::set MachineInstrExceptionSet; #define NUM_OF_IMM_BITS_MOV 16 #define NUM_OF_IMM_BITS_MOVK1 32 #define NUM_OF_IMM_BITS_MOVK2 48 -#define NUM_OF_IMM_BITS_MOVK3 64 -static void handleOffsetWithInstr(MachineInstr &MI, const char * GlobalName) { +static void handleOffsetWithInstr(MachineInstr &MI, const char *GlobalName) { uint64_t SubSecOffset = GetSubSecOffsetForGlobal(GlobalName); MachineBasicBlock &MB = *MI.getParent(); MachineBasicBlock::iterator II = MI.getIterator(); - MachineFunction * MF = MB.getParent(); + MachineFunction *MF = MB.getParent(); DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF->getRegInfo(); @@ -571,109 +568,109 @@ static void handleOffsetWithInstr(MachineInstr &MI, const char * GlobalName) { if (SubSecOffset < ((1 << NUM_OF_IMM_BITS_ADDREF))) { /* Addref */ Register VRegForAddref = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * AddrefMI = BuildMI(MB, ++II, DL, TII->get(XVM::AddRef_ri), VRegForAddref) + MachineInstr *AddrefMI = BuildMI(MB, ++II, DL, TII->get(XVM::AddRef_ri), VRegForAddref) .addReg(MO_def.getReg()).addImm(SubSecOffset); MachineInstrExceptionSet.insert(AddrefMI); - MachineOperandRegisterReplacementMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); + MORegReplaceMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); } else if (SubSecOffset < ((1 << NUM_OF_IMM_BITS_MOV) -1)) { /* Mov */ Register VRegForMov = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) + MachineInstr *MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) .addImm(SubSecOffset); MachineInstrExceptionSet.insert(MovMI); /* Addref */ Register VRegForAddref = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) + MachineInstr *AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) .addReg(MO_def.getReg()).addReg(VRegForMov); MachineInstrExceptionSet.insert(AddrefMI); - MachineOperandRegisterReplacementMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); - } else if (SubSecOffset < ((1 << NUM_OF_IMM_BITS_MOVK1) -1)) { + MORegReplaceMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); + } else if (SubSecOffset < ((1UL << NUM_OF_IMM_BITS_MOVK1) -1)) { /* Mov */ unsigned int imm1 = SubSecOffset & 0X000000000000FFFF; Register VRegForMov = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) + MachineInstr *MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) .addImm(imm1); MachineInstrExceptionSet.insert(MovMI); /* Movk */ unsigned int imm2 = (SubSecOffset & 0X00000000FFFF0000)>>16; Register VRegForMovk1 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * MovkMI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk1) + MachineInstr *MovkMI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk1) .addReg(VRegForMov).addImm(imm2).addImm(1); MachineInstrExceptionSet.insert(MovkMI); /* Addref only*/ Register VRegForAddref = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) + MachineInstr *AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) .addReg(MO_def.getReg()).addReg(VRegForMovk1); MachineInstrExceptionSet.insert(AddrefMI); - MachineOperandRegisterReplacementMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); - } else if (SubSecOffset < ((1 << NUM_OF_IMM_BITS_MOVK2) -1)) { + MORegReplaceMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); + } else if (SubSecOffset < ((1UL << NUM_OF_IMM_BITS_MOVK2) -1)) { /* Mov */ unsigned int imm1 = SubSecOffset & 0X000000000000FFFF; Register VRegForMov = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) + MachineInstr *MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) .addImm(imm1); MachineInstrExceptionSet.insert(MovMI); /* Movk */ unsigned int imm2 = (SubSecOffset & 0X00000000FFFF0000)>>16; Register VRegForMovk1 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * Movk1MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk1) + MachineInstr *Movk1MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk1) .addReg(VRegForMov).addImm(imm2).addImm(1); MachineInstrExceptionSet.insert(Movk1MI); /* Movk */ unsigned int imm3 = (SubSecOffset & 0X0000FFFF00000000)>>32; Register VRegForMovk2 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * Movk2MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk2) + MachineInstr *Movk2MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk2) .addReg(VRegForMovk1).addImm(imm3).addImm(2); MachineInstrExceptionSet.insert(Movk2MI); /* Addref only*/ Register VRegForAddref = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) + MachineInstr *AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) .addReg(MO_def.getReg()).addReg(VRegForMovk2); MachineInstrExceptionSet.insert(AddrefMI); - MachineOperandRegisterReplacementMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); - } else if (SubSecOffset < ((1 << NUM_OF_IMM_BITS_MOVK3) -1)) { + MORegReplaceMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); + } else { /* Mov */ unsigned int imm1 = SubSecOffset & 0X000000000000FFFF; Register VRegForMov = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) + MachineInstr *MovMI = BuildMI(MB, ++II, DL, TII->get(XVM::MOV_ri), VRegForMov) .addImm(imm1); MachineInstrExceptionSet.insert(MovMI); /* Movk */ unsigned int imm2 = (SubSecOffset & 0X00000000FFFF0000)>>16; Register VRegForMovk1 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * Movk1MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk1) + MachineInstr *Movk1MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk1) .addReg(VRegForMov).addImm(imm2).addImm(1); MachineInstrExceptionSet.insert(Movk1MI); /* Movk */ unsigned int imm3 = (SubSecOffset & 0X0000FFFF00000000)>>32; Register VRegForMovk2 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * Movk2MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk2) + MachineInstr *Movk2MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk2) .addReg(VRegForMovk1).addImm(imm3).addImm(2); MachineInstrExceptionSet.insert(Movk2MI); /* Movk */ unsigned int imm4 = (SubSecOffset & 0XFFFF000000000000)>>48; Register VRegForMovk3 = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * Movk3MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk3) + MachineInstr *Movk3MI = BuildMI(MB, II, DL, TII->get(XVM::MOVK_ri), VRegForMovk3) .addReg(VRegForMovk2).addImm(imm4).addImm(3); MachineInstrExceptionSet.insert(Movk3MI); /* Addref only*/ Register VRegForAddref = MRI.createVirtualRegister(&XVM::XVMGPRRegClass); - MachineInstr * AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) + MachineInstr *AddrefMI = BuildMI(MB, II, DL, TII->get(XVM::AddRef_rr), VRegForAddref) .addReg(MO_def.getReg()).addReg(VRegForMovk3); MachineInstrExceptionSet.insert(AddrefMI); - MachineOperandRegisterReplacementMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); + MORegReplaceMap.insert(std::pair(MO_def.getReg(), &AddrefMI->getOperand(0))); } } } static void updatePtrRegRefBasedGlobals(MachineInstr &MI) { - switch(MI.getOpcode()) { + switch (MI.getOpcode()) { case XVM::LD_global_imm64: { assert(MI.getNumOperands() >= 2); MachineOperand &MO_def = MI.getOperand(0); MachineOperand &MO_use = MI.getOperand(1); if (MO_use.isGlobal()) { - const char * GlobalName = MO_use.getGlobal()->getName().data(); + const char *GlobalName = MO_use.getGlobal()->getName().data(); LLVM_DEBUG(dbgs() << "Global:" << GlobalName << ' to load.\n'); MapRefRegInFunc.insert(std::pair(MO_def.getReg(), XVM_SYM_REG_REF)); unsigned int ptrLevel = GetPtrRegisterLevelBasedOnName(GlobalName); @@ -738,7 +735,7 @@ static void checkStoreMIWithRef(MachineInstr &MI) { // always be ref MapRefRegInFunc.insert(std::pair(MO_use2.getReg(), XVM_SYM_REG_REF)); } else if (MO_use2.isFI()) { - /* FIXME: we might need a fix for FI scenario: + /* Note: we might need a fix for FI scenario: STB killed %6:xvmgpr, %stack.2.atomic-temp, 0 :: (store (s8) into %ir.atomic-temp) It will be handled in eliminateFrameIndex. */ @@ -748,7 +745,7 @@ static void checkStoreMIWithRef(MachineInstr &MI) { } } -static bool updateStoreMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateStoreMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { if (MI.getOpcode() == XVM::STD) { assert(MI.getNumOperands() == 3); MachineOperand &MO_use1 = MI.getOperand(0); @@ -770,7 +767,7 @@ static void checkPhiMIWithRef(MachineInstr &MI) { unsigned numOfFrom = MI.getNumOperands() / 2; assert(numOfFrom * 2 + 1 == MI.getNumOperands()); MachineOperand &MO_def = MI.getOperand(0); - for(unsigned idx = 0; idx < numOfFrom; idx++) { + for (unsigned idx = 0; idx < numOfFrom; idx++) { MachineOperand &MO_use = MI.getOperand(idx*2+1); setRefFlagFor2Ops(MO_def, MO_use); } @@ -778,20 +775,20 @@ static void checkPhiMIWithRef(MachineInstr &MI) { } } -static bool updatePhiMIWithRef(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updatePhiMIWithRef(MachineInstr &MI, const XVMInstrInfo *TII) { /* No update for Phi*/ return false; } -static bool updateRegistersInMI(MachineInstr &MI, const XVMInstrInfo * TII) { +static bool updateRegistersInMI(MachineInstr &MI, const XVMInstrInfo *TII) { SmallVector OperandsInMI; bool replaceOperand = false; - if ( MachineInstrExceptionSet.find(&MI) == MachineInstrExceptionSet.end()) { - for(unsigned int i = 0; i < MI.getNumOperands(); i++) { + if (MachineInstrExceptionSet.find(&MI) == MachineInstrExceptionSet.end()) { + for (unsigned int i = 0; i < MI.getNumOperands(); i++) { MachineOperand &MO = MI.getOperand(i); if (MO.isReg()) { - std::map::iterator I = MachineOperandRegisterReplacementMap.find(MO.getReg()); - if (I == MachineOperandRegisterReplacementMap.end()) { + std::map::iterator I = MORegReplaceMap.find(MO.getReg()); + if (I == MORegReplaceMap.end()) { OperandsInMI.push_back(MO); } else { bool isDef = false; @@ -808,12 +805,12 @@ static bool updateRegistersInMI(MachineInstr &MI, const XVMInstrInfo * TII) { if (replaceOperand) { MachineBasicBlock &MB = *MI.getParent(); MachineBasicBlock::iterator II = MI.getIterator(); - MachineFunction * MF = MB.getParent(); + MachineFunction *MF = MB.getParent(); DebugLoc DL = MI.getDebugLoc(); const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); MachineRegisterInfo &MRI = MF->getRegInfo(); - MachineInstr * ReplaceMI = BuildMI(MB, II, DL, TII->get(MI.getOpcode())); - for( MachineOperand pMO: OperandsInMI) { + MachineInstr *ReplaceMI = BuildMI(MB, II, DL, TII->get(MI.getOpcode())); + for (MachineOperand pMO: OperandsInMI) { ReplaceMI->addOperand(pMO); } MB.remove_instr(&MI); @@ -829,7 +826,7 @@ static bool updateRegistersInMI(MachineInstr &MI, const XVMInstrInfo * TII) { * */ static void propogateNonRefInfo(const MachineBasicBlock &MBB) { MachineBasicBlock::const_iterator MBBI = MBB.begin(), E = MBB.end(); - while(MBBI != E) { + while (MBBI != E) { MachineBasicBlock::const_iterator NMBBI = std::next(MBBI); const MachineInstr &MI = *MBBI; MBBI = NMBBI; @@ -852,9 +849,9 @@ static void propogateNonRefInfo(const MachineBasicBlock &MBB) { * * */ static void updateNonRefInfoViaCalls(const MachineBasicBlock &MBB, - std::set &FuncSet) { + std::set &FuncSet) { MachineBasicBlock::const_iterator MBBI = MBB.begin(), E = MBB.end(); - while(MBBI != E) { + while (MBBI != E) { MachineBasicBlock::const_iterator NMBBI = std::next(MBBI); const MachineInstr &MI = *MBBI; MBBI = NMBBI; @@ -878,7 +875,7 @@ static void updateNonRefInfoViaCalls(const MachineBasicBlock &MBB, } } // save va reg from the copy with r0 - const MachineInstr &NextNextMI =*MBBI; + const MachineInstr &NextNextMI = *MBBI; if (NextNextMI.getOpcode() == XVM::COPY || NextNextMI.getOpcode() == XVM::MOV_rr) { assert(NextNextMI.getNumOperands() == 2); @@ -926,7 +923,7 @@ bool XVMUpdateRefInstrForMI::runOnMachineFunction(MachineFunction &MF) { MapRefRegInFunc.clear(); MapPtrRegInFunc.clear(); - MachineOperandRegisterReplacementMap.clear(); + MORegReplaceMap.clear(); MachineInstrExceptionSet.clear(); SetNonRefRegInFunc.clear(); CheckFunctionArgs(MF.getFunction()); @@ -956,7 +953,7 @@ bool XVMUpdateRefInstrForMI::updateRefInfoInMBB(MachineBasicBlock &MBB) { bool Modified = false; updatePtrRefInMBB(MBB); - /* FIXME: the two passes may be merged for efficiency */ + /* Note: the two passes may be merged for efficiency */ MachineBasicBlock::reverse_iterator MBBI = MBB.rbegin(), E = MBB.rend(); InstNumber = std::distance(MBB.begin(), MBB.end()); for (int i = 0; i < InstNumber; i++) { @@ -993,9 +990,7 @@ bool XVMUpdateRefInstrForMI::updateRefInfoInMBB(MachineBasicBlock &MBB) { INITIALIZE_PASS(XVMUpdateRefInstrForMI, "xvm-Ref-Determine-pseudo", XVM_REF_DETERMINE_NAME, false, false) namespace llvm { - FunctionPass *createXVMUpdateRefInstrForMIPass() { return new XVMUpdateRefInstrForMI(); } - } #endif