From 67b45c1423450d8f0237df833600562975b4afce Mon Sep 17 00:00:00 2001
From: kosovpavel <kosov.pavel@huawei.com>
Date: Tue, 27 Sep 2022 09:52:03 +0300
Subject: [PATCH] [OHOS] Add riscv64-linux-ohos target

Signed-off-by: kosovpavel <kosov.pavel@huawei.com>
---
 clang/lib/Basic/Targets.cpp                   |   7 +-
 clang/lib/Driver/ToolChains/Arch/RISCV.cpp    |   5 +-
 clang/lib/Driver/ToolChains/OHOS.cpp          |   2 +
 clang/test/Preprocessor/ohos.c                |   2 +
 .../lib/sanitizer_common/sanitizer_linux.cpp  |   2 +-
 .../lib/sanitizer_common/sanitizer_linux.h    |   3 +
 llvm-build/Makefile                           |   8 +
 llvm-build/build.py                           |  22 +-
 llvm-build/build_musl.sh                      |   6 +-
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp   |   2 +
 llvm/test/CodeGen/RISCV/emutls.ll             | 307 ++++++++++++++++++
 llvm/test/CodeGen/RISCV/emutls_generic.ll     |  75 +++++
 12 files changed, 432 insertions(+), 9 deletions(-)
 create mode 100644 llvm/test/CodeGen/RISCV/emutls.ll
 create mode 100644 llvm/test/CodeGen/RISCV/emutls_generic.ll

diff --git a/clang/lib/Basic/Targets.cpp b/clang/lib/Basic/Targets.cpp
index b0c3e9ce9c97..8ba3f5c3223b 100644
--- a/clang/lib/Basic/Targets.cpp
+++ b/clang/lib/Basic/Targets.cpp
@@ -420,7 +420,12 @@ TargetInfo *AllocateTarget(const llvm::Triple &Triple,
     case llvm::Triple::Fuchsia:
       return new FuchsiaTargetInfo<RISCV64TargetInfo>(Triple, Opts);
     case llvm::Triple::Linux:
-      return new LinuxTargetInfo<RISCV64TargetInfo>(Triple, Opts);
+      switch (Triple.getEnvironment()) {
+      default:
+        return new LinuxTargetInfo<RISCV64TargetInfo>(Triple, Opts);
+      case llvm::Triple::OpenHOS:
+        return new OHOSTargetInfo<RISCV64TargetInfo>(Triple, Opts);
+      }
     default:
       return new RISCV64TargetInfo(Triple, Opts);
     }
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index c7f2a3ea5e02..57142464e568 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -554,8 +554,9 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
   if (Args.hasArg(options::OPT_ffixed_x31))
     Features.push_back("+reserve-x31");
 
-  // -mrelax is default, unless -mno-relax is specified.
-  if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
+  // lld does not support relocations used by -mrelax on RISC-V
+  bool DefaultMRelax = !Triple.isOpenHOS();
+  if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, DefaultMRelax))
     Features.push_back("+relax");
   else
     Features.push_back("-relax");
diff --git a/clang/lib/Driver/ToolChains/OHOS.cpp b/clang/lib/Driver/ToolChains/OHOS.cpp
index 0c243a1ef723..efbe8fb778d1 100644
--- a/clang/lib/Driver/ToolChains/OHOS.cpp
+++ b/clang/lib/Driver/ToolChains/OHOS.cpp
@@ -103,6 +103,8 @@ std::string OHOS::getMultiarchTriple(const llvm::Triple &T) const {
     return T.isOSLiteOS() ? "arm-liteos-ohos" : "arm-linux-ohos";
   case llvm::Triple::riscv32:
     return "riscv32-liteos-ohos";
+  case llvm::Triple::riscv64:
+    return "riscv64-linux-ohos";
   case llvm::Triple::x86:
     return "i686-linux-ohos";
   case llvm::Triple::x86_64:
diff --git a/clang/test/Preprocessor/ohos.c b/clang/test/Preprocessor/ohos.c
index 9c3a81bbceed..f67d342aa7cb 100644
--- a/clang/test/Preprocessor/ohos.c
+++ b/clang/test/Preprocessor/ohos.c
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 -x c++ -E -dM -ffreestanding -triple=arm-linux-ohos < /dev/null | FileCheck %s -match-full-lines -check-prefix=ARM-OHOS-CXX
 // RUN: %clang_cc1 -x c++ -E -dM -ffreestanding -triple=aarch64-linux-ohos < /dev/null | FileCheck %s -match-full-lines -check-prefix=ARM64-OHOS-CXX
+// RUN: %clang_cc1 -x c++ -E -dM -ffreestanding -triple=riscv64-linux-ohos < /dev/null | FileCheck %s -match-full-lines -check-prefix=RISCV64-OHOS-CXX
 // RUN: %clang_cc1 -x c++ -E -dM -ffreestanding -triple=x86_64-linux-ohos < /dev/null | FileCheck %s -match-full-lines -check-prefix=X86_64-OHOS-CXX
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=arm-linux-ohos < /dev/null | FileCheck %s -check-prefix=OHOS-DEFS
 
@@ -7,6 +8,7 @@
 // ARM-OHOS-CXX: #define __STDCPP_DEFAULT_NEW_ALIGNMENT__ 8U
 // ARM64-HOS-CXX: #define __STDCPP_DEFAULT_NEW_ALIGNMENT__ 16UL
 // ARM64-OHOS-CXX: #define __STDCPP_DEFAULT_NEW_ALIGNMENT__ 16UL
+// RISCV64-OHOS-CXX: #define __STDCPP_DEFAULT_NEW_ALIGNMENT__ 16UL
 // X86_64-OHOS-CXX: #define __STDCPP_DEFAULT_NEW_ALIGNMENT__ 16UL
 // OHOS-DEFS: __OHOS_FAMILY__
 // OHOS-DEFS: __OHOS__
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
index bef7eb5d7f52..1f75c5813362 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp
@@ -34,7 +34,7 @@
 // format. Struct kernel_stat is defined as 'struct stat' in asm/stat.h. To
 // access stat from asm/stat.h, without conflicting with definition in
 // sys/stat.h, we use this trick.
-#if defined(__mips64)
+#if defined(__mips64) || defined(__riscv)
 #include <asm/unistd.h>
 #include <sys/types.h>
 #define stat kernel_stat
diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux.h b/compiler-rt/lib/sanitizer_common/sanitizer_linux.h
index 4aefab43b13c..66a510bec909 100644
--- a/compiler-rt/lib/sanitizer_common/sanitizer_linux.h
+++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux.h
@@ -134,6 +134,9 @@ inline void ReleaseMemoryPagesToOSAndZeroFill(uptr beg, uptr end) {
                "rdhwr   %0,$29\n" \
                ".set    pop\n" : "=r"(__v)); \
        __v; })
+#elif defined(__riscv)
+# define __get_tls() \
+    ({ void** __v; __asm__("mv %0, tp" : "=r"(__v)); __v; })
 #elif defined(__i386__)
 # define __get_tls() \
     ({ void** __v; __asm__("movl %%gs:0, %0" : "=r"(__v)); __v; })
diff --git a/llvm-build/Makefile b/llvm-build/Makefile
index d6e8933dc328..916533aa8e7b 100644
--- a/llvm-build/Makefile
+++ b/llvm-build/Makefile
@@ -73,6 +73,9 @@ else
 ifeq ($(ARCH),aarch64)
 ARCH_CFLAGS =
 else
+ifeq ($(ARCH),riscv64)
+ARCH_CFLAGS =
+else
 ifeq ($(ARCH),x86_64)
 ARCH_CFLAGS =
 else
@@ -81,16 +84,21 @@ ARCH_CFLAGS =
 endif
 endif
 endif
+endif
 
 ifeq ($(ARCH),aarch64)
 CFLAGS = -march=armv8 -O2 -Wall -fstack-protector-strong -D_FORTIFY_SOURCE=2 -Wl,-z,relro,-z,now,-z,noexecstack
 else
+ifeq ($(ARCH),riscv64)
+CFLAGS = -march=rv64gc -O2 -Wall -fstack-protector-strong -D_FORTIFY_SOURCE=2 -Wl,-z,relro,-z,now,-z,noexecstack
+else
 ifeq ($(ARCH),x86_64)
 CFLAGS = -march=x86-64 -O2 -Wall -fstack-protector-strong -D_FORTIFY_SOURCE=2 -Wl,-z,relro,-z,now,-z,noexecstack
 else
 CFLAGS = -march=armv7-a -O2 -Wall -fstack-protector-strong -D_FORTIFY_SOURCE=2 -Wl,-z,relro,-z,now,-z,noexecstack
 endif
 endif
+endif
 
 .PHONY: $(TARGETS:%=musl_copy_for_%)
 .PHONY: $(TARGETS:%=musl_patch_for_%)
diff --git a/llvm-build/build.py b/llvm-build/build.py
index a0ec239bef45..ca750134af34 100755
--- a/llvm-build/build.py
+++ b/llvm-build/build.py
@@ -25,6 +25,7 @@ import subprocess
 import shutil
 import argparse
 import mingw
+import stat
 
 
 class BuildConfig():
@@ -46,13 +47,14 @@ class BuildConfig():
 
         self.no_build_arm = args.skip_build or args.no_build_arm
         self.no_build_aarch64 = args.skip_build or args.no_build_aarch64
+        self.no_build_riscv64 = args.skip_build or args.no_build_riscv64
         self.no_build_x86_64 = args.skip_build or args.no_build_x86_64
 
         self.CURRENT_DIR = os.path.abspath(os.path.dirname(__file__))
         self.REPOROOT_DIR = os.path.abspath(os.path.join(self.CURRENT_DIR, '../../'))
         self.LLVM_PROJECT_DIR = os.path.abspath(os.path.join(self.REPOROOT_DIR, 'toolchain', 'llvm-project'))
         self.OUT_PATH = os.path.join(self.REPOROOT_DIR, 'out')
-        self.TARGETS = 'AArch64;ARM;BPF;X86'
+        self.TARGETS = 'AArch64;ARM;BPF;RISCV;X86'
         self.ORIG_ENV = dict(os.environ)
         self.VERSION = None # autodetected
 
@@ -94,6 +96,12 @@ class BuildConfig():
             default=False,
             help='Omit build os target: aarch64.')
 
+        parser.add_argument(
+            '--no-build-riscv64',
+            action='store_true',
+            default=False,
+            help='Omit build os target: 64-bit RISC-V.')
+
         parser.add_argument(
             '--no-build-x86_64',
             action='store_true',
@@ -835,6 +843,7 @@ class LlvmLibs(BuildUtils):
             ('arm', self.open_ohos_triple('arm'),
              '-march=armv7-a -mcpu=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4', 'a7_hard_neon-vfpv4'),
             ('aarch64', self.open_ohos_triple('aarch64'), '', ''),
+            ('riscv64', self.open_ohos_triple('riscv64'), '', ''),
             ('x86_64', self.open_ohos_triple('x86_64'), '', ''),]
 
         cc = os.path.join(llvm_install, 'bin', 'clang')
@@ -848,6 +857,8 @@ class LlvmLibs(BuildUtils):
             if llvm_build != llvm_triple:
                 continue
 
+            has_lldb_server = arch not in ['riscv64']
+
             defines = {}
             ldflags = []
             cflags = []
@@ -856,7 +867,7 @@ class LlvmLibs(BuildUtils):
 
             llvm_path = self.merge_out_path('llvm_make')
             arch_list = [self.liteos_triple('arm'), self.open_ohos_triple('arm'), self.open_ohos_triple('aarch64'),
-                         self.open_ohos_triple('x86_64')]
+                         self.open_ohos_triple('riscv64'), self.open_ohos_triple('x86_64')]
             if precompilation:
                 self.build_crts(llvm_install, arch, llvm_triple, cflags, ldflags, multilib_suffix, defines)
                 continue
@@ -869,7 +880,7 @@ class LlvmLibs(BuildUtils):
                                 first_time=False)
 
             if llvm_triple in arch_list:
-                if need_lldb_server and llvm_triple not in seen_arch_list:
+                if need_lldb_server and has_lldb_server and llvm_triple not in seen_arch_list:
                     self.build_lldb_server(llvm_install, llvm_path, arch, llvm_triple, cflags, ldflags,
                                                    defines)
                     seen_arch_list.append(llvm_triple)
@@ -877,7 +888,7 @@ class LlvmLibs(BuildUtils):
 
             self.build_libomp(llvm_install, arch, llvm_triple, cflags, ldflags, multilib_suffix, defines)
             self.build_libz(arch, llvm_triple, cflags, ldflags, defines)
-            if need_lldb_server and llvm_triple not in seen_arch_list:
+            if need_lldb_server and has_lldb_server and llvm_triple not in seen_arch_list:
                 self.build_lldb_server(llvm_install, llvm_path, arch, llvm_triple, cflags, ldflags, defines)
                 seen_arch_list.append(llvm_triple)
 
@@ -1974,6 +1985,9 @@ def main():
     if not build_config.no_build_aarch64:
         configs.append(('arm64', build_utils.open_ohos_triple('aarch64')))
 
+    if not build_config.no_build_riscv64:
+        configs.append(('riscv64', build_utils.open_ohos_triple('riscv64')))
+
     if not build_config.no_build_x86_64:
         configs.append(('x86_64', build_utils.open_ohos_triple('x86_64')))
 
diff --git a/llvm-build/build_musl.sh b/llvm-build/build_musl.sh
index a05b87229d3c..8956ccd83414 100755
--- a/llvm-build/build_musl.sh
+++ b/llvm-build/build_musl.sh
@@ -72,6 +72,9 @@ if [ $TARGET_TRIPLE == "arm-liteos-ohos" ]; then
 elif [ $TARGET_TRIPLE == "arm-linux-ohos" ]; then
     TARGET_USER="linux_user"
     TARGETS_PREFIX="arm"
+elif [ $TARGET_TRIPLE == "riscv64-linux-ohos" ]; then
+    TARGET_USER="linux_user"
+    TARGETS_PREFIX="riscv64"
 elif [ $TARGET_TRIPLE == "x86_64-linux-ohos" ]; then
     TARGET_USER="linux_user"
     TARGETS_PREFIX="x86_64"
@@ -94,7 +97,8 @@ make musl_header_install_for_${TARGET_USER} CLANG="${CLANG_BIN_ROOT}/clang" TOPD
 
 # build musl_libs
 if ((make_libs == 1)); then
-    if [ $TARGET_TRIPLE == "aarch64-linux-ohos" ] || [ $TARGET_TRIPLE == "x86_64-linux-ohos" ]; then
+    if [ $TARGET_TRIPLE == "aarch64-linux-ohos" ] || [ $TARGET_TRIPLE == "riscv64-linux-ohos" ] || \
+       [ $TARGET_TRIPLE == "x86_64-linux-ohos" ]; then
         make CLANG="${CLANG_BIN_ROOT}/clang" TOPDIR=${PWD}/../../ SYSROOTDIR=${OUT}/sysroot TARGETS=${TARGET_USER}\
             TARGET=${TARGET_TRIPLE} ARCH=${TARGETS_PREFIX} -f Makefile
     else
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 97f46d9731b1..c97cf68183e9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -972,6 +972,8 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
   SDLoc DL(Op);
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
+  if (DAG.getTarget().useEmulatedTLS())
+    return LowerToTLSEmulatedModel(N, DAG);
   int64_t Offset = N->getOffset();
   MVT XLenVT = Subtarget.getXLenVT();
 
diff --git a/llvm/test/CodeGen/RISCV/emutls.ll b/llvm/test/CodeGen/RISCV/emutls.ll
new file mode 100644
index 000000000000..441bb9897ce1
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/emutls.ll
@@ -0,0 +1,307 @@
+; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-gnu | FileCheck -check-prefix=RISCV64 %s
+; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos | FileCheck -check-prefix=RISCV64 %s
+
+; RUN: llc < %s -mtriple=riscv64-linux-gnu | FileCheck -check-prefix=NoEMU %s
+; RUN: llc < %s -mtriple=riscv64-linux-ohos | FileCheck -check-prefix=RISCV64 %s
+
+; Copied from X86/emutls.ll
+
+; NoEMU-NOT: __emutls
+
+; Use my_emutls_get_address like __emutls_get_address.
+@my_emutls_v_xyz = external global i8*, align 4
+declare i8* @my_emutls_get_address(i8*)
+
+define dso_local i32 @my_get_xyz() {
+; RISCV64-LABEL: my_get_xyz:
+; RISCV64:         lui a0, %hi(my_emutls_v_xyz)
+; RISCV64-NEXT:    addi a0, a0, %lo(my_emutls_v_xyz)
+; RISCV64-NEXT:    call my_emutls_get_address@plt
+; RISCV64-NEXT:    lw a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*))
+  %0 = bitcast i8* %call to i32*
+  %1 = load i32, i32* %0, align 4
+  ret i32 %1
+}
+
+@i1 = dso_local thread_local global i32 15
+@i2 = external thread_local global i32
+@i3 = internal thread_local global i32 15
+@i4 = hidden thread_local global i32 15
+@i5 = external hidden thread_local global i32
+@s1 = dso_local thread_local global i16 15
+@b1 = dso_local thread_local global i8 0
+
+define dso_local i32 @f1() {
+; RISCV64-LABEL: f1:
+; RISCV64:         lui a0, %hi(__emutls_v.i1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lw a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i32, i32* @i1
+  ret i32 %tmp1
+}
+
+define dso_local i32* @f2() {
+; RISCV64-LABEL: f2:
+; RISCV64:         lui a0, %hi(__emutls_v.i1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  ret i32* @i1
+}
+
+define dso_local i32 @f3() nounwind {
+; RISCV64-LABEL: f3:
+; RISCV64:         lui a0, %hi(__emutls_v.i2)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i2)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lw a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i32, i32* @i2
+  ret i32 %tmp1
+}
+
+define dso_local i32* @f4() {
+; RISCV64-LABEL: f4:
+; RISCV64:         lui a0, %hi(__emutls_v.i2)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i2)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  ret i32* @i2
+}
+
+define dso_local i32 @f5() nounwind {
+; RISCV64-LABEL: f5:
+; RISCV64:         lui a0, %hi(__emutls_v.i3)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i3)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lw a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i32, i32* @i3
+  ret i32 %tmp1
+}
+
+define dso_local i32* @f6() {
+; RISCV64-LABEL: f6:
+; RISCV64:         lui a0, %hi(__emutls_v.i3)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i3)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  ret i32* @i3
+}
+
+define dso_local i32 @f7() {
+; RISCV64-LABEL: f7:
+; RISCV64:         lui a0, %hi(__emutls_v.i4)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i4)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lw a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i32, i32* @i4
+  ret i32 %tmp1
+}
+
+define dso_local i32* @f8() {
+; RISCV64-LABEL: f8:
+; RISCV64:         lui a0, %hi(__emutls_v.i4)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i4)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  ret i32* @i4
+}
+
+define dso_local i32 @f9() {
+; RISCV64-LABEL: f9:
+; RISCV64:         lui a0, %hi(__emutls_v.i5)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i5)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lw a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i32, i32* @i5
+  ret i32 %tmp1
+}
+
+define dso_local i32* @f10() {
+; RISCV64-LABEL: f10:
+; RISCV64:         lui a0, %hi(__emutls_v.i5)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.i5)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  ret i32* @i5
+}
+
+define dso_local i16 @f11() {
+; RISCV64-LABEL: f11:
+; RISCV64:         lui a0, %hi(__emutls_v.s1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.s1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lh a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i16, i16* @s1
+  ret i16 %tmp1
+}
+
+define dso_local i32 @f12sext() {
+; RISCV64-LABEL: f12sext:
+; RISCV64:         lui a0, %hi(__emutls_v.s1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.s1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lh a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i16, i16* @s1
+  %tmp2 = sext i16 %tmp1 to i32
+  ret i32 %tmp2
+}
+
+define dso_local i32 @f12zext() {
+; RISCV64-LABEL: f12zext:
+; RISCV64:         lui a0, %hi(__emutls_v.s1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.s1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lhu a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i16, i16* @s1
+  %tmp2 = zext i16 %tmp1 to i32
+  ret i32 %tmp2
+}
+
+define dso_local i8 @f13() {
+; RISCV64-LABEL: f13:
+; RISCV64:         lui a0, %hi(__emutls_v.b1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.b1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lb a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i8, i8* @b1
+  ret i8 %tmp1
+}
+
+define dso_local i32 @f14sext() {
+; RISCV64-LABEL: f14sext:
+; RISCV64:         lui a0, %hi(__emutls_v.b1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.b1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lb a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i8, i8* @b1
+  %tmp2 = sext i8 %tmp1 to i32
+  ret i32 %tmp2
+}
+
+define dso_local i32 @f14zext() {
+; RISCV64-LABEL: f14zext:
+; RISCV64:         lui a0, %hi(__emutls_v.b1)
+; RISCV64-NEXT:    addi a0, a0, %lo(__emutls_v.b1)
+; RISCV64-NEXT:    call __emutls_get_address@plt
+; RISCV64-NEXT:    lbu a0, 0(a0)
+; RISCV64-NEXT:    ld ra, 8(sp)
+; RISCV64-NEXT:    addi sp, sp, 16
+; RISCV64-NEXT:    ret
+entry:
+  %tmp1 = load i8, i8* @b1
+  %tmp2 = zext i8 %tmp1 to i32
+  ret i32 %tmp2
+}
+
+;;;;;;;;;;;;;; 64-bit __emutls_v. and __emutls_t.
+
+; RISCV64-LABEL: __emutls_v.i1:
+; RISCV64-NEXT: .quad 4
+; RISCV64-NEXT: .quad 4
+; RISCV64-NEXT: .quad 0
+; RISCV64-NEXT: .quad __emutls_t.i1
+
+; RISCV64-LABEL: __emutls_t.i1:
+; RISCV64-NEXT: .word 15
+
+; RISCV64-NOT:   __emutls_v.i2
+
+; RISCV64-LABEL: __emutls_v.i3:
+; RISCV64-NEXT: .quad 4
+; RISCV64-NEXT: .quad 4
+; RISCV64-NEXT: .quad 0
+; RISCV64-NEXT: .quad __emutls_t.i3
+
+; RISCV64-LABEL: __emutls_t.i3:
+; RISCV64-NEXT: .word 15
+
+; RISCV64-LABEL: __emutls_v.i4:
+; RISCV64-NEXT: .quad 4
+; RISCV64-NEXT: .quad 4
+; RISCV64-NEXT: .quad 0
+; RISCV64-NEXT: .quad __emutls_t.i4
+
+; RISCV64-LABEL: __emutls_t.i4:
+; RISCV64-NEXT: .word 15
+
+; RISCV64-NOT:   __emutls_v.i5:
+; RISCV64:      .hidden __emutls_v.i5
+; RISCV64-NOT:   __emutls_v.i5:
+
+; RISCV64-LABEL: __emutls_v.s1:
+; RISCV64-NEXT: .quad 2
+; RISCV64-NEXT: .quad 2
+; RISCV64-NEXT: .quad 0
+; RISCV64-NEXT: .quad __emutls_t.s1
+
+; RISCV64-LABEL: __emutls_t.s1:
+; RISCV64-NEXT: .half 15
+
+; RISCV64-LABEL: __emutls_v.b1:
+; RISCV64-NEXT: .quad 1
+; RISCV64-NEXT: .quad 1
+; RISCV64-NEXT: .quad 0
+; RISCV64-NEXT: .quad 0
+
+; RISCV64-NOT:  __emutls_t.b1
diff --git a/llvm/test/CodeGen/RISCV/emutls_generic.ll b/llvm/test/CodeGen/RISCV/emutls_generic.ll
new file mode 100644
index 000000000000..9f2345d8e673
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/emutls_generic.ll
@@ -0,0 +1,75 @@
+; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-gnu -O3 \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos -relocation-model=pic \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos -relocation-model=pic -O3 \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+; RUN: llc < %s -emulated-tls -mtriple=riscv64-linux-ohos -O3 \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+
+; RUN: llc < %s -mtriple=riscv64-linux-gnu -O3 \
+; RUN:     | FileCheck -check-prefix=NoEMU %s
+; RUN: llc < %s -mtriple=riscv64-linux-ohos -relocation-model=pic \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+; RUN: llc < %s -mtriple=riscv64-linux-ohos -relocation-model=pic -O3 \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+; RUN: llc < %s -mtriple=riscv64-linux-ohos -O3 \
+; RUN:     | FileCheck -check-prefix=RISCV64 %s
+
+; NoEMU-NOT: __emutls
+
+; Make sure that TLS symbols are emitted in expected order.
+
+@external_x = external thread_local global i32, align 8
+@external_y = thread_local global i8 7, align 2
+@internal_y = internal thread_local global i64 9, align 16
+
+define i32* @get_external_x() {
+entry:
+  ret i32* @external_x
+}
+
+define i8* @get_external_y() {
+entry:
+  ret i8* @external_y
+}
+
+define i64* @get_internal_y() {
+entry:
+  ret i64* @internal_y
+}
+
+; RISCV64-LABEL:  get_external_x:
+; RISCV64:      __emutls_v.external_x
+; RISCV64:      __emutls_get_address
+; RISCV64-LABEL:  get_external_y:
+; RISCV64:      __emutls_v.external_y
+; RISCV64:      __emutls_get_address
+; RISCV64-LABEL:  get_internal_y:
+; RISCV64:      __emutls_v.internal_y
+; RISCV64:      __emutls_get_address
+; RISCV64-NOT:   __emutls_t.external_x
+; RISCV64-NOT:   __emutls_v.external_x:
+; RISCV64:        .data{{$}}
+; RISCV64:        .globl __emutls_v.external_y
+; RISCV64:        .p2align 3
+; RISCV64-LABEL:  __emutls_v.external_y:
+; RISCV64-NEXT:   .quad 1
+; RISCV64-NEXT:   .quad 2
+; RISCV64-NEXT:   .quad 0
+; RISCV64-NEXT:   .quad __emutls_t.external_y
+; RISCV64-NOT:    __emutls_v.external_x:
+; RISCV64:        .section .r{{o?}}data,
+; RISCV64-LABEL:  __emutls_t.external_y:
+; RISCV64-NEXT:   .byte 7
+; RISCV64:        .data{{$}}
+; RISCV64-NOT:    .globl __emutls_v
+; RISCV64:        .p2align 3
+; RISCV64-LABEL:  __emutls_v.internal_y:
+; RISCV64-NEXT:   .quad 8
+; RISCV64-NEXT:   .quad 16
+; RISCV64-NEXT:   .quad 0
+; RISCV64-NEXT:   .quad __emutls_t.internal_y
+; RISCV64:        .section .r{{o?}}data,
+; RISCV64-LABEL:  __emutls_t.internal_y:
+; RISCV64-NEXT:   .quad 9
-- 
Gitee