diff --git a/u-boot-2020.01/board/hisilicon/hi3516dv300/hi3516dv300.c b/u-boot-2020.01/board/hisilicon/hi3516dv300/hi3516dv300.c index 318fd1cefa50e9b022eef6e42ba197441e183b8c..c77e2a214c81fd9c5919abad24aa10ca9e8a0bb7 100755 --- a/u-boot-2020.01/board/hisilicon/hi3516dv300/hi3516dv300.c +++ b/u-boot-2020.01/board/hisilicon/hi3516dv300/hi3516dv300.c @@ -466,6 +466,31 @@ static void ChangeBootArgs(void) // get bootargs from emmc } } +#define MISC_HEAD_LEN 512 +#define MISC_ADDR_LEN 16 +#define RGB_FILE_MAX_SIZE 1024 * 2038 +int ReadMiscLogoBuffer(void) +{ + char blk[MISC_HEAD_LEN] = {0}; + char addr[MISC_ADDR_LEN] = {0}; + int addrOffset = (PARTITION_INFO_POS + PARTITION_INFO_MAX_LENGTH + MISC_HEAD_LEN - 1) / MISC_HEAD_LEN; + if (BlkDevRead(blk, MISC_LOCATION*(M_1/EMMC_SECTOR_SIZE) + addrOffset, 1) < 0) { + return -1; + } + + unsigned int magicNum = 0; + unsigned int rgbSize = 0; + const unsigned int magic = 0XABCABCAB; + magicNum = *(unsigned int*) blk; + rgbSize = *(unsigned int*) (blk + 4); // offset 4 byte + if ((magicNum == magic) && (rgbSize > 0) && (rgbSize < RGB_FILE_MAX_SIZE)) { + env_set("flag", "1"); + sprintf(addr, "0x%08X", (MISC_LOCATION * (M_1 / EMMC_SECTOR_SIZE) + addrOffset)); + env_set("misc_addr", addr); + } + return 0; +} + int EmmcInitParam(void) // get "boot_updater" string in misc,then set env { const char rebootHead[] = "mem=640M console=ttyAMA0,115200 mmz=anonymous,0,0xA8000000,384M " @@ -474,14 +499,14 @@ int EmmcInitParam(void) // get "boot_updater" string in misc,then s const char defaultRebootStr[] = "mem=640M console=ttyAMA0,115200 mmz=anonymous,0,0xA8000000,384M " "clk_ignore_unused androidboot.selinux=permissive skip_initramfs rootdelay=10 hardware=Hi3516DV300 init=/init " "root=/dev/ram0 blkdevparts=mmcblk0:1M(boot),15M(kernel),20M(updater)," - "1M(misc),3307M(system),256M(vendor),-(userdata)"; + "2M(misc),3307M(system),256M(vendor),-(userdata)"; const char updaterHead[] = "mem=640M console=ttyAMA0,115200 mmz=anonymous,0,0xA8000000,384M clk_ignore_unused " "androidboot.selinux=permissive skip_initramfs " "rootdelay=10 hardware=Hi3516DV300 init=/init root=/dev/mmcblk0p3 rootfstype=ext4 rw blkdevparts="; const char defaultUpdaterStr[] = "mem=640M console=ttyAMA0,115200 mmz=anonymous,0,0xA8000000,384M " "clk_ignore_unused androidboot.selinux=permissive skip_initramfs rootdelay=10 hardware=Hi3516DV300 init=/init " "root=/dev/mmcblk0p3 rootfstype=ext4 rw blkdevparts=mmcblk0:1M(boot),15M(kernel),20M(updater)," - "1M(misc),3307M(system),256M(vendor),-(userdata)"; + "2M(misc),3307M(system),256M(vendor),-(userdata)"; char block2[EMMC_SECTOR_SIZE*EMMC_SECTOR_CNT]; if (BlkDevRead(block2, MISC_LOCATION*(M_1/EMMC_SECTOR_SIZE), EMMC_SECTOR_CNT) < 0) { return -1; @@ -657,6 +682,9 @@ int misc_init_r(void) if (EmmcInitParam() == -1) { return 0; } + + ReadMiscLogoBuffer(); + ChangeBootArgs(); env_set("bootargs", g_bootArgsStr); diff --git a/u-boot-2020.01/cmd/bootm.c b/u-boot-2020.01/cmd/bootm.c index e2a15e99f1f1ecada8514ae452ac6149a0fea6ec..89276404be7ea04da373cc46801bd8041a6fd666 100644 --- a/u-boot-2020.01/cmd/bootm.c +++ b/u-boot-2020.01/cmd/bootm.c @@ -20,6 +20,7 @@ #include #include #include +#include "hi3516cv500_vo.h" #if defined(CONFIG_OHOS_SEC_BOOT_SUPPORT) #include "../product/hisec/sec_boot.h" #endif @@ -92,8 +93,38 @@ static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc, /* bootm - boot application image from image in memory */ /*******************************************************************/ +#define MISC_LOGO_VO_ADDR 0X85000008 +#define MISC_LOAD_LOGO_ADDR 0X85000000 +#define MISC_RGB_MAX_LEN 0xFEC +#define MISC_SIGN_LEN 8 +#define lOGO_SIZE 480 * 960 * 3 +char g_tempMemory[lOGO_SIZE] = {0}; int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { +if (strcmp(env_get("flag"), "1") == 0) { + extern int start_vo(unsigned int dev, unsigned int type, unsigned int sync); + extern int stop_vo(unsigned int dev); + extern int mipi_tx_display(unsigned int vosync); + extern int start_gx(unsigned int layer, unsigned addr, unsigned int strd, + unsigned int x, unsigned int y, unsigned int w, unsigned int h); + extern int stop_gx(unsigned int layer); + extern int set_vobg(unsigned int dev, unsigned int rgb); + + const char cmd[100] = {0}; + + sprintf(cmd, "mmc read 0x0 %x %s %x", MISC_LOAD_LOGO_ADDR, env_get("misc_addr"), MISC_RGB_MAX_LEN); + run_command(cmd, 0); + for (int i = 0; i < lOGO_SIZE; i++) { + g_tempMemory[i] = *(unsigned char*)(MISC_LOGO_VO_ADDR + i); + } + set_vobg(0, 0xFFFFFF); + /* mipi 16384 */ + start_vo(0, 16384, VO_OUTPUT_480x960_60); + mipi_tx_display(VO_OUTPUT_480x960_60); + start_gx(0, (unsigned int)g_tempMemory, 1440, 0, 0, 480, 960); + printf("END!!!"); +} + #if defined(CONFIG_OHOS_SEC_BOOT_SUPPORT) if (CONFIG_OHOS_SEC_BOOT_ENABLE) { int ret = check_security_boot(CONFIG_OHOS_X509_BIN_START_ADDR); diff --git a/u-boot-2020.01/include/hi3516cv500_vo.h b/u-boot-2020.01/include/hi3516cv500_vo.h index 213f135b07bc74ffbefe12e6a5c2d2f1fa2223af..75c3526efa6ed7239b6c6d5105c489e5f6a37180 100755 --- a/u-boot-2020.01/include/hi3516cv500_vo.h +++ b/u-boot-2020.01/include/hi3516cv500_vo.h @@ -96,6 +96,7 @@ typedef enum { VO_OUTPUT_800x600_50, /* For LCD at 50 Hz (24bit) */ VO_OUTPUT_720x1280_60, /* For MIPI DSI Tx 720 x1280 at 60 Hz */ VO_OUTPUT_1080x1920_60, /* For MIPI DSI Tx 1080x1920 at 60 Hz */ + VO_OUTPUT_480x960_60, /* For MIPI 480 x 960 at 60Hz */ VO_OUTPUT_7680x4320_30, /* For HDMI2.0 at 30 Hz */ VO_OUTPUT_USER, /* User timing. */ diff --git a/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx.c b/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx.c index 3e888f76c0f469d8fe6caf84fac6b0bbd7c65eb9..3ddb73a416ce3dc632a758c12b01d7410871a771 100755 --- a/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx.c +++ b/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx.c @@ -27,10 +27,63 @@ #define HIMEDIA_DYNAMIC_MINOR 255 +#define REGFLAG_DELAY 0XFFE +#define REGFLAG_END_OF_TABLE 0xFFF // END OF REGISTERS MARKER +#define DTYPE_DCS_WRITE 0x5 // 0x15 short write, 1 parameter +#define DTYPE_DCS_WRITE1 0x15 // 0x23 short write, 2 parameter +#define DTYPE_DCS_LWRITE 0x39 // 0x29 long write + typedef struct { combo_dev_cfg_t dev_cfg; } mipi_tx_dev_ctx_t; +struct LCM_setting_table { + unsigned cmd; + unsigned char count; + unsigned char para_list[100]; +}; + +static struct LCM_setting_table lcm_initialization_setting[] = { + {DTYPE_DCS_LWRITE, 3, {0xF0, 0x5A, 0x5A}}, + {DTYPE_DCS_LWRITE, 3, {0xF1, 0xA5, 0xA5}}, + + {DTYPE_DCS_LWRITE, 12, {0xB3, 0x03, 0x03, 0x03, 0x07, 0x05, 0x0D, 0x0F, 0x11, 0x13, 0x09, 0x0B}}, + {DTYPE_DCS_LWRITE, 12, {0xB4, 0x03, 0x03, 0x03, 0x06, 0x04, 0x0C, 0x0E, 0x10, 0x12, 0x08, 0x0A}}, + {DTYPE_DCS_LWRITE, 13, {0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x60, 0x00, 0x60, 0x1C}}, + {DTYPE_DCS_LWRITE, 9, {0xB1, 0x32, 0x84, 0x02, 0x87, 0x12, 0x00, 0x50, 0x1C}}, + {DTYPE_DCS_LWRITE, 4, {0xB2, 0x73, 0x09, 0x08}}, + + {DTYPE_DCS_LWRITE, 4, {0xB6, 0x5C, 0x5C, 0x05}}, + // {DTYPE_DCS_WRITE1, 2, {0xC0, 0x11}}, //BIST color bar and color test disable + + {DTYPE_DCS_LWRITE, 6, {0xB8, 0x23, 0x41, 0x32, 0x30, 0x03}}, + {DTYPE_DCS_LWRITE, 11, {0xBC, 0xD2, 0x0E, 0x63, 0x63, 0x5A, 0x32, 0x22, 0x14, 0x22, 0x03}}, + {DTYPE_DCS_WRITE1, 2, {0xB7, 0x41}}, + {DTYPE_DCS_LWRITE, 7, {0xC1, 0x0C, 0x10, 0x04, 0x0C, 0x10, 0x04}}, + {DTYPE_DCS_LWRITE, 3, {0xC2, 0x10, 0xE0}}, + {DTYPE_DCS_LWRITE, 3, {0xC3, 0x22, 0x11}}, + + {DTYPE_DCS_LWRITE, 3, {0xD0, 0x07, 0xFF}}, + {DTYPE_DCS_LWRITE, 5, {0xD2, 0x63,0x0B,0x08,0x88}}, //ESD + + {DTYPE_DCS_LWRITE, 8, {0xC6, 0x08, 0x15, 0xFF, 0x10, 0x16, 0x80, 0x60}}, + {DTYPE_DCS_WRITE1, 2, {0xC7, 0x04}}, + + {DTYPE_DCS_WRITE1, 2, {0x36, 0x08}}, // add tsl 2020.08.31; Hi3516dv300 output is bgr, so set mipi bgr + + {DTYPE_DCS_LWRITE, 39, {0xC8, 0x7C, 0x50, 0x3B, 0x2C, 0x25, 0x16, 0x1C, \ + 0x08, 0x27, 0x2B, 0x2F, 0x52, 0x43, 0x4C, 0x40, \ + 0x3D, 0x30, 0x1E, 0x06, 0x7C, 0x50, 0x3B, 0x2C, \ + 0x25, 0x16, 0x1C, 0x08, 0x27, 0x2B, 0x2F, 0x52, \ + 0x43, 0x4C, 0x40, 0x3D, 0x30, 0x1E, 0x06}}, // G2.0 + + {DTYPE_DCS_WRITE, 1, {0x11}}, // exit sleep + {REGFLAG_DELAY, 0, {}}, + {DTYPE_DCS_WRITE, 1, {0x29}}, // display on + {REGFLAG_DELAY,0,{}}, + {REGFLAG_END_OF_TABLE, 0x00,{}} +}; + mipi_tx_dev_ctx_t g_mipi_tx_dev_ctx; /* the numbers below is the initialization of the dev config, not magic number */ @@ -56,6 +109,28 @@ static combo_dev_cfg_t g_mipi_tx_720x576_50_config = { .pixel_clk = 27000, }; +/* 480x960_60 sync config */ +static combo_dev_cfg_t g_mipi_tx_480x960_60_config = { + .devno = 0, + .lane_id = { 0, 1, -1, -1 }, + .output_mode = OUTPUT_MODE_DSI_VIDEO, //OUTPUT_MODE_DSI_CMD, + .output_format = OUT_FORMAT_RGB_24_BIT, + .video_mode = BURST_MODE, + .sync_info = { + .vid_pkt_size = 480, // hact + .vid_hsa_pixels = 10, // hsa + .vid_hbp_pixels = 20, // hbp + .vid_hline_pixels = 530, // hact(480) + hsa(10) + hbp(20) + hfp(20) + .vid_vsa_lines = 2, // vsa + .vid_vbp_lines = 14, // vbp + .vid_vfp_lines = 16, // vfp + .vid_active_lines = 960, // vact + .edpi_cmd_size = 0, + }, + .phy_data_rate = 379, + .pixel_clk = 31546, +}; + /* 1280x720_60 sync config */ static combo_dev_cfg_t g_mipi_tx_1280x720_60_config = { .devno = 0, @@ -330,6 +405,56 @@ void mipi_tx_module_exit(void) printf("unload mipi_tx driver ok!\n"); } +static void push_table(struct LCM_setting_table *table, unsigned int count, unsigned char force_update) +{ + unsigned int i; + int s32Ret; + + for(i = 0; i < count; i++) { + unsigned cmd; + cmd = table[i].cmd; + cmd_info_t cmd_info = {0}; + + switch (cmd) { + case REGFLAG_DELAY : + mdelay(120); + break; + case REGFLAG_END_OF_TABLE : + break; + default: + if (cmd == DTYPE_DCS_LWRITE) { + cmd_info.devno = 0; + cmd_info.cmd_size = table[i].count; + cmd_info.data_type = table[i].cmd; + cmd_info.cmd = &table[i].para_list[0]; + s32Ret = mipi_tx_ioctl(HI_MIPI_TX_SET_CMD, (unsigned long)(&cmd_info)); + mdelay(1); + } else if (cmd == DTYPE_DCS_WRITE1) { + cmd_info.devno = 0; + cmd_info.cmd_size |= table[i].para_list[1] << 8; + cmd_info.cmd_size |= table[i].para_list[0]; + cmd_info.data_type = table[i].cmd; + cmd_info.cmd = NULL; + s32Ret = mipi_tx_ioctl(HI_MIPI_TX_SET_CMD, (unsigned long)(&cmd_info)); + mdelay(1); + } else if (cmd == DTYPE_DCS_WRITE) { + cmd_info.devno = 0; + cmd_info.cmd_size = table[i].para_list[0]; + cmd_info.data_type = table[i].cmd; + cmd_info.cmd = NULL; + s32Ret = mipi_tx_ioctl(HI_MIPI_TX_SET_CMD, (unsigned long)(&cmd_info)); + mdelay(1); + } + } + } +} + +static void PLE_PRIVATE_VO_InitScreen480x960(void) +{ + printf("Send mipi cmd \n"); + push_table(lcm_initialization_setting, sizeof(lcm_initialization_setting) / sizeof(struct LCM_setting_table), 1); +} + int mipi_tx_display(unsigned int vosync) { int ret; @@ -339,6 +464,9 @@ int mipi_tx_display(unsigned int vosync) mipi_tx_module_init(); switch (vosync) { + case VO_OUTPUT_480x960_60: + mipi_tx_config = &g_mipi_tx_480x960_60_config; + break; case VO_OUTPUT_576P50: mipi_tx_config = &g_mipi_tx_720x576_50_config; break; @@ -374,6 +502,8 @@ int mipi_tx_display(unsigned int vosync) /* step 2 : init display device (do it yourself ). */ udelay(10000); /* delay 10000 us for the stable signal */ + PLE_PRIVATE_VO_InitScreen480x960(); + udelay(10000); /* step 3 : enable mipi_tx controller. */ ret = mipi_tx_ioctl(HI_MIPI_TX_ENABLE, (unsigned long)0); diff --git a/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx_hal.c b/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx_hal.c index d3725bb06bc875b62efb4260e4e65354f4e7fac3..04fd0e86f09735da1f7a08c3c3f8087ed11412c5 100755 --- a/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx_hal.c +++ b/u-boot-2020.01/product/hiosd/mipi_tx/hi3516cv500/mipi_tx_hal.c @@ -938,9 +938,46 @@ static void mipi_tx_drv_hw_init(void) write_reg32(mipi_tx_crg_addr, 1 << 2, 0x1 << 2); /* set bit 2 */ } +static void reset_mipi_lcm() +{ + unsigned long mipi_tx_multip_gpio_addr; + + // GPIO0_5 output + mipi_tx_multip_gpio_addr = (unsigned long)IO_ADDRESS(0x120D0400); + write_reg32(mipi_tx_multip_gpio_addr, 0x20, 0x20); + mdelay(10); + + // data 0 + mipi_tx_multip_gpio_addr = (unsigned long)IO_ADDRESS(0x120D03FC); + write_reg32(mipi_tx_multip_gpio_addr, 0, 0x0); + mdelay(50); + + // data 1 + mipi_tx_multip_gpio_addr = (unsigned long)IO_ADDRESS(0x120D03FC); + write_reg32(mipi_tx_multip_gpio_addr, 0x20, 0x20); + mdelay(120); +} + +static void pwm_mipi_lcm() +{ + unsigned long mipi_tx_multip_gpio_addr; + + // GPIO6_7 output + mipi_tx_multip_gpio_addr = (unsigned long)IO_ADDRESS(0x120D6400); + write_reg32(mipi_tx_multip_gpio_addr, 0x80, 0x80); + mdelay(10); + + // GPIO6_7 data 1 + mipi_tx_multip_gpio_addr = (unsigned long)IO_ADDRESS(0x120D63FC); + write_reg32(mipi_tx_multip_gpio_addr, 0x80, 0x80); + mdelay(120); +} + int mipi_tx_drv_init(void) { int ret; + pwm_mipi_lcm(); + reset_mipi_lcm(); ret = mipi_tx_drv_reg_init(); if (ret < 0) { diff --git a/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou.c b/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou.c index a95d4867b113dbe8341ddfb6f425ddc91a060496..a8c8d9218d7e4e5676498bcc46bc443c373cd56e 100755 --- a/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou.c +++ b/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou.c @@ -233,7 +233,10 @@ hi_void vo_set_disp_max_size(vo_hal_dev vo_dev, vo_intf_sync vo_out_mode) max_width = 7680; max_height = 4320; break; - + case VO_OUTPUT_480x960_60: + max_width = 480; + max_height = 960; + break; default: max_width = 1920; max_height = 1080; @@ -468,7 +471,7 @@ int start_gx(unsigned int layer, unsigned long addr, unsigned int strd, hi_vo_re hal_gfx_set_src_resolution(vo_layer, &disp_rect); - hal_layer_set_layer_data_fmt(vo_layer, HAL_INPUTFMT_ARGB_1555); + hal_layer_set_layer_data_fmt(vo_layer, HAL_INPUTFMT_RGB_888); hal_layer_enable_layer(vo_layer, HI_TRUE); hal_layer_set_reg_up(hal_gfx_layer); diff --git a/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou_drv.c b/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou_drv.c index 0855e1644404eef3b14c3999e1e7bb0190257804..282eae636d923e9b5f1b61cd12652feddea41de5 100755 --- a/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou_drv.c +++ b/u-boot-2020.01/product/hiosd/vo/hi3516cv500/vou_drv.c @@ -143,6 +143,7 @@ hal_disp_syncinfo g_sync_timing[VO_OUTPUT_BUTT] = { { 0, 1, 1, 600, 23, 12, 800, 210, 46, 1, 1, 1, 1, 2, 1, 0, 0, 0 }, /* 800X600@60 24bit LCD */ { 0, 1, 1, 1280, 24, 8, 720, 123, 99, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* 720 x1280 at 60 hz */ { 0, 1, 1, 1920, 36, 16, 1080, 28, 130, 1, 1, 1, 1, 24, 4, 0, 0, 0 }, /* 1080 x1920 at 60 hz */ + { 0, 1, 1, 960, 16, 16, 480, 30, 20, 1, 1, 1, 1, 10, 2, 0, 0, 0 }, /* 480 x960 at 60 hz */ { 0, 1, 1, 4320, 64, 16, 7680, 768, 552, 1, 1, 1, 1, 176, 20, 0, 0, 0 }, /* 7680x4320@30 */ {} /* user */ }; @@ -575,6 +576,16 @@ hi_void vo_drv_set_dev_clk(vo_hal_dev vo_dev) hdmiclk_div = 0x0; break; } + case VO_OUTPUT_480x960_60: { + fbdiv = 257; + frac = 0x9f559b; + refdiv = 4; + postdiv1 = 7; + postdiv2 = 7; + + hdmiclk_div = 0x0; + break; + } default: { return; }