From 46b49688f8d11a1029a6d2d6a0d4b962bce38626 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9C=B1=E8=80=BF=E5=AE=87?= Date: Tue, 10 Sep 2024 01:07:25 +0000 Subject: [PATCH 1/2] =?UTF-8?q?=E5=9C=A8=20RTEMS=20=E5=9F=BA=E7=BA=BF?= =?UTF-8?q?=E5=86=85=E6=A0=B8=E5=A2=9E=E5=8A=A0=20Phytium=20BSP?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 1 + bsps/aarch64/phytium/console/console.c | 68 ++ bsps/aarch64/phytium/fdt/bsp_fdt.c | 54 ++ bsps/aarch64/phytium/include/bsp.h | 198 +++++ bsps/aarch64/phytium/include/bsp/irq.h | 90 +++ .../phytium/include/soc/d2000/fparameters.h | 391 ++++++++++ .../phytium/include/soc/e2000d/fparameters.h | 367 +++++++++ .../include/soc/e2000d/fparameters_comm.h | 691 +++++++++++++++++ .../phytium/include/soc/e2000q/fparameters.h | 370 +++++++++ .../include/soc/e2000q/fparameters_comm.h | 691 +++++++++++++++++ .../phytium/include/soc/ft2004/fparameters.h | 362 +++++++++ .../include/soc/phytiumpi/fparameters.h | 298 ++++++++ .../include/soc/phytiumpi/fparameters_comm.h | 718 ++++++++++++++++++ bsps/aarch64/phytium/include/tm27.h | 45 ++ bsps/aarch64/phytium/start/bspcpuid.S | 164 ++++ bsps/aarch64/phytium/start/bspl3cache.c | 132 ++++ .../aarch64/phytium/start/bspreset_watchdog.c | 82 ++ bsps/aarch64/phytium/start/bspsmp.c | 274 +++++++ bsps/aarch64/phytium/start/bspstart.c | 63 ++ bsps/aarch64/phytium/start/bspstarthooks.c | 92 +++ bsps/aarch64/phytium/start/bspstartmmu.c | 113 +++ bsps/aarch64/shared/start/aarch64-smp.c | 14 +- bsps/aarch64/shared/start/start.S | 16 + bsps/include/dev/irq/arm-gic-regs.h | 4 + bsps/include/dev/irq/arm-gic.h | 5 + bsps/include/dev/irq/arm-gicv3.h | 38 + bsps/shared/dev/irq/arm-gicv3.c | 22 + cpukit/libmisc/shell/main_df.c | 12 +- .../cpu/aarch64/include/rtems/score/cpu.h | 12 +- spec/build/bsps/aarch64/optflushcacheboot.yml | 17 + spec/build/bsps/aarch64/phytium/abi.yml | 18 + .../bsps/aarch64/phytium/bspd2000test.yml | 150 ++++ .../bsps/aarch64/phytium/bspe2000ddemo.yml | 170 +++++ .../bsps/aarch64/phytium/bspe2000qdemo.yml | 168 ++++ .../bsps/aarch64/phytium/bspft2004dsk.yml | 150 ++++ .../bsps/aarch64/phytium/bspphytiumpi.yml | 168 ++++ .../build/bsps/aarch64/phytium/linkercmds.yml | 73 ++ .../bsps/aarch64/phytium/objphytiumgicv3.yml | 41 + .../bsps/aarch64/phytium/optd2000test.yml | 20 + .../bsps/aarch64/phytium/opte2000ddemo.yml | 20 + .../bsps/aarch64/phytium/opte2000qdemo.yml | 20 + .../bsps/aarch64/phytium/optft2004dsk.yml | 20 + .../build/bsps/aarch64/phytium/optloadoff.yml | 19 + .../build/bsps/aarch64/phytium/optphytium.yml | 20 + .../bsps/aarch64/phytium/optphytiumpi.yml | 20 + spec/build/bsps/aarch64/phytium/optramlen.yml | 21 + spec/build/bsps/aarch64/phytium/optramori.yml | 21 + spec/build/cpukit/optsmp.yml | 5 + spec/build/testsuites/smptests/grp.yml | 4 +- 49 files changed, 6512 insertions(+), 20 deletions(-) create mode 100644 bsps/aarch64/phytium/console/console.c create mode 100644 bsps/aarch64/phytium/fdt/bsp_fdt.c create mode 100644 bsps/aarch64/phytium/include/bsp.h create mode 100644 bsps/aarch64/phytium/include/bsp/irq.h create mode 100644 bsps/aarch64/phytium/include/soc/d2000/fparameters.h create mode 100644 bsps/aarch64/phytium/include/soc/e2000d/fparameters.h create mode 100644 bsps/aarch64/phytium/include/soc/e2000d/fparameters_comm.h create mode 100644 bsps/aarch64/phytium/include/soc/e2000q/fparameters.h create mode 100644 bsps/aarch64/phytium/include/soc/e2000q/fparameters_comm.h create mode 100644 bsps/aarch64/phytium/include/soc/ft2004/fparameters.h create mode 100644 bsps/aarch64/phytium/include/soc/phytiumpi/fparameters.h create mode 100644 bsps/aarch64/phytium/include/soc/phytiumpi/fparameters_comm.h create mode 100644 bsps/aarch64/phytium/include/tm27.h create mode 100644 bsps/aarch64/phytium/start/bspcpuid.S create mode 100644 bsps/aarch64/phytium/start/bspl3cache.c create mode 100644 bsps/aarch64/phytium/start/bspreset_watchdog.c create mode 100644 bsps/aarch64/phytium/start/bspsmp.c create mode 100644 bsps/aarch64/phytium/start/bspstart.c create mode 100644 bsps/aarch64/phytium/start/bspstarthooks.c create mode 100644 bsps/aarch64/phytium/start/bspstartmmu.c create mode 100644 spec/build/bsps/aarch64/optflushcacheboot.yml create mode 100644 spec/build/bsps/aarch64/phytium/abi.yml create mode 100644 spec/build/bsps/aarch64/phytium/bspd2000test.yml create mode 100644 spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml create mode 100644 spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml create mode 100644 spec/build/bsps/aarch64/phytium/bspft2004dsk.yml create mode 100644 spec/build/bsps/aarch64/phytium/bspphytiumpi.yml create mode 100644 spec/build/bsps/aarch64/phytium/linkercmds.yml create mode 100644 spec/build/bsps/aarch64/phytium/objphytiumgicv3.yml create mode 100644 spec/build/bsps/aarch64/phytium/optd2000test.yml create mode 100644 spec/build/bsps/aarch64/phytium/opte2000ddemo.yml create mode 100644 spec/build/bsps/aarch64/phytium/opte2000qdemo.yml create mode 100644 spec/build/bsps/aarch64/phytium/optft2004dsk.yml create mode 100644 spec/build/bsps/aarch64/phytium/optloadoff.yml create mode 100644 spec/build/bsps/aarch64/phytium/optphytium.yml create mode 100644 spec/build/bsps/aarch64/phytium/optphytiumpi.yml create mode 100644 spec/build/bsps/aarch64/phytium/optramlen.yml create mode 100644 spec/build/bsps/aarch64/phytium/optramori.yml diff --git a/.gitignore b/.gitignore index 8b28b186e1..6668ba5f02 100644 --- a/.gitignore +++ b/.gitignore @@ -12,3 +12,4 @@ Makefile.in /testsuites/build/build /testsuites/build/wscript .waf* +/.vscode \ No newline at end of file diff --git a/bsps/aarch64/phytium/console/console.c b/bsps/aarch64/phytium/console/console.c new file mode 100644 index 0000000000..bf8c44959f --- /dev/null +++ b/bsps/aarch64/phytium/console/console.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief Console Configuration + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include + +#include + +arm_pl011_context phytium_vpl011_context = { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"), + .regs = (volatile pl011 *) BSP_PHYTIUM_CONSOLE_UART_BASE, + .initial_baud = 115200 +}; + +const console_device console_device_table[] = { + { + .device_file = "/dev/ttyS0", + .probe = console_device_probe_default, + .handler = &arm_pl011_fns, + .context = &phytium_vpl011_context.base + } +}; + +const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table); + +static void output_char( char c ) +{ + arm_pl011_write_polled(&phytium_vpl011_context.base, c); +} + +BSP_output_char_function_type BSP_output_char = output_char; + +BSP_polling_getchar_function_type BSP_poll_char = NULL; diff --git a/bsps/aarch64/phytium/fdt/bsp_fdt.c b/bsps/aarch64/phytium/fdt/bsp_fdt.c new file mode 100644 index 0000000000..be1052d7dd --- /dev/null +++ b/bsps/aarch64/phytium/fdt/bsp_fdt.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief This source file contains the implementatin of bsp_fdt_get(). + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +extern unsigned char phytium_dtb[]; + +const void *bsp_fdt_get(void) +{ + return phytium_dtb; +} + +uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells) +{ + if (icells != 3) { + return 0; + } + + /* PPI start at 16, SPI start at 32 */ + return (intr[0] == 0 ? 32 : 16) + intr[1]; +} \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/bsp.h b/bsps/aarch64/phytium/include/bsp.h new file mode 100644 index 0000000000..76d6aacff0 --- /dev/null +++ b/bsps/aarch64/phytium/include/bsp.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief Core BSP definitions + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_AARCH64_PHYTIUM_BSP_H +#define LIBBSP_AARCH64_PHYTIUM_BSP_H + +/** + * @addtogroup RTEMSBSPsAArch64 + * + * @{ + */ + +#include + +#ifndef ASM +#include +#include +#endif + +#if defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) +#include +#elif defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) +#include +#elif defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) +#include +#elif defined(PHYTIUM_BSP_TYPE_D2000_TEST) +#include +#elif defined(PHYTIUM_BSP_TYPE_FT2004_DSK) +#include +#else +#error "Target unselected !!!" +#endif + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* definition of core information */ +#ifdef CORE0_AFF +#define BSP_CORE0_AFF CORE0_AFF +#endif + +#ifdef CORE1_AFF +#define BSP_CORE1_AFF CORE1_AFF +#endif + +#ifdef CORE2_AFF +#define BSP_CORE2_AFF CORE2_AFF +#endif + +#ifdef CORE3_AFF +#define BSP_CORE3_AFF CORE3_AFF +#endif + +#ifdef CORE4_AFF +#define BSP_CORE4_AFF CORE4_AFF +#endif + +#ifdef CORE5_AFF +#define BSP_CORE5_AFF CORE5_AFF +#endif + +#ifdef CORE6_AFF +#define BSP_CORE6_AFF CORE6_AFF +#endif + +#ifdef CORE7_AFF +#define BSP_CORE7_AFF CORE7_AFF +#endif + +#define BSP_CORE_NUM FCORE_NUM + +#ifndef ASM + +#define BSP_CPU_ON_USES_SMC + +/* definition for interrupts */ +#define BSP_SGI_INT_MAX SGI_INT_MAX +#define BSP_PPI_INT_LAST (SPI_START_INT_NUM - 1) + +#define BSP_ARM_GIC_CPUIF_BASE GICV3_BASE_ADDR +#define BSP_ARM_GIC_DIST_BASE GICV3_DISTRIBUTOR_BASE_ADDR +#if defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) || defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) +#define BSP_ARM_GIC_RD0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x80000U) +#define BSP_ARM_GIC_SGI0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x90000U) +#define BSP_ARM_GIC_RD1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xA0000U) +#define BSP_ARM_GIC_SGI1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xB0000U) +#define BSP_ARM_GIC_RD2_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xC0000U) +#define BSP_ARM_GIC_SGI2_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xD0000U) +#define BSP_ARM_GIC_RD3_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xE0000U) +#define BSP_ARM_GIC_SGI3_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xF0000U) +#elif defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) +#define BSP_ARM_GIC_RD0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xC0000U) +#define BSP_ARM_GIC_SGI0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xD0000U) +#define BSP_ARM_GIC_RD1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xE0000U) +#define BSP_ARM_GIC_SGI1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xF0000U) +#elif defined(PHYTIUM_BSP_TYPE_D2000_TEST) +#define BSP_ARM_GIC_RD0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x100000U) +#define BSP_ARM_GIC_SGI0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x110000U) +#define BSP_ARM_GIC_RD1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x120000U) +#define BSP_ARM_GIC_SGI1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x130000U) +#define BSP_ARM_GIC_RD2_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x140000U) +#define BSP_ARM_GIC_SGI2_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x150000U) +#define BSP_ARM_GIC_RD3_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x160000U) +#define BSP_ARM_GIC_SGI3_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x170000U) +#define BSP_ARM_GIC_RD4_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x180000U) +#define BSP_ARM_GIC_SGI4_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x190000U) +#define BSP_ARM_GIC_RD5_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x1A0000U) +#define BSP_ARM_GIC_SGI5_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x1B0000U) +#define BSP_ARM_GIC_RD6_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x1C0000U) +#define BSP_ARM_GIC_SGI6_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x1D0000U) +#define BSP_ARM_GIC_RD7_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x1E0000U) +#define BSP_ARM_GIC_SGI7_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x1F0000U) +#elif defined(PHYTIUM_BSP_TYPE_FT2004_DSK) +#define BSP_ARM_GIC_RD0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x80000U) +#define BSP_ARM_GIC_SGI0_BASE (BSP_ARM_GIC_CPUIF_BASE + 0x90000U) +#define BSP_ARM_GIC_RD1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xA0000U) +#define BSP_ARM_GIC_SGI1_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xB0000U) +#define BSP_ARM_GIC_RD2_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xC0000U) +#define BSP_ARM_GIC_SGI2_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xD0000U) +#define BSP_ARM_GIC_RD3_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xE0000U) +#define BSP_ARM_GIC_SGI3_BASE (BSP_ARM_GIC_CPUIF_BASE + 0xF0000U) +#endif + +#ifdef BSP_ARM_GIC_REDIST_BASE +#undef BSP_ARM_GIC_REDIST_BASE +#endif + +/* assert primary core is physical core-2, affinity 0x200 */ +#if defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) || defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) +#define BSP_ARM_GIC_REDIST_BASE BSP_ARM_GIC_RD2_BASE +#define BSP_ARM_GIC_MAIN_AFF BSP_CORE2_AFF +#else +#define BSP_ARM_GIC_REDIST_BASE BSP_ARM_GIC_RD0_BASE +#define BSP_ARM_GIC_MAIN_AFF BSP_CORE0_AFF +#endif + +/* definition for peripherals */ +#define BSP_FDT_IS_SUPPORTED + +#if defined(FUART1_BASE_ADDR) +#define BSP_PHYTIUM_UART1_BASE FUART1_BASE_ADDR +#define BSP_PHYTIUM_UART1_LENGTH FUART_REG_LENGTH + +#define BSP_PHYTIUM_CONSOLE_UART_BASE BSP_PHYTIUM_UART1_BASE +#define BSP_PHYTIUM_CONSOLE_UART_LENGTH BSP_PHYTIUM_UART1_LENGTH +#endif + +#if defined(FXMAC0_BASE_ADDR) +#define BSP_PHYTIUM_XMAC0_BASE FXMAC0_BASE_ADDR +#endif + +#if defined(FXMAC1_BASE_ADDR) +#define BSP_PHYTIUM_XMAC1_BASE FXMAC1_BASE_ADDR +#endif + +#endif /* ASM */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +/** @} */ + +#endif /* LIBBSP_AARCH64_PHYTIUM_BSP_H */ diff --git a/bsps/aarch64/phytium/include/bsp/irq.h b/bsps/aarch64/phytium/include/bsp/irq.h new file mode 100644 index 0000000000..294dabb435 --- /dev/null +++ b/bsps/aarch64/phytium/include/bsp/irq.h @@ -0,0 +1,90 @@ +#include +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief BSP IRQ definitions + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_AARCH64_PHYTIUM_IRQ_H +#define LIBBSP_AARCH64_PHYTIUM_IRQ_H + +#ifndef ASM + +#include +#include + +#if defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) +#include +#elif defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) +#include +#elif defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) +#include +#elif defined(PHYTIUM_BSP_TYPE_D2000_TEST) +#include +#elif defined(PHYTIUM_BSP_TYPE_FT2004_DSK) +#include +#else +#error "Target unselected !!!" +#endif + +/** + * @defgroup phytium_interrupt Interrrupt Support + * + * @ingroup RTEMSBSPsARMPhytium + * + * @brief Interrupt support. + */ + +#ifdef BSP_INTERRUPT_VECTOR_COUNT +#undef BSP_INTERRUPT_VECTOR_COUNT +#endif + +#define BSP_INTERRUPT_VECTOR_COUNT 270 + +/* Interrupts vectors */ +#define BSP_TIMER_VIRT_PPI GENERIC_VTIMER_IRQ_NUM +#define BSP_TIMER_PHYS_NS_PPI GENERIC_TIMER_NS_IRQ_NUM + +#if defined(FXMAC0_QUEUE0_IRQ_NUM) +#define BSP_PHYTIUM_XMAC0_IRQ FXMAC0_QUEUE0_IRQ_NUM +#endif + +#if defined(FXMAC1_QUEUE0_IRQ_NUM) +#define BSP_PHYTIUM_XMAC1_IRQ FXMAC1_QUEUE0_IRQ_NUM +#endif + +#if defined(FPCIE_ECAM_INTA_IRQ_NUM) +#define BSP_PHYTIUM_INTA_IRQ FPCIE_ECAM_INTA_IRQ_NUM +#endif + +#endif /* ASM */ +#endif /* LIBBSP_AARCH64_PHYTIUM_IRQ_H */ diff --git a/bsps/aarch64/phytium/include/soc/d2000/fparameters.h b/bsps/aarch64/phytium/include/soc/d2000/fparameters.h new file mode 100644 index 0000000000..6f890aec6f --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/d2000/fparameters.h @@ -0,0 +1,391 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 17:58:51 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef D2000_FPARAMETERS_H +#define D2000_FPARAMETERS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + + +#define SOC_TARGET_D2000 + +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x1 +#define CORE2_AFF 0x100 +#define CORE3_AFF 0x101 +#define CORE4_AFF 0x200 +#define CORE5_AFF 0x201 +#define CORE6_AFF 0x300 +#define CORE7_AFF 0x301 +#define FCORE_NUM 8 + +/* cache */ +#define CACHE_LINE_ADDR_MASK 0x3FUL +#define CACHE_LINE 64U + +/* Device register address */ +#define FDEV_BASE_ADDR 0x28000000 +#define FDEV_END_ADDR 0x2FFFFFFF + + +/* PCIE ECAM */ + +/* Pci express */ +#define FPCIE_ECAM_INSTANCE_NUM 1 +#define FPCIE_ECAM_INSTANCE0 0 + +#define FPCIE_ECAM_MAX_OUTBOUND_NUM 8 + +/* Bus, Device and Function */ +#define FPCIE_ECAM_CFG_MAX_NUM_OF_BUS 256 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_DEV 32 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_FUN 8 + +#define FPCIE_ECAM_INTA_IRQ_NUM 60 +#define FPCIE_ECAM_INTB_IRQ_NUM 61 +#define FPCIE_ECAM_INTC_IRQ_NUM 62 +#define FPCIE_ECAM_INTD_IRQ_NUM 63 + +/* max scan*/ +#define FPCIE_MAX_SCAN_NUMBER 128 + +/* memory space */ +#define FPCI_ECAM_CONFIG_BASE_ADDR 0x40000000 /* ecam */ +#define FPCI_ECAM_CONFIG_REG_LENGTH 0x10000000 + +#define FPCI_ECAM_IO_CONFIG_BASE_ADDR 0x50000000 /* io address space */ +#define FPCI_ECAM_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FPCI_ECAM_MEM32_BASE_ADDR 0x58000000 /* mmio 32 */ +#define FPCI_ECAM_MEM32_REG_LENGTH 0x27ffffff + +#define FPCI_ECAM_MEM64_BASE_ADDR 0x1000000000 /* mmio 64 */ +#define FPCI_ECAM_MEM64_REG_LENGTH 0x1fffffffff + +#define FPCI_ECAM_INTX_NEED_EOI 1 +#define FPCI_ECAM_INTX_CONTROL_STATUS_REG_NUM 2 +#define FPCI_ECAM_INTX_CONTROL_STATUS_REG0 0x29100000 +#define FPCI_ECAM_INTX_CONTROL_STATUS_REG1 0x29101000 + +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_NUM 6 +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_REG0 0x29000184 +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_REG1 0x29010184 +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_REG2 0x29020184 +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_REG3 0x29030184 +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_REG4 0x29040184 +#define FPCI_ECAM_INTX_CONFIG_ISTATUS_REG5 0x29050184 + + +/* platform ahci host */ +#define PLAT_AHCI_HOST_MAX_COUNT 5 +#define AHCI_BASE_0 0 +#define AHCI_BASE_1 0 +#define AHCI_BASE_2 0 +#define AHCI_BASE_3 0 +#define AHCI_BASE_4 0 + +#define AHCI_IRQ_0 0 +#define AHCI_IRQ_1 0 +#define AHCI_IRQ_2 0 +#define AHCI_IRQ_3 0 +#define AHCI_IRQ_4 0 + +/* UART */ +#define FUART0_ID 0 +#define FUART1_ID 1 +#define FUART2_ID 2 +#define FUART3_ID 3 +#define FUART_NUM 4 + + +#define FUART0_IRQ_NUM 38 +#define FUART0_BASE_ADDR 0x28000000 +#define FUART0_CLK_FREQ_HZ 48000000 + +#define FUART1_IRQ_NUM 39 +#define FUART1_BASE_ADDR 0x28001000 +#define FUART1_CLK_FREQ_HZ 48000000 + +#define FUART2_IRQ_NUM 40 +#define FUART2_BASE_ADDR 0x28002000 +#define FUART2_CLK_FREQ_HZ 48000000 + +#define FUART3_IRQ_NUM 41 +#define FUART3_BASE_ADDR 0x28003000 +#define FUART3_CLK_FREQ_HZ 48000000 + +#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR +#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR + +/* QSPI */ +#define FQSPI0_ID 0 +#define FQSPI_NUM 1 + +/* FQSPI cs 0_3, chip number */ + +#define FQSPI_CS_0 0 +#define FQSPI_CS_1 1 +#define FQSPI_CS_2 2 +#define FQSPI_CS_3 3 +#define FQSPI_CS_NUM 4 + +#define FQSPI_BASE_ADDR 0x28014000 +#define FQSPI_MEM_START_ADDR 0x0 +#define FQSPI_MEM_END_ADDR 0x1FFFFFFF + +/* GIC v3 */ +#define ARM_GIC_NR_IRQS 1024 +#define ARM_GIC_IRQ_START 0 +#define FGIC_NUM 1 + + +#define GICV3_BASE_ADDR 0x29a00000U +#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) +#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x100000U) +#define GICV3_RD_OFFSET (2U << 16) +#define GICV3_RD_SIZE (16U << 16) + +#define GICV3_ITS_BASE_ADDR (GICV3_BASE_ADDR + 0x20000U) + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ + +/* GPIO */ +#define FGPIO0_BASE_ADDR (0x28004000) +#define FGPIO1_BASE_ADDR (0x28005000) + +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_NUM 2U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_B 1U +#define FGPIO_PORT_NUM 2U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_NUM 8U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, port, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((port) * FGPIO_PIN_NUM) + (pin)) + +/* IOCTRL */ +#define FIOCTRL_BASE_ADDR 0x28180000 + +#define FIOCTRL0_ID 0 +#define FIOCTRL_NUM 1 + + +#define FIOCTRL_INDEX(offset, func_beg) \ + { \ + /* reg_off */ (offset), \ + /* reg_bit */ (func_beg) \ + } + +#define FIOCTRL_CRU_CLK_OBV_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x200, 24) +#define FIOCTRL_SPI0_CSN0_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 16) +#define FIOCTRL_SPI0_SCK_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 12) +#define FIOCTRL_SPI0_SO_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 8) +#define FIOCTRL_SPI0_SI_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 4) + +#define FIOCTRL_TJTAG_TDI_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */ +#define FIOCTRL_SWDITMS_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */ + +#define FIOCTRL_NTRST_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */ +#define FIOCTRL_SWDO_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */ + +#define FIOCTRL_I2C0_SCL_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */ +#define FIOCTRL_I2C0_SDA_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */ +#define FIOCTRL_ALL_PLL_LOCK_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */ +#define FIOCTRL_CRU_CLK_OBV_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */ +#define FIOCTRL_SWDO_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */ +#define FIOCTRL_TDO_SWJ_IN_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */ +#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */ +#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */ + +#define FIOCTRL_SPI0_CSN0_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 16) /* gpio1_a_5: func 2 */ +#define FIOCTRL_SPI0_SCK_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 12) /* gpio1_a_6: func 2 */ +#define FIOCTRL_SPI0_SO_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 8) /* gpio1_a_7: func 2 */ +#define FIOCTRL_SPI0_SI_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 4) /* gpio1_b_0: func 2 */ + +#define FIOCTRL_UART_2_RXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */ +#define FIOCTRL_UART_2_TXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */ +#define FIOCTRL_UART_3_RXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */ +#define FIOCTRL_UART_3_TXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */ +#define FIOCTRL_QSPI_CSN2_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */ +#define FIOCTRL_QSPI_CSN3_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */ + +#define FIOCTRL_LPC_LAD0_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x218, 12) /* gpio_1_a_3: func 1 */ +#define FIOCTRL_LPC_LAD1_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x218, 8) /* gpio_1_a_4: func 1 */ + +/* SPI */ +#define FSPI0_BASE_ADDR 0x2800c000 +#define FSPI1_BASE_ADDR 0x28013000 +#define FSPI0_ID 0 +#define FSPI1_ID 1 +#define FSPI_CLK_FREQ_HZ 48000000 +#define FSPI_NUM 2 +#define FSPI0_IRQ_NUM 50 +#define FSPI1_IRQ_NUM 51 + +#define FSPI_DMA_CAPACITY BIT(0) +#define FSPIM0_DMA_CAPACITY 0 +#define FSPIM1_DMA_CAPACITY 0 + +/* I2C */ + +#define FI2C0_ID 0 +#define FI2C1_ID 1 +#define FI2C2_ID 2 +#define FI2C3_ID 3 +#define FI2C_NUM 4 + + + +#define FI2C0_BASE_ADDR 0x28006000 +#define FI2C1_BASE_ADDR 0x28007000 +#define FI2C2_BASE_ADDR 0x28008000 +#define FI2C3_BASE_ADDR 0x28009000 + +#define FI2C0_IRQ_NUM 44 +#define FI2C1_IRQ_NUM 45 +#define FI2C2_IRQ_NUM 46 +#define FI2C3_IRQ_NUM 47 + +#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */ + +/* WDT */ + + +#define FWDT0_ID 0 +#define FWDT1_ID 1 +#define FWDT_NUM 2 + + +#define FWDT0_REFRESH_BASE_ADDR 0x2800a000 +#define FWDT1_REFRESH_BASE_ADDR 0x28016000 + +#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) + +#define FWDT0_IRQ_NUM 48 +#define FWDT1_IRQ_NUM 49 + +#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */ + +/* SDCI */ + +#define FSDMMC0_ID 0 +#define FSDMMC_NUM 1 + +#define FSDMMC0_BASE_ADDR 0x28207C00 + +#define FSDMMC0_DMA_IRQ_NUM 52 +#define FSDMMC0_CMD_IRQ_NUM 53 +#define FSDMMC0_ERR_IRQ_NUM 54 + +#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */ + +/* GMAC */ +#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */ + + +#define FGMAC0_ID 0 +#define FGMAC1_ID 1 +#define FGMAC_NUM 2 + +#define FGMAC0_BASE_ADDR 0x2820C000 +#define FGMAC1_BASE_ADDR 0x28210000 + +#define FGMAC0_IRQ_NUM 81 +#define FGMAC1_IRQ_NUM 82 + +#define FGMAC_DMA_MIN_ALIGN 128 +#define FGMAC_MAX_PACKET_SIZE 1600 + +/* rtc base address */ +#define RTC_CONTROL_BASE 0x2800D000 + +/* can */ +#define FCAN_CLK_FREQ_HZ 600000000 + +#define FCAN_REG_LENGTH 0x1000 +#define FCAN0_BASE_ADDR 0x28207000 +#define FCAN1_BASE_ADDR 0x28207400 +#define FCAN2_BASE_ADDR 0x28207800 +#define FCAN0_IRQ_NUM 119 +#define FCAN1_IRQ_NUM 123 +#define FCAN2_IRQNUM 124 + +#define FCAN0_ID 0 +#define FCAN1_ID 1 +#define FCAN2_ID 2 +#define FCAN_NUM 3 + +/* can capacity */ +#define FCAN_FD_CAPACITY BIT(0) /* Whether canfd is supported */ +#define FCAN_CAPACITY 0 + +/* generic timer */ +/* non-secure physical timer int id */ +#define GENERIC_TIMER_NS_IRQ_NUM 30U + +/* virtual timer int id */ +#define GENERIC_VTIMER_IRQ_NUM 27U + + +#define GENERIC_TIMER_ID0 0 /* non-secure physical timer */ +#define GENERIC_TIMER_ID1 1 /* virtual timer */ +#define GENERIC_TIMER_NUM 2 + +/* PMU */ +#define FPMU_IRQ_NUM 23 + + +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/e2000d/fparameters.h b/bsps/aarch64/phytium/include/soc/e2000d/fparameters.h new file mode 100644 index 0000000000..88a6d73fea --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/e2000d/fparameters.h @@ -0,0 +1,367 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters.h + * Date: 2022-02-11 13:33:28 + * LastEditTime: 2022-02-17 18:00:50 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef E2000D_FPARAMETERS_H +#define E2000D_FPARAMETERS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************** Include Files *********************************/ +#include "fparameters_comm.h" + +/************************** Constant Definitions *****************************/ +#define SOC_TARGET_E2000D + +#define CORE0_AFF 0x200U +#define CORE1_AFF 0x201U +#define FCORE_NUM 2 + +/* PWM */ +#define FPWM0_ID 0 +#define FPWM1_ID 1 +#define FPWM2_ID 2 +#define FPWM3_ID 3 +#define FPWM_NUM 4 + +#define FPWM_CHANNEL_0 0 +#define FPWM_CHANNEL_1 1 +#define FPWM_CHANNEL_NUM 2 + +#define FPWM_BASE_ADDR 0x2804A000U + +#define FPWM_CLK_FREQ_HZ 50000000U /* 50MHz */ + +#define FPWM0_IRQ_NUM 205U +#define FPWM1_IRQ_NUM 206U +#define FPWM2_IRQ_NUM 207U +#define FPWM3_IRQ_NUM 208U +#define FPWM4_IRQ_NUM 209U +#define FPWM5_IRQ_NUM 210U +#define FPWM6_IRQ_NUM 211U +#define FPWM7_IRQ_NUM 212U + +#define FPWM_CYCLE_PROCESSING(reg_val) ((reg_val) - 0x1) + +/* I2S */ + +#define FI2S0_ID 0U +#define FI2S1_ID 1U +#define FI2S2_ID 2U +#define FI2S_NUM 3U + +#define FI2S0_BASE_ADDR 0x28009000 +#define FI2S0_IRQ_NUM 112 + +#define FI2S1_BASE_ADDR 0x32009000 /*i2s for dp0*/ +#define FI2S1_IRQ_NUM 77 + +#define FI2S2_BASE_ADDR 0x3200B000 /*i2s for dp1*/ +#define FI2S2_IRQ_NUM 78 + +#define FI2S_CLK_FREQ_HZ 600000000 /* 600MHz */ + +/* sata controller */ +#define FSATA0_BASE_ADDR 0x31A40000U +#define FSATA1_BASE_ADDR 0x32014000U + +#define FSATA0_IRQ_NUM 74 +#define FSATA1_IRQ_NUM 75 + +#define FSATA0_ID 0 +#define FSATA1_ID 1 +#define FSATA_NUM 2 + +/* CANFD */ +#define FCAN_CLK_FREQ_HZ 200000000U + +#define FCAN0_BASE_ADDR 0x2800A000U +#define FCAN1_BASE_ADDR 0x2800B000U + +#define FCAN0_IRQ_NUM 113U +#define FCAN1_IRQ_NUM 114U + +#define FCAN0_ID 0 +#define FCAN1_ID 1 +#define FCAN_NUM 2 + +/* can capacity */ +#define FCAN_FD_CAPACITY BIT(0) /* Whether canfd is supported */ +#define FCAN_CAPACITY FCAN_FD_CAPACITY + +/* register offset of iopad function / pull / driver strength */ +#define FIOPAD_AN55_REG0_OFFSET 0x0000U +#define FIOPAD_AW43_REG0_OFFSET 0x0004U +#define FIOPAD_AR51_REG0_OFFSET 0x0020U +#define FIOPAD_AJ51_REG0_OFFSET 0x0024U +#define FIOPAD_AL51_REG0_OFFSET 0x0028U +#define FIOPAD_AL49_REG0_OFFSET 0x002CU +#define FIOPAD_AN47_REG0_OFFSET 0x0030U +#define FIOPAD_AR47_REG0_OFFSET 0x0034U +#define FIOPAD_BA53_REG0_OFFSET 0x0038U +#define FIOPAD_BA55_REG0_OFFSET 0x003CU +#define FIOPAD_AW53_REG0_OFFSET 0x0040U +#define FIOPAD_AW55_REG0_OFFSET 0x0044U +#define FIOPAD_AU51_REG0_OFFSET 0x0048U +#define FIOPAD_AN53_REG0_OFFSET 0x004CU +#define FIOPAD_AL55_REG0_OFFSET 0x0050U +#define FIOPAD_AJ55_REG0_OFFSET 0x0054U +#define FIOPAD_AJ53_REG0_OFFSET 0x0058U +#define FIOPAD_AG55_REG0_OFFSET 0x005CU +#define FIOPAD_AG53_REG0_OFFSET 0x0060U +#define FIOPAD_AE55_REG0_OFFSET 0x0064U +#define FIOPAD_AC55_REG0_OFFSET 0x0068U +#define FIOPAD_AC53_REG0_OFFSET 0x006CU +#define FIOPAD_AR45_REG0_OFFSET 0x0070U +#define FIOPAD_BA51_REG0_OFFSET 0x0074U +#define FIOPAD_BA49_REG0_OFFSET 0x0078U +#define FIOPAD_AR55_REG0_OFFSET 0x007CU +#define FIOPAD_AU55_REG0_OFFSET 0x0080U +#define FIOPAD_AR53_REG0_OFFSET 0x0084U +#define FIOPAD_BA45_REG0_OFFSET 0x0088U +#define FIOPAD_AW51_REG0_OFFSET 0x008CU +#define FIOPAD_A31_REG0_OFFSET 0x0090U +#define FIOPAD_R53_REG0_OFFSET 0x0094U +#define FIOPAD_R55_REG0_OFFSET 0x0098U +#define FIOPAD_U55_REG0_OFFSET 0x009CU +#define FIOPAD_W55_REG0_OFFSET 0x00A0U +#define FIOPAD_U53_REG0_OFFSET 0x00A4U +#define FIOPAD_AA53_REG0_OFFSET 0x00A8U +#define FIOPAD_AA55_REG0_OFFSET 0x00ACU +#define FIOPAD_AW47_REG0_OFFSET 0x00B0U +#define FIOPAD_AU47_REG0_OFFSET 0x00B4U +#define FIOPAD_A35_REG0_OFFSET 0x00B8U +#define FIOPAD_C35_REG0_OFFSET 0x00BCU +#define FIOPAD_C33_REG0_OFFSET 0x00C0U +#define FIOPAD_A33_REG0_OFFSET 0x00C4U +#define FIOPAD_A37_REG0_OFFSET 0x00C8U +#define FIOPAD_A39_REG0_OFFSET 0x00CCU +#define FIOPAD_A41_REG0_OFFSET 0x00D0U +#define FIOPAD_C41_REG0_OFFSET 0x00D4U +#define FIOPAD_A43_REG0_OFFSET 0x00D8U +#define FIOPAD_A45_REG0_OFFSET 0x00DCU +#define FIOPAD_C45_REG0_OFFSET 0x00E0U +#define FIOPAD_A47_REG0_OFFSET 0x00E4U +#define FIOPAD_A29_REG0_OFFSET 0x00E8U +#define FIOPAD_C29_REG0_OFFSET 0x00ECU +#define FIOPAD_C27_REG0_OFFSET 0x00F0U +#define FIOPAD_A27_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ49_REG0_OFFSET 0x00F8U +#define FIOPAD_AL45_REG0_OFFSET 0x00FCU +#define FIOPAD_AL43_REG0_OFFSET 0x0100U +#define FIOPAD_AN45_REG0_OFFSET 0x0104U +#define FIOPAD_AG47_REG0_OFFSET 0x0108U +#define FIOPAD_AJ47_REG0_OFFSET 0x010CU +#define FIOPAD_AG45_REG0_OFFSET 0x0110U +#define FIOPAD_AE51_REG0_OFFSET 0x0114U +#define FIOPAD_AE49_REG0_OFFSET 0x0118U +#define FIOPAD_AG51_REG0_OFFSET 0x011CU +#define FIOPAD_AJ45_REG0_OFFSET 0x0120U +#define FIOPAD_AC51_REG0_OFFSET 0x0124U +#define FIOPAD_AC49_REG0_OFFSET 0x0128U +#define FIOPAD_AE47_REG0_OFFSET 0x012CU +#define FIOPAD_W47_REG0_OFFSET 0x0130U +#define FIOPAD_W51_REG0_OFFSET 0x0134U +#define FIOPAD_W49_REG0_OFFSET 0x0138U +#define FIOPAD_U51_REG0_OFFSET 0x013CU +#define FIOPAD_U49_REG0_OFFSET 0x0140U +#define FIOPAD_AE45_REG0_OFFSET 0x0144U +#define FIOPAD_AC45_REG0_OFFSET 0x0148U +#define FIOPAD_AE43_REG0_OFFSET 0x014CU +#define FIOPAD_AA43_REG0_OFFSET 0x0150U +#define FIOPAD_AA45_REG0_OFFSET 0x0154U +#define FIOPAD_W45_REG0_OFFSET 0x0158U +#define FIOPAD_AA47_REG0_OFFSET 0x015CU +#define FIOPAD_U45_REG0_OFFSET 0x0160U +#define FIOPAD_G55_REG0_OFFSET 0x0164U +#define FIOPAD_J55_REG0_OFFSET 0x0168U +#define FIOPAD_L53_REG0_OFFSET 0x016CU +#define FIOPAD_C55_REG0_OFFSET 0x0170U +#define FIOPAD_E55_REG0_OFFSET 0x0174U +#define FIOPAD_J53_REG0_OFFSET 0x0178U +#define FIOPAD_L55_REG0_OFFSET 0x017CU +#define FIOPAD_N55_REG0_OFFSET 0x0180U +#define FIOPAD_C53_REG0_OFFSET 0x0184U +#define FIOPAD_E53_REG0_OFFSET 0x0188U +#define FIOPAD_E27_REG0_OFFSET 0x018CU +#define FIOPAD_G27_REG0_OFFSET 0x0190U +#define FIOPAD_N37_REG0_OFFSET 0x0194U +#define FIOPAD_N35_REG0_OFFSET 0x0198U +#define FIOPAD_J29_REG0_OFFSET 0x019CU +#define FIOPAD_N29_REG0_OFFSET 0x01A0U +#define FIOPAD_L29_REG0_OFFSET 0x01A4U +#define FIOPAD_N41_REG0_OFFSET 0x01A8U +#define FIOPAD_N39_REG0_OFFSET 0x01ACU +#define FIOPAD_L27_REG0_OFFSET 0x01B0U +#define FIOPAD_J27_REG0_OFFSET 0x01B4U +#define FIOPAD_J25_REG0_OFFSET 0x01B8U +#define FIOPAD_E25_REG0_OFFSET 0x01BCU +#define FIOPAD_G25_REG0_OFFSET 0x01C0U +#define FIOPAD_N23_REG0_OFFSET 0x01C4U +#define FIOPAD_L25_REG0_OFFSET 0x01C8U +#define FIOPAD_J33_REG0_OFFSET 0x01CCU +#define FIOPAD_J35_REG0_OFFSET 0x01D0U +#define FIOPAD_G37_REG0_OFFSET 0x01D4U +#define FIOPAD_E39_REG0_OFFSET 0x01D8U +#define FIOPAD_L39_REG0_OFFSET 0x01DCU +#define FIOPAD_C39_REG0_OFFSET 0x01E0U +#define FIOPAD_E37_REG0_OFFSET 0x01E4U +#define FIOPAD_L41_REG0_OFFSET 0x01E8U +#define FIOPAD_J39_REG0_OFFSET 0x01ECU +#define FIOPAD_J37_REG0_OFFSET 0x01F0U +#define FIOPAD_L35_REG0_OFFSET 0x01F4U +#define FIOPAD_E33_REG0_OFFSET 0x01F8U +#define FIOPAD_E31_REG0_OFFSET 0x01FCU +#define FIOPAD_G31_REG0_OFFSET 0x0200U +#define FIOPAD_J31_REG0_OFFSET 0x0204U +#define FIOPAD_L33_REG0_OFFSET 0x0208U +#define FIOPAD_N31_REG0_OFFSET 0x020CU +#define FIOPAD_R47_REG0_OFFSET 0x0210U +#define FIOPAD_R45_REG0_OFFSET 0x0214U +#define FIOPAD_N47_REG0_OFFSET 0x0218U +#define FIOPAD_N51_REG0_OFFSET 0x021CU +#define FIOPAD_L51_REG0_OFFSET 0x0220U +#define FIOPAD_J51_REG0_OFFSET 0x0224U +#define FIOPAD_J41_REG0_OFFSET 0x0228U +#define FIOPAD_E43_REG0_OFFSET 0x022CU +#define FIOPAD_G43_REG0_OFFSET 0x0230U +#define FIOPAD_J43_REG0_OFFSET 0x0234U +#define FIOPAD_J45_REG0_OFFSET 0x0238U +#define FIOPAD_N45_REG0_OFFSET 0x023CU +#define FIOPAD_L47_REG0_OFFSET 0x0240U +#define FIOPAD_L45_REG0_OFFSET 0x0244U +#define FIOPAD_N49_REG0_OFFSET 0x0248U +#define FIOPAD_J49_REG0_OFFSET 0x024CU + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN55_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J49_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ51_REG1_OFFSET 0x1024U +#define FIOPAD_AL51_REG1_OFFSET 0x1028U +#define FIOPAD_AL49_REG1_OFFSET 0x102CU +#define FIOPAD_AN47_REG1_OFFSET 0x1030U +#define FIOPAD_AR47_REG1_OFFSET 0x1034U +#define FIOPAD_AJ53_REG1_OFFSET 0x1058U +#define FIOPAD_AG55_REG1_OFFSET 0x105CU +#define FIOPAD_AG53_REG1_OFFSET 0x1060U +#define FIOPAD_AE55_REG1_OFFSET 0x1064U +#define FIOPAD_BA51_REG1_OFFSET 0x1074U +#define FIOPAD_BA49_REG1_OFFSET 0x1078U +#define FIOPAD_AR55_REG1_OFFSET 0x107CU +#define FIOPAD_AU55_REG1_OFFSET 0x1080U +#define FIOPAD_A41_REG1_OFFSET 0x10D0U +#define FIOPAD_C41_REG1_OFFSET 0x10D4U +#define FIOPAD_A43_REG1_OFFSET 0x10D8U +#define FIOPAD_A45_REG1_OFFSET 0x10DCU +#define FIOPAD_C45_REG1_OFFSET 0x10E0U +#define FIOPAD_A47_REG1_OFFSET 0x10E4U +#define FIOPAD_A29_REG1_OFFSET 0x10E8U +#define FIOPAD_C29_REG1_OFFSET 0x10ECU +#define FIOPAD_C27_REG1_OFFSET 0x10F0U +#define FIOPAD_A27_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ49_REG1_OFFSET 0x10F8U +#define FIOPAD_AL45_REG1_OFFSET 0x10FCU +#define FIOPAD_AL43_REG1_OFFSET 0x1100U +#define FIOPAD_AN45_REG1_OFFSET 0x1104U +#define FIOPAD_AG47_REG1_OFFSET 0x1108U +#define FIOPAD_AJ47_REG1_OFFSET 0x110CU +#define FIOPAD_AG45_REG1_OFFSET 0x1110U +#define FIOPAD_AE51_REG1_OFFSET 0x1114U +#define FIOPAD_AE49_REG1_OFFSET 0x1118U +#define FIOPAD_AG51_REG1_OFFSET 0x111CU +#define FIOPAD_AJ45_REG1_OFFSET 0x1120U +#define FIOPAD_AC51_REG1_OFFSET 0x1124U +#define FIOPAD_AC49_REG1_OFFSET 0x1128U +#define FIOPAD_AE47_REG1_OFFSET 0x112CU +#define FIOPAD_W47_REG1_OFFSET 0x1130U +#define FIOPAD_W49_REG1_OFFSET 0x1138U +#define FIOPAD_U51_REG1_OFFSET 0x113CU +#define FIOPAD_U49_REG1_OFFSET 0x1140U +#define FIOPAD_AE45_REG1_OFFSET 0x1144U +#define FIOPAD_AC45_REG1_OFFSET 0x1148U +#define FIOPAD_AE43_REG1_OFFSET 0x114CU +#define FIOPAD_AA43_REG1_OFFSET 0x1150U +#define FIOPAD_AA45_REG1_OFFSET 0x1154U +#define FIOPAD_W45_REG1_OFFSET 0x1158U +#define FIOPAD_AA47_REG1_OFFSET 0x115CU +#define FIOPAD_U45_REG1_OFFSET 0x1160U +#define FIOPAD_J55_REG1_OFFSET 0x1168U +#define FIOPAD_L53_REG1_OFFSET 0x116CU +#define FIOPAD_C55_REG1_OFFSET 0x1170U +#define FIOPAD_E55_REG1_OFFSET 0x1174U +#define FIOPAD_J53_REG1_OFFSET 0x1178U +#define FIOPAD_L55_REG1_OFFSET 0x117CU +#define FIOPAD_N55_REG1_OFFSET 0x1180U +#define FIOPAD_E27_REG1_OFFSET 0x118CU +#define FIOPAD_G27_REG1_OFFSET 0x1190U +#define FIOPAD_N37_REG1_OFFSET 0x1194U +#define FIOPAD_N35_REG1_OFFSET 0x1198U +#define FIOPAD_J29_REG1_OFFSET 0x119CU +#define FIOPAD_N29_REG1_OFFSET 0x11A0U +#define FIOPAD_L29_REG1_OFFSET 0x11A4U +#define FIOPAD_N41_REG1_OFFSET 0x11A8U +#define FIOPAD_N39_REG1_OFFSET 0x11ACU +#define FIOPAD_L27_REG1_OFFSET 0x11B0U +#define FIOPAD_J27_REG1_OFFSET 0x11B4U +#define FIOPAD_J25_REG1_OFFSET 0x11B8U +#define FIOPAD_E25_REG1_OFFSET 0x11BCU +#define FIOPAD_G25_REG1_OFFSET 0x11C0U +#define FIOPAD_J33_REG1_OFFSET 0x11CCU +#define FIOPAD_J35_REG1_OFFSET 0x11D0U +#define FIOPAD_G37_REG1_OFFSET 0x11D4U +#define FIOPAD_E39_REG1_OFFSET 0x11D8U +#define FIOPAD_L39_REG1_OFFSET 0x11DCU +#define FIOPAD_C39_REG1_OFFSET 0x11E0U +#define FIOPAD_E37_REG1_OFFSET 0x11E4U +#define FIOPAD_L41_REG1_OFFSET 0x11E8U +#define FIOPAD_J39_REG1_OFFSET 0x11ECU +#define FIOPAD_J37_REG1_OFFSET 0x11F0U +#define FIOPAD_L35_REG1_OFFSET 0x11F4U +#define FIOPAD_E33_REG1_OFFSET 0x11F8U +#define FIOPAD_E31_REG1_OFFSET 0x11FCU +#define FIOPAD_G31_REG1_OFFSET 0x1200U +#define FIOPAD_L51_REG1_OFFSET 0x1220U +#define FIOPAD_J51_REG1_OFFSET 0x1224U +#define FIOPAD_J41_REG1_OFFSET 0x1228U +#define FIOPAD_E43_REG1_OFFSET 0x122CU +#define FIOPAD_G43_REG1_OFFSET 0x1230U +#define FIOPAD_J43_REG1_OFFSET 0x1234U +#define FIOPAD_J45_REG1_OFFSET 0x1238U +#define FIOPAD_N45_REG1_OFFSET 0x123CU +#define FIOPAD_L47_REG1_OFFSET 0x1240U +#define FIOPAD_L45_REG1_OFFSET 0x1244U +#define FIOPAD_N49_REG1_OFFSET 0x1248U +#define FIOPAD_J49_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ51_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J49_REG1_OFFSET + +#ifdef __cplusplus +} + +#endif + +#endif \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/e2000d/fparameters_comm.h b/bsps/aarch64/phytium/include/soc/e2000d/fparameters_comm.h new file mode 100644 index 0000000000..85bddcbd5b --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/e2000d/fparameters_comm.h @@ -0,0 +1,691 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters_comm.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 18:01:11 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef E2000_FPARAMETERS_COMMON_H +#define E2000_FPARAMETERS_COMMON_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************** Include Files *********************************/ + +#define SOC_TARGET_E2000 +/************************** Constant Definitions *****************************/ +/* CACHE */ +#define CACHE_LINE_ADDR_MASK 0x3FUL +#define CACHE_LINE 64U + +/* DEVICE Register Address */ +#define FT_DEV_BASE_ADDR 0x28000000U +#define FT_DEV_END_ADDR 0x2FFFFFFFU + +/* PCIE */ + +/* PCIE ECAM */ + +/* Pci express */ +#define FPCIE_ECAM_INSTANCE_NUM 1 +#define FPCIE_ECAM_INSTANCE0 0 + +#define FPCIE_ECAM_MAX_OUTBOUND_NUM 8 + +/* Bus, Device and Function */ +#define FPCIE_ECAM_CFG_MAX_NUM_OF_BUS 256 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_DEV 32 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_FUN 8 + +#define FPCIE_ECAM_INTA_IRQ_NUM 36 +#define FPCIE_ECAM_INTB_IRQ_NUM 37 +#define FPCIE_ECAM_INTC_IRQ_NUM 38 +#define FPCIE_ECAM_INTD_IRQ_NUM 39 + +/* max scan*/ +#define FPCIE_MAX_SCAN_NUMBER 128 + +/* memory space */ +#define FPCI_ECAM_CONFIG_BASE_ADDR 0x40000000 /* ecam */ +#define FPCI_ECAM_CONFIG_REG_LENGTH 0x10000000 + +#define FPCI_ECAM_IO_CONFIG_BASE_ADDR 0x50000000 /* io address space */ +#define FPCI_ECAM_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FPCI_ECAM_MEM32_BASE_ADDR 0x58000000 /* mmio 32 */ +#define FPCI_ECAM_MEM32_REG_LENGTH 0x27ffffff + +#define FPCI_ECAM_MEM64_BASE_ADDR 0x1000000000 /* mmio 64 */ +#define FPCI_ECAM_MEM64_REG_LENGTH 0x1fffffffff + + +/* FPCIE Controler */ +#define FPCIEC_INSTANCE_NUM 6 + +#define FPCIEC_INSTANCE0_INDEX 0 /* psu.c0 */ +#define FPCIEC_INSTANCE1_INDEX 1 /* psu.c1 */ +#define FPCIEC_INSTANCE2_INDEX 2 /* peu.c0 */ +#define FPCIEC_INSTANCE3_INDEX 3 /* peu.c1 */ +#define FPCIEC_INSTANCE4_INDEX 4 /* peu.c2 */ +#define FPCIEC_INSTANCE5_INDEX 5 /* peu.c3 */ + +#define FPCIEC_INSTANCE0_MISC_IRQ_NUM 42 + +#define FPCIEC_INSTANCE3_MISC_IRQ_NUM 40 + +#define FPCIEC_INSTANCE0_NUM 0 /* psu.c0 */ +#define FPCIEC_INSTANCE1_NUM 1 /* psu.c1 */ +#define FPCIEC_INSTANCE2_NUM 0 /* peu.c0 */ +#define FPCIEC_INSTANCE3_NUM 1 /* peu.c1 */ +#define FPCIEC_INSTANCE4_NUM 2 /* peu.c2 */ +#define FPCIEC_INSTANCE5_NUM 3 /* peu.c3 */ + +#define FPCIEC_INSTANCE0_CONTROL_BASE 0x31000000U +#define FPCIEC_INSTANCE1_CONTROL_BASE 0x31020000U +#define FPCIEC_INSTANCE2_CONTROL_BASE 0x31040000U +#define FPCIEC_INSTANCE3_CONTROL_BASE 0x31060000U +#define FPCIEC_INSTANCE4_CONTROL_BASE 0x31080000U +#define FPCIEC_INSTANCE5_CONTROL_BASE 0x310a0000U + +#define FPCIEC_INSTANCE0_CONFIG_BASE 0x31100000U +#define FPCIEC_INSTANCE1_CONFIG_BASE 0x31100000U +#define FPCIEC_INSTANCE2_CONFIG_BASE 0x31101000U +#define FPCIEC_INSTANCE3_CONFIG_BASE 0x31101000U +#define FPCIEC_INSTANCE4_CONFIG_BASE 0x31101000U +#define FPCIEC_INSTANCE5_CONFIG_BASE 0x31101000U + +#define FPCIEC_INSTANCE0_DMA_NUM 2 +#define FPCIEC_INSTANCE1_DMA_NUM 0 +#define FPCIEC_INSTANCE2_DMA_NUM 2 +#define FPCIEC_INSTANCE3_DMA_NUM 0 +#define FPCIEC_INSTANCE4_DMA_NUM 0 +#define FPCIEC_INSTANCE5_DMA_NUM 0 + +#define FPCIEC_INSTANCE0_DMABASE (0x31000000U + 0x400U) +#define FPCIEC_INSTANCE1_DMABASE (0U) +#define FPCIEC_INSTANCE2_DMABASE (0x31040000U + 0x400U) +#define FPCIEC_INSTANCE3_DMABASE (0U) +#define FPCIEC_INSTANCE4_DMABASE (0U) +#define FPCIEC_INSTANCE5_DMABASE (0U) + +#define FPCIEC_MAX_OUTBOUND_NUM 8 + + +/* platform ahci host */ +#define PLAT_AHCI_HOST_MAX_COUNT 5 +#define AHCI_BASE_0 0 +#define AHCI_BASE_1 0 +#define AHCI_BASE_2 0 +#define AHCI_BASE_3 0 +#define AHCI_BASE_4 0 + +#define AHCI_IRQ_0 0 +#define AHCI_IRQ_1 0 +#define AHCI_IRQ_2 0 +#define AHCI_IRQ_3 0 +#define AHCI_IRQ_4 0 + + +/* SCMI and MHU */ +#define FSCMI_MHU_BASE_ADDR 0x32a00000 +#define FSCMI_MHU_IRQ_NUM (22U + 32U) +#define FSCMI_SHR_MEM_ADDR 0x32a11400 +#define FSCMI_MEM_TX_OFSET 0x1400 +#define FSCMI_MEM_RX_OFSET 0x1000 +#define FSCMI_SHR_MEM_SIZE 0x400 + +#define FSCMI_MSG_SIZE 128 +#define FSCMI_MAX_STR_SIZE 16 +#define FSCMI_MAX_NUM_SENSOR 16 +#define FSCMI_MAX_PROTOCOLS_IMP 16 +#define FSCMI_MAX_PERF_DOMAINS 3 +#define FSCMI_MAX_OPPS 4 + +/* UART */ +#define FUART_NUM 4U +#define FUART_REG_LENGTH 0x18000U + +#define FUART0_ID 0U +#define FUART0_IRQ_NUM (85 + 30) +#define FUART0_BASE_ADDR 0x2800c000U +#define FUART0_CLK_FREQ_HZ 100000000U + +#define FUART1_ID 1U +#define FUART1_IRQ_NUM (86 + 30) +#define FUART1_BASE_ADDR 0x2800d000U +#define FUART1_CLK_FREQ_HZ 100000000U + +#define FUART2_ID 2U +#define FUART2_IRQ_NUM (87 + 30) +#define FUART2_BASE_ADDR 0x2800e000U +#define FUART2_CLK_FREQ_HZ 100000000U + +#define FUART3_BASE_ADDR 0x2800f000U +#define FUART3_ID 3U +#define FUART3_IRQ_NUM (88 + 30) +#define FUART3_CLK_FREQ_HZ 100000000U + +#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR +#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000U + + + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_NR_IRQS 270U +#define ARM_GIC_IRQ_START 0U +#define FGIC_NUM 1U + +#define ARM_GIC_IPI_COUNT 16U /* MPCore IPI count */ +#define SGI_INT_MAX 16U +#define SPI_START_INT_NUM 32U /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16U /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */ + +#define GICV3_BASE_ADDR 0x30800000U +#define GICV3_ITS_BASE_ADDR (GICV3_BASE_ADDR+ 0x20000U) +#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) +#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U) +#define GICV3_RD_OFFSET (2U << 16) +#define GICV3_RD_SIZE (8U << 16) + +/* GPIO */ +#define FGPIO0_BASE_ADDR 0x28034000U +#define FGPIO1_BASE_ADDR 0x28035000U +#define FGPIO2_BASE_ADDR 0x28036000U +#define FGPIO3_BASE_ADDR 0x28037000U +#define FGPIO4_BASE_ADDR 0x28038000U +#define FGPIO5_BASE_ADDR 0x28039000U + +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_2 2 +#define FGPIO_CTRL_3 3 +#define FGPIO_CTRL_4 4 +#define FGPIO_CTRL_5 5 +#define FGPIO_CTRL_NUM 6U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_NUM 1U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_8 8U +#define FGPIO_PIN_9 9U +#define FGPIO_PIN_10 10U +#define FGPIO_PIN_11 11U +#define FGPIO_PIN_12 12U +#define FGPIO_PIN_13 13U +#define FGPIO_PIN_14 14U +#define FGPIO_PIN_15 15U +#define FGPIO_PIN_NUM 16U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((FGPIO_PORT_A) * FGPIO_PIN_NUM) + (pin)) + +/* SPI */ +#define FSPI0_BASE_ADDR 0x2803A000U +#define FSPI1_BASE_ADDR 0x2803B000U +#define FSPI2_BASE_ADDR 0x2803C000U +#define FSPI3_BASE_ADDR 0x2803D000U +#define FSPI0_ID 0U +#define FSPI1_ID 1U +#define FSPI2_ID 2U +#define FSPI3_ID 3U + +#define FSPI0_IRQ_NUM 191U +#define FSPI1_IRQ_NUM 192U +#define FSPI2_IRQ_NUM 193U +#define FSPI3_IRQ_NUM 194U + +#define FSPI_CLK_FREQ_HZ 50000000U +#define FSPI_NUM 4U + +#define FSPI_DMA_CAPACITY BIT(0) +#define FSPIM0_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM1_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM2_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM3_DMA_CAPACITY FSPI_DMA_CAPACITY + +/* XMAC */ +#define FXMAC_NUM 4U + +#define FXMAC0_ID 0U +#define FXMAC1_ID 1U +#define FXMAC2_ID 2U +#define FXMAC3_ID 3U + +#define FXMAC0_BASE_ADDR 0x3200C000U +#define FXMAC1_BASE_ADDR 0x3200E000U +#define FXMAC2_BASE_ADDR 0x32010000U +#define FXMAC3_BASE_ADDR 0x32012000U + +#define FXMAC0_MODE_SEL_BASE_ADDR 0x3200DC00U +#define FXMAC0_LOOPBACK_SEL_BASE_ADDR 0x3200DC04U +#define FXMAC1_MODE_SEL_BASE_ADDR 0x3200FC00U +#define FXMAC1_LOOPBACK_SEL_BASE_ADDR 0x3200FC04U +#define FXMAC2_MODE_SEL_BASE_ADDR 0x32011C00U +#define FXMAC2_LOOPBACK_SEL_BASE_ADDR 0x32011C04U +#define FXMAC3_MODE_SEL_BASE_ADDR 0x32013C00U +#define FXMAC3_LOOPBACK_SEL_BASE_ADDR 0x32013C04U + +#define FXMAC0_PCLK 50000000U +#define FXMAC1_PCLK 50000000U +#define FXMAC2_PCLK 50000000U +#define FXMAC3_PCLK 50000000U +#define FXMAC0_HOTPLUG_IRQ_NUM (53U + 30U) +#define FXMAC1_HOTPLUG_IRQ_NUM (54U + 30U) +#define FXMAC2_HOTPLUG_IRQ_NUM (55U + 30U) +#define FXMAC3_HOTPLUG_IRQ_NUM (56U + 30U) + +#define FXMAC_QUEUE_MAX_NUM 16U + +#define FXMAC0_QUEUE0_IRQ_NUM (57U + 30U) +#define FXMAC0_QUEUE1_IRQ_NUM (58U + 30U) +#define FXMAC0_QUEUE2_IRQ_NUM (59U + 30U) +#define FXMAC0_QUEUE3_IRQ_NUM (60U + 30U) +#define FXMAC0_QUEUE4_IRQ_NUM (30U + 30U) +#define FXMAC0_QUEUE5_IRQ_NUM (31U + 30U) +#define FXMAC0_QUEUE6_IRQ_NUM (32U + 30U) +#define FXMAC0_QUEUE7_IRQ_NUM (33U + 30U) + +#define FXMAC1_QUEUE0_IRQ_NUM (61U + 30U) +#define FXMAC1_QUEUE1_IRQ_NUM (62U + 30U) +#define FXMAC1_QUEUE2_IRQ_NUM (63U + 30U) +#define FXMAC1_QUEUE3_IRQ_NUM (64U + 30U) + +#define FXMAC2_QUEUE0_IRQ_NUM (66U + 30U) +#define FXMAC2_QUEUE1_IRQ_NUM (67U + 30U) +#define FXMAC2_QUEUE2_IRQ_NUM (68U + 30U) +#define FXMAC2_QUEUE3_IRQ_NUM (69U + 30U) + +#define FXMAC3_QUEUE0_IRQ_NUM (70U + 30U) +#define FXMAC3_QUEUE1_IRQ_NUM (71U + 30U) +#define FXMAC3_QUEUE2_IRQ_NUM (72U + 30U) +#define FXMAC3_QUEUE3_IRQ_NUM (73U + 30U) + +#define FXMAC_PHY_MAX_NUM 32U + +#define FXMAC_CLK_TYPE_0 + +/* IOPAD */ +#define FIOPAD0_ID 0 +#define FIOPAD_NUM 1 + +/* QSPI */ +#define FQSPI0_ID 0 +#define FQSPI_NUM 1 + +/* FQSPI cs 0_3, chip number */ + +#define FQSPI_CS_0 0 +#define FQSPI_CS_1 1 +#define FQSPI_CS_2 2 +#define FQSPI_CS_3 3 +#define FQSPI_CS_NUM 4 +#define FQSPI_BASE_ADDR 0x028008000U + +#define FQSPI_MEM_START_ADDR 0x0U +#define FQSPI_MEM_END_ADDR 0x0FFFFFFFU /* 256MB */ +#define FQSPI_MEM_START_ADDR_64 0x100000000U +#define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */ + +/* TIMER and TACHO */ +#define FTIMER_NUM 38U +#define FTIMER_CLK_FREQ_HZ 50000000ULL /* 50MHz */ +#define FTIMER_TICK_PERIOD_NS 20U /* 20ns */ +#define FTIMER_TACHO_IRQ_NUM(n) (226U + (n)) +#define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n)) + + +#define FTACHO0_ID 0 +#define FTACHO1_ID 1 +#define FTACHO2_ID 2 +#define FTACHO3_ID 3 +#define FTACHO4_ID 4 +#define FTACHO5_ID 5 +#define FTACHO6_ID 6 +#define FTACHO7_ID 7 +#define FTACHO8_ID 8 +#define FTACHO9_ID 9 +#define FTACHO10_ID 10 +#define FTACHO11_ID 11 +#define FTACHO12_ID 12 +#define FTACHO13_ID 13 +#define FTACHO14_ID 14 +#define FTACHO15_ID 15 +#define FTACHO_NUM 16 + +/* GDMA */ +#define FGDMA0_ID 0U +#define FGDMA0_BASE_ADDR 0x32B34000U +#define FGDMA0_CHANNEL0_IRQ_NUM 266U +#define FGDMA_NUM_OF_CHAN 16 +#define FGDMA_INSTANCE_NUM 1U +#define FGDMA0_CAPACITY (1U<<0) + +/* WDT */ + +#define FWDT0_ID 0 +#define FWDT1_ID 1 +#define FWDT_NUM 2 + +#define FWDT0_REFRESH_BASE_ADDR 0x28040000U +#define FWDT1_REFRESH_BASE_ADDR 0x28042000U + +#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) + +#define FWDT0_IRQ_NUM 196U +#define FWDT1_IRQ_NUM 197U + +#define FWDT_CLK_FREQ_HZ 48000000U /* 48MHz */ + +/*MIO*/ +#define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n)) +#define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000 +#define FMIO_IRQ_NUM(n) (124+n) +#define FMIO_CLK_FREQ_HZ 50000000 /* 50MHz */ + + +#define FMIO0_ID 0 +#define FMIO1_ID 1 +#define FMIO2_ID 2 +#define FMIO3_ID 3 +#define FMIO4_ID 4 +#define FMIO5_ID 5 +#define FMIO6_ID 6 +#define FMIO7_ID 7 +#define FMIO8_ID 8 +#define FMIO9_ID 9 +#define FMIO10_ID 10 +#define FMIO11_ID 11 +#define FMIO12_ID 12 +#define FMIO13_ID 13 +#define FMIO14_ID 14 +#define FMIO15_ID 15 +#define FMIO_NUM 16 + +/*I2C0 -> PMBUS0 +* I2C1 -> PMBUS1 +* I2C2 -> SMBUS0 +*/ + + +#define FI2C0_ID 0 +#define FI2C1_ID 1 +#define FI2C2_ID 2 +#define FI2C_NUM 3 + +#define FI2C0_BASE_ADDR 0x28011000 +#define FI2C1_BASE_ADDR 0x28012000 +#define FI2C2_BASE_ADDR 0x28013000 + +#define FI2C0_IRQ_NUM 121 +#define FI2C1_IRQ_NUM 122 +#define FI2C2_IRQ_NUM 123 + +#define FI2C_CLK_FREQ_HZ 50000000 /* 50MHz */ + +/* SDIF */ +#define FSDIF0_ID 0 +#define FSDIF1_ID 1 +#define FSDIF_NUM 2 + + +#define FSDIF0_BASE_ADDR 0x28000000U +#define FSDIF1_BASE_ADDR 0x28001000U + +#define FSDIF0_IRQ_NUM 104U +#define FSDIF1_IRQ_NUM 105U + +#define FSDIF_CLK_FREQ_HZ (1200000000UL) /* 1.2GHz */ + +/* NAND */ +#define FNAND_NUM 1U +#define FNAND_INSTANCE0 0U +#define FNAND_BASE_ADDR 0x28002000U +#define FNAND_IRQ_NUM (106U) +#define FNAND_CONNECT_MAX_NUM 1U + +#define FIOPAD_BASE_ADDR 0x32B30000U + +/* DDMA */ +#define FDDMA0_ID 0U +#define FDDMA0_BASE_ADDR 0x28003000U +#define FDDMA0_IRQ_NUM 107U +#define FDDMA0_CAPACITY (1U<<1) + +#define FDDMA1_ID 1U +#define FDDMA1_BASE_ADDR 0x28004000U +#define FDDMA1_IRQ_NUM 108U +#define FDDMA1_CAPACITY (1U<<1) + +#define FDDMA2_I2S_ID 2U +#define FDDMA2_BASE_ADDR 0x28005000U +#define FDDMA2_IRQ_NUM 109U +#define FDDMA2_CAPACITY (1U<<0) + +#define FDDMA3_DP0_I2S_ID 3U +#define FDDMA3_BASE_ADDR 0x32008000U +#define FDDMA3_IRQ_NUM 79U +#define FDDMA3_CAPACITY (1U<<0) + +#define FDDMA4_DP1_I2S_ID 4U +#define FDDMA4_BASE_ADDR 0x3200A000U +#define FDDMA4_IRQ_NUM 80U +#define FDDMA4_CAPACITY (1U<<0) + +#define FDDMA_INSTANCE_NUM 5U + +#define FDDMA0_CAN0_TX_SLAVE_ID 0U /* can0 tx slave-id */ +#define FDDMA0_CAN1_TX_SLAVE_ID 1U /* can1 tx slave-id */ +#define FDDMA0_UART0_TX_SLAVE_ID 2U /* uart0 tx slave-id */ +#define FDDMA0_UART1_TX_SLAVE_ID 3U /* uart1 tx slave-id */ +#define FDDMA0_UART2_TX_SLAVE_ID 4U /* uart2 tx slave-id */ +#define FDDMA0_UART3_TX_SLAVE_ID 5U /* uart3 tx slave-id */ + +#define FDDMA0_SPIM0_TX_SLAVE_ID 6U /* spi0 tx slave-id */ +#define FDDMA0_SPIM1_TX_SLAVE_ID 7U /* spi1 tx slave-id */ +#define FDDMA0_SPIM2_TX_SLAVE_ID 8U /* spi2 tx slave-id */ +#define FDDMA0_SPIM3_TX_SLAVE_ID 9U /* spi3 tx slave-id */ + +#define FDDMA0_CAN0_RX_SLAVE_ID 13U /* can0 rx slave-id */ +#define FDDMA0_CAN1_RX_SLAVE_ID 14U /* can1 rx slave-id */ +#define FDDMA0_UART0_RX_SLAVE_ID 15U /* uart0 rx slave-id */ +#define FDDMA0_UART1_RX_SLAVE_ID 16U /* uart1 rx slave-id */ +#define FDDMA0_UART2_RX_SLAVE_ID 17U /* uart2 rx slave-id */ +#define FDDMA0_UART3_RX_SLAVE_ID 18U /* uart3 rx slave-id */ + +#define FDDMA0_SPIM0_RX_SLAVE_ID 19U /* spi0 rx slave-id */ +#define FDDMA0_SPIM1_RX_SLAVE_ID 20U /* spi1 rx slave-id */ +#define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */ +#define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */ + +/* FDDMA1_ID */ +#define FDDMA1_MIO0_TX_SLAVE_ID 0U /* mio0 rx slave-id */ +#define FDDMA1_MIO1_TX_SLAVE_ID 1U /* mio1 rx slave-id */ +#define FDDMA1_MIO2_TX_SLAVE_ID 2U /* mio2 rx slave-id */ +#define FDDMA1_MIO3_TX_SLAVE_ID 3U /* mio3 rx slave-id */ +#define FDDMA1_MIO4_TX_SLAVE_ID 4U /* mio4 rx slave-id */ +#define FDDMA1_MIO5_TX_SLAVE_ID 5U /* mio5 rx slave-id */ +#define FDDMA1_MIO6_TX_SLAVE_ID 6U /* mio6 rx slave-id */ +#define FDDMA1_MIO7_TX_SLAVE_ID 7U /* mio7 rx slave-id */ +#define FDDMA1_MIO8_TX_SLAVE_ID 8U /* mio8 rx slave-id */ +#define FDDMA1_MIO9_TX_SLAVE_ID 9U /* mio9 rx slave-id */ +#define FDDMA1_MIO10_TX_SLAVE_ID 10U /* mio10 rx slave-id */ +#define FDDMA1_MIO11_TX_SLAVE_ID 11U /* mio11 rx slave-id */ +#define FDDMA1_MIO12_TX_SLAVE_ID 12U /* mio12 rx slave-id */ +#define FDDMA1_MIO13_TX_SLAVE_ID 13U /* mio13 rx slave-id */ +#define FDDMA1_MIO14_TX_SLAVE_ID 14U /* mio14 rx slave-id */ +#define FDDMA1_MIO15_TX_SLAVE_ID 15U /* mio15 rx slave-id */ + +#define FDDMA1_MIO0_RX_SLAVE_ID 16U /* mio0 tx slave-id */ +#define FDDMA1_MIO1_RX_SLAVE_ID 17U /* mio1 tx slave-id */ +#define FDDMA1_MIO2_RX_SLAVE_ID 18U /* mio2 tx slave-id */ +#define FDDMA1_MIO3_RX_SLAVE_ID 19U /* mio3 tx slave-id */ +#define FDDMA1_MIO4_RX_SLAVE_ID 20U /* mio4 tx slave-id */ +#define FDDMA1_MIO5_RX_SLAVE_ID 21U /* mio5 tx slave-id */ +#define FDDMA1_MIO6_RX_SLAVE_ID 22U /* mio6 tx slave-id */ +#define FDDMA1_MIO7_RX_SLAVE_ID 23U /* mio7 tx slave-id */ +#define FDDMA1_MIO8_RX_SLAVE_ID 24U /* mio8 tx slave-id */ +#define FDDMA1_MIO9_RX_SLAVE_ID 25U /* mio9 tx slave-id */ +#define FDDMA1_MIO10_RX_SLAVE_ID 26U /* mio10 tx slave-id */ +#define FDDMA1_MIO11_RX_SLAVE_ID 27U /* mio11 tx slave-id */ +#define FDDMA1_MIO12_RX_SLAVE_ID 28U /* mio12 tx slave-id */ +#define FDDMA1_MIO13_RX_SLAVE_ID 29U /* mio13 tx slave-id */ +#define FDDMA1_MIO14_RX_SLAVE_ID 30U /* mio14 tx slave-id */ +#define FDDMA1_MIO15_RX_SLAVE_ID 31U /* mio15 tx slave-id */ + +#define FDDMA_MIN_SLAVE_ID 0U +#define FDDMA_MAX_SLAVE_ID 31U + +/* Semaphore */ +#define FSEMA0_ID 0U +#define FSEMA0_BASE_ADDR 0x32B36000U +#define FSEMA_INSTANCE_NUM 1U + +/* LSD Config */ +#define FLSD_CONFIG_BASE 0x2807E000U +#define FLSD_NAND_MMCSD_HADDR 0xC0U +#define FLSD_CK_STOP_CONFIG0_HADDR 0x10U +#define FLSD_PWM_HADDR 0x20 /* bit0-bit7 corresponds to pwm0-pwm7 */ + +/* USB3 */ +#define FUSB3_ID_0 0U +#define FUSB3_ID_1 1U +#define FUSB3_NUM 2U +#define FUSB3_XHCI_OFFSET 0x8000U +#define FUSB3_0_BASE_ADDR 0x31A00000U +#define FUSB3_1_BASE_ADDR 0x31A20000U +#define FUSB3_0_IRQ_NUM 48U +#define FUSB3_1_IRQ_NUM 49U + +/* DcDp */ + + +#define FDCDP_ID0 0 +#define FDCDP_ID1 1 + +#define FDCDP_INSTANCE_NUM 2 + +#define FDC_CTRL_BASE_OFFSET 0x32000000U + +#define FDC0_CHANNEL_BASE_OFFSET 0x32001000U +#define FDC1_CHANNEL_BASE_OFFSET (FDC0_CHANNEL_BASE_OFFSET + 0x1000U) + +#define FDP0_CHANNEL_BASE_OFFSET 0x32004000U +#define FDP1_CHANNEL_BASE_OFFSET (FDP0_CHANNEL_BASE_OFFSET + 0x1000U) + +#define FDP0_PHY_BASE_OFFSET 0x32300000U +#define FDP1_PHY_BASE_OFFSET (FDP0_PHY_BASE_OFFSET + 0x100000U) + +#define FDCDP_IRQ_NUM 76 + +/* generic timer */ +/* non-secure physical timer int id */ +#define GENERIC_TIMER_NS_IRQ_NUM 30U + +/* virtual timer int id */ +#define GENERIC_VTIMER_IRQ_NUM 27U + + +#define GENERIC_TIMER_ID0 0 /* non-secure physical timer */ +#define GENERIC_TIMER_ID1 1 /* virtual timer */ +#define GENERIC_TIMER_NUM 2 + + +/* PMU */ +#define FPMU_IRQ_NUM 23 + +/* USB2 OTG */ +#if !defined(__ASSEMBLER__) + +enum +{ + FUSB2_ID_VHUB_0 = 0, + FUSB2_ID_1, + FUSB2_ID_2, + FUSB2_ID_VHUB_1, + FUSB2_ID_VHUB_2, + + FUSB2_INSTANCE_NUM +}; + +#endif + +#define FUSB2_0_VHUB_BASE_ADDR 0x31800000U +#define FUSB2_1_VHUB_BASE_ADDR 0x31880000U +#define FUSB2_2_VHUB_BASE_ADDR 0x31900000U + +#define FUSB2_VHUB_CFG_BASE_ADDR 0x319C0000U +#define FUSB2_DEV_1_CFG_BASE_ADDR 0x31990000U +#define FUSB2_DEV_2_CFG_BASE_ADDR 0x319A0000U +#define FUSB2_DEV_3_CFG_BASE_ADDR 0x319B0000U + +#define FUSB2_0_VHUB_IRQ_NUM 64U +#define FUSB2_1_VHUB_IRQ_NUM 65U +#define FUSB2_2_VHUB_IRQ_NUM 66U + +#define FUSB2_0_VHUB_WAKEUP_IRQ_NUM 67U +#define FUSB2_1_VHUB_WAKEUP_IRQ_NUM 68U +#define FUSB2_2_VHUB_WAKEUP_IRQ_NUM 69U + +#define FUSB2_1_BASE_ADDR 0x32800000U +#define FUSB2_2_BASE_ADDR 0x32840000U +#define FUSB2_1_UIB_BASE_ADDR 0x32880000U +#define FUSB2_2_UIB_BASE_ADDR 0x328C0000U +#define FUSB2_MMIO_SIZE 0x00200000U /* 2MB */ + +#define FUSB2_1_IRQ_NUM 46U +#define FUSB2_2_IRQ_NUM 47U + +#define FUSB2_1_WAKEUP_IRQ_NUM 50U +#define FUSB2_2_WAKEUP_IRQ_NUM 51U + + +/*****************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/e2000q/fparameters.h b/bsps/aarch64/phytium/include/soc/e2000q/fparameters.h new file mode 100644 index 0000000000..2b35fffced --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/e2000q/fparameters.h @@ -0,0 +1,370 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters.h + * Date: 2022-02-11 13:33:28 + * LastEditTime: 2022-02-17 18:00:50 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef E2000Q_FPARAMETERS_H +#define E2000Q_FPARAMETERS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************** Include Files *********************************/ +#include "fparameters_comm.h" + +/************************** Constant Definitions *****************************/ +#define SOC_TARGET_E2000Q + +#define CORE0_AFF 0x000U +#define CORE1_AFF 0x100U +#define CORE2_AFF 0x200U +#define CORE3_AFF 0x201U +#define FCORE_NUM 4 + +/* PWM */ +#define FPWM0_ID 0 +#define FPWM1_ID 1 +#define FPWM2_ID 2 +#define FPWM3_ID 3 +#define FPWM_NUM 4 + +#define FPWM_CHANNEL_0 0 +#define FPWM_CHANNEL_1 1 +#define FPWM_CHANNEL_NUM 2 + +#define FPWM_BASE_ADDR 0x2804A000U + +#define FPWM_CLK_FREQ_HZ 50000000U /* 50MHz */ + +#define FPWM0_IRQ_NUM 205U +#define FPWM1_IRQ_NUM 206U +#define FPWM2_IRQ_NUM 207U +#define FPWM3_IRQ_NUM 208U +#define FPWM4_IRQ_NUM 209U +#define FPWM5_IRQ_NUM 210U +#define FPWM6_IRQ_NUM 211U +#define FPWM7_IRQ_NUM 212U + +#define FPWM_CYCLE_PROCESSING(reg_val) ((reg_val) - 0x1) + +/* I2S */ + +#define FI2S0_ID 0U +#define FI2S1_ID 1U +#define FI2S2_ID 2U +#define FI2S_NUM 3U + +#define FI2S0_BASE_ADDR 0x28009000 +#define FI2S0_IRQ_NUM 112 + +#define FI2S1_BASE_ADDR 0x32009000 /*i2s for dp0*/ +#define FI2S1_IRQ_NUM 77 + +#define FI2S2_BASE_ADDR 0x3200B000 /*i2s for dp1*/ +#define FI2S2_IRQ_NUM 78 + +#define FI2S_CLK_FREQ_HZ 600000000 /* 600MHz */ + +/* sata controller */ +#define FSATA0_BASE_ADDR 0x31A40000U +#define FSATA1_BASE_ADDR 0x32014000U + +#define FSATA0_IRQ_NUM 74 +#define FSATA1_IRQ_NUM 75 + +#define FSATA0_ID 0 +#define FSATA1_ID 1 +#define FSATA_NUM 2 + +/* CANFD */ +#define FCAN_CLK_FREQ_HZ 200000000U + +#define FCAN0_BASE_ADDR 0x2800A000U +#define FCAN1_BASE_ADDR 0x2800B000U + +#define FCAN0_IRQ_NUM 113U +#define FCAN1_IRQ_NUM 114U + +#define FCAN0_ID 0 +#define FCAN1_ID 1 +#define FCAN_NUM 2 + +/* can capacity */ +#define FCAN_FD_CAPACITY BIT(0) /* Whether canfd is supported */ +#define FCAN_CAPACITY FCAN_FD_CAPACITY + +/*****************************************************************************/ +/* register offset of iopad function / pull / driver strength */ +#define FIOPAD_AN59_REG0_OFFSET 0x0000U +#define FIOPAD_AW47_REG0_OFFSET 0x0004U +#define FIOPAD_AR55_REG0_OFFSET 0x0020U +#define FIOPAD_AJ55_REG0_OFFSET 0x0024U +#define FIOPAD_AL55_REG0_OFFSET 0x0028U +#define FIOPAD_AL53_REG0_OFFSET 0x002CU +#define FIOPAD_AN51_REG0_OFFSET 0x0030U +#define FIOPAD_AR51_REG0_OFFSET 0x0034U +#define FIOPAD_BA57_REG0_OFFSET 0x0038U +#define FIOPAD_BA59_REG0_OFFSET 0x003CU +#define FIOPAD_AW57_REG0_OFFSET 0x0040U +#define FIOPAD_AW59_REG0_OFFSET 0x0044U +#define FIOPAD_AU55_REG0_OFFSET 0x0048U +#define FIOPAD_AN57_REG0_OFFSET 0x004CU +#define FIOPAD_AL59_REG0_OFFSET 0x0050U +#define FIOPAD_AJ59_REG0_OFFSET 0x0054U +#define FIOPAD_AJ57_REG0_OFFSET 0x0058U +#define FIOPAD_AG59_REG0_OFFSET 0x005CU +#define FIOPAD_AG57_REG0_OFFSET 0x0060U +#define FIOPAD_AE59_REG0_OFFSET 0x0064U +#define FIOPAD_AC59_REG0_OFFSET 0x0068U +#define FIOPAD_AC57_REG0_OFFSET 0x006CU +#define FIOPAD_AR49_REG0_OFFSET 0x0070U +#define FIOPAD_BA55_REG0_OFFSET 0x0074U +#define FIOPAD_BA53_REG0_OFFSET 0x0078U +#define FIOPAD_AR59_REG0_OFFSET 0x007CU +#define FIOPAD_AU59_REG0_OFFSET 0x0080U +#define FIOPAD_AR57_REG0_OFFSET 0x0084U +#define FIOPAD_BA49_REG0_OFFSET 0x0088U +#define FIOPAD_AW55_REG0_OFFSET 0x008CU +#define FIOPAD_A35_REG0_OFFSET 0x0090U +#define FIOPAD_R57_REG0_OFFSET 0x0094U +#define FIOPAD_R59_REG0_OFFSET 0x0098U +#define FIOPAD_U59_REG0_OFFSET 0x009CU +#define FIOPAD_W59_REG0_OFFSET 0x00A0U +#define FIOPAD_U57_REG0_OFFSET 0x00A4U +#define FIOPAD_AA57_REG0_OFFSET 0x00A8U +#define FIOPAD_AA59_REG0_OFFSET 0x00ACU +#define FIOPAD_AW51_REG0_OFFSET 0x00B0U +#define FIOPAD_AU51_REG0_OFFSET 0x00B4U +#define FIOPAD_A39_REG0_OFFSET 0x00B8U +#define FIOPAD_C39_REG0_OFFSET 0x00BCU +#define FIOPAD_C37_REG0_OFFSET 0x00C0U +#define FIOPAD_A37_REG0_OFFSET 0x00C4U +#define FIOPAD_A41_REG0_OFFSET 0x00C8U +#define FIOPAD_A43_REG0_OFFSET 0x00CCU +#define FIOPAD_A45_REG0_OFFSET 0x00D0U +#define FIOPAD_C45_REG0_OFFSET 0x00D4U +#define FIOPAD_A47_REG0_OFFSET 0x00D8U +#define FIOPAD_A49_REG0_OFFSET 0x00DCU +#define FIOPAD_C49_REG0_OFFSET 0x00E0U +#define FIOPAD_A51_REG0_OFFSET 0x00E4U +#define FIOPAD_A33_REG0_OFFSET 0x00E8U +#define FIOPAD_C33_REG0_OFFSET 0x00ECU +#define FIOPAD_C31_REG0_OFFSET 0x00F0U +#define FIOPAD_A31_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ53_REG0_OFFSET 0x00F8U +#define FIOPAD_AL49_REG0_OFFSET 0x00FCU +#define FIOPAD_AL47_REG0_OFFSET 0x0100U +#define FIOPAD_AN49_REG0_OFFSET 0x0104U +#define FIOPAD_AG51_REG0_OFFSET 0x0108U +#define FIOPAD_AJ51_REG0_OFFSET 0x010CU +#define FIOPAD_AG49_REG0_OFFSET 0x0110U +#define FIOPAD_AE55_REG0_OFFSET 0x0114U +#define FIOPAD_AE53_REG0_OFFSET 0x0118U +#define FIOPAD_AG55_REG0_OFFSET 0x011CU +#define FIOPAD_AJ49_REG0_OFFSET 0x0120U +#define FIOPAD_AC55_REG0_OFFSET 0x0124U +#define FIOPAD_AC53_REG0_OFFSET 0x0128U +#define FIOPAD_AE51_REG0_OFFSET 0x012CU +#define FIOPAD_W51_REG0_OFFSET 0x0130U +#define FIOPAD_W55_REG0_OFFSET 0x0134U +#define FIOPAD_W53_REG0_OFFSET 0x0138U +#define FIOPAD_U55_REG0_OFFSET 0x013CU +#define FIOPAD_U53_REG0_OFFSET 0x0140U +#define FIOPAD_AE49_REG0_OFFSET 0x0144U +#define FIOPAD_AC49_REG0_OFFSET 0x0148U +#define FIOPAD_AE47_REG0_OFFSET 0x014CU +#define FIOPAD_AA47_REG0_OFFSET 0x0150U +#define FIOPAD_AA49_REG0_OFFSET 0x0154U +#define FIOPAD_W49_REG0_OFFSET 0x0158U +#define FIOPAD_AA51_REG0_OFFSET 0x015CU +#define FIOPAD_U49_REG0_OFFSET 0x0160U +#define FIOPAD_G59_REG0_OFFSET 0x0164U +#define FIOPAD_J59_REG0_OFFSET 0x0168U +#define FIOPAD_L57_REG0_OFFSET 0x016CU +#define FIOPAD_C59_REG0_OFFSET 0x0170U +#define FIOPAD_E59_REG0_OFFSET 0x0174U +#define FIOPAD_J57_REG0_OFFSET 0x0178U +#define FIOPAD_L59_REG0_OFFSET 0x017CU +#define FIOPAD_N59_REG0_OFFSET 0x0180U +#define FIOPAD_C57_REG0_OFFSET 0x0184U +#define FIOPAD_E57_REG0_OFFSET 0x0188U +#define FIOPAD_E31_REG0_OFFSET 0x018CU +#define FIOPAD_G31_REG0_OFFSET 0x0190U +#define FIOPAD_N41_REG0_OFFSET 0x0194U +#define FIOPAD_N39_REG0_OFFSET 0x0198U +#define FIOPAD_J33_REG0_OFFSET 0x019CU +#define FIOPAD_N33_REG0_OFFSET 0x01A0U +#define FIOPAD_L33_REG0_OFFSET 0x01A4U +#define FIOPAD_N45_REG0_OFFSET 0x01A8U +#define FIOPAD_N43_REG0_OFFSET 0x01ACU +#define FIOPAD_L31_REG0_OFFSET 0x01B0U +#define FIOPAD_J31_REG0_OFFSET 0x01B4U +#define FIOPAD_J29_REG0_OFFSET 0x01B8U +#define FIOPAD_E29_REG0_OFFSET 0x01BCU +#define FIOPAD_G29_REG0_OFFSET 0x01C0U +#define FIOPAD_N27_REG0_OFFSET 0x01C4U +#define FIOPAD_L29_REG0_OFFSET 0x01C8U +#define FIOPAD_J37_REG0_OFFSET 0x01CCU +#define FIOPAD_J39_REG0_OFFSET 0x01D0U +#define FIOPAD_G41_REG0_OFFSET 0x01D4U +#define FIOPAD_E43_REG0_OFFSET 0x01D8U +#define FIOPAD_L43_REG0_OFFSET 0x01DCU +#define FIOPAD_C43_REG0_OFFSET 0x01E0U +#define FIOPAD_E41_REG0_OFFSET 0x01E4U +#define FIOPAD_L45_REG0_OFFSET 0x01E8U +#define FIOPAD_J43_REG0_OFFSET 0x01ECU +#define FIOPAD_J41_REG0_OFFSET 0x01F0U +#define FIOPAD_L39_REG0_OFFSET 0x01F4U +#define FIOPAD_E37_REG0_OFFSET 0x01F8U +#define FIOPAD_E35_REG0_OFFSET 0x01FCU +#define FIOPAD_G35_REG0_OFFSET 0x0200U +#define FIOPAD_J35_REG0_OFFSET 0x0204U +#define FIOPAD_L37_REG0_OFFSET 0x0208U +#define FIOPAD_N35_REG0_OFFSET 0x020CU +#define FIOPAD_R51_REG0_OFFSET 0x0210U +#define FIOPAD_R49_REG0_OFFSET 0x0214U +#define FIOPAD_N51_REG0_OFFSET 0x0218U +#define FIOPAD_N55_REG0_OFFSET 0x021CU +#define FIOPAD_L55_REG0_OFFSET 0x0220U +#define FIOPAD_J55_REG0_OFFSET 0x0224U +#define FIOPAD_J45_REG0_OFFSET 0x0228U +#define FIOPAD_E47_REG0_OFFSET 0x022CU +#define FIOPAD_G47_REG0_OFFSET 0x0230U +#define FIOPAD_J47_REG0_OFFSET 0x0234U +#define FIOPAD_J49_REG0_OFFSET 0x0238U +#define FIOPAD_N49_REG0_OFFSET 0x023CU +#define FIOPAD_L51_REG0_OFFSET 0x0240U +#define FIOPAD_L49_REG0_OFFSET 0x0244U +#define FIOPAD_N53_REG0_OFFSET 0x0248U +#define FIOPAD_J53_REG0_OFFSET 0x024CU + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN59_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J53_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ55_REG1_OFFSET 0x1024U +#define FIOPAD_AL55_REG1_OFFSET 0x1028U +#define FIOPAD_AL53_REG1_OFFSET 0x102CU +#define FIOPAD_AN51_REG1_OFFSET 0x1030U +#define FIOPAD_AR51_REG1_OFFSET 0x1034U +#define FIOPAD_AJ57_REG1_OFFSET 0x1058U +#define FIOPAD_AG59_REG1_OFFSET 0x105CU +#define FIOPAD_AG57_REG1_OFFSET 0x1060U +#define FIOPAD_AE59_REG1_OFFSET 0x1064U +#define FIOPAD_BA55_REG1_OFFSET 0x1074U +#define FIOPAD_BA53_REG1_OFFSET 0x1078U +#define FIOPAD_AR59_REG1_OFFSET 0x107CU +#define FIOPAD_AU59_REG1_OFFSET 0x1080U +#define FIOPAD_A45_REG1_OFFSET 0x10D0U +#define FIOPAD_C45_REG1_OFFSET 0x10D4U +#define FIOPAD_A47_REG1_OFFSET 0x10D8U +#define FIOPAD_A49_REG1_OFFSET 0x10DCU +#define FIOPAD_C49_REG1_OFFSET 0x10E0U +#define FIOPAD_A51_REG1_OFFSET 0x10E4U +#define FIOPAD_A33_REG1_OFFSET 0x10E8U +#define FIOPAD_C33_REG1_OFFSET 0x10ECU +#define FIOPAD_C31_REG1_OFFSET 0x10F0U +#define FIOPAD_A31_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ53_REG1_OFFSET 0x10F8U +#define FIOPAD_AL49_REG1_OFFSET 0x10FCU +#define FIOPAD_AL47_REG1_OFFSET 0x1100U +#define FIOPAD_AN49_REG1_OFFSET 0x1104U +#define FIOPAD_AG51_REG1_OFFSET 0x1108U +#define FIOPAD_AJ51_REG1_OFFSET 0x110CU +#define FIOPAD_AG49_REG1_OFFSET 0x1110U +#define FIOPAD_AE55_REG1_OFFSET 0x1114U +#define FIOPAD_AE53_REG1_OFFSET 0x1118U +#define FIOPAD_AG55_REG1_OFFSET 0x111CU +#define FIOPAD_AJ49_REG1_OFFSET 0x1120U +#define FIOPAD_AC55_REG1_OFFSET 0x1124U +#define FIOPAD_AC53_REG1_OFFSET 0x1128U +#define FIOPAD_AE51_REG1_OFFSET 0x112CU +#define FIOPAD_W51_REG1_OFFSET 0x1130U +#define FIOPAD_W53_REG1_OFFSET 0x1138U +#define FIOPAD_U55_REG1_OFFSET 0x113CU +#define FIOPAD_U53_REG1_OFFSET 0x1140U +#define FIOPAD_AE49_REG1_OFFSET 0x1144U +#define FIOPAD_AC49_REG1_OFFSET 0x1148U +#define FIOPAD_AE47_REG1_OFFSET 0x114CU +#define FIOPAD_AA47_REG1_OFFSET 0x1150U +#define FIOPAD_AA49_REG1_OFFSET 0x1154U +#define FIOPAD_W49_REG1_OFFSET 0x1158U +#define FIOPAD_AA51_REG1_OFFSET 0x115CU +#define FIOPAD_U49_REG1_OFFSET 0x1160U +#define FIOPAD_J59_REG1_OFFSET 0x1168U +#define FIOPAD_L57_REG1_OFFSET 0x116CU +#define FIOPAD_C59_REG1_OFFSET 0x1170U +#define FIOPAD_E59_REG1_OFFSET 0x1174U +#define FIOPAD_J57_REG1_OFFSET 0x1178U +#define FIOPAD_L59_REG1_OFFSET 0x117CU +#define FIOPAD_N59_REG1_OFFSET 0x1180U +#define FIOPAD_E31_REG1_OFFSET 0x118CU +#define FIOPAD_G31_REG1_OFFSET 0x1190U +#define FIOPAD_N41_REG1_OFFSET 0x1194U +#define FIOPAD_N39_REG1_OFFSET 0x1198U +#define FIOPAD_J33_REG1_OFFSET 0x119CU +#define FIOPAD_N33_REG1_OFFSET 0x11A0U +#define FIOPAD_L33_REG1_OFFSET 0x11A4U +#define FIOPAD_N45_REG1_OFFSET 0x11A8U +#define FIOPAD_N43_REG1_OFFSET 0x11ACU +#define FIOPAD_L31_REG1_OFFSET 0x11B0U +#define FIOPAD_J31_REG1_OFFSET 0x11B4U +#define FIOPAD_J29_REG1_OFFSET 0x11B8U +#define FIOPAD_E29_REG1_OFFSET 0x11BCU +#define FIOPAD_G29_REG1_OFFSET 0x11C0U +#define FIOPAD_J37_REG1_OFFSET 0x11CCU +#define FIOPAD_J39_REG1_OFFSET 0x11D0U +#define FIOPAD_G41_REG1_OFFSET 0x11D4U +#define FIOPAD_E43_REG1_OFFSET 0x11D8U +#define FIOPAD_L43_REG1_OFFSET 0x11DCU +#define FIOPAD_C43_REG1_OFFSET 0x11E0U +#define FIOPAD_E41_REG1_OFFSET 0x11E4U +#define FIOPAD_L45_REG1_OFFSET 0x11E8U +#define FIOPAD_J43_REG1_OFFSET 0x11ECU +#define FIOPAD_J41_REG1_OFFSET 0x11F0U +#define FIOPAD_L39_REG1_OFFSET 0x11F4U +#define FIOPAD_E37_REG1_OFFSET 0x11F8U +#define FIOPAD_E35_REG1_OFFSET 0x11FCU +#define FIOPAD_G35_REG1_OFFSET 0x1200U +#define FIOPAD_L55_REG1_OFFSET 0x1220U +#define FIOPAD_J55_REG1_OFFSET 0x1224U +#define FIOPAD_J45_REG1_OFFSET 0x1228U +#define FIOPAD_E47_REG1_OFFSET 0x122CU +#define FIOPAD_G47_REG1_OFFSET 0x1230U +#define FIOPAD_J47_REG1_OFFSET 0x1234U +#define FIOPAD_J49_REG1_OFFSET 0x1238U +#define FIOPAD_N49_REG1_OFFSET 0x123CU +#define FIOPAD_L51_REG1_OFFSET 0x1240U +#define FIOPAD_L49_REG1_OFFSET 0x1244U +#define FIOPAD_N53_REG1_OFFSET 0x1248U +#define FIOPAD_J53_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ55_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J53_REG1_OFFSET + +#ifdef __cplusplus +} + +#endif + +#endif \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/e2000q/fparameters_comm.h b/bsps/aarch64/phytium/include/soc/e2000q/fparameters_comm.h new file mode 100644 index 0000000000..85bddcbd5b --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/e2000q/fparameters_comm.h @@ -0,0 +1,691 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters_comm.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 18:01:11 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef E2000_FPARAMETERS_COMMON_H +#define E2000_FPARAMETERS_COMMON_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************** Include Files *********************************/ + +#define SOC_TARGET_E2000 +/************************** Constant Definitions *****************************/ +/* CACHE */ +#define CACHE_LINE_ADDR_MASK 0x3FUL +#define CACHE_LINE 64U + +/* DEVICE Register Address */ +#define FT_DEV_BASE_ADDR 0x28000000U +#define FT_DEV_END_ADDR 0x2FFFFFFFU + +/* PCIE */ + +/* PCIE ECAM */ + +/* Pci express */ +#define FPCIE_ECAM_INSTANCE_NUM 1 +#define FPCIE_ECAM_INSTANCE0 0 + +#define FPCIE_ECAM_MAX_OUTBOUND_NUM 8 + +/* Bus, Device and Function */ +#define FPCIE_ECAM_CFG_MAX_NUM_OF_BUS 256 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_DEV 32 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_FUN 8 + +#define FPCIE_ECAM_INTA_IRQ_NUM 36 +#define FPCIE_ECAM_INTB_IRQ_NUM 37 +#define FPCIE_ECAM_INTC_IRQ_NUM 38 +#define FPCIE_ECAM_INTD_IRQ_NUM 39 + +/* max scan*/ +#define FPCIE_MAX_SCAN_NUMBER 128 + +/* memory space */ +#define FPCI_ECAM_CONFIG_BASE_ADDR 0x40000000 /* ecam */ +#define FPCI_ECAM_CONFIG_REG_LENGTH 0x10000000 + +#define FPCI_ECAM_IO_CONFIG_BASE_ADDR 0x50000000 /* io address space */ +#define FPCI_ECAM_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FPCI_ECAM_MEM32_BASE_ADDR 0x58000000 /* mmio 32 */ +#define FPCI_ECAM_MEM32_REG_LENGTH 0x27ffffff + +#define FPCI_ECAM_MEM64_BASE_ADDR 0x1000000000 /* mmio 64 */ +#define FPCI_ECAM_MEM64_REG_LENGTH 0x1fffffffff + + +/* FPCIE Controler */ +#define FPCIEC_INSTANCE_NUM 6 + +#define FPCIEC_INSTANCE0_INDEX 0 /* psu.c0 */ +#define FPCIEC_INSTANCE1_INDEX 1 /* psu.c1 */ +#define FPCIEC_INSTANCE2_INDEX 2 /* peu.c0 */ +#define FPCIEC_INSTANCE3_INDEX 3 /* peu.c1 */ +#define FPCIEC_INSTANCE4_INDEX 4 /* peu.c2 */ +#define FPCIEC_INSTANCE5_INDEX 5 /* peu.c3 */ + +#define FPCIEC_INSTANCE0_MISC_IRQ_NUM 42 + +#define FPCIEC_INSTANCE3_MISC_IRQ_NUM 40 + +#define FPCIEC_INSTANCE0_NUM 0 /* psu.c0 */ +#define FPCIEC_INSTANCE1_NUM 1 /* psu.c1 */ +#define FPCIEC_INSTANCE2_NUM 0 /* peu.c0 */ +#define FPCIEC_INSTANCE3_NUM 1 /* peu.c1 */ +#define FPCIEC_INSTANCE4_NUM 2 /* peu.c2 */ +#define FPCIEC_INSTANCE5_NUM 3 /* peu.c3 */ + +#define FPCIEC_INSTANCE0_CONTROL_BASE 0x31000000U +#define FPCIEC_INSTANCE1_CONTROL_BASE 0x31020000U +#define FPCIEC_INSTANCE2_CONTROL_BASE 0x31040000U +#define FPCIEC_INSTANCE3_CONTROL_BASE 0x31060000U +#define FPCIEC_INSTANCE4_CONTROL_BASE 0x31080000U +#define FPCIEC_INSTANCE5_CONTROL_BASE 0x310a0000U + +#define FPCIEC_INSTANCE0_CONFIG_BASE 0x31100000U +#define FPCIEC_INSTANCE1_CONFIG_BASE 0x31100000U +#define FPCIEC_INSTANCE2_CONFIG_BASE 0x31101000U +#define FPCIEC_INSTANCE3_CONFIG_BASE 0x31101000U +#define FPCIEC_INSTANCE4_CONFIG_BASE 0x31101000U +#define FPCIEC_INSTANCE5_CONFIG_BASE 0x31101000U + +#define FPCIEC_INSTANCE0_DMA_NUM 2 +#define FPCIEC_INSTANCE1_DMA_NUM 0 +#define FPCIEC_INSTANCE2_DMA_NUM 2 +#define FPCIEC_INSTANCE3_DMA_NUM 0 +#define FPCIEC_INSTANCE4_DMA_NUM 0 +#define FPCIEC_INSTANCE5_DMA_NUM 0 + +#define FPCIEC_INSTANCE0_DMABASE (0x31000000U + 0x400U) +#define FPCIEC_INSTANCE1_DMABASE (0U) +#define FPCIEC_INSTANCE2_DMABASE (0x31040000U + 0x400U) +#define FPCIEC_INSTANCE3_DMABASE (0U) +#define FPCIEC_INSTANCE4_DMABASE (0U) +#define FPCIEC_INSTANCE5_DMABASE (0U) + +#define FPCIEC_MAX_OUTBOUND_NUM 8 + + +/* platform ahci host */ +#define PLAT_AHCI_HOST_MAX_COUNT 5 +#define AHCI_BASE_0 0 +#define AHCI_BASE_1 0 +#define AHCI_BASE_2 0 +#define AHCI_BASE_3 0 +#define AHCI_BASE_4 0 + +#define AHCI_IRQ_0 0 +#define AHCI_IRQ_1 0 +#define AHCI_IRQ_2 0 +#define AHCI_IRQ_3 0 +#define AHCI_IRQ_4 0 + + +/* SCMI and MHU */ +#define FSCMI_MHU_BASE_ADDR 0x32a00000 +#define FSCMI_MHU_IRQ_NUM (22U + 32U) +#define FSCMI_SHR_MEM_ADDR 0x32a11400 +#define FSCMI_MEM_TX_OFSET 0x1400 +#define FSCMI_MEM_RX_OFSET 0x1000 +#define FSCMI_SHR_MEM_SIZE 0x400 + +#define FSCMI_MSG_SIZE 128 +#define FSCMI_MAX_STR_SIZE 16 +#define FSCMI_MAX_NUM_SENSOR 16 +#define FSCMI_MAX_PROTOCOLS_IMP 16 +#define FSCMI_MAX_PERF_DOMAINS 3 +#define FSCMI_MAX_OPPS 4 + +/* UART */ +#define FUART_NUM 4U +#define FUART_REG_LENGTH 0x18000U + +#define FUART0_ID 0U +#define FUART0_IRQ_NUM (85 + 30) +#define FUART0_BASE_ADDR 0x2800c000U +#define FUART0_CLK_FREQ_HZ 100000000U + +#define FUART1_ID 1U +#define FUART1_IRQ_NUM (86 + 30) +#define FUART1_BASE_ADDR 0x2800d000U +#define FUART1_CLK_FREQ_HZ 100000000U + +#define FUART2_ID 2U +#define FUART2_IRQ_NUM (87 + 30) +#define FUART2_BASE_ADDR 0x2800e000U +#define FUART2_CLK_FREQ_HZ 100000000U + +#define FUART3_BASE_ADDR 0x2800f000U +#define FUART3_ID 3U +#define FUART3_IRQ_NUM (88 + 30) +#define FUART3_CLK_FREQ_HZ 100000000U + +#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR +#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000U + + + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_NR_IRQS 270U +#define ARM_GIC_IRQ_START 0U +#define FGIC_NUM 1U + +#define ARM_GIC_IPI_COUNT 16U /* MPCore IPI count */ +#define SGI_INT_MAX 16U +#define SPI_START_INT_NUM 32U /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16U /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */ + +#define GICV3_BASE_ADDR 0x30800000U +#define GICV3_ITS_BASE_ADDR (GICV3_BASE_ADDR+ 0x20000U) +#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) +#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U) +#define GICV3_RD_OFFSET (2U << 16) +#define GICV3_RD_SIZE (8U << 16) + +/* GPIO */ +#define FGPIO0_BASE_ADDR 0x28034000U +#define FGPIO1_BASE_ADDR 0x28035000U +#define FGPIO2_BASE_ADDR 0x28036000U +#define FGPIO3_BASE_ADDR 0x28037000U +#define FGPIO4_BASE_ADDR 0x28038000U +#define FGPIO5_BASE_ADDR 0x28039000U + +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_2 2 +#define FGPIO_CTRL_3 3 +#define FGPIO_CTRL_4 4 +#define FGPIO_CTRL_5 5 +#define FGPIO_CTRL_NUM 6U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_NUM 1U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_8 8U +#define FGPIO_PIN_9 9U +#define FGPIO_PIN_10 10U +#define FGPIO_PIN_11 11U +#define FGPIO_PIN_12 12U +#define FGPIO_PIN_13 13U +#define FGPIO_PIN_14 14U +#define FGPIO_PIN_15 15U +#define FGPIO_PIN_NUM 16U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((FGPIO_PORT_A) * FGPIO_PIN_NUM) + (pin)) + +/* SPI */ +#define FSPI0_BASE_ADDR 0x2803A000U +#define FSPI1_BASE_ADDR 0x2803B000U +#define FSPI2_BASE_ADDR 0x2803C000U +#define FSPI3_BASE_ADDR 0x2803D000U +#define FSPI0_ID 0U +#define FSPI1_ID 1U +#define FSPI2_ID 2U +#define FSPI3_ID 3U + +#define FSPI0_IRQ_NUM 191U +#define FSPI1_IRQ_NUM 192U +#define FSPI2_IRQ_NUM 193U +#define FSPI3_IRQ_NUM 194U + +#define FSPI_CLK_FREQ_HZ 50000000U +#define FSPI_NUM 4U + +#define FSPI_DMA_CAPACITY BIT(0) +#define FSPIM0_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM1_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM2_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM3_DMA_CAPACITY FSPI_DMA_CAPACITY + +/* XMAC */ +#define FXMAC_NUM 4U + +#define FXMAC0_ID 0U +#define FXMAC1_ID 1U +#define FXMAC2_ID 2U +#define FXMAC3_ID 3U + +#define FXMAC0_BASE_ADDR 0x3200C000U +#define FXMAC1_BASE_ADDR 0x3200E000U +#define FXMAC2_BASE_ADDR 0x32010000U +#define FXMAC3_BASE_ADDR 0x32012000U + +#define FXMAC0_MODE_SEL_BASE_ADDR 0x3200DC00U +#define FXMAC0_LOOPBACK_SEL_BASE_ADDR 0x3200DC04U +#define FXMAC1_MODE_SEL_BASE_ADDR 0x3200FC00U +#define FXMAC1_LOOPBACK_SEL_BASE_ADDR 0x3200FC04U +#define FXMAC2_MODE_SEL_BASE_ADDR 0x32011C00U +#define FXMAC2_LOOPBACK_SEL_BASE_ADDR 0x32011C04U +#define FXMAC3_MODE_SEL_BASE_ADDR 0x32013C00U +#define FXMAC3_LOOPBACK_SEL_BASE_ADDR 0x32013C04U + +#define FXMAC0_PCLK 50000000U +#define FXMAC1_PCLK 50000000U +#define FXMAC2_PCLK 50000000U +#define FXMAC3_PCLK 50000000U +#define FXMAC0_HOTPLUG_IRQ_NUM (53U + 30U) +#define FXMAC1_HOTPLUG_IRQ_NUM (54U + 30U) +#define FXMAC2_HOTPLUG_IRQ_NUM (55U + 30U) +#define FXMAC3_HOTPLUG_IRQ_NUM (56U + 30U) + +#define FXMAC_QUEUE_MAX_NUM 16U + +#define FXMAC0_QUEUE0_IRQ_NUM (57U + 30U) +#define FXMAC0_QUEUE1_IRQ_NUM (58U + 30U) +#define FXMAC0_QUEUE2_IRQ_NUM (59U + 30U) +#define FXMAC0_QUEUE3_IRQ_NUM (60U + 30U) +#define FXMAC0_QUEUE4_IRQ_NUM (30U + 30U) +#define FXMAC0_QUEUE5_IRQ_NUM (31U + 30U) +#define FXMAC0_QUEUE6_IRQ_NUM (32U + 30U) +#define FXMAC0_QUEUE7_IRQ_NUM (33U + 30U) + +#define FXMAC1_QUEUE0_IRQ_NUM (61U + 30U) +#define FXMAC1_QUEUE1_IRQ_NUM (62U + 30U) +#define FXMAC1_QUEUE2_IRQ_NUM (63U + 30U) +#define FXMAC1_QUEUE3_IRQ_NUM (64U + 30U) + +#define FXMAC2_QUEUE0_IRQ_NUM (66U + 30U) +#define FXMAC2_QUEUE1_IRQ_NUM (67U + 30U) +#define FXMAC2_QUEUE2_IRQ_NUM (68U + 30U) +#define FXMAC2_QUEUE3_IRQ_NUM (69U + 30U) + +#define FXMAC3_QUEUE0_IRQ_NUM (70U + 30U) +#define FXMAC3_QUEUE1_IRQ_NUM (71U + 30U) +#define FXMAC3_QUEUE2_IRQ_NUM (72U + 30U) +#define FXMAC3_QUEUE3_IRQ_NUM (73U + 30U) + +#define FXMAC_PHY_MAX_NUM 32U + +#define FXMAC_CLK_TYPE_0 + +/* IOPAD */ +#define FIOPAD0_ID 0 +#define FIOPAD_NUM 1 + +/* QSPI */ +#define FQSPI0_ID 0 +#define FQSPI_NUM 1 + +/* FQSPI cs 0_3, chip number */ + +#define FQSPI_CS_0 0 +#define FQSPI_CS_1 1 +#define FQSPI_CS_2 2 +#define FQSPI_CS_3 3 +#define FQSPI_CS_NUM 4 +#define FQSPI_BASE_ADDR 0x028008000U + +#define FQSPI_MEM_START_ADDR 0x0U +#define FQSPI_MEM_END_ADDR 0x0FFFFFFFU /* 256MB */ +#define FQSPI_MEM_START_ADDR_64 0x100000000U +#define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */ + +/* TIMER and TACHO */ +#define FTIMER_NUM 38U +#define FTIMER_CLK_FREQ_HZ 50000000ULL /* 50MHz */ +#define FTIMER_TICK_PERIOD_NS 20U /* 20ns */ +#define FTIMER_TACHO_IRQ_NUM(n) (226U + (n)) +#define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n)) + + +#define FTACHO0_ID 0 +#define FTACHO1_ID 1 +#define FTACHO2_ID 2 +#define FTACHO3_ID 3 +#define FTACHO4_ID 4 +#define FTACHO5_ID 5 +#define FTACHO6_ID 6 +#define FTACHO7_ID 7 +#define FTACHO8_ID 8 +#define FTACHO9_ID 9 +#define FTACHO10_ID 10 +#define FTACHO11_ID 11 +#define FTACHO12_ID 12 +#define FTACHO13_ID 13 +#define FTACHO14_ID 14 +#define FTACHO15_ID 15 +#define FTACHO_NUM 16 + +/* GDMA */ +#define FGDMA0_ID 0U +#define FGDMA0_BASE_ADDR 0x32B34000U +#define FGDMA0_CHANNEL0_IRQ_NUM 266U +#define FGDMA_NUM_OF_CHAN 16 +#define FGDMA_INSTANCE_NUM 1U +#define FGDMA0_CAPACITY (1U<<0) + +/* WDT */ + +#define FWDT0_ID 0 +#define FWDT1_ID 1 +#define FWDT_NUM 2 + +#define FWDT0_REFRESH_BASE_ADDR 0x28040000U +#define FWDT1_REFRESH_BASE_ADDR 0x28042000U + +#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) + +#define FWDT0_IRQ_NUM 196U +#define FWDT1_IRQ_NUM 197U + +#define FWDT_CLK_FREQ_HZ 48000000U /* 48MHz */ + +/*MIO*/ +#define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n)) +#define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000 +#define FMIO_IRQ_NUM(n) (124+n) +#define FMIO_CLK_FREQ_HZ 50000000 /* 50MHz */ + + +#define FMIO0_ID 0 +#define FMIO1_ID 1 +#define FMIO2_ID 2 +#define FMIO3_ID 3 +#define FMIO4_ID 4 +#define FMIO5_ID 5 +#define FMIO6_ID 6 +#define FMIO7_ID 7 +#define FMIO8_ID 8 +#define FMIO9_ID 9 +#define FMIO10_ID 10 +#define FMIO11_ID 11 +#define FMIO12_ID 12 +#define FMIO13_ID 13 +#define FMIO14_ID 14 +#define FMIO15_ID 15 +#define FMIO_NUM 16 + +/*I2C0 -> PMBUS0 +* I2C1 -> PMBUS1 +* I2C2 -> SMBUS0 +*/ + + +#define FI2C0_ID 0 +#define FI2C1_ID 1 +#define FI2C2_ID 2 +#define FI2C_NUM 3 + +#define FI2C0_BASE_ADDR 0x28011000 +#define FI2C1_BASE_ADDR 0x28012000 +#define FI2C2_BASE_ADDR 0x28013000 + +#define FI2C0_IRQ_NUM 121 +#define FI2C1_IRQ_NUM 122 +#define FI2C2_IRQ_NUM 123 + +#define FI2C_CLK_FREQ_HZ 50000000 /* 50MHz */ + +/* SDIF */ +#define FSDIF0_ID 0 +#define FSDIF1_ID 1 +#define FSDIF_NUM 2 + + +#define FSDIF0_BASE_ADDR 0x28000000U +#define FSDIF1_BASE_ADDR 0x28001000U + +#define FSDIF0_IRQ_NUM 104U +#define FSDIF1_IRQ_NUM 105U + +#define FSDIF_CLK_FREQ_HZ (1200000000UL) /* 1.2GHz */ + +/* NAND */ +#define FNAND_NUM 1U +#define FNAND_INSTANCE0 0U +#define FNAND_BASE_ADDR 0x28002000U +#define FNAND_IRQ_NUM (106U) +#define FNAND_CONNECT_MAX_NUM 1U + +#define FIOPAD_BASE_ADDR 0x32B30000U + +/* DDMA */ +#define FDDMA0_ID 0U +#define FDDMA0_BASE_ADDR 0x28003000U +#define FDDMA0_IRQ_NUM 107U +#define FDDMA0_CAPACITY (1U<<1) + +#define FDDMA1_ID 1U +#define FDDMA1_BASE_ADDR 0x28004000U +#define FDDMA1_IRQ_NUM 108U +#define FDDMA1_CAPACITY (1U<<1) + +#define FDDMA2_I2S_ID 2U +#define FDDMA2_BASE_ADDR 0x28005000U +#define FDDMA2_IRQ_NUM 109U +#define FDDMA2_CAPACITY (1U<<0) + +#define FDDMA3_DP0_I2S_ID 3U +#define FDDMA3_BASE_ADDR 0x32008000U +#define FDDMA3_IRQ_NUM 79U +#define FDDMA3_CAPACITY (1U<<0) + +#define FDDMA4_DP1_I2S_ID 4U +#define FDDMA4_BASE_ADDR 0x3200A000U +#define FDDMA4_IRQ_NUM 80U +#define FDDMA4_CAPACITY (1U<<0) + +#define FDDMA_INSTANCE_NUM 5U + +#define FDDMA0_CAN0_TX_SLAVE_ID 0U /* can0 tx slave-id */ +#define FDDMA0_CAN1_TX_SLAVE_ID 1U /* can1 tx slave-id */ +#define FDDMA0_UART0_TX_SLAVE_ID 2U /* uart0 tx slave-id */ +#define FDDMA0_UART1_TX_SLAVE_ID 3U /* uart1 tx slave-id */ +#define FDDMA0_UART2_TX_SLAVE_ID 4U /* uart2 tx slave-id */ +#define FDDMA0_UART3_TX_SLAVE_ID 5U /* uart3 tx slave-id */ + +#define FDDMA0_SPIM0_TX_SLAVE_ID 6U /* spi0 tx slave-id */ +#define FDDMA0_SPIM1_TX_SLAVE_ID 7U /* spi1 tx slave-id */ +#define FDDMA0_SPIM2_TX_SLAVE_ID 8U /* spi2 tx slave-id */ +#define FDDMA0_SPIM3_TX_SLAVE_ID 9U /* spi3 tx slave-id */ + +#define FDDMA0_CAN0_RX_SLAVE_ID 13U /* can0 rx slave-id */ +#define FDDMA0_CAN1_RX_SLAVE_ID 14U /* can1 rx slave-id */ +#define FDDMA0_UART0_RX_SLAVE_ID 15U /* uart0 rx slave-id */ +#define FDDMA0_UART1_RX_SLAVE_ID 16U /* uart1 rx slave-id */ +#define FDDMA0_UART2_RX_SLAVE_ID 17U /* uart2 rx slave-id */ +#define FDDMA0_UART3_RX_SLAVE_ID 18U /* uart3 rx slave-id */ + +#define FDDMA0_SPIM0_RX_SLAVE_ID 19U /* spi0 rx slave-id */ +#define FDDMA0_SPIM1_RX_SLAVE_ID 20U /* spi1 rx slave-id */ +#define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */ +#define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */ + +/* FDDMA1_ID */ +#define FDDMA1_MIO0_TX_SLAVE_ID 0U /* mio0 rx slave-id */ +#define FDDMA1_MIO1_TX_SLAVE_ID 1U /* mio1 rx slave-id */ +#define FDDMA1_MIO2_TX_SLAVE_ID 2U /* mio2 rx slave-id */ +#define FDDMA1_MIO3_TX_SLAVE_ID 3U /* mio3 rx slave-id */ +#define FDDMA1_MIO4_TX_SLAVE_ID 4U /* mio4 rx slave-id */ +#define FDDMA1_MIO5_TX_SLAVE_ID 5U /* mio5 rx slave-id */ +#define FDDMA1_MIO6_TX_SLAVE_ID 6U /* mio6 rx slave-id */ +#define FDDMA1_MIO7_TX_SLAVE_ID 7U /* mio7 rx slave-id */ +#define FDDMA1_MIO8_TX_SLAVE_ID 8U /* mio8 rx slave-id */ +#define FDDMA1_MIO9_TX_SLAVE_ID 9U /* mio9 rx slave-id */ +#define FDDMA1_MIO10_TX_SLAVE_ID 10U /* mio10 rx slave-id */ +#define FDDMA1_MIO11_TX_SLAVE_ID 11U /* mio11 rx slave-id */ +#define FDDMA1_MIO12_TX_SLAVE_ID 12U /* mio12 rx slave-id */ +#define FDDMA1_MIO13_TX_SLAVE_ID 13U /* mio13 rx slave-id */ +#define FDDMA1_MIO14_TX_SLAVE_ID 14U /* mio14 rx slave-id */ +#define FDDMA1_MIO15_TX_SLAVE_ID 15U /* mio15 rx slave-id */ + +#define FDDMA1_MIO0_RX_SLAVE_ID 16U /* mio0 tx slave-id */ +#define FDDMA1_MIO1_RX_SLAVE_ID 17U /* mio1 tx slave-id */ +#define FDDMA1_MIO2_RX_SLAVE_ID 18U /* mio2 tx slave-id */ +#define FDDMA1_MIO3_RX_SLAVE_ID 19U /* mio3 tx slave-id */ +#define FDDMA1_MIO4_RX_SLAVE_ID 20U /* mio4 tx slave-id */ +#define FDDMA1_MIO5_RX_SLAVE_ID 21U /* mio5 tx slave-id */ +#define FDDMA1_MIO6_RX_SLAVE_ID 22U /* mio6 tx slave-id */ +#define FDDMA1_MIO7_RX_SLAVE_ID 23U /* mio7 tx slave-id */ +#define FDDMA1_MIO8_RX_SLAVE_ID 24U /* mio8 tx slave-id */ +#define FDDMA1_MIO9_RX_SLAVE_ID 25U /* mio9 tx slave-id */ +#define FDDMA1_MIO10_RX_SLAVE_ID 26U /* mio10 tx slave-id */ +#define FDDMA1_MIO11_RX_SLAVE_ID 27U /* mio11 tx slave-id */ +#define FDDMA1_MIO12_RX_SLAVE_ID 28U /* mio12 tx slave-id */ +#define FDDMA1_MIO13_RX_SLAVE_ID 29U /* mio13 tx slave-id */ +#define FDDMA1_MIO14_RX_SLAVE_ID 30U /* mio14 tx slave-id */ +#define FDDMA1_MIO15_RX_SLAVE_ID 31U /* mio15 tx slave-id */ + +#define FDDMA_MIN_SLAVE_ID 0U +#define FDDMA_MAX_SLAVE_ID 31U + +/* Semaphore */ +#define FSEMA0_ID 0U +#define FSEMA0_BASE_ADDR 0x32B36000U +#define FSEMA_INSTANCE_NUM 1U + +/* LSD Config */ +#define FLSD_CONFIG_BASE 0x2807E000U +#define FLSD_NAND_MMCSD_HADDR 0xC0U +#define FLSD_CK_STOP_CONFIG0_HADDR 0x10U +#define FLSD_PWM_HADDR 0x20 /* bit0-bit7 corresponds to pwm0-pwm7 */ + +/* USB3 */ +#define FUSB3_ID_0 0U +#define FUSB3_ID_1 1U +#define FUSB3_NUM 2U +#define FUSB3_XHCI_OFFSET 0x8000U +#define FUSB3_0_BASE_ADDR 0x31A00000U +#define FUSB3_1_BASE_ADDR 0x31A20000U +#define FUSB3_0_IRQ_NUM 48U +#define FUSB3_1_IRQ_NUM 49U + +/* DcDp */ + + +#define FDCDP_ID0 0 +#define FDCDP_ID1 1 + +#define FDCDP_INSTANCE_NUM 2 + +#define FDC_CTRL_BASE_OFFSET 0x32000000U + +#define FDC0_CHANNEL_BASE_OFFSET 0x32001000U +#define FDC1_CHANNEL_BASE_OFFSET (FDC0_CHANNEL_BASE_OFFSET + 0x1000U) + +#define FDP0_CHANNEL_BASE_OFFSET 0x32004000U +#define FDP1_CHANNEL_BASE_OFFSET (FDP0_CHANNEL_BASE_OFFSET + 0x1000U) + +#define FDP0_PHY_BASE_OFFSET 0x32300000U +#define FDP1_PHY_BASE_OFFSET (FDP0_PHY_BASE_OFFSET + 0x100000U) + +#define FDCDP_IRQ_NUM 76 + +/* generic timer */ +/* non-secure physical timer int id */ +#define GENERIC_TIMER_NS_IRQ_NUM 30U + +/* virtual timer int id */ +#define GENERIC_VTIMER_IRQ_NUM 27U + + +#define GENERIC_TIMER_ID0 0 /* non-secure physical timer */ +#define GENERIC_TIMER_ID1 1 /* virtual timer */ +#define GENERIC_TIMER_NUM 2 + + +/* PMU */ +#define FPMU_IRQ_NUM 23 + +/* USB2 OTG */ +#if !defined(__ASSEMBLER__) + +enum +{ + FUSB2_ID_VHUB_0 = 0, + FUSB2_ID_1, + FUSB2_ID_2, + FUSB2_ID_VHUB_1, + FUSB2_ID_VHUB_2, + + FUSB2_INSTANCE_NUM +}; + +#endif + +#define FUSB2_0_VHUB_BASE_ADDR 0x31800000U +#define FUSB2_1_VHUB_BASE_ADDR 0x31880000U +#define FUSB2_2_VHUB_BASE_ADDR 0x31900000U + +#define FUSB2_VHUB_CFG_BASE_ADDR 0x319C0000U +#define FUSB2_DEV_1_CFG_BASE_ADDR 0x31990000U +#define FUSB2_DEV_2_CFG_BASE_ADDR 0x319A0000U +#define FUSB2_DEV_3_CFG_BASE_ADDR 0x319B0000U + +#define FUSB2_0_VHUB_IRQ_NUM 64U +#define FUSB2_1_VHUB_IRQ_NUM 65U +#define FUSB2_2_VHUB_IRQ_NUM 66U + +#define FUSB2_0_VHUB_WAKEUP_IRQ_NUM 67U +#define FUSB2_1_VHUB_WAKEUP_IRQ_NUM 68U +#define FUSB2_2_VHUB_WAKEUP_IRQ_NUM 69U + +#define FUSB2_1_BASE_ADDR 0x32800000U +#define FUSB2_2_BASE_ADDR 0x32840000U +#define FUSB2_1_UIB_BASE_ADDR 0x32880000U +#define FUSB2_2_UIB_BASE_ADDR 0x328C0000U +#define FUSB2_MMIO_SIZE 0x00200000U /* 2MB */ + +#define FUSB2_1_IRQ_NUM 46U +#define FUSB2_2_IRQ_NUM 47U + +#define FUSB2_1_WAKEUP_IRQ_NUM 50U +#define FUSB2_2_WAKEUP_IRQ_NUM 51U + + +/*****************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/ft2004/fparameters.h b/bsps/aarch64/phytium/include/soc/ft2004/fparameters.h new file mode 100644 index 0000000000..eb21394350 --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/ft2004/fparameters.h @@ -0,0 +1,362 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 18:01:11 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef FT2004_FPARAMETERS_H +#define FT2004_FPARAMETERS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define SOC_TARGET_FT2004 + +#define CORE0_AFF 0x0 +#define CORE1_AFF 0x1 +#define CORE2_AFF 0x100 +#define CORE3_AFF 0x101 +#define FCORE_NUM 8 + +/* cache */ +#define CACHE_LINE_ADDR_MASK 0x3FUL +#define CACHE_LINE 64U + + +/* Device register address */ +#define FDEV_BASE_ADDR 0x28000000 +#define FDEV_END_ADDR 0x2FFFFFFF + +/* PCIE ECAM */ + +/* Pci express */ +#define FPCIE_ECAM_INSTANCE_NUM 1 +#define FPCIE_ECAM_INSTANCE0 0 + +#define FPCIE_ECAM_MAX_OUTBOUND_NUM 8 + +/* Bus, Device and Function */ +#define FPCIE_ECAM_CFG_MAX_NUM_OF_BUS 256 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_DEV 32 +#define FPCIE_ECAM_CFG_MAX_NUM_OF_FUN 8 + +#define FPCIE_ECAM_INTA_IRQ_NUM 60 +#define FPCIE_ECAM_INTB_IRQ_NUM 61 +#define FPCIE_ECAM_INTC_IRQ_NUM 62 +#define FPCIE_ECAM_INTD_IRQ_NUM 63 + +/* max scan*/ +#define FPCIE_MAX_SCAN_NUMBER 128 + +/* memory space */ +#define FPCI_ECAM_CONFIG_BASE_ADDR 0x40000000 /* ecam */ +#define FPCI_ECAM_CONFIG_REG_LENGTH 0x10000000 + +#define FPCI_ECAM_IO_CONFIG_BASE_ADDR 0x50000000 /* io address space */ +#define FPCI_ECAM_IO_CONFIG_REG_LENGTH 0x08000000 + +#define FPCI_ECAM_MEM32_BASE_ADDR 0x58000000 /* mmio 32 */ +#define FPCI_ECAM_MEM32_REG_LENGTH 0x27ffffff + +#define FPCI_ECAM_MEM64_BASE_ADDR 0x1000000000 /* mmio 64 */ +#define FPCI_ECAM_MEM64_REG_LENGTH 0x1fffffffff + +#define FPCIE_NEED_SKIP_TYPE0 + + +/* platform ahci host */ +#define PLAT_AHCI_HOST_MAX_COUNT 5 +#define AHCI_BASE_0 0 +#define AHCI_BASE_1 0 +#define AHCI_BASE_2 0 +#define AHCI_BASE_3 0 +#define AHCI_BASE_4 0 + +#define AHCI_IRQ_0 0 +#define AHCI_IRQ_1 0 +#define AHCI_IRQ_2 0 +#define AHCI_IRQ_3 0 +#define AHCI_IRQ_4 0 + +// UART + +#define FUART_NUM 4 +#define FUART_REG_LENGTH 0x18000 + +#define FUART0_ID 0 +#define FUART0_IRQ_NUM 38 +#define FUART0_BASE_ADDR 0x28000000 +#define FUART0_CLK_FREQ_HZ 48000000 + +#define FUART1_ID 1 +#define FUART1_IRQ_NUM 39 +#define FUART1_BASE_ADDR 0x28001000 +#define FUART1_CLK_FREQ_HZ 48000000 + +#define FUART2_ID 2 +#define FUART2_IRQ_NUM 40 +#define FUART2_BASE_ADDR 0x28002000 +#define FUART2_CLK_FREQ_HZ 48000000 + +#define FUART3_BASE_ADDR 0x28003000 +#define FUART3_ID 3 +#define FUART3_IRQ_NUM 41 +#define FUART3_CLK_FREQ_HZ 48000000 + +#define FT_STDOUT_BASE_ADDRESS FUART1_BASE_ADDR +#define FT_STDIN_BASE_ADDRESS FUART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000 + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U +#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ +#define SGI_INT_MAX 16 +#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ +#define GICV3_BASE_ADDR 0x29900000U +#define GICV3_ITS_BASE_ADDR (GICV3_BASE_ADDR + 0x20000U) +#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) +#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U) +#define GICV3_RD_OFFSET (2U << 16) +#define GICV3_RD_SIZE (8U << 16) + + +/* GPIO */ +#define FGPIO0_BASE_ADDR (0x28004000) +#define FGPIO1_BASE_ADDR (0x28005000) + +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_NUM 2U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_B 1U +#define FGPIO_PORT_NUM 2U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_NUM 8U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, port, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((port) * FGPIO_PIN_NUM) + (pin)) + +/* SPI */ +#define FSPI0_BASE_ADDR 0x2800c000 +#define FSPI1_BASE_ADDR 0x28013000 +#define FSPI0_ID 0 +#define FSPI1_ID 1 +#define FSPI_CLK_FREQ_HZ 48000000 +#define FSPI_NUM 2 +#define FSPI0_IRQ_NUM 50 +#define FSPI1_IRQ_NUM 51 + +#define FSPI_DMA_CAPACITY BIT(0) +#define FSPIM0_DMA_CAPACITY 0 +#define FSPIM1_DMA_CAPACITY 0 + +/* QSPI */ +#define FQSPI0_ID 0 +#define FQSPI_NUM 1 + +/* FQSPI cs 0_3, chip number */ + +#define FQSPI_CS_0 0 +#define FQSPI_CS_1 1 +#define FQSPI_CS_2 2 +#define FQSPI_CS_3 3 +#define FQSPI_CS_NUM 4 + +#define FQSPI_BASE_ADDR 0x28014000 +#define FQSPI_MEM_START_ADDR 0x0 +#define FQSPI_MEM_END_ADDR 0x1FFFFFFF + +/* IOCTRL */ +#define FIOCTRL_BASE_ADDR 0x28180000 + +#define FIOCTRL0_ID 0 +#define FIOCTRL_NUM 1 + +#define FIOCTRL_INDEX(offset, func_beg) \ + { \ + /* reg_off */ (offset), \ + /* reg_bit */ (func_beg) \ + } + +#define FIOCTRL_CRU_CLK_OBV_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x200, 24) +#define FIOCTRL_SPI0_CSN0_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 16) +#define FIOCTRL_SPI0_SCK_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 12) +#define FIOCTRL_SPI0_SO_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 8) +#define FIOCTRL_SPI0_SI_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 4) + +#define FIOCTRL_TJTAG_TDI_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */ +#define FIOCTRL_SWDITMS_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */ + +#define FIOCTRL_NTRST_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */ +#define FIOCTRL_SWDO_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */ + +#define FIOCTRL_I2C0_SCL_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */ +#define FIOCTRL_I2C0_SDA_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */ +#define FIOCTRL_ALL_PLL_LOCK_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */ +#define FIOCTRL_CRU_CLK_OBV_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */ +#define FIOCTRL_SWDO_SWJ_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */ +#define FIOCTRL_TDO_SWJ_IN_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */ +#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */ +#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */ + +#define FIOCTRL_UART_2_RXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */ +#define FIOCTRL_UART_2_TXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */ +#define FIOCTRL_UART_3_RXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */ +#define FIOCTRL_UART_3_TXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */ +#define FIOCTRL_QSPI_CSN2_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */ +#define FIOCTRL_QSPI_CSN3_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */ + + +// Gic +#define ARM_GIC_NR_IRQS 1024 +#define ARM_GIC_IRQ_START 0 +#define FGIC_NUM 1 + +/* can */ +#define FCAN0_ID 0 +#define FCAN1_ID 1 +#define FCAN2_ID 2 +#define FCAN_NUM 3 + +#define FCAN_CLK_FREQ_HZ 600000000 + +#define FCAN0_BASE_ADDR 0x28207000 +#define FCAN1_BASE_ADDR 0x28207400 +#define FCAN2_BASE_ADDR 0x28207800 +#define FCAN0_IRQ_NUM 119 +#define FCAN1_IRQ_NUM 123 +#define FCAN2_IRQNUM 124 + +/* can capacity */ +#define FCAN_FD_CAPACITY BIT(0) /* Whether canfd is supported */ +#define FCAN_CAPACITY 0 + +/* I2C */ +#define FI2C0_ID 0 +#define FI2C1_ID 1 +#define FI2C2_ID 2 +#define FI2C3_ID 3 +#define FI2C_NUM 4 + +#define FI2C0_BASE_ADDR 0x28006000 +#define FI2C1_BASE_ADDR 0x28007000 +#define FI2C2_BASE_ADDR 0x28008000 +#define FI2C3_BASE_ADDR 0x28009000 + +#define FI2C0_IRQ_NUM 44 +#define FI2C1_IRQ_NUM 45 +#define FI2C2_IRQ_NUM 46 +#define FI2C3_IRQ_NUM 47 + +#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */ + +/* WDT */ +#define FWDT0_ID 0 +#define FWDT1_ID 1 +#define FWDT_NUM 2 + +#define FWDT0_REFRESH_BASE_ADDR 0x2800a000 +#define FWDT1_REFRESH_BASE_ADDR 0x28016000 + +#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) + +#define FWDT0_IRQ_NUM 48 +#define FWDT1_IRQ_NUM 49 + +#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */ + +/* SDCI */ +#define FSDMMC0_ID 0 +#define FSDMMC_NUM 1 + +#define FSDMMC0_BASE_ADDR 0x28207C00 + +#define FSDMMC0_DMA_IRQ_NUM 52 +#define FSDMMC0_CMD_IRQ_NUM 53 +#define FSDMMC0_ERR_IRQ_NUM 54 + +#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */ +#define SDCI_SEN_DEBNCE 10000000 /* 10 MHz */ +#define SDCI_CMD_TIMEOUT 10000000 /* 1s */ +#define SDCI_DATA_TIMEOUT 40000000 /* 4S */ + +/* GMAC */ +#define FGMAC0_ID 0 +#define FGMAC1_ID 1 +#define FGMAC_NUM 2 + +#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */ + +#define FGMAC0_BASE_ADDR 0x2820C000 +#define FGMAC1_BASE_ADDR 0x28210000 + +#define FGMAC0_IRQ_NUM 81 +#define FGMAC1_IRQ_NUM 82 + +#define FGMAC_DMA_MIN_ALIGN 128 +#define FGMAC_MAX_PACKET_SIZE 1600 + +/*RTC*/ +#define RTC_CONTROL_BASE 0x2800D000 + +/* generic timer */ +/* non-secure physical timer int id */ +#define GENERIC_TIMER_NS_IRQ_NUM 30U + +/* virtual timer int id */ +#define GENERIC_VTIMER_IRQ_NUM 27U + +#define GENERIC_TIMER_ID0 0 /* non-secure physical timer */ +#define GENERIC_TIMER_ID1 1 /* virtual timer */ +#define GENERIC_TIMER_NUM 2 + + +/* PMU */ +#define FPMU_IRQ_NUM 23 + +#ifdef __cplusplus +} +#endif + +#endif // ! \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/phytiumpi/fparameters.h b/bsps/aarch64/phytium/include/soc/phytiumpi/fparameters.h new file mode 100644 index 0000000000..086e57f5ae --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/phytiumpi/fparameters.h @@ -0,0 +1,298 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters.h + * Date: 2022-02-11 13:33:28 + * LastEditTime: 2022-02-17 18:00:50 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef PHYTIUMPI_FPARAMTERERS_H +#define PHYTIUMPI_FPARAMTERERS_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************** Include Files *********************************/ +#include "fparameters_comm.h" + +#define SOC_TARGET_PHYTIUMPI + +/************************** Constant Definitions *****************************/ +#define CORE0_AFF 0x000U +#define CORE1_AFF 0x100U +#define CORE2_AFF 0x200U +#define CORE3_AFF 0x201U +#define FCORE_NUM 4 + +/*****************************************************************************/ +/* register offset of iopad function / pull / driver strength */ +#define FIOPAD_AN59_REG0_OFFSET 0x0000U +#define FIOPAD_AW47_REG0_OFFSET 0x0004U +#define FIOPAD_AR55_REG0_OFFSET 0x0020U +#define FIOPAD_AJ55_REG0_OFFSET 0x0024U +#define FIOPAD_AL55_REG0_OFFSET 0x0028U +#define FIOPAD_AL53_REG0_OFFSET 0x002CU +#define FIOPAD_AN51_REG0_OFFSET 0x0030U +#define FIOPAD_AR51_REG0_OFFSET 0x0034U +#define FIOPAD_BA57_REG0_OFFSET 0x0038U +#define FIOPAD_BA59_REG0_OFFSET 0x003CU +#define FIOPAD_AW57_REG0_OFFSET 0x0040U +#define FIOPAD_AW59_REG0_OFFSET 0x0044U +#define FIOPAD_AU55_REG0_OFFSET 0x0048U +#define FIOPAD_AN57_REG0_OFFSET 0x004CU +#define FIOPAD_AL59_REG0_OFFSET 0x0050U +#define FIOPAD_AJ59_REG0_OFFSET 0x0054U +#define FIOPAD_AJ57_REG0_OFFSET 0x0058U +#define FIOPAD_AG59_REG0_OFFSET 0x005CU +#define FIOPAD_AG57_REG0_OFFSET 0x0060U +#define FIOPAD_AE59_REG0_OFFSET 0x0064U +#define FIOPAD_AC59_REG0_OFFSET 0x0068U +#define FIOPAD_AC57_REG0_OFFSET 0x006CU +#define FIOPAD_AR49_REG0_OFFSET 0x0070U +#define FIOPAD_BA55_REG0_OFFSET 0x0074U +#define FIOPAD_BA53_REG0_OFFSET 0x0078U +#define FIOPAD_AR59_REG0_OFFSET 0x007CU +#define FIOPAD_AU59_REG0_OFFSET 0x0080U +#define FIOPAD_AR57_REG0_OFFSET 0x0084U +#define FIOPAD_BA49_REG0_OFFSET 0x0088U +#define FIOPAD_AW55_REG0_OFFSET 0x008CU +#define FIOPAD_A35_REG0_OFFSET 0x0090U +#define FIOPAD_R57_REG0_OFFSET 0x0094U +#define FIOPAD_R59_REG0_OFFSET 0x0098U +#define FIOPAD_U59_REG0_OFFSET 0x009CU +#define FIOPAD_W59_REG0_OFFSET 0x00A0U +#define FIOPAD_U57_REG0_OFFSET 0x00A4U +#define FIOPAD_AA57_REG0_OFFSET 0x00A8U +#define FIOPAD_AA59_REG0_OFFSET 0x00ACU +#define FIOPAD_AW51_REG0_OFFSET 0x00B0U +#define FIOPAD_AU51_REG0_OFFSET 0x00B4U +#define FIOPAD_A39_REG0_OFFSET 0x00B8U +#define FIOPAD_C39_REG0_OFFSET 0x00BCU +#define FIOPAD_C37_REG0_OFFSET 0x00C0U +#define FIOPAD_A37_REG0_OFFSET 0x00C4U +#define FIOPAD_A41_REG0_OFFSET 0x00C8U +#define FIOPAD_A43_REG0_OFFSET 0x00CCU +#define FIOPAD_A45_REG0_OFFSET 0x00D0U +#define FIOPAD_C45_REG0_OFFSET 0x00D4U +#define FIOPAD_A47_REG0_OFFSET 0x00D8U +#define FIOPAD_A49_REG0_OFFSET 0x00DCU +#define FIOPAD_C49_REG0_OFFSET 0x00E0U +#define FIOPAD_A51_REG0_OFFSET 0x00E4U +#define FIOPAD_A33_REG0_OFFSET 0x00E8U +#define FIOPAD_C33_REG0_OFFSET 0x00ECU +#define FIOPAD_C31_REG0_OFFSET 0x00F0U +#define FIOPAD_A31_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ53_REG0_OFFSET 0x00F8U +#define FIOPAD_AL49_REG0_OFFSET 0x00FCU +#define FIOPAD_AL47_REG0_OFFSET 0x0100U +#define FIOPAD_AN49_REG0_OFFSET 0x0104U +#define FIOPAD_AG51_REG0_OFFSET 0x0108U +#define FIOPAD_AJ51_REG0_OFFSET 0x010CU +#define FIOPAD_AG49_REG0_OFFSET 0x0110U +#define FIOPAD_AE55_REG0_OFFSET 0x0114U +#define FIOPAD_AE53_REG0_OFFSET 0x0118U +#define FIOPAD_AG55_REG0_OFFSET 0x011CU +#define FIOPAD_AJ49_REG0_OFFSET 0x0120U +#define FIOPAD_AC55_REG0_OFFSET 0x0124U +#define FIOPAD_AC53_REG0_OFFSET 0x0128U +#define FIOPAD_AE51_REG0_OFFSET 0x012CU +#define FIOPAD_W51_REG0_OFFSET 0x0130U +#define FIOPAD_W55_REG0_OFFSET 0x0134U +#define FIOPAD_W53_REG0_OFFSET 0x0138U +#define FIOPAD_U55_REG0_OFFSET 0x013CU +#define FIOPAD_U53_REG0_OFFSET 0x0140U +#define FIOPAD_AE49_REG0_OFFSET 0x0144U +#define FIOPAD_AC49_REG0_OFFSET 0x0148U +#define FIOPAD_AE47_REG0_OFFSET 0x014CU +#define FIOPAD_AA47_REG0_OFFSET 0x0150U +#define FIOPAD_AA49_REG0_OFFSET 0x0154U +#define FIOPAD_W49_REG0_OFFSET 0x0158U +#define FIOPAD_AA51_REG0_OFFSET 0x015CU +#define FIOPAD_U49_REG0_OFFSET 0x0160U +#define FIOPAD_G59_REG0_OFFSET 0x0164U +#define FIOPAD_J59_REG0_OFFSET 0x0168U +#define FIOPAD_L57_REG0_OFFSET 0x016CU +#define FIOPAD_C59_REG0_OFFSET 0x0170U +#define FIOPAD_E59_REG0_OFFSET 0x0174U +#define FIOPAD_J57_REG0_OFFSET 0x0178U +#define FIOPAD_L59_REG0_OFFSET 0x017CU +#define FIOPAD_N59_REG0_OFFSET 0x0180U +#define FIOPAD_C57_REG0_OFFSET 0x0184U +#define FIOPAD_E57_REG0_OFFSET 0x0188U +#define FIOPAD_E31_REG0_OFFSET 0x018CU +#define FIOPAD_G31_REG0_OFFSET 0x0190U +#define FIOPAD_N41_REG0_OFFSET 0x0194U +#define FIOPAD_N39_REG0_OFFSET 0x0198U +#define FIOPAD_J33_REG0_OFFSET 0x019CU +#define FIOPAD_N33_REG0_OFFSET 0x01A0U +#define FIOPAD_L33_REG0_OFFSET 0x01A4U +#define FIOPAD_N45_REG0_OFFSET 0x01A8U +#define FIOPAD_N43_REG0_OFFSET 0x01ACU +#define FIOPAD_L31_REG0_OFFSET 0x01B0U +#define FIOPAD_J31_REG0_OFFSET 0x01B4U +#define FIOPAD_J29_REG0_OFFSET 0x01B8U +#define FIOPAD_E29_REG0_OFFSET 0x01BCU +#define FIOPAD_G29_REG0_OFFSET 0x01C0U +#define FIOPAD_N27_REG0_OFFSET 0x01C4U +#define FIOPAD_L29_REG0_OFFSET 0x01C8U +#define FIOPAD_J37_REG0_OFFSET 0x01CCU +#define FIOPAD_J39_REG0_OFFSET 0x01D0U +#define FIOPAD_G41_REG0_OFFSET 0x01D4U +#define FIOPAD_E43_REG0_OFFSET 0x01D8U +#define FIOPAD_L43_REG0_OFFSET 0x01DCU +#define FIOPAD_C43_REG0_OFFSET 0x01E0U +#define FIOPAD_E41_REG0_OFFSET 0x01E4U +#define FIOPAD_L45_REG0_OFFSET 0x01E8U +#define FIOPAD_J43_REG0_OFFSET 0x01ECU +#define FIOPAD_J41_REG0_OFFSET 0x01F0U +#define FIOPAD_L39_REG0_OFFSET 0x01F4U +#define FIOPAD_E37_REG0_OFFSET 0x01F8U +#define FIOPAD_E35_REG0_OFFSET 0x01FCU +#define FIOPAD_G35_REG0_OFFSET 0x0200U +#define FIOPAD_J35_REG0_OFFSET 0x0204U +#define FIOPAD_L37_REG0_OFFSET 0x0208U +#define FIOPAD_N35_REG0_OFFSET 0x020CU +#define FIOPAD_R51_REG0_OFFSET 0x0210U +#define FIOPAD_R49_REG0_OFFSET 0x0214U +#define FIOPAD_N51_REG0_OFFSET 0x0218U +#define FIOPAD_N55_REG0_OFFSET 0x021CU +#define FIOPAD_L55_REG0_OFFSET 0x0220U +#define FIOPAD_J55_REG0_OFFSET 0x0224U +#define FIOPAD_J45_REG0_OFFSET 0x0228U +#define FIOPAD_E47_REG0_OFFSET 0x022CU +#define FIOPAD_G47_REG0_OFFSET 0x0230U +#define FIOPAD_J47_REG0_OFFSET 0x0234U +#define FIOPAD_J49_REG0_OFFSET 0x0238U +#define FIOPAD_N49_REG0_OFFSET 0x023CU +#define FIOPAD_L51_REG0_OFFSET 0x0240U +#define FIOPAD_L49_REG0_OFFSET 0x0244U +#define FIOPAD_N53_REG0_OFFSET 0x0248U +#define FIOPAD_J53_REG0_OFFSET 0x024CU + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN59_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J53_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ55_REG1_OFFSET 0x1024U +#define FIOPAD_AL55_REG1_OFFSET 0x1028U +#define FIOPAD_AL53_REG1_OFFSET 0x102CU +#define FIOPAD_AN51_REG1_OFFSET 0x1030U +#define FIOPAD_AR51_REG1_OFFSET 0x1034U +#define FIOPAD_AJ57_REG1_OFFSET 0x1058U +#define FIOPAD_AG59_REG1_OFFSET 0x105CU +#define FIOPAD_AG57_REG1_OFFSET 0x1060U +#define FIOPAD_AE59_REG1_OFFSET 0x1064U +#define FIOPAD_BA55_REG1_OFFSET 0x1074U +#define FIOPAD_BA53_REG1_OFFSET 0x1078U +#define FIOPAD_AR59_REG1_OFFSET 0x107CU +#define FIOPAD_AU59_REG1_OFFSET 0x1080U +#define FIOPAD_A45_REG1_OFFSET 0x10D0U +#define FIOPAD_C45_REG1_OFFSET 0x10D4U +#define FIOPAD_A47_REG1_OFFSET 0x10D8U +#define FIOPAD_A49_REG1_OFFSET 0x10DCU +#define FIOPAD_C49_REG1_OFFSET 0x10E0U +#define FIOPAD_A51_REG1_OFFSET 0x10E4U +#define FIOPAD_A33_REG1_OFFSET 0x10E8U +#define FIOPAD_C33_REG1_OFFSET 0x10ECU +#define FIOPAD_C31_REG1_OFFSET 0x10F0U +#define FIOPAD_A31_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ53_REG1_OFFSET 0x10F8U +#define FIOPAD_AL49_REG1_OFFSET 0x10FCU +#define FIOPAD_AL47_REG1_OFFSET 0x1100U +#define FIOPAD_AN49_REG1_OFFSET 0x1104U +#define FIOPAD_AG51_REG1_OFFSET 0x1108U +#define FIOPAD_AJ51_REG1_OFFSET 0x110CU +#define FIOPAD_AG49_REG1_OFFSET 0x1110U +#define FIOPAD_AE55_REG1_OFFSET 0x1114U +#define FIOPAD_AE53_REG1_OFFSET 0x1118U +#define FIOPAD_AG55_REG1_OFFSET 0x111CU +#define FIOPAD_AJ49_REG1_OFFSET 0x1120U +#define FIOPAD_AC55_REG1_OFFSET 0x1124U +#define FIOPAD_AC53_REG1_OFFSET 0x1128U +#define FIOPAD_AE51_REG1_OFFSET 0x112CU +#define FIOPAD_W51_REG1_OFFSET 0x1130U +#define FIOPAD_W53_REG1_OFFSET 0x1138U +#define FIOPAD_U55_REG1_OFFSET 0x113CU +#define FIOPAD_U53_REG1_OFFSET 0x1140U +#define FIOPAD_AE49_REG1_OFFSET 0x1144U +#define FIOPAD_AC49_REG1_OFFSET 0x1148U +#define FIOPAD_AE47_REG1_OFFSET 0x114CU +#define FIOPAD_AA47_REG1_OFFSET 0x1150U +#define FIOPAD_AA49_REG1_OFFSET 0x1154U +#define FIOPAD_W49_REG1_OFFSET 0x1158U +#define FIOPAD_AA51_REG1_OFFSET 0x115CU +#define FIOPAD_U49_REG1_OFFSET 0x1160U +#define FIOPAD_J59_REG1_OFFSET 0x1168U +#define FIOPAD_L57_REG1_OFFSET 0x116CU +#define FIOPAD_C59_REG1_OFFSET 0x1170U +#define FIOPAD_E59_REG1_OFFSET 0x1174U +#define FIOPAD_J57_REG1_OFFSET 0x1178U +#define FIOPAD_L59_REG1_OFFSET 0x117CU +#define FIOPAD_N59_REG1_OFFSET 0x1180U +#define FIOPAD_E31_REG1_OFFSET 0x118CU +#define FIOPAD_G31_REG1_OFFSET 0x1190U +#define FIOPAD_N41_REG1_OFFSET 0x1194U +#define FIOPAD_N39_REG1_OFFSET 0x1198U +#define FIOPAD_J33_REG1_OFFSET 0x119CU +#define FIOPAD_N33_REG1_OFFSET 0x11A0U +#define FIOPAD_L33_REG1_OFFSET 0x11A4U +#define FIOPAD_N45_REG1_OFFSET 0x11A8U +#define FIOPAD_N43_REG1_OFFSET 0x11ACU +#define FIOPAD_L31_REG1_OFFSET 0x11B0U +#define FIOPAD_J31_REG1_OFFSET 0x11B4U +#define FIOPAD_J29_REG1_OFFSET 0x11B8U +#define FIOPAD_E29_REG1_OFFSET 0x11BCU +#define FIOPAD_G29_REG1_OFFSET 0x11C0U +#define FIOPAD_J37_REG1_OFFSET 0x11CCU +#define FIOPAD_J39_REG1_OFFSET 0x11D0U +#define FIOPAD_G41_REG1_OFFSET 0x11D4U +#define FIOPAD_E43_REG1_OFFSET 0x11D8U +#define FIOPAD_L43_REG1_OFFSET 0x11DCU +#define FIOPAD_C43_REG1_OFFSET 0x11E0U +#define FIOPAD_E41_REG1_OFFSET 0x11E4U +#define FIOPAD_L45_REG1_OFFSET 0x11E8U +#define FIOPAD_J43_REG1_OFFSET 0x11ECU +#define FIOPAD_J41_REG1_OFFSET 0x11F0U +#define FIOPAD_L39_REG1_OFFSET 0x11F4U +#define FIOPAD_E37_REG1_OFFSET 0x11F8U +#define FIOPAD_E35_REG1_OFFSET 0x11FCU +#define FIOPAD_G35_REG1_OFFSET 0x1200U +#define FIOPAD_L55_REG1_OFFSET 0x1220U +#define FIOPAD_J55_REG1_OFFSET 0x1224U +#define FIOPAD_J45_REG1_OFFSET 0x1228U +#define FIOPAD_E47_REG1_OFFSET 0x122CU +#define FIOPAD_G47_REG1_OFFSET 0x1230U +#define FIOPAD_J47_REG1_OFFSET 0x1234U +#define FIOPAD_J49_REG1_OFFSET 0x1238U +#define FIOPAD_N49_REG1_OFFSET 0x123CU +#define FIOPAD_L51_REG1_OFFSET 0x1240U +#define FIOPAD_L49_REG1_OFFSET 0x1244U +#define FIOPAD_N53_REG1_OFFSET 0x1248U +#define FIOPAD_J53_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ55_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J53_REG1_OFFSET + +#ifdef __cplusplus +} + +#endif + +#endif \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/soc/phytiumpi/fparameters_comm.h b/bsps/aarch64/phytium/include/soc/phytiumpi/fparameters_comm.h new file mode 100644 index 0000000000..36cbfe2f75 --- /dev/null +++ b/bsps/aarch64/phytium/include/soc/phytiumpi/fparameters_comm.h @@ -0,0 +1,718 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fparameters_comm.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 18:01:11 + * Description:  This file is for + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + */ + +#ifndef PHYTIUMPI_FPARAMETERS_COMMON_H +#define PHYTIUMPI_FPARAMETERS_COMMON_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************** Include Files *********************************/ + +/************************** Constant Definitions *****************************/ +/* CACHE */ +#define CACHE_LINE_ADDR_MASK 0x3FUL +#define CACHE_LINE 64U + +/* DEVICE Register Address */ +#define FT_DEV_BASE_ADDR 0x28000000U +#define FT_DEV_END_ADDR 0x2FFFFFFFU + +/* PCI */ +#define FPCIE_NUM 1 +#define FPCIE0_ID 0 +#define FPCIE0_MISC_IRQ_NUM 40 + +#define FPCIE_CFG_MAX_NUM_OF_BUS 256 +#define FPCIE_CFG_MAX_NUM_OF_DEV 32 +#define FPCIE_CFG_MAX_NUM_OF_FUN 8 + +#define FPCI_CONFIG_BASE_ADDR 0x40000000U +#define FPCI_CONFIG_REG_LENGTH 0x10000000U + +#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000U +#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000U + +#define FPCI_MEM32_BASE_ADDR 0x58000000U +#define FPCI_MEM32_REG_LENGTH 0x27FFFFFFU + +#define FPCI_MEM64_BASE_ADDR 0x1000000000U +#define FPCI_MEM64_REG_LENGTH 0x1000000000U + +#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29000000U +#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29010000U +#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29020000U +#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29030000U +#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29040000U +#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29050000U + +#define FPCI_EU0_CONFIG_BASE_ADDR 0x29100000U +#define FPCI_EU1_CONFIG_BASE_ADDR 0x29101000U + +#define FPCI_INTA_IRQ_NUM 36 +#define FPCI_INTB_IRQ_NUM 37 +#define FPCI_INTC_IRQ_NUM 38 +#define FPCI_INTD_IRQ_NUM 39 + +#define FPCI_NEED_SKIP 0 + +#define FPCI_INTX_PEU0_STAT 0x29100000U +#define FPCI_INTX_PEU1_STAT 0x29101000U + +#define FPCI_INTX_EU0_C0_CONTROL 0x29000184U +#define FPCI_INTX_EU0_C1_CONTROL 0x29010184U +#define FPCI_INTX_EU0_C2_CONTROL 0x29020184U +#define FPCI_INTX_EU1_C0_CONTROL 0x29030184U +#define FPCI_INTX_EU1_C1_CONTROL 0x29040184U +#define FPCI_INTX_EU1_C2_CONTROL 0x29050184U + +#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */ +#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */ + + +/* platform ahci host */ +#define PLAT_AHCI_HOST_MAX_COUNT 5 +#define AHCI_BASE_0 0 +#define AHCI_BASE_1 0 +#define AHCI_BASE_2 0 +#define AHCI_BASE_3 0 +#define AHCI_BASE_4 0 + +#define AHCI_IRQ_0 0 +#define AHCI_IRQ_1 0 +#define AHCI_IRQ_2 0 +#define AHCI_IRQ_3 0 +#define AHCI_IRQ_4 0 + +/* sata controller */ +#define FSATA0_BASE_ADDR 0x31A40000U +#define FSATA1_BASE_ADDR 0x32014000U + +#define FSATA0_IRQ_NUM 74 +#define FSATA1_IRQ_NUM 75 + + +#define FSATA0_ID 0 +#define FSATA1_ID 1 +#define FSATA_NUM 2 + +/* SCMI and MHU */ +#define FSCMI_MHU_BASE_ADDR 0x32a00000 +#define FSCMI_MHU_IRQ_NUM (22U + 32U) +#define FSCMI_SHR_MEM_ADDR 0x32a11400 +#define FSCMI_MEM_TX_OFSET 0x1400 +#define FSCMI_MEM_RX_OFSET 0x1000 +#define FSCMI_SHR_MEM_SIZE 0x400 + +#define FSCMI_MSG_SIZE 128 +#define FSCMI_MAX_STR_SIZE 16 +#define FSCMI_MAX_NUM_SENSOR 16 +#define FSCMI_MAX_PROTOCOLS_IMP 16 +#define FSCMI_MAX_PERF_DOMAINS 3 +#define FSCMI_MAX_OPPS 4 + +/* UART */ +#define FUART_NUM 4U +#define FUART_REG_LENGTH 0x18000U + +#define FUART0_ID 0U +#define FUART0_IRQ_NUM (85 + 30) +#define FUART0_BASE_ADDR 0x2800c000U +#define FUART0_CLK_FREQ_HZ 100000000U + +#define FUART1_ID 1U +#define FUART1_IRQ_NUM (86 + 30) +#define FUART1_BASE_ADDR 0x2800d000U +#define FUART1_CLK_FREQ_HZ 100000000U + +#define FUART2_ID 2U +#define FUART2_IRQ_NUM (87 + 30) +#define FUART2_BASE_ADDR 0x2800e000U +#define FUART2_CLK_FREQ_HZ 100000000U + +#define FUART3_BASE_ADDR 0x2800f000U +#define FUART3_ID 3U +#define FUART3_IRQ_NUM (88 + 30) +#define FUART3_CLK_FREQ_HZ 100000000U + +#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR +#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR + +/****** GIC v3 *****/ +#define FT_GICV3_INSTANCES_NUM 1U +#define GICV3_REG_LENGTH 0x00009000U + +/* + * The maximum priority value that can be used in the GIC. + */ +#define GICV3_MAX_INTR_PRIO_VAL 240U +#define GICV3_INTR_PRIO_MASK 0x000000f0U + +#define ARM_GIC_NR_IRQS 270U +#define ARM_GIC_IRQ_START 0U +#define FGIC_NUM 1U + +#define ARM_GIC_IPI_COUNT 16U /* MPCore IPI count */ +#define SGI_INT_MAX 16U +#define SPI_START_INT_NUM 32U /* SPI start at ID32 */ +#define PPI_START_INT_NUM 16U /* PPI start at ID16 */ +#define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */ + +#define GICV3_BASE_ADDR 0x30800000U +#define GICV3_ITS_BASE_ADDR 0x30820000U +#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) +#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U) +#define GICV3_RD_OFFSET (2U << 16) +#define GICV3_RD_SIZE (8U << 16) + +/* GPIO */ +#define FGPIO0_BASE_ADDR 0x28034000U +#define FGPIO1_BASE_ADDR 0x28035000U +#define FGPIO2_BASE_ADDR 0x28036000U +#define FGPIO3_BASE_ADDR 0x28037000U +#define FGPIO4_BASE_ADDR 0x28038000U +#define FGPIO5_BASE_ADDR 0x28039000U + +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_2 2 +#define FGPIO_CTRL_3 3 +#define FGPIO_CTRL_4 4 +#define FGPIO_CTRL_5 5 +#define FGPIO_CTRL_NUM 6U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_NUM 1U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_8 8U +#define FGPIO_PIN_9 9U +#define FGPIO_PIN_10 10U +#define FGPIO_PIN_11 11U +#define FGPIO_PIN_12 12U +#define FGPIO_PIN_13 13U +#define FGPIO_PIN_14 14U +#define FGPIO_PIN_15 15U +#define FGPIO_PIN_NUM 16U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((FGPIO_PORT_A) * FGPIO_PIN_NUM) + (pin)) + +/* SPI */ +#define FSPI0_BASE_ADDR 0x2803A000U +#define FSPI1_BASE_ADDR 0x2803B000U +#define FSPI2_BASE_ADDR 0x2803C000U +#define FSPI3_BASE_ADDR 0x2803D000U +#define FSPI0_ID 0U +#define FSPI1_ID 1U +#define FSPI2_ID 2U +#define FSPI3_ID 3U + +#define FSPI0_IRQ_NUM 191U +#define FSPI1_IRQ_NUM 192U +#define FSPI2_IRQ_NUM 193U +#define FSPI3_IRQ_NUM 194U + +#define FSPI_CLK_FREQ_HZ 50000000U +#define FSPI_NUM 4U + +#define FSPI_DMA_CAPACITY BIT(0) +#define FSPIM0_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM1_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM2_DMA_CAPACITY FSPI_DMA_CAPACITY +#define FSPIM3_DMA_CAPACITY FSPI_DMA_CAPACITY + +/* XMAC */ +#define FXMAC_NUM 4U + +#define FXMAC0_ID 0U +#define FXMAC1_ID 1U +#define FXMAC2_ID 2U +#define FXMAC3_ID 3U + +#define FXMAC0_BASE_ADDR 0x3200C000U +#define FXMAC1_BASE_ADDR 0x3200E000U +#define FXMAC2_BASE_ADDR 0x32010000U +#define FXMAC3_BASE_ADDR 0x32012000U + +#define FXMAC0_MODE_SEL_BASE_ADDR 0x3200DC00U +#define FXMAC0_LOOPBACK_SEL_BASE_ADDR 0x3200DC04U +#define FXMAC1_MODE_SEL_BASE_ADDR 0x3200FC00U +#define FXMAC1_LOOPBACK_SEL_BASE_ADDR 0x3200FC04U +#define FXMAC2_MODE_SEL_BASE_ADDR 0x32011C00U +#define FXMAC2_LOOPBACK_SEL_BASE_ADDR 0x32011C04U +#define FXMAC3_MODE_SEL_BASE_ADDR 0x32013C00U +#define FXMAC3_LOOPBACK_SEL_BASE_ADDR 0x32013C04U + +#define FXMAC0_PCLK 50000000U +#define FXMAC1_PCLK 50000000U +#define FXMAC2_PCLK 50000000U +#define FXMAC3_PCLK 50000000U +#define FXMAC0_HOTPLUG_IRQ_NUM (53U + 30U) +#define FXMAC1_HOTPLUG_IRQ_NUM (54U + 30U) +#define FXMAC2_HOTPLUG_IRQ_NUM (55U + 30U) +#define FXMAC3_HOTPLUG_IRQ_NUM (56U + 30U) + +#define FXMAC_QUEUE_MAX_NUM 16U + +#define FXMAC0_QUEUE0_IRQ_NUM (57U + 30U) +#define FXMAC0_QUEUE1_IRQ_NUM (58U + 30U) +#define FXMAC0_QUEUE2_IRQ_NUM (59U + 30U) +#define FXMAC0_QUEUE3_IRQ_NUM (60U + 30U) +#define FXMAC0_QUEUE4_IRQ_NUM (30U + 30U) +#define FXMAC0_QUEUE5_IRQ_NUM (31U + 30U) +#define FXMAC0_QUEUE6_IRQ_NUM (32U + 30U) +#define FXMAC0_QUEUE7_IRQ_NUM (33U + 30U) + +#define FXMAC1_QUEUE0_IRQ_NUM (61U + 30U) +#define FXMAC1_QUEUE1_IRQ_NUM (62U + 30U) +#define FXMAC1_QUEUE2_IRQ_NUM (63U + 30U) +#define FXMAC1_QUEUE3_IRQ_NUM (64U + 30U) + +#define FXMAC2_QUEUE0_IRQ_NUM (66U + 30U) +#define FXMAC2_QUEUE1_IRQ_NUM (67U + 30U) +#define FXMAC2_QUEUE2_IRQ_NUM (68U + 30U) +#define FXMAC2_QUEUE3_IRQ_NUM (69U + 30U) + +#define FXMAC3_QUEUE0_IRQ_NUM (70U + 30U) +#define FXMAC3_QUEUE1_IRQ_NUM (71U + 30U) +#define FXMAC3_QUEUE2_IRQ_NUM (72U + 30U) +#define FXMAC3_QUEUE3_IRQ_NUM (73U + 30U) + +#define FXMAC_PHY_MAX_NUM 32U + +#define FXMAC_CLK_TYPE_0 + +/* IOPAD */ + +#define FIOPAD0_ID 0 +#define FIOPAD_NUM 1 + +/* QSPI */ +#define FQSPI0_ID 0 +#define FQSPI_NUM 1 + +/* FQSPI cs 0_3, chip number */ + +#define FQSPI_CS_0 0 +#define FQSPI_CS_1 1 +#define FQSPI_CS_2 2 +#define FQSPI_CS_3 3 +#define FQSPI_CS_NUM 4 + +#define FQSPI_BASE_ADDR 0x028008000U + +#define FQSPI_MEM_START_ADDR 0x0U +#define FQSPI_MEM_END_ADDR 0x0FFFFFFFU /* 256MB */ +#define FQSPI_MEM_START_ADDR_64 0x100000000U +#define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */ + +/* TIMER and TACHO */ +#define FTIMER_NUM 38U +#define FTIMER_CLK_FREQ_HZ 50000000ULL /* 50MHz */ +#define FTIMER_TICK_PERIOD_NS 20U /* 20ns */ +#define FTIMER_TACHO_IRQ_NUM(n) (226U + (n)) +#define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n)) + +#define FTACHO0_ID 0 +#define FTACHO1_ID 1 +#define FTACHO2_ID 2 +#define FTACHO3_ID 3 +#define FTACHO4_ID 4 +#define FTACHO5_ID 5 +#define FTACHO6_ID 6 +#define FTACHO7_ID 7 +#define FTACHO8_ID 8 +#define FTACHO9_ID 9 +#define FTACHO10_ID 10 +#define FTACHO11_ID 11 +#define FTACHO12_ID 12 +#define FTACHO13_ID 13 +#define FTACHO14_ID 14 +#define FTACHO15_ID 15 +#define FTACHO_NUM 16 + + +/* GDMA */ +#define FGDMA0_ID 0U +#define FGDMA0_BASE_ADDR 0x32B34000U +#define FGDMA0_CHANNEL0_IRQ_NUM 266U +#define FGDMA_NUM_OF_CHAN 16 +#define FGDMA_INSTANCE_NUM 1U +#define FGDMA0_CAPACITY (1U<<0) + +/* CANFD */ +#define FCAN_CLK_FREQ_HZ 200000000U + +#define FCAN0_BASE_ADDR 0x2800A000U +#define FCAN1_BASE_ADDR 0x2800B000U + +#define FCAN0_IRQ_NUM 113U +#define FCAN1_IRQ_NUM 114U + +#define FCAN0_ID 0 +#define FCAN1_ID 1 +#define FCAN_NUM 2 + +/* can capacity */ +#define FCAN_FD_CAPACITY BIT(0) /* Whether canfd is supported */ +#define FCAN_CAPACITY FCAN_FD_CAPACITY + +/* WDT */ +#define FWDT0_ID 0 +#define FWDT1_ID 1 +#define FWDT_NUM 2 + +#define FWDT0_REFRESH_BASE_ADDR 0x28040000U +#define FWDT1_REFRESH_BASE_ADDR 0x28042000U + +#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) + +#define FWDT0_IRQ_NUM 196U +#define FWDT1_IRQ_NUM 197U + +#define FWDT_CLK_FREQ_HZ 48000000U /* 48MHz */ + +/*MIO*/ +#define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n)) +#define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000 +#define FMIO_IRQ_NUM(n) (124+n) +#define FMIO_CLK_FREQ_HZ 50000000 /* 50MHz */ + +#define FMIO0_ID 0 +#define FMIO1_ID 1 +#define FMIO2_ID 2 +#define FMIO3_ID 3 +#define FMIO4_ID 4 +#define FMIO5_ID 5 +#define FMIO6_ID 6 +#define FMIO7_ID 7 +#define FMIO8_ID 8 +#define FMIO9_ID 9 +#define FMIO10_ID 10 +#define FMIO11_ID 11 +#define FMIO12_ID 12 +#define FMIO13_ID 13 +#define FMIO14_ID 14 +#define FMIO15_ID 15 +#define FMIO_NUM 16 + +/*I2C0 -> PMBUS0 +* I2C1 -> PMBUS1 +* I2C2 -> SMBUS0 +*/ +#define FI2C0_ID 0 +#define FI2C1_ID 1 +#define FI2C2_ID 2 +#define FI2C_NUM 3 + +#define FI2C0_BASE_ADDR 0x28011000 +#define FI2C1_BASE_ADDR 0x28012000 +#define FI2C2_BASE_ADDR 0x28013000 + +#define FI2C0_IRQ_NUM 121 +#define FI2C1_IRQ_NUM 122 +#define FI2C2_IRQ_NUM 123 + +#define FI2C_CLK_FREQ_HZ 50000000 /* 50MHz */ + +/* SDIF */ +#define FSDIF0_ID 0 +#define FSDIF1_ID 1 +#define FSDIF_NUM 2 + + +#define FSDIF0_BASE_ADDR 0x28000000U +#define FSDIF1_BASE_ADDR 0x28001000U + +#define FSDIF0_IRQ_NUM 104U +#define FSDIF1_IRQ_NUM 105U + +#define FSDIF_CLK_FREQ_HZ (1200000000UL) /* 1.2GHz */ + +/* NAND */ +#define FNAND_NUM 1U +#define FNAND_INSTANCE0 0U +#define FNAND_BASE_ADDR 0x28002000U +#define FNAND_IRQ_NUM (106U) +#define FNAND_CONNECT_MAX_NUM 1U + +#define FIOPAD_BASE_ADDR 0x32B30000U +/* DDMA */ +#define FDDMA0_ID 0U +#define FDDMA0_BASE_ADDR 0x28003000U +#define FDDMA0_IRQ_NUM 107U +#define FDDMA0_CAPACITY (1U<<1) + +#define FDDMA1_ID 1U +#define FDDMA1_BASE_ADDR 0x28004000U +#define FDDMA1_IRQ_NUM 108U +#define FDDMA1_CAPACITY (1U<<1) + +#define FDDMA2_I2S_ID 2U +#define FDDMA2_BASE_ADDR 0x28005000U +#define FDDMA2_IRQ_NUM 109U +#define FDDMA2_CAPACITY (1U<<0) + +#define FDDMA3_DP0_I2S_ID 3U +#define FDDMA3_BASE_ADDR 0x32008000U +#define FDDMA3_IRQ_NUM 79U +#define FDDMA3_CAPACITY (1U<<0) + +#define FDDMA4_DP1_I2S_ID 4U +#define FDDMA4_BASE_ADDR 0x3200A000U +#define FDDMA4_IRQ_NUM 80U +#define FDDMA4_CAPACITY (1U<<0) + +#define FDDMA_INSTANCE_NUM 5U + +#define FDDMA0_UART0_TX_SLAVE_ID 2U /* uart0 tx slave-id */ +#define FDDMA0_UART1_TX_SLAVE_ID 3U /* uart1 tx slave-id */ +#define FDDMA0_UART2_TX_SLAVE_ID 4U /* uart2 tx slave-id */ +#define FDDMA0_UART3_TX_SLAVE_ID 5U /* uart3 tx slave-id */ + +#define FDDMA0_SPIM0_TX_SLAVE_ID 6U /* spi0 tx slave-id */ +#define FDDMA0_SPIM1_TX_SLAVE_ID 7U /* spi1 tx slave-id */ +#define FDDMA0_SPIM2_TX_SLAVE_ID 8U /* spi2 tx slave-id */ +#define FDDMA0_SPIM3_TX_SLAVE_ID 9U /* spi3 tx slave-id */ + +#define FDDMA0_UART0_RX_SLAVE_ID 15U /* uart0 rx slave-id */ +#define FDDMA0_UART1_RX_SLAVE_ID 16U /* uart1 rx slave-id */ +#define FDDMA0_UART2_RX_SLAVE_ID 17U /* uart2 rx slave-id */ +#define FDDMA0_UART3_RX_SLAVE_ID 18U /* uart3 rx slave-id */ + +#define FDDMA0_SPIM0_RX_SLAVE_ID 19U /* spi0 rx slave-id */ +#define FDDMA0_SPIM1_RX_SLAVE_ID 20U /* spi1 rx slave-id */ +#define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */ +#define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */ + +/* FDDMA1_ID */ +#define FDDMA1_MIO0_TX_SLAVE_ID 0U /* mio0 rx slave-id */ +#define FDDMA1_MIO1_TX_SLAVE_ID 1U /* mio1 rx slave-id */ +#define FDDMA1_MIO2_TX_SLAVE_ID 2U /* mio2 rx slave-id */ +#define FDDMA1_MIO3_TX_SLAVE_ID 3U /* mio3 rx slave-id */ +#define FDDMA1_MIO4_TX_SLAVE_ID 4U /* mio4 rx slave-id */ +#define FDDMA1_MIO5_TX_SLAVE_ID 5U /* mio5 rx slave-id */ +#define FDDMA1_MIO6_TX_SLAVE_ID 6U /* mio6 rx slave-id */ +#define FDDMA1_MIO7_TX_SLAVE_ID 7U /* mio7 rx slave-id */ +#define FDDMA1_MIO8_TX_SLAVE_ID 8U /* mio8 rx slave-id */ +#define FDDMA1_MIO9_TX_SLAVE_ID 9U /* mio9 rx slave-id */ +#define FDDMA1_MIO10_TX_SLAVE_ID 10U /* mio10 rx slave-id */ +#define FDDMA1_MIO11_TX_SLAVE_ID 11U /* mio11 rx slave-id */ +#define FDDMA1_MIO12_TX_SLAVE_ID 12U /* mio12 rx slave-id */ +#define FDDMA1_MIO13_TX_SLAVE_ID 13U /* mio13 rx slave-id */ +#define FDDMA1_MIO14_TX_SLAVE_ID 14U /* mio14 rx slave-id */ +#define FDDMA1_MIO15_TX_SLAVE_ID 15U /* mio15 rx slave-id */ + +#define FDDMA1_MIO0_RX_SLAVE_ID 16U /* mio0 tx slave-id */ +#define FDDMA1_MIO1_RX_SLAVE_ID 17U /* mio1 tx slave-id */ +#define FDDMA1_MIO2_RX_SLAVE_ID 18U /* mio2 tx slave-id */ +#define FDDMA1_MIO3_RX_SLAVE_ID 19U /* mio3 tx slave-id */ +#define FDDMA1_MIO4_RX_SLAVE_ID 20U /* mio4 tx slave-id */ +#define FDDMA1_MIO5_RX_SLAVE_ID 21U /* mio5 tx slave-id */ +#define FDDMA1_MIO6_RX_SLAVE_ID 22U /* mio6 tx slave-id */ +#define FDDMA1_MIO7_RX_SLAVE_ID 23U /* mio7 tx slave-id */ +#define FDDMA1_MIO8_RX_SLAVE_ID 24U /* mio8 tx slave-id */ +#define FDDMA1_MIO9_RX_SLAVE_ID 25U /* mio9 tx slave-id */ +#define FDDMA1_MIO10_RX_SLAVE_ID 26U /* mio10 tx slave-id */ +#define FDDMA1_MIO11_RX_SLAVE_ID 27U /* mio11 tx slave-id */ +#define FDDMA1_MIO12_RX_SLAVE_ID 28U /* mio12 tx slave-id */ +#define FDDMA1_MIO13_RX_SLAVE_ID 29U /* mio13 tx slave-id */ +#define FDDMA1_MIO14_RX_SLAVE_ID 30U /* mio14 tx slave-id */ +#define FDDMA1_MIO15_RX_SLAVE_ID 31U /* mio15 tx slave-id */ + +#define FDDMA_MIN_SLAVE_ID 0U +#define FDDMA_MAX_SLAVE_ID 31U + +/* ADC */ +#define FADC0_ID 0 +#define FADC_NUM 1 + +#if !defined(__ASSEMBLER__) +typedef enum +{ + FADC_CHANNEL_0 = 0, + FADC_CHANNEL_1 = 1, + FADC_CHANNEL_2, + FADC_CHANNEL_3, + FADC_CHANNEL_4, + FADC_CHANNEL_5, + FADC_CHANNEL_6, + FADC_CHANNEL_7, + + FADC_CHANNEL_NUM +} FAdcChannel; +#endif + +#define FADC0_BASE_ADDR 0x2807B000U + +#define FADC0_IRQ_NUM 264U + +/* PWM */ +#define FPWM0_ID 0 +#define FPWM1_ID 1 +#define FPWM2_ID 2 +#define FPWM3_ID 3 +#define FPWM_NUM 4 + +#define FPWM_CHANNEL_0 0 +#define FPWM_CHANNEL_1 1 +#define FPWM_CHANNEL_NUM 2 + +#define FPWM_BASE_ADDR 0x2804A000U + +#define FPWM_CLK_FREQ_HZ 50000000U /* 50MHz */ + +#define FPWM0_IRQ_NUM 205U +#define FPWM1_IRQ_NUM 206U +#define FPWM2_IRQ_NUM 207U +#define FPWM3_IRQ_NUM 208U +#define FPWM4_IRQ_NUM 209U +#define FPWM5_IRQ_NUM 210U +#define FPWM6_IRQ_NUM 211U +#define FPWM7_IRQ_NUM 212U + +#define FPWM_CYCLE_PROCESSING(reg_val) ((reg_val) - 0x1) + +/* Semaphore */ +#define FSEMA0_ID 0U +#define FSEMA0_BASE_ADDR 0x32B36000U +#define FSEMA_INSTANCE_NUM 1U + +/* LSD Config */ +#define FLSD_CONFIG_BASE 0x2807E000U +#define FLSD_NAND_MMCSD_HADDR 0xC0U +#define FLSD_CK_STOP_CONFIG0_HADDR 0x10U +#define FLSD_PWM_HADDR 0x20 /* bit0-bit7 corresponds to pwm0-pwm7 */ + +/* USB3 */ +#define FUSB3_ID_0 0U +#define FUSB3_ID_1 1U +#define FUSB3_NUM 2U +#define FUSB3_XHCI_OFFSET 0x8000U +#define FUSB3_0_BASE_ADDR 0x31A00000U +#define FUSB3_1_BASE_ADDR 0x31A20000U +#define FUSB3_0_IRQ_NUM 48U +#define FUSB3_1_IRQ_NUM 49U + +/* DcDp */ + +#define FDCDP_ID0 0 +#define FDCDP_ID1 1 + +#define FDCDP_INSTANCE_NUM 2 + +#define FDC_CTRL_BASE_OFFSET 0x32000000U + +#define FDC0_CHANNEL_BASE_OFFSET 0x32001000U +#define FDC1_CHANNEL_BASE_OFFSET (FDC0_CHANNEL_BASE_OFFSET + 0x1000U) + +#define FDP0_CHANNEL_BASE_OFFSET 0x32004000U +#define FDP1_CHANNEL_BASE_OFFSET (FDP0_CHANNEL_BASE_OFFSET + 0x1000U) + +#define FDP0_PHY_BASE_OFFSET 0x32300000U +#define FDP1_PHY_BASE_OFFSET (FDP0_PHY_BASE_OFFSET + 0x100000U) + +#define FDCDP_IRQ_NUM 76 + +/* generic timer */ +/* non-secure physical timer int id */ +#define GENERIC_TIMER_NS_IRQ_NUM 30U + +/* virtual timer int id */ +#define GENERIC_VTIMER_IRQ_NUM 27U + +#define GENERIC_TIMER_ID0 0 /* non-secure physical timer */ +#define GENERIC_TIMER_ID1 1 /* virtual timer */ +#define GENERIC_TIMER_NUM 2 + +/* PMU */ +#define FPMU_IRQ_NUM 23 + +/* USB2 OTG */ +#if !defined(__ASSEMBLER__) + +enum +{ + FUSB2_ID_VHUB_0 = 0, + FUSB2_ID_1, + FUSB2_ID_2, + FUSB2_ID_VHUB_1, + FUSB2_ID_VHUB_2, + + FUSB2_INSTANCE_NUM +}; + +#endif + +#define FUSB2_0_VHUB_BASE_ADDR 0x31800000U +#define FUSB2_1_VHUB_BASE_ADDR 0x31880000U +#define FUSB2_2_VHUB_BASE_ADDR 0x31900000U + +#define FUSB2_VHUB_CFG_BASE_ADDR 0x319C0000U +#define FUSB2_DEV_1_CFG_BASE_ADDR 0x31990000U +#define FUSB2_DEV_2_CFG_BASE_ADDR 0x319A0000U +#define FUSB2_DEV_3_CFG_BASE_ADDR 0x319B0000U + +#define FUSB2_0_VHUB_IRQ_NUM 64U +#define FUSB2_1_VHUB_IRQ_NUM 65U +#define FUSB2_2_VHUB_IRQ_NUM 66U + +#define FUSB2_0_VHUB_WAKEUP_IRQ_NUM 67U +#define FUSB2_1_VHUB_WAKEUP_IRQ_NUM 68U +#define FUSB2_2_VHUB_WAKEUP_IRQ_NUM 69U + +#define FUSB2_1_BASE_ADDR 0x32800000U +#define FUSB2_2_BASE_ADDR 0x32840000U +#define FUSB2_1_UIB_BASE_ADDR 0x32880000U +#define FUSB2_2_UIB_BASE_ADDR 0x328C0000U +#define FUSB2_MMIO_SIZE 0x00200000U /* 2MB */ + +#define FUSB2_1_IRQ_NUM 46U +#define FUSB2_2_IRQ_NUM 47U + +#define FUSB2_1_WAKEUP_IRQ_NUM 50U +#define FUSB2_2_WAKEUP_IRQ_NUM 51U + +/*****************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif \ No newline at end of file diff --git a/bsps/aarch64/phytium/include/tm27.h b/bsps/aarch64/phytium/include/tm27.h new file mode 100644 index 0000000000..19457e458b --- /dev/null +++ b/bsps/aarch64/phytium/include/tm27.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief BSP tm27 header + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include + +#endif /* __tm27_h */ diff --git a/bsps/aarch64/phytium/start/bspcpuid.S b/bsps/aarch64/phytium/start/bspcpuid.S new file mode 100644 index 0000000000..988e6bda09 --- /dev/null +++ b/bsps/aarch64/phytium/start/bspcpuid.S @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsPhytiumCPUID + * + * @brief Get cpu id. + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .global _ASM_CPU_SMP_Get_current_processor +_ASM_CPU_SMP_Get_current_processor: + mov x9, lr + mrs x0, MPIDR_EL1 + and x1, x0, #15 + + ubfx x0, x0, #0, #12 +#if defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) || \ + defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) + ldr x1, =BSP_CORE2_AFF + cmp x0, x1 + beq core0 + + ldr x1, =BSP_CORE3_AFF + cmp x0, x1 + beq core1 + + ldr x1, =BSP_CORE0_AFF + cmp x0, x1 + beq core2 + + ldr x1, =BSP_CORE1_AFF + cmp x0, x1 + beq core3 + /* PHYTIUM_BSP_TYPE_E2000Q_DEMO */ + /* PHYTIUM_BSP_TYPE_PHYTIUM_PI */ +#elif defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) + ldr x1, =BSP_CORE0_AFF + cmp x0, x1 + beq core0 + + ldr x1, =BSP_CORE1_AFF + cmp x0, x1 + beq core1 + /* PHYTIUM_BSP_TYPE_E2000D_DEMO */ +#elif defined(PHYTIUM_BSP_TYPE_D2000_TEST) + ldr x1, =BSP_CORE0_AFF + cmp x0, x1 + beq core0 + + ldr x1, =BSP_CORE1_AFF + cmp x0, x1 + beq core1 + + ldr x1, =BSP_CORE2_AFF + cmp x0, x1 + beq core2 + + ldr x1, =BSP_CORE3_AFF + cmp x0, x1 + beq core3 + + ldr x1, =BSP_CORE4_AFF + cmp x0, x1 + beq core4 + + ldr x1, =BSP_CORE5_AFF + cmp x0, x1 + beq core5 + + ldr x1, =BSP_CORE6_AFF + cmp x0, x1 + beq core6 + + ldr x1, =BSP_CORE7_AFF + cmp x0, x1 + beq core7 + /* PHYTIUM_BSP_TYPE_D2000_TEST */ +#elif defined(PHYTIUM_BSP_TYPE_FT2004_DSK) + ldr x1, =BSP_CORE0_AFF + cmp x0, x1 + beq core0 + + ldr x1, =BSP_CORE1_AFF + cmp x0, x1 + beq core1 + + ldr x1, =BSP_CORE2_AFF + cmp x0, x1 + beq core2 + + ldr x1, =BSP_CORE3_AFF + cmp x0, x1 + beq core3 + /* PHYTIUM_BSP_TYPE_FT2004_DSK */ +#endif + + b default + +core0: + mov x0, #0 + b return + +core1: + mov x0, #1 + b return + +core2: + mov x0, #2 + b return + +core3: + mov x0, #3 + b return + +core4: + mov x0, #4 + b return + +core5: + mov x0, #5 + b return + +core6: + mov x0, #6 + b return + +core7: + mov x0, #7 + b return + +default: + and x0, x0, #15 + +return: + mov lr, x9 + RET \ No newline at end of file diff --git a/bsps/aarch64/phytium/start/bspl3cache.c b/bsps/aarch64/phytium/start/bspl3cache.c new file mode 100644 index 0000000000..22b3592225 --- /dev/null +++ b/bsps/aarch64/phytium/start/bspl3cache.c @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief BSP L3 Cache operations + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#define HNF_BASE (unsigned long)(0x3A200000) +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 + +void FCacheL3CacheEnable(void); +void FCacheL3CacheDisable(void); +void FCacheL3CacheInvalidate(void); +void FCacheL3CacheFlush(void); + + +void FCacheL3CacheDisable(void) +{ + int i, pstate; + + + for (i = 0; i < 8; i++) + { + FtOut32(0x3A200010 + i * 0x10000, 1); + } + + for (i = 0; i < 8; i++) + { + do + { + pstate = FtIn32(0x3A200018 + i * 0x10000); + } + while ((pstate & 0xf) != (0x1 << 2)); + } +} + + +void FCacheL3CacheFlush(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + { + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + } + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } + while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + { + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); + } + + return ; +} + + +void FCacheL3CacheInvalidate(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + { + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); + } + + for (i = 0; i < HNF_COUNT; i++) + { + do + { + pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); + } + while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + { + FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); + } + + return ; +} + + +void FCacheL3CacheEnable(void) +{ + return ; +} \ No newline at end of file diff --git a/bsps/aarch64/phytium/start/bspreset_watchdog.c b/bsps/aarch64/phytium/start/bspreset_watchdog.c new file mode 100644 index 0000000000..cae265445d --- /dev/null +++ b/bsps/aarch64/phytium/start/bspreset_watchdog.c @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief BSP Shutdown and Reset + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include + +RTEMS_NO_RETURN void bsp_reset(rtems_fatal_source source, rtems_fatal_code code) +{ + uintptr_t watchdog_reg = FWDT_CONTROL_BASE_ADDR(FWDT0_REFRESH_BASE_ADDR); + uint32_t frequency = 0; + uint32_t irq = 0; + + arm_generic_timer_get_config(&frequency, &irq); + (void)irq; + + printk("System reset by watchdog after 3 seconds ...\n"); + FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WOR, 3 * frequency); /* no timeout */ + FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WCS, FWDT_GWDT_WCS_WDT_EN); + + while (true) { + /* wait for watchdog reset */ + } +} + +void rtems_monitor_reset_cmd( + int argc, + char **argv, + const rtems_monitor_command_arg_t* command_arg, + bool verbose +) +{ + uintptr_t watchdog_reg = FWDT_CONTROL_BASE_ADDR(FWDT0_REFRESH_BASE_ADDR); + uint32_t frequency = 0; + uint32_t irq = 0; + + arm_generic_timer_get_config(&frequency, &irq); + (void)irq; + + printk("System reseting ...\n"); + FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WOR, 1 * frequency); /* no timeout */ + FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WCS, FWDT_GWDT_WCS_WDT_EN); + + while (true) { + /* wait for watchdog reset */ + } +} \ No newline at end of file diff --git a/bsps/aarch64/phytium/start/bspsmp.c b/bsps/aarch64/phytium/start/bspsmp.c new file mode 100644 index 0000000000..056e0c73a6 --- /dev/null +++ b/bsps/aarch64/phytium/start/bspsmp.c @@ -0,0 +1,274 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsShared + * + * @brief PSCI-based BSP CPU start. + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include + +#define REGISTER_PREFIX "x" + +typedef struct { + /* cpu affinity */ + uint64_t mpidr; + /* cpu id physically */ + uint32_t phyiscal_id; + /* gic offset */ + void *redist_base; + void *sgi_ppi_base; +} phytium_smp_core_info; + +uint32_t _CPU_SMP_Get_processor_affinity(uint32_t cpu_index); +void _CPU_SMP_Get_processor_affinity_by_mask(uint32_t cpu_mask, uint32_t *cluster_id, uint32_t *target_list); +void *_CPU_SMP_Get_processor_redist(uint32_t cpu_index); +void *_CPU_SMP_Get_processor_sgi_ppi(uint32_t cpu_index); + +#if defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) || \ + defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) +const phytium_smp_core_info BSP_core_info[BSP_CORE_NUM] = +{ + { /* core-0 */ + .mpidr = BSP_CORE2_AFF, /* 0x200U */ + .phyiscal_id = 2, + .redist_base = (void *)BSP_ARM_GIC_RD2_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI2_BASE + }, + { /* core-1 */ + .mpidr = BSP_CORE3_AFF, /* 0x201U */ + .phyiscal_id = 3, + .redist_base = (void *)BSP_ARM_GIC_RD3_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI3_BASE + }, + { /* core-2 */ + .mpidr = BSP_CORE0_AFF, /* 0x000U */ + .phyiscal_id = 0, + .redist_base = (void *)BSP_ARM_GIC_RD0_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI0_BASE + }, + { /* core-3 */ + .mpidr = BSP_CORE1_AFF, /* 0x100U */ + .phyiscal_id = 1, + .redist_base = (void *)BSP_ARM_GIC_RD1_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI1_BASE + }, +}; +#elif defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) +const phytium_smp_core_info BSP_core_info[BSP_CORE_NUM] = +{ + { + .mpidr = BSP_CORE0_AFF, + .phyiscal_id = 0, + .redist_base = (void *)BSP_ARM_GIC_RD0_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI0_BASE + }, + { + .mpidr = BSP_CORE1_AFF, + .phyiscal_id = 1, + .redist_base = (void *)BSP_ARM_GIC_RD1_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI1_BASE + }, +}; +#elif defined(PHYTIUM_BSP_TYPE_D2000_TEST) +const phytium_smp_core_info BSP_core_info[BSP_CORE_NUM] = +{ + { + .mpidr = BSP_CORE0_AFF, + .phyiscal_id = 0, + .redist_base = (void *)BSP_ARM_GIC_RD0_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI0_BASE + }, + { + .mpidr = BSP_CORE1_AFF, + .phyiscal_id = 1, + .redist_base = (void *)BSP_ARM_GIC_RD1_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI1_BASE + }, + { + .mpidr = BSP_CORE2_AFF, + .phyiscal_id = 2, + .redist_base = (void *)BSP_ARM_GIC_RD2_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI2_BASE + }, + { + .mpidr = BSP_CORE3_AFF, + .phyiscal_id = 3, + .redist_base = (void *)BSP_ARM_GIC_RD3_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI3_BASE + }, + { + .mpidr = BSP_CORE4_AFF, + .phyiscal_id = 4, + .redist_base = (void *)BSP_ARM_GIC_RD4_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI4_BASE + }, + { + .mpidr = BSP_CORE5_AFF, + .phyiscal_id = 5, + .redist_base = (void *)BSP_ARM_GIC_RD5_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI5_BASE + }, + { + .mpidr = BSP_CORE6_AFF, + .phyiscal_id = 6, + .redist_base = (void *)BSP_ARM_GIC_RD6_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI6_BASE + }, + { + .mpidr = BSP_CORE7_AFF, + .phyiscal_id = 7, + .redist_base = (void *)BSP_ARM_GIC_RD7_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI7_BASE + }, +}; +#elif defined(PHYTIUM_BSP_TYPE_FT2004_DSK) +const phytium_smp_core_info BSP_core_info[BSP_CORE_NUM] = +{ + { + .mpidr = BSP_CORE0_AFF, + .phyiscal_id = 0, + .redist_base = (void *)BSP_ARM_GIC_RD0_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI0_BASE + }, + { + .mpidr = BSP_CORE1_AFF, + .phyiscal_id = 1, + .redist_base = (void *)BSP_ARM_GIC_RD1_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI1_BASE + }, + { + .mpidr = BSP_CORE2_AFF, + .phyiscal_id = 2, + .redist_base = (void *)BSP_ARM_GIC_RD2_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI2_BASE + }, + { + .mpidr = BSP_CORE3_AFF, + .phyiscal_id = 3, + .redist_base = (void *)BSP_ARM_GIC_RD3_BASE, + .sgi_ppi_base = (void *)BSP_ARM_GIC_SGI3_BASE + }, +}; +#else +#error "SMP affinitiy map undefined !!!" +#endif + +uint32_t _CPU_SMP_Get_processor_affinity(uint32_t cpu_index) +{ + assert(cpu_index < BSP_CORE_NUM); + return BSP_core_info[cpu_index].mpidr; +} + +void *_CPU_SMP_Get_processor_redist(uint32_t cpu_index) +{ + assert(cpu_index < BSP_CORE_NUM); + return BSP_core_info[cpu_index].redist_base; +} + +void *_CPU_SMP_Get_processor_sgi_ppi(uint32_t cpu_index) +{ + assert(cpu_index < BSP_CORE_NUM); + return BSP_core_info[cpu_index].sgi_ppi_base; +} + +bool _CPU_SMP_Start_processor( uint32_t cpu_index ) +{ + uint32_t PSCI_FN_SYSTEM_CPU_ON = 0xC4000003; + uint64_t ret = 0; + uint64_t target_cpu = _CPU_SMP_Get_processor_affinity(cpu_index); + + __asm__ volatile ( + "mov " REGISTER_PREFIX "0, %1\n" + "mov " REGISTER_PREFIX "1, %2\n" + "mov " REGISTER_PREFIX "2, %3\n" + "mov " REGISTER_PREFIX "3, #0\n" +#ifdef BSP_CPU_ON_USES_SMC + "smc #0\n" +#else + "hvc #0\n" +#endif + "mov %0, " REGISTER_PREFIX "0\n" + : "=r" ( ret ) : "r" ( PSCI_FN_SYSTEM_CPU_ON ), "r" ( target_cpu ), + "r" ( _start ) + : REGISTER_PREFIX "0", REGISTER_PREFIX "1", REGISTER_PREFIX "2", + REGISTER_PREFIX "3" + ); + + if ( ret != 0 ) { + return false; + } + + return _Per_CPU_State_wait_for_non_initial_state( cpu_index, 0 ); +} + +void _CPU_SMP_Get_processor_affinity_by_mask(uint32_t cpu_mask, uint32_t *cluster_id, uint32_t *target_list) +{ + assert(cluster_id && target_list); + + const phytium_smp_core_info *core_info; + uint32_t cpu_index = __builtin_ctz(cpu_mask); + assert(cpu_index < BSP_CORE_NUM); + *target_list = 0; + *cluster_id = 0; + + core_info = &BSP_core_info[cpu_index]; + + *target_list = ((core_info->mpidr & 0xf) + 1); + *cluster_id = (core_info->mpidr & 0xff0); +} + +uint32_t _CPU_SMP_Get_current_processor( void ) +{ + uint32_t mpidr; + uint32_t core; + + __asm__ volatile ( + "mrs %[mpidr], mpidr_el1\n" + : [mpidr] "=&r" (mpidr) + ); + + mpidr &= 0xfffU; + + for (core = 0; core < BSP_CORE_NUM; core++) { + if (BSP_core_info[core].mpidr == mpidr) { + break; + } + } + + assert(core < BSP_CORE_NUM); + return core; +} \ No newline at end of file diff --git a/bsps/aarch64/phytium/start/bspstart.c b/bsps/aarch64/phytium/start/bspstart.c new file mode 100644 index 0000000000..7217fd9ff8 --- /dev/null +++ b/bsps/aarch64/phytium/start/bspstart.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief BSP Startup + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#if defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) || \ + defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) || \ + defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) +#include +#endif + +void bsp_start( void ) +{ + bsp_interrupt_initialize(); + rtems_cache_coherent_add_area( + bsp_section_nocacheheap_begin, + (uintptr_t) bsp_section_nocacheheap_size + ); + + /* board init */ + FIOMuxInit(); +#if defined(PHYTIUM_BSP_TYPE_E2000D_DEMO) || \ + defined(PHYTIUM_BSP_TYPE_E2000Q_DEMO) || \ + defined(PHYTIUM_BSP_TYPE_PHYTIUM_PI) + FSdifTimingInit(); +#endif +} diff --git a/bsps/aarch64/phytium/start/bspstarthooks.c b/bsps/aarch64/phytium/start/bspstarthooks.c new file mode 100644 index 0000000000..356dc3ef0d --- /dev/null +++ b/bsps/aarch64/phytium/start/bspstarthooks.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief BSP Startup Hooks + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#ifdef RTEMS_SMP +#include +#include + +#include + +BSP_START_TEXT_SECTION void phytium_setup_secondary_cpu_mmu_and_cache( void ); +#endif + +BSP_START_TEXT_SECTION void phytium_setup_mmu_and_cache(void); + +BSP_START_TEXT_SECTION void bsp_start_hook_0(void) +{ + /* Do nothing */ +} + +BSP_START_TEXT_SECTION void bsp_start_hook_1(void) +{ +#ifdef RTEMS_SMP + uint32_t cpu_index_self; + + cpu_index_self = _SMP_Get_current_processor(); + + if ( cpu_index_self != 0 ) { + /* Start secondary cpu core */ + if ( + cpu_index_self >= rtems_configuration_get_maximum_processors() + || !_SMP_Should_start_processor( cpu_index_self ) + ) { + while ( true ) { + _AARCH64_Wait_for_event(); + } + } + + /* Change the VBAR from the start to the normal vector table */ + AArch64_start_set_vector_base(); + + phytium_setup_secondary_cpu_mmu_and_cache(); + arm_gic_irq_initialize_secondary_cpu(); + + bsp_interrupt_vector_enable( ARM_GIC_IRQ_SGI_0 ); + _SMP_Start_multitasking_on_secondary_processor( + _Per_CPU_Get_by_index( cpu_index_self ) + ); + + /* Unreached */ + } +#endif /* RTEMS_SMP */ + /* Only primary core will reach here */ + AArch64_start_set_vector_base(); + bsp_start_copy_sections(); + phytium_setup_mmu_and_cache(); + bsp_start_clear_bss(); +} \ No newline at end of file diff --git a/bsps/aarch64/phytium/start/bspstartmmu.c b/bsps/aarch64/phytium/start/bspstartmmu.c new file mode 100644 index 0000000000..6c573d6b02 --- /dev/null +++ b/bsps/aarch64/phytium/start/bspstartmmu.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsAArch64Phytium + * + * @brief This source file contains the default MMU tables and setup. + */ + +/* + * Copyright (C) 2024 Phytium Technology Co., Ltd. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#if defined(PHYTIUM_BSP_TYPE_D2000_TEST) +void FCacheL3CacheDisable(void); +#endif + +BSP_START_DATA_SECTION static const aarch64_mmu_config_entry +phytium_mmu_config_table[] = { + AARCH64_MMU_DEFAULT_SECTIONS, + { /* DEVICE_REGION */ + .begin = 0x00ULL, + .end = 0x00ULL + 0x40000000ULL, + .flags = AARCH64_MMU_DEVICE + }, + + { /* PCIE_CONFIG_REGION */ + .begin = 0x40000000ULL, + .end = 0x40000000ULL + 0x10000000ULL, + .flags = AARCH64_MMU_DEVICE + }, + + { /* PCIE_CONFIG_REGION */ + .begin = 0x50000000ULL, + .end = 0x50000000ULL + 0x30000000ULL, + .flags = AARCH64_MMU_DEVICE + }, + + { /* PCIE_MEM64_REGION */ + .begin = 0x1000000000ULL, + .end = 0x1000000000ULL + 0x1000000000ULL, + .flags = AARCH64_MMU_DEVICE + }, +}; + +/* + * Make weak and let the user override. + */ +BSP_START_TEXT_SECTION void +phytium_setup_mmu_and_cache( void ) __attribute__ ((weak)); + +BSP_START_TEXT_SECTION void +phytium_setup_mmu_and_cache( void ) +{ + aarch64_mmu_setup(); + + aarch64_mmu_setup_translation_table( + &phytium_mmu_config_table[ 0 ], + RTEMS_ARRAY_SIZE( phytium_mmu_config_table ) + ); + +#if defined(PHYTIUM_BSP_TYPE_D2000_TEST) + FCacheL3CacheDisable(); +#endif + + aarch64_mmu_enable(); +} + +#ifdef RTEMS_SMP +/* + * Make weak and let the user override. + */ +BSP_START_TEXT_SECTION void phytium_setup_secondary_cpu_mmu_and_cache( void ) +__attribute__ ( ( weak ) ); + +BSP_START_TEXT_SECTION void phytium_setup_secondary_cpu_mmu_and_cache( void ) +{ + /* Perform basic MMU setup */ + aarch64_mmu_setup(); + + /* Use the existing root page table already configured by CPU0 */ + _AArch64_Write_ttbr0_el1( (uintptr_t) bsp_translation_table_base ); + + aarch64_mmu_enable(); +} +#endif \ No newline at end of file diff --git a/bsps/aarch64/shared/start/aarch64-smp.c b/bsps/aarch64/shared/start/aarch64-smp.c index b982b1e00f..8c6634aeba 100644 --- a/bsps/aarch64/shared/start/aarch64-smp.c +++ b/bsps/aarch64/shared/start/aarch64-smp.c @@ -81,7 +81,19 @@ void _CPU_SMP_Prepare_start_multitasking( void ) /* Do nothing */ } -void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ) +RTEMS_WEAK uint32_t _CPU_SMP_Get_current_processor( void ) +{ + uint32_t mpidr; + + __asm__ volatile ( + "mrs %[mpidr], mpidr_el1\n" + : [mpidr] "=&r" (mpidr) + ); + + return mpidr & 0xffU; +} + +RTEMS_WEAK void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ) { arm_gic_irq_generate_software_irq( ARM_GIC_IRQ_SGI_0, diff --git a/bsps/aarch64/shared/start/start.S b/bsps/aarch64/shared/start/start.S index 0237583463..e76532fe43 100644 --- a/bsps/aarch64/shared/start/start.S +++ b/bsps/aarch64/shared/start/start.S @@ -47,6 +47,16 @@ _start: +#ifdef AARCH64_FLUSH_CACHE_BOOT_UP + /* + * We do dcache flush only for the primary core startup + */ + bl _ASM_CPU_SMP_Get_current_processor + cmp x0, #0 + bne _skip_flush_start + bl rtems_cache_flush_entire_data +_skip_flush_start: +#endif /* * We do not save the context since we do not return to the boot * loader but preserve x1 and x2 to allow access to bootloader parameters @@ -219,10 +229,16 @@ _el2_start: _el1_start: #ifdef RTEMS_SMP +#if defined(BSP_AARCH64_PHYTIUM) + /* Let bsp to define the rule and order of core */ + bl _ASM_CPU_SMP_Get_current_processor + mov x7, x0 +#else /* Read MPIDR and get current processor index */ mrs x7, mpidr_el1 and x7, x7, #0xff #endif +#endif #ifdef RTEMS_SMP /* diff --git a/bsps/include/dev/irq/arm-gic-regs.h b/bsps/include/dev/irq/arm-gic-regs.h index c03a7a7a07..ecd7710adb 100644 --- a/bsps/include/dev/irq/arm-gic-regs.h +++ b/bsps/include/dev/irq/arm-gic-regs.h @@ -171,6 +171,10 @@ typedef struct { #define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) #define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) #define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t reserved_f04[5183]; + uint64_t icdrouter[1024]; /* GICD_IROUTER 0x6000, n = 32 - 1019 */ +#define GIC_DIST_ICDROUTER_MODE_ANY BSP_BIT64(31) /* 0: route to specicifc core, 1: route to any core */ +#define GIC_DIST_ICDROUTER_AFF_MASK BSP_MSK64(0, 23) } gic_dist; /* GICv3 only */ diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h index 4e418de68f..6665601a60 100644 --- a/bsps/include/dev/irq/arm-gic.h +++ b/bsps/include/dev/irq/arm-gic.h @@ -181,6 +181,11 @@ static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) return dist->icdiptr[id]; } +static inline void gic_id_set_irouter(volatile gic_dist *dist, uint32_t id, uint32_t affinity) +{ + dist->icdrouter[id] = affinity; +} + typedef enum { GIC_LEVEL_SENSITIVE, GIC_EDGE_TRIGGERED diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h index 5cce29cf03..15401935a6 100644 --- a/bsps/include/dev/irq/arm-gicv3.h +++ b/bsps/include/dev/irq/arm-gicv3.h @@ -154,6 +154,20 @@ extern "C" { #endif /* ARM_MULTILIB_ARCH_V4 */ +#if defined(BSP_AARCH64_PHYTIUM) +void *_CPU_SMP_Get_processor_redist(uint32_t cpu_index); +void *_CPU_SMP_Get_processor_sgi_ppi(uint32_t cpu_index); + +static inline volatile gic_redist *gicv3_get_redist(uint32_t cpu_index) +{ + return (volatile gic_redist *)_CPU_SMP_Get_processor_redist(cpu_index); +} + +static inline volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index) +{ + return (volatile gic_sgi_ppi *)_CPU_SMP_Get_processor_sgi_ppi(cpu_index); +} +#else static inline volatile gic_redist *gicv3_get_redist(uint32_t cpu_index) { return (volatile gic_redist *) @@ -165,6 +179,7 @@ static inline volatile gic_sgi_ppi *gicv3_get_sgi_ppi(uint32_t cpu_index) return (volatile gic_sgi_ppi *) ((uintptr_t)BSP_ARM_GIC_REDIST_BASE + cpu_index * 0x20000 + 0x10000); } +#endif static inline void gicv3_sgi_ppi_enable( rtems_vector_number vector, @@ -252,6 +267,28 @@ static inline void gicv3_ppi_clear_pending( sgi_ppi->icspicpendr[0] = 1U << vector; } +#if defined(BSP_AARCH64_PHYTIUM) +void _CPU_SMP_Get_processor_affinity_by_mask(uint32_t cpu_mask, uint32_t *cluster_id, uint32_t *target_list); + +static inline void gicv3_trigger_sgi( + rtems_vector_number vector, + uint32_t targets +) +{ + uint32_t cluster_id, target_list; + uint64_t value; + uint32_t cpu_mask = targets; + + /* sgi target core may be not in the same cluster */ + _CPU_SMP_Get_processor_affinity_by_mask(cpu_mask, &cluster_id, &target_list); + value = ICC_SGIR_INTID(vector) + | ICC_SGIR_CPU_TARGET_LIST(target_list) + | ICC_SGIR_AFFINITY1(((cluster_id >> 8) & 0xFFULL)) + | ICC_SGIR_AFFINITY2(((cluster_id >> 16) & 0xFFULL)) + | ICC_SGIR_AFFINITY3(((cluster_id >> 24) & 0xFFUll)); + WRITE64_SR(ICC_SGI1, value); +} +#else static inline void gicv3_trigger_sgi( rtems_vector_number vector, uint32_t targets @@ -272,6 +309,7 @@ static inline void gicv3_trigger_sgi( #endif WRITE64_SR(ICC_SGI1, value); } +#endif static inline uint32_t gicv3_get_id_count(volatile gic_dist *dist) { diff --git a/bsps/shared/dev/irq/arm-gicv3.c b/bsps/shared/dev/irq/arm-gicv3.c index 2976b19108..77a7826708 100644 --- a/bsps/shared/dev/irq/arm-gicv3.c +++ b/bsps/shared/dev/irq/arm-gicv3.c @@ -175,6 +175,11 @@ rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) volatile gic_dist *dist = ARM_GIC_DIST; gic_id_enable(dist, vector); +#if defined(BSP_AARCH64_PHYTIUM) + /* some primary code does not have affinity 0, therefore set and + route spi interrupt to primary core */ + gic_id_set_irouter(dist, vector, BSP_ARM_GIC_MAIN_AFF); +#endif } else { gicv3_sgi_ppi_enable(vector, _SMP_Get_current_processor()); } @@ -205,6 +210,14 @@ void bsp_interrupt_facility_initialize(void) } #ifdef RTEMS_SMP +#if defined(BSP_AARCH64_PHYTIUM) +BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) +{ + volatile gic_dist *dist = ARM_GIC_DIST; + + gicv3_init_cpu_interface(_SMP_Get_current_processor()); +} +#else BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) { volatile gic_dist *dist = ARM_GIC_DIST; @@ -216,6 +229,7 @@ BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) gicv3_init_cpu_interface(_SMP_Get_current_processor()); } #endif +#endif rtems_status_code bsp_interrupt_set_priority( rtems_vector_number vector, @@ -306,6 +320,13 @@ void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets) } #ifdef RTEMS_SMP +#if defined(BSP_AARCH64_PHYTIUM) +uint32_t arm_gic_irq_processor_count(void) +{ + /* User may not want to use all processors */ + return BSP_CORE_NUM; +} +#else uint32_t arm_gic_irq_processor_count(void) { volatile gic_dist *dist = ARM_GIC_DIST; @@ -332,3 +353,4 @@ uint32_t arm_gic_irq_processor_count(void) return cpu_count; } #endif +#endif diff --git a/cpukit/libmisc/shell/main_df.c b/cpukit/libmisc/shell/main_df.c index d4266147a6..6d81ae6444 100644 --- a/cpukit/libmisc/shell/main_df.c +++ b/cpukit/libmisc/shell/main_df.c @@ -56,7 +56,7 @@ static unsigned rtems_shell_df_parse_size(const char *str) return result; } -static char *rtems_shell_df_humanize_size(unsigned block_size, char *buf, +static char *rtems_shell_df_humanize_size(uint64_t block_size, char *buf, size_t size) { int i = 0; @@ -67,7 +67,7 @@ static char *rtems_shell_df_humanize_size(unsigned block_size, char *buf, i++; } - snprintf(buf, size, "%d%c", block_size, suffixes[i]); + snprintf(buf, size, "%ld%c", block_size, suffixes[i]); return buf; } @@ -96,11 +96,11 @@ static bool rtems_shell_df_print_entry( } else { - rtems_shell_df_humanize_size(svfs.f_blocks * svfs.f_frsize, f_buf, + rtems_shell_df_humanize_size((uint64_t)(svfs.f_blocks * svfs.f_frsize), f_buf, sizeof(f_buf)); - rtems_shell_df_humanize_size((svfs.f_blocks - svfs.f_bfree) * svfs.f_frsize, + rtems_shell_df_humanize_size((uint64_t)((svfs.f_blocks - svfs.f_bfree) * svfs.f_frsize), u_buf, sizeof(u_buf)); - rtems_shell_df_humanize_size(svfs.f_bfree * svfs.f_frsize, a_buf, + rtems_shell_df_humanize_size((uint64_t)(svfs.f_bfree * svfs.f_frsize), a_buf, sizeof(a_buf)); printf("%-15s %10s %9s %11s %9" PRIu64 "%% %14s\n", mt_entry->dev == NULL ? "none" : mt_entry->dev, f_buf, u_buf, a_buf, @@ -142,7 +142,7 @@ static int rtems_shell_main_df(int argc, char **argv) else printf( "Filesystem %s-blocks Used Available Use%% Mounted on\n", - rtems_shell_df_humanize_size(context.block_size, buf, sizeof(buf))); + rtems_shell_df_humanize_size((uint64_t)context.block_size, buf, sizeof(buf))); rtems_filesystem_mount_iterate(rtems_shell_df_print_entry, &context); diff --git a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h index 4cd217caae..2285065c37 100644 --- a/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/aarch64/include/rtems/score/cpu.h @@ -339,17 +339,7 @@ RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); void _CPU_SMP_Prepare_start_multitasking( void ); - static inline uint32_t _CPU_SMP_Get_current_processor( void ) - { - uint32_t mpidr; - - __asm__ volatile ( - "mrs %[mpidr], mpidr_el1\n" - : [mpidr] "=&r" (mpidr) - ); - - return mpidr & 0xffU; - } + uint32_t _CPU_SMP_Get_current_processor( void ); void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); diff --git a/spec/build/bsps/aarch64/optflushcacheboot.yml b/spec/build/bsps/aarch64/optflushcacheboot.yml new file mode 100644 index 0000000000..8ceff846af --- /dev/null +++ b/spec/build/bsps/aarch64/optflushcacheboot.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: false +description: | + If set to true, dcache will be flushed when startup, this feature is for JTAG bootup or + Uboot/UEFI bootup without decache flsuh/off support +enabled-by: true +links: [] +name: AARCH64_FLUSH_CACHE_BOOT_UP +type: build \ No newline at end of file diff --git a/spec/build/bsps/aarch64/phytium/abi.yml b/spec/build/bsps/aarch64/phytium/abi.yml new file mode 100644 index 0000000000..a2bac462b3 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/abi.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Technology Co., Ltd. +default: +- enabled-by: true + value: + - -march=armv8-a +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/aarch64/phytium/bspd2000test.yml b/spec/build/bsps/aarch64/phytium/bspd2000test.yml new file mode 100644 index 0000000000..08920c2ee7 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/bspd2000test.yml @@ -0,0 +1,150 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: aarch64 +bsp: phytium_d2000_test +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +cppflags: [] +enabled-by: true +family: phytium +includes: + - bsps/../../port/standalone + - bsps/../../../standalone/common + - bsps/../../../standalone/arch/armv8/common + - bsps/../../../standalone/arch/armv8/aarch64 + - bsps/aarch64/phytium/include/soc/d2000 + - bsps/../../../standalone/board/d2000_test + - bsps/../../../standalone/board/port + - bsps/../../../standalone/drivers/iomux/fioctrl + - bsps/../../../standalone/drivers/watchdog/fwdt + +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/aarch64/phytium/include/bsp.h + - bsps/aarch64/phytium/include/tm27.h + + # support source files using #include "fparameters.h" + - bsps/aarch64/phytium/include/soc/d2000/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/aarch64/phytium/include/bsp/irq.h + +# support source files using #inclde +- destination: ${BSP_INCLUDEDIR}/soc/d2000 + source: + - bsps/aarch64/phytium/include/soc/d2000/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/phytium + source: + - bsps/../../port/standalone/fdrivers_port.h + - bsps/../../port/standalone/fboard_port.h + - bsps/../../port/standalone/fdebug.h + - bsps/../../port/standalone/debug_printf.h + + - bsps/../../../standalone/arch/armv8/aarch64/faarch.h + + - bsps/../../../standalone/common/fassert.h + - bsps/../../../standalone/common/ferror_code.h + - bsps/../../../standalone/common/fio.h + - bsps/../../../standalone/common/fkernel.h + - bsps/../../../standalone/common/ftypes.h + + - bsps/../../../standalone/board/d2000_test/fio_mux.h + - bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl_hw.h + - bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl.h + + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt_hw.h + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt.h + +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../optmmupages +- role: build-dependency + uid: abi +- role: build-dependency + uid: ../../../cpukit/objsmp +- role: build-dependency + uid: optd2000test +- role: build-dependency + uid: optphytium +- role: build-dependency + uid: ../../optcachedata +- role: build-dependency + uid: ../../optcacheinst +# option compile BSP with -O2/-O0/-Og +# - role: build-dependency +# uid: ../../opto2 +- role: build-dependency + uid: ../../optog +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: optloadoff +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: linkercmds +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: objphytiumgicv3 +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../objclockarmgenerictimer + +source: +- bsps/../../port/standalone/fdrivers_port.c +- bsps/../../port/standalone/fboard_port.c +- bsps/../../port/standalone/debug_uart.c +- bsps/../../port/standalone/debug_printf.c +- bsps/../../../standalone/common/fassert.c + +- bsps/../../../standalone/board/d2000_test/fio_mux.c + +- bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl_g.c +- bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl_sinit.c +- bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl.c + +- bsps/../../../configs/dtb/d2000-test-board.c + +- bsps/aarch64/phytium/fdt/bsp_fdt.c +- bsps/aarch64/phytium/console/console.c +- bsps/aarch64/phytium/start/bspstart.c +- bsps/aarch64/phytium/start/bspstarthooks.c +- bsps/aarch64/phytium/start/bspstartmmu.c +- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspl3cache.c +- bsps/aarch64/phytium/start/bspsmp.c +- bsps/aarch64/phytium/start/bspcpuid.S + +- bsps/aarch64/shared/cache/cache.c +- bsps/aarch64/shared/mmu/vmsav8-64.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/dev/serial/arm-pl011.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/irq/irq-default-handler.c + +- bsps/aarch64/shared/start/aarch64-smp.c + +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +- bsps/shared/start/wkspaceinitone.c +- bsps/shared/start/mallocinitmulti.c +- bsps/shared/start/bspgetworkarea-default.c +type: build diff --git a/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml b/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml new file mode 100644 index 0000000000..8f7c83c270 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml @@ -0,0 +1,170 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: aarch64 +bsp: phytium_e2000d_demo +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +cppflags: [] +enabled-by: true +family: phytium +includes: + - bsps/../../port/standalone + - bsps/../../../standalone/common + - bsps/../../../standalone/arch/armv8/common + - bsps/../../../standalone/arch/armv8/aarch64 + - bsps/aarch64/phytium/include/soc/e2000d + - bsps/../../../standalone/board/e2000d_demo + - bsps/../../../standalone/board/port + - bsps/../../../standalone/drivers/iomux/fiopad + - bsps/../../../standalone/drivers/mmc/fsdif + - bsps/../../../standalone/drivers/watchdog/fwdt + +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/aarch64/phytium/include/bsp.h + - bsps/aarch64/phytium/include/tm27.h + + # support source files using #include "fparameters.h" + - bsps/aarch64/phytium/include/soc/e2000d/fparameters_comm.h + - bsps/aarch64/phytium/include/soc/e2000d/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/aarch64/phytium/include/bsp/irq.h + +# support source files using #inclde +- destination: ${BSP_INCLUDEDIR}/soc/e2000d + source: + - bsps/aarch64/phytium/include/soc/e2000d/fparameters_comm.h + - bsps/aarch64/phytium/include/soc/e2000d/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/phytium + source: + - bsps/../../port/standalone/fdrivers_port.h + - bsps/../../port/standalone/fboard_port.h + - bsps/../../port/standalone/fdebug.h + - bsps/../../port/standalone/debug_printf.h + + - bsps/../../../standalone/arch/armv8/aarch64/faarch.h + + - bsps/../../../standalone/common/fassert.h + - bsps/../../../standalone/common/ferror_code.h + - bsps/../../../standalone/common/fio.h + - bsps/../../../standalone/common/fkernel.h + - bsps/../../../standalone/common/ftypes.h + + - bsps/../../../standalone/board/e2000d_demo/fio_mux.h + - bsps/../../../standalone/board/e2000d_demo/fsdif_timing.h + - bsps/../../../standalone/drivers/iomux/fiopad/fiopad_hw.h + - bsps/../../../standalone/drivers/iomux/fiopad/fiopad.h + + - bsps/../../../standalone/drivers/mmc/fsdif/fsdif_hw.h + - bsps/../../../standalone/drivers/mmc/fsdif/fsdif.h + + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt_hw.h + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt.h + + +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../optmmupages +- role: build-dependency + uid: abi +- role: build-dependency + uid: ../../../cpukit/objsmp +- role: build-dependency + uid: opte2000ddemo +- role: build-dependency + uid: optphytium +- role: build-dependency + uid: ../../optcachedata +- role: build-dependency + uid: ../../optcacheinst +# option compile BSP with -O2/-O0/-Og +# - role: build-dependency +# uid: ../../opto2 +- role: build-dependency + uid: ../../optog +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: optloadoff +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: linkercmds +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: objphytiumgicv3 +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../objclockarmgenerictimer +- role: build-dependency + uid: ../optflushcacheboot + +source: +- bsps/../../port/standalone/fdrivers_port.c +- bsps/../../port/standalone/fboard_port.c +- bsps/../../port/standalone/debug_uart.c +- bsps/../../port/standalone/debug_printf.c +- bsps/../../../standalone/common/fassert.c + +- bsps/../../../standalone/board/e2000d_demo/fsdif_timing.c +- bsps/../../../standalone/board/e2000d_demo/fio_mux.c + +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_g.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_hw.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_sinit.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad.c + +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_cmd.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_dma.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_intr.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_pio.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_selftest.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_sinit.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_g.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif.c + +- bsps/../../../configs/dtb/e2000d-demo-board.c + +- bsps/aarch64/phytium/fdt/bsp_fdt.c +- bsps/aarch64/phytium/console/console.c +- bsps/aarch64/phytium/start/bspstart.c +- bsps/aarch64/phytium/start/bspstarthooks.c +- bsps/aarch64/phytium/start/bspstartmmu.c +- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspsmp.c +- bsps/aarch64/phytium/start/bspcpuid.S + +- bsps/aarch64/shared/cache/cache.c +- bsps/aarch64/shared/mmu/vmsav8-64.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/dev/serial/arm-pl011.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/irq/irq-default-handler.c + +- bsps/aarch64/shared/start/aarch64-smp.c + +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +- bsps/shared/start/wkspaceinitone.c +- bsps/shared/start/mallocinitmulti.c +- bsps/shared/start/bspgetworkarea-default.c +type: build diff --git a/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml b/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml new file mode 100644 index 0000000000..90632b25b9 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml @@ -0,0 +1,168 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: aarch64 +bsp: phytium_e2000q_demo +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +cppflags: [] +enabled-by: true +family: phytium +includes: + - bsps/../../port/standalone + - bsps/../../../standalone/common + - bsps/../../../standalone/arch/armv8/common + - bsps/../../../standalone/arch/armv8/aarch64 + - bsps/aarch64/phytium/include/soc/e2000q + - bsps/../../../standalone/board/e2000q_demo + - bsps/../../../standalone/board/port + - bsps/../../../standalone/drivers/iomux/fiopad + - bsps/../../../standalone/drivers/mmc/fsdif + - bsps/../../../standalone/drivers/watchdog/fwdt + +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/aarch64/phytium/include/bsp.h + - bsps/aarch64/phytium/include/tm27.h + + # support source files using #include "fparameters.h" + - bsps/aarch64/phytium/include/soc/e2000q/fparameters_comm.h + - bsps/aarch64/phytium/include/soc/e2000q/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/aarch64/phytium/include/bsp/irq.h + +# support source files using #inclde +- destination: ${BSP_INCLUDEDIR}/soc/e2000q + source: + - bsps/aarch64/phytium/include/soc/e2000q/fparameters_comm.h + - bsps/aarch64/phytium/include/soc/e2000q/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/phytium + source: + - bsps/../../port/standalone/fdrivers_port.h + - bsps/../../port/standalone/fboard_port.h + - bsps/../../port/standalone/fdebug.h + - bsps/../../port/standalone/debug_printf.h + + - bsps/../../../standalone/arch/armv8/aarch64/faarch.h + + - bsps/../../../standalone/common/fassert.h + - bsps/../../../standalone/common/ferror_code.h + - bsps/../../../standalone/common/fio.h + - bsps/../../../standalone/common/fkernel.h + - bsps/../../../standalone/common/ftypes.h + + - bsps/../../../standalone/board/e2000q_demo/fio_mux.h + - bsps/../../../standalone/board/e2000q_demo/fsdif_timing.h + - bsps/../../../standalone/drivers/iomux/fiopad/fiopad_hw.h + - bsps/../../../standalone/drivers/iomux/fiopad/fiopad.h + - bsps/../../../standalone/drivers/mmc/fsdif/fsdif_hw.h + - bsps/../../../standalone/drivers/mmc/fsdif/fsdif.h + + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt_hw.h + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt.h + +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../optmmupages +- role: build-dependency + uid: abi +- role: build-dependency + uid: ../../../cpukit/objsmp +- role: build-dependency + uid: opte2000qdemo +- role: build-dependency + uid: optphytium +- role: build-dependency + uid: ../../optcachedata +- role: build-dependency + uid: ../../optcacheinst +# option compile BSP with -O2/-O0/-Og +# - role: build-dependency +# uid: ../../opto2 +- role: build-dependency + uid: ../../optog +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: optloadoff +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: linkercmds +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: objphytiumgicv3 +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../objclockarmgenerictimer +- role: build-dependency + uid: ../optflushcacheboot + +source: +- bsps/../../port/standalone/fdrivers_port.c +- bsps/../../port/standalone/fboard_port.c +- bsps/../../port/standalone/debug_uart.c +- bsps/../../port/standalone/debug_printf.c +- bsps/../../../standalone/common/fassert.c + +- bsps/../../../standalone/board/e2000q_demo/fsdif_timing.c +- bsps/../../../standalone/board/e2000q_demo/fio_mux.c + +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_g.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_hw.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_sinit.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad.c + +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_cmd.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_dma.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_intr.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_pio.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_selftest.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_sinit.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_g.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif.c + +- bsps/../../../configs/dtb/e2000q-demo-board.c + +- bsps/aarch64/phytium/fdt/bsp_fdt.c +- bsps/aarch64/phytium/console/console.c +- bsps/aarch64/phytium/start/bspstart.c +- bsps/aarch64/phytium/start/bspstarthooks.c +- bsps/aarch64/phytium/start/bspstartmmu.c +- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspsmp.c +- bsps/aarch64/phytium/start/bspcpuid.S + +- bsps/aarch64/shared/cache/cache.c +- bsps/aarch64/shared/mmu/vmsav8-64.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/dev/serial/arm-pl011.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/irq/irq-default-handler.c + +- bsps/aarch64/shared/start/aarch64-smp.c + +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +- bsps/shared/start/wkspaceinitone.c +- bsps/shared/start/mallocinitmulti.c +- bsps/shared/start/bspgetworkarea-default.c +type: build diff --git a/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml b/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml new file mode 100644 index 0000000000..dc102e78ec --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml @@ -0,0 +1,150 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: aarch64 +bsp: phytium_ft2004_dsk +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +cppflags: [] +enabled-by: true +family: phytium +includes: + - bsps/../../port/standalone + - bsps/../../../standalone/common + - bsps/../../../standalone/arch/armv8/common + - bsps/../../../standalone/arch/armv8/aarch64 + - bsps/aarch64/phytium/include/soc/ft2004 + - bsps/../../../standalone/board/ft2004_dsk + - bsps/../../../standalone/board/port + - bsps/../../../standalone/drivers/iomux/fioctrl + - bsps/../../../standalone/drivers/watchdog/fwdt + +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/aarch64/phytium/include/bsp.h + - bsps/aarch64/phytium/include/tm27.h + + # support source files using #include "fparameters.h" + - bsps/aarch64/phytium/include/soc/ft2004/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/aarch64/phytium/include/bsp/irq.h + +# support source files using #inclde +- destination: ${BSP_INCLUDEDIR}/soc/ft2004 + source: + - bsps/aarch64/phytium/include/soc/ft2004/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/phytium + source: + - bsps/../../port/standalone/fdrivers_port.h + - bsps/../../port/standalone/fboard_port.h + - bsps/../../port/standalone/fdebug.h + - bsps/../../port/standalone/debug_printf.h + + - bsps/../../../standalone/arch/armv8/aarch64/faarch.h + + - bsps/../../../standalone/common/fassert.h + - bsps/../../../standalone/common/ferror_code.h + - bsps/../../../standalone/common/fio.h + - bsps/../../../standalone/common/fkernel.h + - bsps/../../../standalone/common/ftypes.h + + - bsps/../../../standalone/board/ft2004_dsk/fio_mux.h + - bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl_hw.h + - bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl.h + + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt_hw.h + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt.h + +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../optmmupages +- role: build-dependency + uid: abi +- role: build-dependency + uid: ../../../cpukit/objsmp +- role: build-dependency + uid: optft2004dsk +- role: build-dependency + uid: optphytium +- role: build-dependency + uid: ../../optcachedata +- role: build-dependency + uid: ../../optcacheinst +# option compile BSP with -O2/-O0/-Og +# - role: build-dependency +# uid: ../../opto2 +- role: build-dependency + uid: ../../optog +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: optloadoff +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: linkercmds +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: objphytiumgicv3 +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../objclockarmgenerictimer + +source: +- bsps/../../port/standalone/fdrivers_port.c +- bsps/../../port/standalone/fboard_port.c +- bsps/../../port/standalone/debug_uart.c +- bsps/../../port/standalone/debug_printf.c +- bsps/../../../standalone/common/fassert.c + +- bsps/../../../standalone/board/ft2004_dsk/fio_mux.c + +- bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl_g.c +- bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl_sinit.c +- bsps/../../../standalone/drivers/iomux/fioctrl/fioctrl.c + +- bsps/../../../configs/dtb/ft2004-dsk-board.c + +- bsps/aarch64/phytium/fdt/bsp_fdt.c +- bsps/aarch64/phytium/console/console.c +- bsps/aarch64/phytium/start/bspstart.c +- bsps/aarch64/phytium/start/bspstarthooks.c +- bsps/aarch64/phytium/start/bspstartmmu.c +- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspl3cache.c +- bsps/aarch64/phytium/start/bspsmp.c +- bsps/aarch64/phytium/start/bspcpuid.S + +- bsps/aarch64/shared/cache/cache.c +- bsps/aarch64/shared/mmu/vmsav8-64.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/dev/serial/arm-pl011.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/irq/irq-default-handler.c + +- bsps/aarch64/shared/start/aarch64-smp.c + +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +- bsps/shared/start/wkspaceinitone.c +- bsps/shared/start/mallocinitmulti.c +- bsps/shared/start/bspgetworkarea-default.c +type: build diff --git a/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml b/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml new file mode 100644 index 0000000000..0fbe2328c2 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml @@ -0,0 +1,168 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: aarch64 +bsp: phytium_pi +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +cppflags: [] +enabled-by: true +family: phytium +includes: + - bsps/../../port/standalone + - bsps/../../../standalone/common + - bsps/../../../standalone/arch/armv8/common + - bsps/../../../standalone/arch/armv8/aarch64 + - bsps/aarch64/phytium/include/soc/phytiumpi + - bsps/../../../standalone/board/firefly + - bsps/../../../standalone/board/port + - bsps/../../../standalone/drivers/iomux/fiopad + - bsps/../../../standalone/drivers/mmc/fsdif + - bsps/../../../standalone/drivers/watchdog/fwdt + +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/aarch64/phytium/include/bsp.h + - bsps/aarch64/phytium/include/tm27.h + + # support source files using #include "fparameters.h" + - bsps/aarch64/phytium/include/soc/phytiumpi/fparameters_comm.h + - bsps/aarch64/phytium/include/soc/phytiumpi/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/aarch64/phytium/include/bsp/irq.h + +# support source files using #inclde +- destination: ${BSP_INCLUDEDIR}/soc/phytiumpi + source: + - bsps/aarch64/phytium/include/soc/phytiumpi/fparameters_comm.h + - bsps/aarch64/phytium/include/soc/phytiumpi/fparameters.h + +- destination: ${BSP_INCLUDEDIR}/phytium + source: + - bsps/../../port/standalone/fdrivers_port.h + - bsps/../../port/standalone/fboard_port.h + - bsps/../../port/standalone/fdebug.h + - bsps/../../port/standalone/debug_printf.h + + - bsps/../../../standalone/arch/armv8/aarch64/faarch.h + + - bsps/../../../standalone/common/fassert.h + - bsps/../../../standalone/common/ferror_code.h + - bsps/../../../standalone/common/fio.h + - bsps/../../../standalone/common/fkernel.h + - bsps/../../../standalone/common/ftypes.h + + - bsps/../../../standalone/board/firefly/fio_mux.h + - bsps/../../../standalone/board/firefly/fsdif_timing.h + - bsps/../../../standalone/drivers/iomux/fiopad/fiopad_hw.h + - bsps/../../../standalone/drivers/iomux/fiopad/fiopad.h + - bsps/../../../standalone/drivers/mmc/fsdif/fsdif_hw.h + - bsps/../../../standalone/drivers/mmc/fsdif/fsdif.h + + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt_hw.h + - bsps/../../../standalone/drivers/watchdog/fwdt/fwdt.h + +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: ../start +- role: build-dependency + uid: ../optmmupages +- role: build-dependency + uid: abi +- role: build-dependency + uid: ../../../cpukit/objsmp +- role: build-dependency + uid: optphytiumpi +- role: build-dependency + uid: optphytium +- role: build-dependency + uid: ../../optcachedata +- role: build-dependency + uid: ../../optcacheinst +# option compile BSP with -O2/-O0/-Og +# - role: build-dependency +# uid: ../../opto2 +- role: build-dependency + uid: ../../optog +- role: build-dependency + uid: ../../bspopts +- role: build-dependency + uid: optloadoff +- role: build-dependency + uid: optramlen +- role: build-dependency + uid: optramori +- role: build-dependency + uid: linkercmds +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: objphytiumgicv3 +- role: build-dependency + uid: ../../objmem +- role: build-dependency + uid: ../objclockarmgenerictimer +- role: build-dependency + uid: ../optflushcacheboot + +source: +- bsps/../../port/standalone/fdrivers_port.c +- bsps/../../port/standalone/fboard_port.c +- bsps/../../port/standalone/debug_uart.c +- bsps/../../port/standalone/debug_printf.c +- bsps/../../../standalone/common/fassert.c + +- bsps/../../../standalone/board/firefly/fsdif_timing.c +- bsps/../../../standalone/board/firefly/fio_mux.c + +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_g.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_hw.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad_sinit.c +- bsps/../../../standalone/drivers/iomux/fiopad/fiopad.c + +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_cmd.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_dma.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_intr.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_pio.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_selftest.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_sinit.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif_g.c +- bsps/../../../standalone/drivers/mmc/fsdif/fsdif.c + +- bsps/../../../configs/dtb/phytium-pi.c + +- bsps/aarch64/phytium/fdt/bsp_fdt.c +- bsps/aarch64/phytium/console/console.c +- bsps/aarch64/phytium/start/bspstart.c +- bsps/aarch64/phytium/start/bspstarthooks.c +- bsps/aarch64/phytium/start/bspstartmmu.c +- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspsmp.c +- bsps/aarch64/phytium/start/bspcpuid.S + +- bsps/aarch64/shared/cache/cache.c +- bsps/aarch64/shared/mmu/vmsav8-64.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/dev/serial/arm-pl011.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/irq/irq-default-handler.c + +- bsps/aarch64/shared/start/aarch64-smp.c + +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +- bsps/shared/start/stackalloc.c +- bsps/shared/start/wkspaceinitone.c +- bsps/shared/start/mallocinitmulti.c +- bsps/shared/start/bspgetworkarea-default.c +type: build diff --git a/spec/build/bsps/aarch64/phytium/linkercmds.yml b/spec/build/bsps/aarch64/phytium/linkercmds.yml new file mode 100644 index 0000000000..59b5d6a4ee --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/linkercmds.yml @@ -0,0 +1,73 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + /* SPDX-License-Identifier: BSD-2-Clause */ + + /* + * Copyright (C) 2024 Phytium Information Technology, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + MEMORY { + RAM : ORIGIN = ${BSP_PHYTIUM_RAM_BASE} + ${BSP_PHYTIUM_LOAD_OFFSET}, LENGTH = ${BSP_PHYTIUM_RAM_LENGTH} - ${BSP_PHYTIUM_LOAD_OFFSET} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) + RAM_MMU : ORIGIN = ${BSP_PHYTIUM_RAM_BASE} + ${BSP_PHYTIUM_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES} + } + + REGION_ALIAS ("REGION_START", RAM); + REGION_ALIAS ("REGION_VECTOR", RAM); + REGION_ALIAS ("REGION_TEXT", RAM); + REGION_ALIAS ("REGION_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_RODATA", RAM); + REGION_ALIAS ("REGION_RODATA_LOAD", RAM); + REGION_ALIAS ("REGION_DATA", RAM); + REGION_ALIAS ("REGION_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_TEXT", RAM); + REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_DATA", RAM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_BSS", RAM); + REGION_ALIAS ("REGION_WORK", RAM); + REGION_ALIAS ("REGION_STACK", RAM); + REGION_ALIAS ("REGION_NOCACHE", RAM); + REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM); + + bsp_stack_exception_size = DEFINED (bsp_stack_exception_size) ? bsp_stack_exception_size : 1024; + + bsp_section_rwbarrier_align = DEFINED (bsp_section_rwbarrier_align) ? bsp_section_rwbarrier_align : 1M; + + bsp_vector_table_in_start_section = 1; + + bsp_translation_table_base = ORIGIN (RAM_MMU); + bsp_translation_table_end = ORIGIN (RAM_MMU) + LENGTH (RAM_MMU); + + OUTPUT_FORMAT ("elf64-littleaarch64") + OUTPUT_ARCH (aarch64) + + INCLUDE linkcmds.base +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/aarch64/phytium/objphytiumgicv3.yml b/spec/build/bsps/aarch64/phytium/objphytiumgicv3.yml new file mode 100644 index 0000000000..6f781a9d71 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/objphytiumgicv3.yml @@ -0,0 +1,41 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2024 Phytium Technology Co., Ltd. +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR}/dev/irq + source: + - bsps/include/dev/irq/arm-gic.h + - bsps/include/dev/irq/arm-gic-irq.h + - bsps/include/dev/irq/arm-gic-regs.h + - bsps/include/dev/irq/arm-gic-tm27.h + - bsps/include/dev/irq/arm-gicv3.h +links: +#- role: build-dependency +# uid: ../../dev/irq/optarmgic-enable-fiq-for-group-0 +#- role: build-dependency +# uid: ../../dev/irq/optarmgic-icc-bpr0 +- role: build-dependency + uid: ../../dev/irq/optarmgic-icc-bpr1 +- role: build-dependency + uid: ../../dev/irq/optarmgic-icc-ctrl +#- role: build-dependency +# uid: ../../dev/irq/optarmgic-icc-igrpen0 +- role: build-dependency + uid: ../../dev/irq/optarmgic-icc-igrpen1 +- role: build-dependency + uid: ../../dev/irq/optarmgic-icc-pmr +- role: build-dependency + uid: ../../dev/irq/optarmgic-icc-sre +- role: build-dependency + uid: ../../dev/irq/grpaarch64gic +- role: build-dependency + uid: ../../dev/irq/grparmgic +source: +- bsps/shared/dev/irq/arm-gicv3.c +type: build diff --git a/spec/build/bsps/aarch64/phytium/optd2000test.yml b/spec/build/bsps/aarch64/phytium/optd2000test.yml new file mode 100644 index 0000000000..034c1fce3e --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optd2000test.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0 +- assert-le: 1 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 1 +description: | + D2000 Test board +enabled-by: true +format: '{}' +links: [] +name: PHYTIUM_BSP_TYPE_D2000_TEST +type: build \ No newline at end of file diff --git a/spec/build/bsps/aarch64/phytium/opte2000ddemo.yml b/spec/build/bsps/aarch64/phytium/opte2000ddemo.yml new file mode 100644 index 0000000000..b9a8ba04ef --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/opte2000ddemo.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0 +- assert-le: 1 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 1 +description: | + E2000D Demo board +enabled-by: true +format: '{}' +links: [] +name: PHYTIUM_BSP_TYPE_E2000D_DEMO +type: build diff --git a/spec/build/bsps/aarch64/phytium/opte2000qdemo.yml b/spec/build/bsps/aarch64/phytium/opte2000qdemo.yml new file mode 100644 index 0000000000..ad2ca636fb --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/opte2000qdemo.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0 +- assert-le: 1 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 1 +description: | + E2000Q Demo board +enabled-by: true +format: '{}' +links: [] +name: PHYTIUM_BSP_TYPE_E2000Q_DEMO +type: build \ No newline at end of file diff --git a/spec/build/bsps/aarch64/phytium/optft2004dsk.yml b/spec/build/bsps/aarch64/phytium/optft2004dsk.yml new file mode 100644 index 0000000000..71d7c3f762 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optft2004dsk.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0 +- assert-le: 1 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 1 +description: | + FT2004 DSK board +enabled-by: true +format: '{}' +links: [] +name: PHYTIUM_BSP_TYPE_FT2004_DSK +type: build \ No newline at end of file diff --git a/spec/build/bsps/aarch64/phytium/optloadoff.yml b/spec/build/bsps/aarch64/phytium/optloadoff.yml new file mode 100644 index 0000000000..4e3870b123 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optloadoff.yml @@ -0,0 +1,19 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 0x100000 +description: | + offset of RAM region from memory area base +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_PHYTIUM_LOAD_OFFSET +type: build diff --git a/spec/build/bsps/aarch64/phytium/optphytium.yml b/spec/build/bsps/aarch64/phytium/optphytium.yml new file mode 100644 index 0000000000..95d164796a --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optphytium.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0 +- assert-le: 1 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 1 +description: | + Phytium BSP +enabled-by: true +format: '{}' +links: [] +name: BSP_AARCH64_PHYTIUM +type: build \ No newline at end of file diff --git a/spec/build/bsps/aarch64/phytium/optphytiumpi.yml b/spec/build/bsps/aarch64/phytium/optphytiumpi.yml new file mode 100644 index 0000000000..ed9951051c --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optphytiumpi.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-ge: 0 +- assert-le: 1 +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 1 +description: | + Firefly Phytium PI +enabled-by: true +format: '{}' +links: [] +name: PHYTIUM_BSP_TYPE_PHYTIUM_PI +type: build \ No newline at end of file diff --git a/spec/build/bsps/aarch64/phytium/optramlen.yml b/spec/build/bsps/aarch64/phytium/optramlen.yml new file mode 100644 index 0000000000..c6f78723ed --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optramlen.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint64: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 0x10000000 +description: | + This option defines the length in bytes of the DDR memory area which is + statically available to the application. The default value takes a NULL + pointer protection are of 64KiB sizea into account. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_PHYTIUM_RAM_LENGTH +type: build diff --git a/spec/build/bsps/aarch64/phytium/optramori.yml b/spec/build/bsps/aarch64/phytium/optramori.yml new file mode 100644 index 0000000000..e45bcf9ed8 --- /dev/null +++ b/spec/build/bsps/aarch64/phytium/optramori.yml @@ -0,0 +1,21 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint64: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2024 Phytium Information Technology, Inc. +default: +- enabled-by: true + value: 0x80000000 +description: | + This option defines the base address of the DDR memory area which is + statically available to the application. The default value takes a NULL + pointer protection area of 64KiB size into account. +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_PHYTIUM_RAM_BASE +type: build diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml index b965cdf804..3abfe0a6a7 100644 --- a/spec/build/cpukit/optsmp.yml +++ b/spec/build/cpukit/optsmp.yml @@ -21,6 +21,11 @@ enabled-by: - arm/xilinx_zynqmp_ultra96 - bsps/aarch64/xilinx-zynqmp - bsps/arm/xilinx-zynq +- aarch64/phytium_e2000q_demo +- aarch64/phytium_e2000d_demo +- aarch64/phytium_pi +- aarch64/phytium_d2000_test +- aarch64/phytium_ft2004_dsk - i386/pc386 - i386/pc486 - i386/pc586 diff --git a/spec/build/testsuites/smptests/grp.yml b/spec/build/testsuites/smptests/grp.yml index 3a1e5ead4d..2200fbe13f 100644 --- a/spec/build/testsuites/smptests/grp.yml +++ b/spec/build/testsuites/smptests/grp.yml @@ -55,8 +55,8 @@ links: uid: smpfatal05 - role: build-dependency uid: smpfatal06 -- role: build-dependency - uid: smpfatal08 +#- role: build-dependency +# uid: smpfatal08 - role: build-dependency uid: smpfatal09 - role: build-dependency -- Gitee From 7d0d7973dd11481a94b9bcb700763c659d31b71b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E6=9C=B1=E8=80=BF=E5=AE=87?= Date: Tue, 24 Sep 2024 03:41:14 +0000 Subject: [PATCH 2/2] =?UTF-8?q?=E4=BF=AE=E6=94=B9=20BSP=20=E9=80=82?= =?UTF-8?q?=E9=85=8D=E6=B5=8B=E8=AF=95=E6=A1=86=E6=9E=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../start/{bspreset_watchdog.c => bspreset.c} | 16 +++------------- bsps/aarch64/phytium/start/bspstartmmu.c | 2 +- spec/build/bsps/aarch64/phytium/bspd2000test.yml | 2 +- .../build/bsps/aarch64/phytium/bspe2000ddemo.yml | 2 +- .../build/bsps/aarch64/phytium/bspe2000qdemo.yml | 2 +- spec/build/bsps/aarch64/phytium/bspft2004dsk.yml | 2 +- spec/build/bsps/aarch64/phytium/bspphytiumpi.yml | 2 +- 7 files changed, 9 insertions(+), 19 deletions(-) rename bsps/aarch64/phytium/start/{bspreset_watchdog.c => bspreset.c} (83%) diff --git a/bsps/aarch64/phytium/start/bspreset_watchdog.c b/bsps/aarch64/phytium/start/bspreset.c similarity index 83% rename from bsps/aarch64/phytium/start/bspreset_watchdog.c rename to bsps/aarch64/phytium/start/bspreset.c index cae265445d..0fb00d6c89 100644 --- a/bsps/aarch64/phytium/start/bspreset_watchdog.c +++ b/bsps/aarch64/phytium/start/bspreset.c @@ -42,19 +42,9 @@ RTEMS_NO_RETURN void bsp_reset(rtems_fatal_source source, rtems_fatal_code code) { - uintptr_t watchdog_reg = FWDT_CONTROL_BASE_ADDR(FWDT0_REFRESH_BASE_ADDR); - uint32_t frequency = 0; - uint32_t irq = 0; - - arm_generic_timer_get_config(&frequency, &irq); - (void)irq; - - printk("System reset by watchdog after 3 seconds ...\n"); - FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WOR, 3 * frequency); /* no timeout */ - FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WCS, FWDT_GWDT_WCS_WDT_EN); - + printk("System shutdown ...\n"); while (true) { - /* wait for watchdog reset */ + /* forever waiting here */ } } @@ -73,7 +63,7 @@ void rtems_monitor_reset_cmd( (void)irq; printk("System reseting ...\n"); - FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WOR, 1 * frequency); /* no timeout */ + FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WOR, 1 * frequency); /* timeout 1 seconds */ FWDT_WRITE_REG32(watchdog_reg, FWDT_GWDT_WCS, FWDT_GWDT_WCS_WDT_EN); while (true) { diff --git a/bsps/aarch64/phytium/start/bspstartmmu.c b/bsps/aarch64/phytium/start/bspstartmmu.c index 6c573d6b02..20e5f0a176 100644 --- a/bsps/aarch64/phytium/start/bspstartmmu.c +++ b/bsps/aarch64/phytium/start/bspstartmmu.c @@ -86,7 +86,7 @@ phytium_setup_mmu_and_cache( void ) RTEMS_ARRAY_SIZE( phytium_mmu_config_table ) ); -#if defined(PHYTIUM_BSP_TYPE_D2000_TEST) +#if defined(PHYTIUM_BSP_TYPE_D2000_TEST) || defined(PHYTIUM_BSP_TYPE_FT2004_DSK) FCacheL3CacheDisable(); #endif diff --git a/spec/build/bsps/aarch64/phytium/bspd2000test.yml b/spec/build/bsps/aarch64/phytium/bspd2000test.yml index 08920c2ee7..16c27c3553 100644 --- a/spec/build/bsps/aarch64/phytium/bspd2000test.yml +++ b/spec/build/bsps/aarch64/phytium/bspd2000test.yml @@ -124,7 +124,7 @@ source: - bsps/aarch64/phytium/start/bspstart.c - bsps/aarch64/phytium/start/bspstarthooks.c - bsps/aarch64/phytium/start/bspstartmmu.c -- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspreset.c - bsps/aarch64/phytium/start/bspl3cache.c - bsps/aarch64/phytium/start/bspsmp.c - bsps/aarch64/phytium/start/bspcpuid.S diff --git a/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml b/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml index 8f7c83c270..11a8f6436c 100644 --- a/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml +++ b/spec/build/bsps/aarch64/phytium/bspe2000ddemo.yml @@ -145,7 +145,7 @@ source: - bsps/aarch64/phytium/start/bspstart.c - bsps/aarch64/phytium/start/bspstarthooks.c - bsps/aarch64/phytium/start/bspstartmmu.c -- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspreset.c - bsps/aarch64/phytium/start/bspsmp.c - bsps/aarch64/phytium/start/bspcpuid.S diff --git a/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml b/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml index 90632b25b9..da2089ad39 100644 --- a/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml +++ b/spec/build/bsps/aarch64/phytium/bspe2000qdemo.yml @@ -143,7 +143,7 @@ source: - bsps/aarch64/phytium/start/bspstart.c - bsps/aarch64/phytium/start/bspstarthooks.c - bsps/aarch64/phytium/start/bspstartmmu.c -- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspreset.c - bsps/aarch64/phytium/start/bspsmp.c - bsps/aarch64/phytium/start/bspcpuid.S diff --git a/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml b/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml index dc102e78ec..3eab58a604 100644 --- a/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml +++ b/spec/build/bsps/aarch64/phytium/bspft2004dsk.yml @@ -124,7 +124,7 @@ source: - bsps/aarch64/phytium/start/bspstart.c - bsps/aarch64/phytium/start/bspstarthooks.c - bsps/aarch64/phytium/start/bspstartmmu.c -- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspreset.c - bsps/aarch64/phytium/start/bspl3cache.c - bsps/aarch64/phytium/start/bspsmp.c - bsps/aarch64/phytium/start/bspcpuid.S diff --git a/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml b/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml index 0fbe2328c2..9ea47e1427 100644 --- a/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml +++ b/spec/build/bsps/aarch64/phytium/bspphytiumpi.yml @@ -143,7 +143,7 @@ source: - bsps/aarch64/phytium/start/bspstart.c - bsps/aarch64/phytium/start/bspstarthooks.c - bsps/aarch64/phytium/start/bspstartmmu.c -- bsps/aarch64/phytium/start/bspreset_watchdog.c +- bsps/aarch64/phytium/start/bspreset.c - bsps/aarch64/phytium/start/bspsmp.c - bsps/aarch64/phytium/start/bspcpuid.S -- Gitee