diff --git "a/2.\351\205\215\345\245\227\350\275\257\344\273\266/OpenOCD\351\205\215\347\275\256\346\226\207\344\273\266/ultralink-rp2350.cfg" "b/2.\351\205\215\345\245\227\350\275\257\344\273\266/OpenOCD\351\205\215\347\275\256\346\226\207\344\273\266/ultralink-rp2350.cfg"
new file mode 100644
index 0000000000000000000000000000000000000000..104e8ecc4d8d65b7ac2c2a7d9dfd40a704cae701
--- /dev/null
+++ "b/2.\351\205\215\345\245\227\350\275\257\344\273\266/OpenOCD\351\205\215\347\275\256\346\226\207\344\273\266/ultralink-rp2350.cfg"
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# RP2350 is a microcontroller with dual Cortex-M33 cores or dual Hazard3 cores.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2350.html
+
+transport select swd
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME rp2350
+}
+
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0x10000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x00040927
+}
+
+# Set to '0' or '1' for single core configuration, 'SMP' for -rtos hwthread
+# handling of both cores, anything else for isolated debugging of both cores
+if { [info exists USE_CORE] } {
+    set _USE_CORE $USE_CORE
+} else {
+    set _USE_CORE SMP
+}
+set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
+
+swj_newdap $_CHIPNAME swd -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.swd -adiv6
+# core 0
+if { $_USE_CORE != 1 } {
+    set _TARGETNAME_0 $_CHIPNAME.dap.core0
+    target create $_CHIPNAME.dap.core0 cortex_m -dap $_CHIPNAME.dap -ap-num 0x2000 -coreid 0 -rtos hwthread
+}
+# core 1
+if { $_USE_CORE != 0 } {
+    set _TARGETNAME_1 $_CHIPNAME.dap.core1
+    target create $_CHIPNAME.dap.core1 cortex_m -dap $_CHIPNAME.dap -ap-num 0x4000 -coreid 1 -rtos hwthread
+}
+
+if {[string compare $_USE_CORE SMP] == 0} {
+    $_TARGETNAME_0 configure  -rtos hwthread
+    $_TARGETNAME_1 configure  -rtos hwthread
+    target smp $_TARGETNAME_0 $_TARGETNAME_1
+}
+
+if { $_USE_CORE == 1 } {
+    set _FLASH_TARGET $_TARGETNAME_1
+} else {
+    set _FLASH_TARGET $_TARGETNAME_0
+}
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+set _FLASHBASE 0x10000000
+# Max size is 2 x 16 MiB (for two chip selects with 24-bit addressing) -> 32 MiB
+set _FLASHSIZE 0x2000000
+flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME_0
+
+if { $_BOTH_CORES } {
+    # Alias to ensure gdb connecting to core 1 gets the correct memory map
+    flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
+
+    # Select core 0
+    targets $_TARGETNAME_0
+}
+
+# srst does not exist; use SYSRESETREQ to perform a soft reset
+cortex_m reset_config sysresetreq