# riscv_vitar_core

**Repository Path**: robinsani/riscv_vitar_core

## Basic Information

- **Project Name**: riscv_vitar_core
- **Description**: riscv_vitar_core
- **Primary Language**: Verilog
- **License**: GPL-3.0
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 0
- **Forks**: 0
- **Created**: 2023-07-28
- **Last Updated**: 2024-10-16

## Categories & Tags

**Categories**: Uncategorized

**Tags**: riscv, CPU, systemverilog

## README

No README documentation available for this project.